sr9800.h 6.4 KB

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  1. /* CoreChip-sz SR9800 one chip USB 2.0 Ethernet Devices
  2. *
  3. * Author : Liu Junliang <liujunliang_ljl@163.com>
  4. *
  5. * This file is licensed under the terms of the GNU General Public License
  6. * version 2. This program is licensed "as is" without any warranty of any
  7. * kind, whether express or implied.
  8. */
  9. #ifndef _SR9800_H
  10. #define _SR9800_H
  11. /* SR9800 spec. command table on Linux Platform */
  12. /* command : Software Station Management Control Reg */
  13. #define SR_CMD_SET_SW_MII 0x06
  14. /* command : PHY Read Reg */
  15. #define SR_CMD_READ_MII_REG 0x07
  16. /* command : PHY Write Reg */
  17. #define SR_CMD_WRITE_MII_REG 0x08
  18. /* command : Hardware Station Management Control Reg */
  19. #define SR_CMD_SET_HW_MII 0x0a
  20. /* command : SROM Read Reg */
  21. #define SR_CMD_READ_EEPROM 0x0b
  22. /* command : SROM Write Reg */
  23. #define SR_CMD_WRITE_EEPROM 0x0c
  24. /* command : SROM Write Enable Reg */
  25. #define SR_CMD_WRITE_ENABLE 0x0d
  26. /* command : SROM Write Disable Reg */
  27. #define SR_CMD_WRITE_DISABLE 0x0e
  28. /* command : RX Control Read Reg */
  29. #define SR_CMD_READ_RX_CTL 0x0f
  30. #define SR_RX_CTL_PRO (1 << 0)
  31. #define SR_RX_CTL_AMALL (1 << 1)
  32. #define SR_RX_CTL_SEP (1 << 2)
  33. #define SR_RX_CTL_AB (1 << 3)
  34. #define SR_RX_CTL_AM (1 << 4)
  35. #define SR_RX_CTL_AP (1 << 5)
  36. #define SR_RX_CTL_ARP (1 << 6)
  37. #define SR_RX_CTL_SO (1 << 7)
  38. #define SR_RX_CTL_RH1M (1 << 8)
  39. #define SR_RX_CTL_RH2M (1 << 9)
  40. #define SR_RX_CTL_RH3M (1 << 10)
  41. /* command : RX Control Write Reg */
  42. #define SR_CMD_WRITE_RX_CTL 0x10
  43. /* command : IPG0/IPG1/IPG2 Control Read Reg */
  44. #define SR_CMD_READ_IPG012 0x11
  45. /* command : IPG0/IPG1/IPG2 Control Write Reg */
  46. #define SR_CMD_WRITE_IPG012 0x12
  47. /* command : Node ID Read Reg */
  48. #define SR_CMD_READ_NODE_ID 0x13
  49. /* command : Node ID Write Reg */
  50. #define SR_CMD_WRITE_NODE_ID 0x14
  51. /* command : Multicast Filter Array Read Reg */
  52. #define SR_CMD_READ_MULTI_FILTER 0x15
  53. /* command : Multicast Filter Array Write Reg */
  54. #define SR_CMD_WRITE_MULTI_FILTER 0x16
  55. /* command : Eth/HomePNA PHY Address Reg */
  56. #define SR_CMD_READ_PHY_ID 0x19
  57. /* command : Medium Status Read Reg */
  58. #define SR_CMD_READ_MEDIUM_STATUS 0x1a
  59. #define SR_MONITOR_LINK (1 << 1)
  60. #define SR_MONITOR_MAGIC (1 << 2)
  61. #define SR_MONITOR_HSFS (1 << 4)
  62. /* command : Medium Status Write Reg */
  63. #define SR_CMD_WRITE_MEDIUM_MODE 0x1b
  64. #define SR_MEDIUM_GM (1 << 0)
  65. #define SR_MEDIUM_FD (1 << 1)
  66. #define SR_MEDIUM_AC (1 << 2)
  67. #define SR_MEDIUM_ENCK (1 << 3)
  68. #define SR_MEDIUM_RFC (1 << 4)
  69. #define SR_MEDIUM_TFC (1 << 5)
  70. #define SR_MEDIUM_JFE (1 << 6)
  71. #define SR_MEDIUM_PF (1 << 7)
  72. #define SR_MEDIUM_RE (1 << 8)
  73. #define SR_MEDIUM_PS (1 << 9)
  74. #define SR_MEDIUM_RSV (1 << 10)
  75. #define SR_MEDIUM_SBP (1 << 11)
  76. #define SR_MEDIUM_SM (1 << 12)
  77. /* command : Monitor Mode Status Read Reg */
  78. #define SR_CMD_READ_MONITOR_MODE 0x1c
  79. /* command : Monitor Mode Status Write Reg */
  80. #define SR_CMD_WRITE_MONITOR_MODE 0x1d
  81. /* command : GPIO Status Read Reg */
  82. #define SR_CMD_READ_GPIOS 0x1e
  83. #define SR_GPIO_GPO0EN (1 << 0) /* GPIO0 Output enable */
  84. #define SR_GPIO_GPO_0 (1 << 1) /* GPIO0 Output value */
  85. #define SR_GPIO_GPO1EN (1 << 2) /* GPIO1 Output enable */
  86. #define SR_GPIO_GPO_1 (1 << 3) /* GPIO1 Output value */
  87. #define SR_GPIO_GPO2EN (1 << 4) /* GPIO2 Output enable */
  88. #define SR_GPIO_GPO_2 (1 << 5) /* GPIO2 Output value */
  89. #define SR_GPIO_RESERVED (1 << 6) /* Reserved */
  90. #define SR_GPIO_RSE (1 << 7) /* Reload serial EEPROM */
  91. /* command : GPIO Status Write Reg */
  92. #define SR_CMD_WRITE_GPIOS 0x1f
  93. /* command : Eth PHY Power and Reset Control Reg */
  94. #define SR_CMD_SW_RESET 0x20
  95. #define SR_SWRESET_CLEAR 0x00
  96. #define SR_SWRESET_RR (1 << 0)
  97. #define SR_SWRESET_RT (1 << 1)
  98. #define SR_SWRESET_PRTE (1 << 2)
  99. #define SR_SWRESET_PRL (1 << 3)
  100. #define SR_SWRESET_BZ (1 << 4)
  101. #define SR_SWRESET_IPRL (1 << 5)
  102. #define SR_SWRESET_IPPD (1 << 6)
  103. /* command : Software Interface Selection Status Read Reg */
  104. #define SR_CMD_SW_PHY_STATUS 0x21
  105. /* command : Software Interface Selection Status Write Reg */
  106. #define SR_CMD_SW_PHY_SELECT 0x22
  107. /* command : BULK in Buffer Size Reg */
  108. #define SR_CMD_BULKIN_SIZE 0x2A
  109. /* command : LED_MUX Control Reg */
  110. #define SR_CMD_LED_MUX 0x70
  111. #define SR_LED_MUX_TX_ACTIVE (1 << 0)
  112. #define SR_LED_MUX_RX_ACTIVE (1 << 1)
  113. #define SR_LED_MUX_COLLISION (1 << 2)
  114. #define SR_LED_MUX_DUP_COL (1 << 3)
  115. #define SR_LED_MUX_DUP (1 << 4)
  116. #define SR_LED_MUX_SPEED (1 << 5)
  117. #define SR_LED_MUX_LINK_ACTIVE (1 << 6)
  118. #define SR_LED_MUX_LINK (1 << 7)
  119. /* Register Access Flags */
  120. #define SR_REQ_RD_REG (USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE)
  121. #define SR_REQ_WR_REG (USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE)
  122. /* Multicast Filter Array size & Max Number */
  123. #define SR_MCAST_FILTER_SIZE 8
  124. #define SR_MAX_MCAST 64
  125. /* IPG0/1/2 Default Value */
  126. #define SR9800_IPG0_DEFAULT 0x15
  127. #define SR9800_IPG1_DEFAULT 0x0c
  128. #define SR9800_IPG2_DEFAULT 0x12
  129. /* Medium Status Default Mode */
  130. #define SR9800_MEDIUM_DEFAULT \
  131. (SR_MEDIUM_FD | SR_MEDIUM_RFC | \
  132. SR_MEDIUM_TFC | SR_MEDIUM_PS | \
  133. SR_MEDIUM_AC | SR_MEDIUM_RE)
  134. /* RX Control Default Setting */
  135. #define SR_DEFAULT_RX_CTL \
  136. (SR_RX_CTL_SO | SR_RX_CTL_AB | SR_RX_CTL_RH1M)
  137. /* EEPROM Magic Number & EEPROM Size */
  138. #define SR_EEPROM_MAGIC 0xdeadbeef
  139. #define SR9800_EEPROM_LEN 0xff
  140. /* SR9800 Driver Version and Driver Name */
  141. #define DRIVER_VERSION "11-Nov-2013"
  142. #define DRIVER_NAME "CoreChips"
  143. #define DRIVER_FLAG \
  144. (FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR | FLAG_MULTI_PACKET)
  145. /* SR9800 BULKIN Buffer Size */
  146. #define SR9800_MAX_BULKIN_2K 0
  147. #define SR9800_MAX_BULKIN_4K 1
  148. #define SR9800_MAX_BULKIN_6K 2
  149. #define SR9800_MAX_BULKIN_8K 3
  150. #define SR9800_MAX_BULKIN_16K 4
  151. #define SR9800_MAX_BULKIN_20K 5
  152. #define SR9800_MAX_BULKIN_24K 6
  153. #define SR9800_MAX_BULKIN_32K 7
  154. struct {unsigned short size, byte_cnt, threshold; } SR9800_BULKIN_SIZE[] = {
  155. /* 2k */
  156. {2048, 0x8000, 0x8001},
  157. /* 4k */
  158. {4096, 0x8100, 0x8147},
  159. /* 6k */
  160. {6144, 0x8200, 0x81EB},
  161. /* 8k */
  162. {8192, 0x8300, 0x83D7},
  163. /* 16 */
  164. {16384, 0x8400, 0x851E},
  165. /* 20k */
  166. {20480, 0x8500, 0x8666},
  167. /* 24k */
  168. {24576, 0x8600, 0x87AE},
  169. /* 32k */
  170. {32768, 0x8700, 0x8A3D},
  171. };
  172. /* This structure cannot exceed sizeof(unsigned long [5]) AKA 20 bytes */
  173. struct sr_data {
  174. u8 multi_filter[SR_MCAST_FILTER_SIZE];
  175. u8 mac_addr[ETH_ALEN];
  176. u8 phymode;
  177. u8 ledmode;
  178. u8 eeprom_len;
  179. };
  180. struct sr9800_int_data {
  181. __le16 res1;
  182. u8 link;
  183. __le16 res2;
  184. u8 status;
  185. __le16 res3;
  186. } __packed;
  187. #endif /* _SR9800_H */