r8152.c 134 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
  4. */
  5. #include <linux/signal.h>
  6. #include <linux/slab.h>
  7. #include <linux/module.h>
  8. #include <linux/netdevice.h>
  9. #include <linux/etherdevice.h>
  10. #include <linux/mii.h>
  11. #include <linux/ethtool.h>
  12. #include <linux/usb.h>
  13. #include <linux/crc32.h>
  14. #include <linux/if_vlan.h>
  15. #include <linux/uaccess.h>
  16. #include <linux/list.h>
  17. #include <linux/ip.h>
  18. #include <linux/ipv6.h>
  19. #include <net/ip6_checksum.h>
  20. #include <uapi/linux/mdio.h>
  21. #include <linux/mdio.h>
  22. #include <linux/usb/cdc.h>
  23. #include <linux/suspend.h>
  24. #include <linux/atomic.h>
  25. #include <linux/acpi.h>
  26. /* Information for net-next */
  27. #define NETNEXT_VERSION "10"
  28. /* Information for net */
  29. #define NET_VERSION "11"
  30. #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION
  31. #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
  32. #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
  33. #define MODULENAME "r8152"
  34. #define R8152_PHY_ID 32
  35. #define PLA_IDR 0xc000
  36. #define PLA_RCR 0xc010
  37. #define PLA_RMS 0xc016
  38. #define PLA_RXFIFO_CTRL0 0xc0a0
  39. #define PLA_RXFIFO_CTRL1 0xc0a4
  40. #define PLA_RXFIFO_CTRL2 0xc0a8
  41. #define PLA_DMY_REG0 0xc0b0
  42. #define PLA_FMC 0xc0b4
  43. #define PLA_CFG_WOL 0xc0b6
  44. #define PLA_TEREDO_CFG 0xc0bc
  45. #define PLA_TEREDO_WAKE_BASE 0xc0c4
  46. #define PLA_MAR 0xcd00
  47. #define PLA_BACKUP 0xd000
  48. #define PLA_BDC_CR 0xd1a0
  49. #define PLA_TEREDO_TIMER 0xd2cc
  50. #define PLA_REALWOW_TIMER 0xd2e8
  51. #define PLA_SUSPEND_FLAG 0xd38a
  52. #define PLA_INDICATE_FALG 0xd38c
  53. #define PLA_EXTRA_STATUS 0xd398
  54. #define PLA_EFUSE_DATA 0xdd00
  55. #define PLA_EFUSE_CMD 0xdd02
  56. #define PLA_LEDSEL 0xdd90
  57. #define PLA_LED_FEATURE 0xdd92
  58. #define PLA_PHYAR 0xde00
  59. #define PLA_BOOT_CTRL 0xe004
  60. #define PLA_LWAKE_CTRL_REG 0xe007
  61. #define PLA_GPHY_INTR_IMR 0xe022
  62. #define PLA_EEE_CR 0xe040
  63. #define PLA_EEEP_CR 0xe080
  64. #define PLA_MAC_PWR_CTRL 0xe0c0
  65. #define PLA_MAC_PWR_CTRL2 0xe0ca
  66. #define PLA_MAC_PWR_CTRL3 0xe0cc
  67. #define PLA_MAC_PWR_CTRL4 0xe0ce
  68. #define PLA_WDT6_CTRL 0xe428
  69. #define PLA_TCR0 0xe610
  70. #define PLA_TCR1 0xe612
  71. #define PLA_MTPS 0xe615
  72. #define PLA_TXFIFO_CTRL 0xe618
  73. #define PLA_RSTTALLY 0xe800
  74. #define PLA_CR 0xe813
  75. #define PLA_CRWECR 0xe81c
  76. #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
  77. #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
  78. #define PLA_CONFIG5 0xe822
  79. #define PLA_PHY_PWR 0xe84c
  80. #define PLA_OOB_CTRL 0xe84f
  81. #define PLA_CPCR 0xe854
  82. #define PLA_MISC_0 0xe858
  83. #define PLA_MISC_1 0xe85a
  84. #define PLA_OCP_GPHY_BASE 0xe86c
  85. #define PLA_TALLYCNT 0xe890
  86. #define PLA_SFF_STS_7 0xe8de
  87. #define PLA_PHYSTATUS 0xe908
  88. #define PLA_CONFIG6 0xe90a /* CONFIG6 */
  89. #define PLA_BP_BA 0xfc26
  90. #define PLA_BP_0 0xfc28
  91. #define PLA_BP_1 0xfc2a
  92. #define PLA_BP_2 0xfc2c
  93. #define PLA_BP_3 0xfc2e
  94. #define PLA_BP_4 0xfc30
  95. #define PLA_BP_5 0xfc32
  96. #define PLA_BP_6 0xfc34
  97. #define PLA_BP_7 0xfc36
  98. #define PLA_BP_EN 0xfc38
  99. #define USB_USB2PHY 0xb41e
  100. #define USB_SSPHYLINK1 0xb426
  101. #define USB_SSPHYLINK2 0xb428
  102. #define USB_U2P3_CTRL 0xb460
  103. #define USB_CSR_DUMMY1 0xb464
  104. #define USB_CSR_DUMMY2 0xb466
  105. #define USB_DEV_STAT 0xb808
  106. #define USB_CONNECT_TIMER 0xcbf8
  107. #define USB_MSC_TIMER 0xcbfc
  108. #define USB_BURST_SIZE 0xcfc0
  109. #define USB_LPM_CONFIG 0xcfd8
  110. #define USB_USB_CTRL 0xd406
  111. #define USB_PHY_CTRL 0xd408
  112. #define USB_TX_AGG 0xd40a
  113. #define USB_RX_BUF_TH 0xd40c
  114. #define USB_USB_TIMER 0xd428
  115. #define USB_RX_EARLY_TIMEOUT 0xd42c
  116. #define USB_RX_EARLY_SIZE 0xd42e
  117. #define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */
  118. #define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */
  119. #define USB_TX_DMA 0xd434
  120. #define USB_UPT_RXDMA_OWN 0xd437
  121. #define USB_TOLERANCE 0xd490
  122. #define USB_LPM_CTRL 0xd41a
  123. #define USB_BMU_RESET 0xd4b0
  124. #define USB_U1U2_TIMER 0xd4da
  125. #define USB_UPS_CTRL 0xd800
  126. #define USB_POWER_CUT 0xd80a
  127. #define USB_MISC_0 0xd81a
  128. #define USB_MISC_1 0xd81f
  129. #define USB_AFE_CTRL2 0xd824
  130. #define USB_UPS_CFG 0xd842
  131. #define USB_UPS_FLAGS 0xd848
  132. #define USB_WDT11_CTRL 0xe43c
  133. #define USB_BP_BA 0xfc26
  134. #define USB_BP_0 0xfc28
  135. #define USB_BP_1 0xfc2a
  136. #define USB_BP_2 0xfc2c
  137. #define USB_BP_3 0xfc2e
  138. #define USB_BP_4 0xfc30
  139. #define USB_BP_5 0xfc32
  140. #define USB_BP_6 0xfc34
  141. #define USB_BP_7 0xfc36
  142. #define USB_BP_EN 0xfc38
  143. #define USB_BP_8 0xfc38
  144. #define USB_BP_9 0xfc3a
  145. #define USB_BP_10 0xfc3c
  146. #define USB_BP_11 0xfc3e
  147. #define USB_BP_12 0xfc40
  148. #define USB_BP_13 0xfc42
  149. #define USB_BP_14 0xfc44
  150. #define USB_BP_15 0xfc46
  151. #define USB_BP2_EN 0xfc48
  152. /* OCP Registers */
  153. #define OCP_ALDPS_CONFIG 0x2010
  154. #define OCP_EEE_CONFIG1 0x2080
  155. #define OCP_EEE_CONFIG2 0x2092
  156. #define OCP_EEE_CONFIG3 0x2094
  157. #define OCP_BASE_MII 0xa400
  158. #define OCP_EEE_AR 0xa41a
  159. #define OCP_EEE_DATA 0xa41c
  160. #define OCP_PHY_STATUS 0xa420
  161. #define OCP_NCTL_CFG 0xa42c
  162. #define OCP_POWER_CFG 0xa430
  163. #define OCP_EEE_CFG 0xa432
  164. #define OCP_SRAM_ADDR 0xa436
  165. #define OCP_SRAM_DATA 0xa438
  166. #define OCP_DOWN_SPEED 0xa442
  167. #define OCP_EEE_ABLE 0xa5c4
  168. #define OCP_EEE_ADV 0xa5d0
  169. #define OCP_EEE_LPABLE 0xa5d2
  170. #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
  171. #define OCP_PHY_PATCH_STAT 0xb800
  172. #define OCP_PHY_PATCH_CMD 0xb820
  173. #define OCP_ADC_IOFFSET 0xbcfc
  174. #define OCP_ADC_CFG 0xbc06
  175. #define OCP_SYSCLK_CFG 0xc416
  176. /* SRAM Register */
  177. #define SRAM_GREEN_CFG 0x8011
  178. #define SRAM_LPF_CFG 0x8012
  179. #define SRAM_10M_AMP1 0x8080
  180. #define SRAM_10M_AMP2 0x8082
  181. #define SRAM_IMPEDANCE 0x8084
  182. /* PLA_RCR */
  183. #define RCR_AAP 0x00000001
  184. #define RCR_APM 0x00000002
  185. #define RCR_AM 0x00000004
  186. #define RCR_AB 0x00000008
  187. #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
  188. /* PLA_RXFIFO_CTRL0 */
  189. #define RXFIFO_THR1_NORMAL 0x00080002
  190. #define RXFIFO_THR1_OOB 0x01800003
  191. /* PLA_RXFIFO_CTRL1 */
  192. #define RXFIFO_THR2_FULL 0x00000060
  193. #define RXFIFO_THR2_HIGH 0x00000038
  194. #define RXFIFO_THR2_OOB 0x0000004a
  195. #define RXFIFO_THR2_NORMAL 0x00a0
  196. /* PLA_RXFIFO_CTRL2 */
  197. #define RXFIFO_THR3_FULL 0x00000078
  198. #define RXFIFO_THR3_HIGH 0x00000048
  199. #define RXFIFO_THR3_OOB 0x0000005a
  200. #define RXFIFO_THR3_NORMAL 0x0110
  201. /* PLA_TXFIFO_CTRL */
  202. #define TXFIFO_THR_NORMAL 0x00400008
  203. #define TXFIFO_THR_NORMAL2 0x01000008
  204. /* PLA_DMY_REG0 */
  205. #define ECM_ALDPS 0x0002
  206. /* PLA_FMC */
  207. #define FMC_FCR_MCU_EN 0x0001
  208. /* PLA_EEEP_CR */
  209. #define EEEP_CR_EEEP_TX 0x0002
  210. /* PLA_WDT6_CTRL */
  211. #define WDT6_SET_MODE 0x0010
  212. /* PLA_TCR0 */
  213. #define TCR0_TX_EMPTY 0x0800
  214. #define TCR0_AUTO_FIFO 0x0080
  215. /* PLA_TCR1 */
  216. #define VERSION_MASK 0x7cf0
  217. /* PLA_MTPS */
  218. #define MTPS_JUMBO (12 * 1024 / 64)
  219. #define MTPS_DEFAULT (6 * 1024 / 64)
  220. /* PLA_RSTTALLY */
  221. #define TALLY_RESET 0x0001
  222. /* PLA_CR */
  223. #define CR_RST 0x10
  224. #define CR_RE 0x08
  225. #define CR_TE 0x04
  226. /* PLA_CRWECR */
  227. #define CRWECR_NORAML 0x00
  228. #define CRWECR_CONFIG 0xc0
  229. /* PLA_OOB_CTRL */
  230. #define NOW_IS_OOB 0x80
  231. #define TXFIFO_EMPTY 0x20
  232. #define RXFIFO_EMPTY 0x10
  233. #define LINK_LIST_READY 0x02
  234. #define DIS_MCU_CLROOB 0x01
  235. #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
  236. /* PLA_MISC_1 */
  237. #define RXDY_GATED_EN 0x0008
  238. /* PLA_SFF_STS_7 */
  239. #define RE_INIT_LL 0x8000
  240. #define MCU_BORW_EN 0x4000
  241. /* PLA_CPCR */
  242. #define CPCR_RX_VLAN 0x0040
  243. /* PLA_CFG_WOL */
  244. #define MAGIC_EN 0x0001
  245. /* PLA_TEREDO_CFG */
  246. #define TEREDO_SEL 0x8000
  247. #define TEREDO_WAKE_MASK 0x7f00
  248. #define TEREDO_RS_EVENT_MASK 0x00fe
  249. #define OOB_TEREDO_EN 0x0001
  250. /* PLA_BDC_CR */
  251. #define ALDPS_PROXY_MODE 0x0001
  252. /* PLA_EFUSE_CMD */
  253. #define EFUSE_READ_CMD BIT(15)
  254. #define EFUSE_DATA_BIT16 BIT(7)
  255. /* PLA_CONFIG34 */
  256. #define LINK_ON_WAKE_EN 0x0010
  257. #define LINK_OFF_WAKE_EN 0x0008
  258. /* PLA_CONFIG6 */
  259. #define LANWAKE_CLR_EN BIT(0)
  260. /* PLA_CONFIG5 */
  261. #define BWF_EN 0x0040
  262. #define MWF_EN 0x0020
  263. #define UWF_EN 0x0010
  264. #define LAN_WAKE_EN 0x0002
  265. /* PLA_LED_FEATURE */
  266. #define LED_MODE_MASK 0x0700
  267. /* PLA_PHY_PWR */
  268. #define TX_10M_IDLE_EN 0x0080
  269. #define PFM_PWM_SWITCH 0x0040
  270. #define TEST_IO_OFF BIT(4)
  271. /* PLA_MAC_PWR_CTRL */
  272. #define D3_CLK_GATED_EN 0x00004000
  273. #define MCU_CLK_RATIO 0x07010f07
  274. #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
  275. #define ALDPS_SPDWN_RATIO 0x0f87
  276. /* PLA_MAC_PWR_CTRL2 */
  277. #define EEE_SPDWN_RATIO 0x8007
  278. #define MAC_CLK_SPDWN_EN BIT(15)
  279. /* PLA_MAC_PWR_CTRL3 */
  280. #define PLA_MCU_SPDWN_EN BIT(14)
  281. #define PKT_AVAIL_SPDWN_EN 0x0100
  282. #define SUSPEND_SPDWN_EN 0x0004
  283. #define U1U2_SPDWN_EN 0x0002
  284. #define L1_SPDWN_EN 0x0001
  285. /* PLA_MAC_PWR_CTRL4 */
  286. #define PWRSAVE_SPDWN_EN 0x1000
  287. #define RXDV_SPDWN_EN 0x0800
  288. #define TX10MIDLE_EN 0x0100
  289. #define TP100_SPDWN_EN 0x0020
  290. #define TP500_SPDWN_EN 0x0010
  291. #define TP1000_SPDWN_EN 0x0008
  292. #define EEE_SPDWN_EN 0x0001
  293. /* PLA_GPHY_INTR_IMR */
  294. #define GPHY_STS_MSK 0x0001
  295. #define SPEED_DOWN_MSK 0x0002
  296. #define SPDWN_RXDV_MSK 0x0004
  297. #define SPDWN_LINKCHG_MSK 0x0008
  298. /* PLA_PHYAR */
  299. #define PHYAR_FLAG 0x80000000
  300. /* PLA_EEE_CR */
  301. #define EEE_RX_EN 0x0001
  302. #define EEE_TX_EN 0x0002
  303. /* PLA_BOOT_CTRL */
  304. #define AUTOLOAD_DONE 0x0002
  305. /* PLA_LWAKE_CTRL_REG */
  306. #define LANWAKE_PIN BIT(7)
  307. /* PLA_SUSPEND_FLAG */
  308. #define LINK_CHG_EVENT BIT(0)
  309. /* PLA_INDICATE_FALG */
  310. #define UPCOMING_RUNTIME_D3 BIT(0)
  311. /* PLA_EXTRA_STATUS */
  312. #define LINK_CHANGE_FLAG BIT(8)
  313. /* USB_USB2PHY */
  314. #define USB2PHY_SUSPEND 0x0001
  315. #define USB2PHY_L1 0x0002
  316. /* USB_SSPHYLINK1 */
  317. #define DELAY_PHY_PWR_CHG BIT(1)
  318. /* USB_SSPHYLINK2 */
  319. #define pwd_dn_scale_mask 0x3ffe
  320. #define pwd_dn_scale(x) ((x) << 1)
  321. /* USB_CSR_DUMMY1 */
  322. #define DYNAMIC_BURST 0x0001
  323. /* USB_CSR_DUMMY2 */
  324. #define EP4_FULL_FC 0x0001
  325. /* USB_DEV_STAT */
  326. #define STAT_SPEED_MASK 0x0006
  327. #define STAT_SPEED_HIGH 0x0000
  328. #define STAT_SPEED_FULL 0x0002
  329. /* USB_LPM_CONFIG */
  330. #define LPM_U1U2_EN BIT(0)
  331. /* USB_TX_AGG */
  332. #define TX_AGG_MAX_THRESHOLD 0x03
  333. /* USB_RX_BUF_TH */
  334. #define RX_THR_SUPPER 0x0c350180
  335. #define RX_THR_HIGH 0x7a120180
  336. #define RX_THR_SLOW 0xffff0180
  337. #define RX_THR_B 0x00010001
  338. /* USB_TX_DMA */
  339. #define TEST_MODE_DISABLE 0x00000001
  340. #define TX_SIZE_ADJUST1 0x00000100
  341. /* USB_BMU_RESET */
  342. #define BMU_RESET_EP_IN 0x01
  343. #define BMU_RESET_EP_OUT 0x02
  344. /* USB_UPT_RXDMA_OWN */
  345. #define OWN_UPDATE BIT(0)
  346. #define OWN_CLEAR BIT(1)
  347. /* USB_UPS_CTRL */
  348. #define POWER_CUT 0x0100
  349. /* USB_PM_CTRL_STATUS */
  350. #define RESUME_INDICATE 0x0001
  351. /* USB_USB_CTRL */
  352. #define RX_AGG_DISABLE 0x0010
  353. #define RX_ZERO_EN 0x0080
  354. /* USB_U2P3_CTRL */
  355. #define U2P3_ENABLE 0x0001
  356. /* USB_POWER_CUT */
  357. #define PWR_EN 0x0001
  358. #define PHASE2_EN 0x0008
  359. #define UPS_EN BIT(4)
  360. #define USP_PREWAKE BIT(5)
  361. /* USB_MISC_0 */
  362. #define PCUT_STATUS 0x0001
  363. /* USB_RX_EARLY_TIMEOUT */
  364. #define COALESCE_SUPER 85000U
  365. #define COALESCE_HIGH 250000U
  366. #define COALESCE_SLOW 524280U
  367. /* USB_WDT11_CTRL */
  368. #define TIMER11_EN 0x0001
  369. /* USB_LPM_CTRL */
  370. /* bit 4 ~ 5: fifo empty boundary */
  371. #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
  372. /* bit 2 ~ 3: LMP timer */
  373. #define LPM_TIMER_MASK 0x0c
  374. #define LPM_TIMER_500MS 0x04 /* 500 ms */
  375. #define LPM_TIMER_500US 0x0c /* 500 us */
  376. #define ROK_EXIT_LPM 0x02
  377. /* USB_AFE_CTRL2 */
  378. #define SEN_VAL_MASK 0xf800
  379. #define SEN_VAL_NORMAL 0xa000
  380. #define SEL_RXIDLE 0x0100
  381. /* USB_UPS_CFG */
  382. #define SAW_CNT_1MS_MASK 0x0fff
  383. /* USB_UPS_FLAGS */
  384. #define UPS_FLAGS_R_TUNE BIT(0)
  385. #define UPS_FLAGS_EN_10M_CKDIV BIT(1)
  386. #define UPS_FLAGS_250M_CKDIV BIT(2)
  387. #define UPS_FLAGS_EN_ALDPS BIT(3)
  388. #define UPS_FLAGS_CTAP_SHORT_DIS BIT(4)
  389. #define ups_flags_speed(x) ((x) << 16)
  390. #define UPS_FLAGS_EN_EEE BIT(20)
  391. #define UPS_FLAGS_EN_500M_EEE BIT(21)
  392. #define UPS_FLAGS_EN_EEE_CKDIV BIT(22)
  393. #define UPS_FLAGS_EEE_PLLOFF_100 BIT(23)
  394. #define UPS_FLAGS_EEE_PLLOFF_GIGA BIT(24)
  395. #define UPS_FLAGS_EEE_CMOD_LV_EN BIT(25)
  396. #define UPS_FLAGS_EN_GREEN BIT(26)
  397. #define UPS_FLAGS_EN_FLOW_CTR BIT(27)
  398. enum spd_duplex {
  399. NWAY_10M_HALF,
  400. NWAY_10M_FULL,
  401. NWAY_100M_HALF,
  402. NWAY_100M_FULL,
  403. NWAY_1000M_FULL,
  404. FORCE_10M_HALF,
  405. FORCE_10M_FULL,
  406. FORCE_100M_HALF,
  407. FORCE_100M_FULL,
  408. };
  409. /* OCP_ALDPS_CONFIG */
  410. #define ENPWRSAVE 0x8000
  411. #define ENPDNPS 0x0200
  412. #define LINKENA 0x0100
  413. #define DIS_SDSAVE 0x0010
  414. /* OCP_PHY_STATUS */
  415. #define PHY_STAT_MASK 0x0007
  416. #define PHY_STAT_EXT_INIT 2
  417. #define PHY_STAT_LAN_ON 3
  418. #define PHY_STAT_PWRDN 5
  419. /* OCP_NCTL_CFG */
  420. #define PGA_RETURN_EN BIT(1)
  421. /* OCP_POWER_CFG */
  422. #define EEE_CLKDIV_EN 0x8000
  423. #define EN_ALDPS 0x0004
  424. #define EN_10M_PLLOFF 0x0001
  425. /* OCP_EEE_CONFIG1 */
  426. #define RG_TXLPI_MSK_HFDUP 0x8000
  427. #define RG_MATCLR_EN 0x4000
  428. #define EEE_10_CAP 0x2000
  429. #define EEE_NWAY_EN 0x1000
  430. #define TX_QUIET_EN 0x0200
  431. #define RX_QUIET_EN 0x0100
  432. #define sd_rise_time_mask 0x0070
  433. #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
  434. #define RG_RXLPI_MSK_HFDUP 0x0008
  435. #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
  436. /* OCP_EEE_CONFIG2 */
  437. #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
  438. #define RG_DACQUIET_EN 0x0400
  439. #define RG_LDVQUIET_EN 0x0200
  440. #define RG_CKRSEL 0x0020
  441. #define RG_EEEPRG_EN 0x0010
  442. /* OCP_EEE_CONFIG3 */
  443. #define fast_snr_mask 0xff80
  444. #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
  445. #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
  446. #define MSK_PH 0x0006 /* bit 0 ~ 3 */
  447. /* OCP_EEE_AR */
  448. /* bit[15:14] function */
  449. #define FUN_ADDR 0x0000
  450. #define FUN_DATA 0x4000
  451. /* bit[4:0] device addr */
  452. /* OCP_EEE_CFG */
  453. #define CTAP_SHORT_EN 0x0040
  454. #define EEE10_EN 0x0010
  455. /* OCP_DOWN_SPEED */
  456. #define EN_EEE_CMODE BIT(14)
  457. #define EN_EEE_1000 BIT(13)
  458. #define EN_EEE_100 BIT(12)
  459. #define EN_10M_CLKDIV BIT(11)
  460. #define EN_10M_BGOFF 0x0080
  461. /* OCP_PHY_STATE */
  462. #define TXDIS_STATE 0x01
  463. #define ABD_STATE 0x02
  464. /* OCP_PHY_PATCH_STAT */
  465. #define PATCH_READY BIT(6)
  466. /* OCP_PHY_PATCH_CMD */
  467. #define PATCH_REQUEST BIT(4)
  468. /* OCP_ADC_CFG */
  469. #define CKADSEL_L 0x0100
  470. #define ADC_EN 0x0080
  471. #define EN_EMI_L 0x0040
  472. /* OCP_SYSCLK_CFG */
  473. #define clk_div_expo(x) (min(x, 5) << 8)
  474. /* SRAM_GREEN_CFG */
  475. #define GREEN_ETH_EN BIT(15)
  476. #define R_TUNE_EN BIT(11)
  477. /* SRAM_LPF_CFG */
  478. #define LPF_AUTO_TUNE 0x8000
  479. /* SRAM_10M_AMP1 */
  480. #define GDAC_IB_UPALL 0x0008
  481. /* SRAM_10M_AMP2 */
  482. #define AMP_DN 0x0200
  483. /* SRAM_IMPEDANCE */
  484. #define RX_DRIVING_MASK 0x6000
  485. /* MAC PASSTHRU */
  486. #define AD_MASK 0xfee0
  487. #define BND_MASK 0x0004
  488. #define BD_MASK 0x0001
  489. #define EFUSE 0xcfdb
  490. #define PASS_THRU_MASK 0x1
  491. enum rtl_register_content {
  492. _1000bps = 0x10,
  493. _100bps = 0x08,
  494. _10bps = 0x04,
  495. LINK_STATUS = 0x02,
  496. FULL_DUP = 0x01,
  497. };
  498. #define RTL8152_MAX_TX 4
  499. #define RTL8152_MAX_RX 10
  500. #define INTBUFSIZE 2
  501. #define TX_ALIGN 4
  502. #define RX_ALIGN 8
  503. #define RTL8152_RX_MAX_PENDING 4096
  504. #define RTL8152_RXFG_HEADSZ 256
  505. #define INTR_LINK 0x0004
  506. #define RTL8152_REQT_READ 0xc0
  507. #define RTL8152_REQT_WRITE 0x40
  508. #define RTL8152_REQ_GET_REGS 0x05
  509. #define RTL8152_REQ_SET_REGS 0x05
  510. #define BYTE_EN_DWORD 0xff
  511. #define BYTE_EN_WORD 0x33
  512. #define BYTE_EN_BYTE 0x11
  513. #define BYTE_EN_SIX_BYTES 0x3f
  514. #define BYTE_EN_START_MASK 0x0f
  515. #define BYTE_EN_END_MASK 0xf0
  516. #define RTL8153_MAX_PACKET 9216 /* 9K */
  517. #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - \
  518. ETH_FCS_LEN)
  519. #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
  520. #define RTL8153_RMS RTL8153_MAX_PACKET
  521. #define RTL8152_TX_TIMEOUT (5 * HZ)
  522. #define RTL8152_NAPI_WEIGHT 64
  523. #define rx_reserved_size(x) ((x) + VLAN_ETH_HLEN + ETH_FCS_LEN + \
  524. sizeof(struct rx_desc) + RX_ALIGN)
  525. /* rtl8152 flags */
  526. enum rtl8152_flags {
  527. RTL8152_UNPLUG = 0,
  528. RTL8152_SET_RX_MODE,
  529. WORK_ENABLE,
  530. RTL8152_LINK_CHG,
  531. SELECTIVE_SUSPEND,
  532. PHY_RESET,
  533. SCHEDULE_TASKLET,
  534. GREEN_ETHERNET,
  535. DELL_TB_RX_AGG_BUG,
  536. };
  537. /* Define these values to match your device */
  538. #define VENDOR_ID_REALTEK 0x0bda
  539. #define VENDOR_ID_MICROSOFT 0x045e
  540. #define VENDOR_ID_SAMSUNG 0x04e8
  541. #define VENDOR_ID_LENOVO 0x17ef
  542. #define VENDOR_ID_LINKSYS 0x13b1
  543. #define VENDOR_ID_NVIDIA 0x0955
  544. #define VENDOR_ID_TPLINK 0x2357
  545. #define MCU_TYPE_PLA 0x0100
  546. #define MCU_TYPE_USB 0x0000
  547. struct tally_counter {
  548. __le64 tx_packets;
  549. __le64 rx_packets;
  550. __le64 tx_errors;
  551. __le32 rx_errors;
  552. __le16 rx_missed;
  553. __le16 align_errors;
  554. __le32 tx_one_collision;
  555. __le32 tx_multi_collision;
  556. __le64 rx_unicast;
  557. __le64 rx_broadcast;
  558. __le32 rx_multicast;
  559. __le16 tx_aborted;
  560. __le16 tx_underrun;
  561. };
  562. struct rx_desc {
  563. __le32 opts1;
  564. #define RX_LEN_MASK 0x7fff
  565. __le32 opts2;
  566. #define RD_UDP_CS BIT(23)
  567. #define RD_TCP_CS BIT(22)
  568. #define RD_IPV6_CS BIT(20)
  569. #define RD_IPV4_CS BIT(19)
  570. __le32 opts3;
  571. #define IPF BIT(23) /* IP checksum fail */
  572. #define UDPF BIT(22) /* UDP checksum fail */
  573. #define TCPF BIT(21) /* TCP checksum fail */
  574. #define RX_VLAN_TAG BIT(16)
  575. __le32 opts4;
  576. __le32 opts5;
  577. __le32 opts6;
  578. };
  579. struct tx_desc {
  580. __le32 opts1;
  581. #define TX_FS BIT(31) /* First segment of a packet */
  582. #define TX_LS BIT(30) /* Final segment of a packet */
  583. #define GTSENDV4 BIT(28)
  584. #define GTSENDV6 BIT(27)
  585. #define GTTCPHO_SHIFT 18
  586. #define GTTCPHO_MAX 0x7fU
  587. #define TX_LEN_MAX 0x3ffffU
  588. __le32 opts2;
  589. #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
  590. #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
  591. #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
  592. #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
  593. #define MSS_SHIFT 17
  594. #define MSS_MAX 0x7ffU
  595. #define TCPHO_SHIFT 17
  596. #define TCPHO_MAX 0x7ffU
  597. #define TX_VLAN_TAG BIT(16)
  598. };
  599. struct r8152;
  600. struct rx_agg {
  601. struct list_head list, info_list;
  602. struct urb *urb;
  603. struct r8152 *context;
  604. struct page *page;
  605. void *buffer;
  606. };
  607. struct tx_agg {
  608. struct list_head list;
  609. struct urb *urb;
  610. struct r8152 *context;
  611. void *buffer;
  612. void *head;
  613. u32 skb_num;
  614. u32 skb_len;
  615. };
  616. struct r8152 {
  617. unsigned long flags;
  618. struct usb_device *udev;
  619. struct napi_struct napi;
  620. struct usb_interface *intf;
  621. struct net_device *netdev;
  622. struct urb *intr_urb;
  623. struct tx_agg tx_info[RTL8152_MAX_TX];
  624. struct list_head rx_info, rx_used;
  625. struct list_head rx_done, tx_free;
  626. struct sk_buff_head tx_queue, rx_queue;
  627. spinlock_t rx_lock, tx_lock;
  628. struct delayed_work schedule, hw_phy_work;
  629. struct mii_if_info mii;
  630. struct mutex control; /* use for hw setting */
  631. #ifdef CONFIG_PM_SLEEP
  632. struct notifier_block pm_notifier;
  633. #endif
  634. struct tasklet_struct tx_tl;
  635. struct rtl_ops {
  636. void (*init)(struct r8152 *);
  637. int (*enable)(struct r8152 *);
  638. void (*disable)(struct r8152 *);
  639. void (*up)(struct r8152 *);
  640. void (*down)(struct r8152 *);
  641. void (*unload)(struct r8152 *);
  642. int (*eee_get)(struct r8152 *, struct ethtool_eee *);
  643. int (*eee_set)(struct r8152 *, struct ethtool_eee *);
  644. bool (*in_nway)(struct r8152 *);
  645. void (*hw_phy_cfg)(struct r8152 *);
  646. void (*autosuspend_en)(struct r8152 *tp, bool enable);
  647. } rtl_ops;
  648. struct ups_info {
  649. u32 _10m_ckdiv:1;
  650. u32 _250m_ckdiv:1;
  651. u32 aldps:1;
  652. u32 lite_mode:2;
  653. u32 speed_duplex:4;
  654. u32 eee:1;
  655. u32 eee_lite:1;
  656. u32 eee_ckdiv:1;
  657. u32 eee_plloff_100:1;
  658. u32 eee_plloff_giga:1;
  659. u32 eee_cmod_lv:1;
  660. u32 green:1;
  661. u32 flow_control:1;
  662. u32 ctap_short_off:1;
  663. } ups_info;
  664. atomic_t rx_count;
  665. bool eee_en;
  666. int intr_interval;
  667. u32 saved_wolopts;
  668. u32 msg_enable;
  669. u32 tx_qlen;
  670. u32 coalesce;
  671. u32 advertising;
  672. u32 rx_buf_sz;
  673. u32 rx_copybreak;
  674. u32 rx_pending;
  675. u16 ocp_base;
  676. u16 speed;
  677. u16 eee_adv;
  678. u8 *intr_buff;
  679. u8 version;
  680. u8 duplex;
  681. u8 autoneg;
  682. };
  683. enum rtl_version {
  684. RTL_VER_UNKNOWN = 0,
  685. RTL_VER_01,
  686. RTL_VER_02,
  687. RTL_VER_03,
  688. RTL_VER_04,
  689. RTL_VER_05,
  690. RTL_VER_06,
  691. RTL_VER_07,
  692. RTL_VER_08,
  693. RTL_VER_09,
  694. RTL_VER_MAX
  695. };
  696. enum tx_csum_stat {
  697. TX_CSUM_SUCCESS = 0,
  698. TX_CSUM_TSO,
  699. TX_CSUM_NONE
  700. };
  701. #define RTL_ADVERTISED_10_HALF BIT(0)
  702. #define RTL_ADVERTISED_10_FULL BIT(1)
  703. #define RTL_ADVERTISED_100_HALF BIT(2)
  704. #define RTL_ADVERTISED_100_FULL BIT(3)
  705. #define RTL_ADVERTISED_1000_HALF BIT(4)
  706. #define RTL_ADVERTISED_1000_FULL BIT(5)
  707. /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  708. * The RTL chips use a 64 element hash table based on the Ethernet CRC.
  709. */
  710. static const int multicast_filter_limit = 32;
  711. static unsigned int agg_buf_sz = 16384;
  712. #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \
  713. VLAN_ETH_HLEN - ETH_FCS_LEN)
  714. static
  715. int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
  716. {
  717. int ret;
  718. void *tmp;
  719. tmp = kmalloc(size, GFP_KERNEL);
  720. if (!tmp)
  721. return -ENOMEM;
  722. ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
  723. RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
  724. value, index, tmp, size, 500);
  725. if (ret < 0)
  726. memset(data, 0xff, size);
  727. else
  728. memcpy(data, tmp, size);
  729. kfree(tmp);
  730. return ret;
  731. }
  732. static
  733. int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
  734. {
  735. int ret;
  736. void *tmp;
  737. tmp = kmemdup(data, size, GFP_KERNEL);
  738. if (!tmp)
  739. return -ENOMEM;
  740. ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
  741. RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
  742. value, index, tmp, size, 500);
  743. kfree(tmp);
  744. return ret;
  745. }
  746. static void rtl_set_unplug(struct r8152 *tp)
  747. {
  748. if (tp->udev->state == USB_STATE_NOTATTACHED) {
  749. set_bit(RTL8152_UNPLUG, &tp->flags);
  750. smp_mb__after_atomic();
  751. }
  752. }
  753. static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
  754. void *data, u16 type)
  755. {
  756. u16 limit = 64;
  757. int ret = 0;
  758. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  759. return -ENODEV;
  760. /* both size and indix must be 4 bytes align */
  761. if ((size & 3) || !size || (index & 3) || !data)
  762. return -EPERM;
  763. if ((u32)index + (u32)size > 0xffff)
  764. return -EPERM;
  765. while (size) {
  766. if (size > limit) {
  767. ret = get_registers(tp, index, type, limit, data);
  768. if (ret < 0)
  769. break;
  770. index += limit;
  771. data += limit;
  772. size -= limit;
  773. } else {
  774. ret = get_registers(tp, index, type, size, data);
  775. if (ret < 0)
  776. break;
  777. index += size;
  778. data += size;
  779. size = 0;
  780. break;
  781. }
  782. }
  783. if (ret == -ENODEV)
  784. rtl_set_unplug(tp);
  785. return ret;
  786. }
  787. static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
  788. u16 size, void *data, u16 type)
  789. {
  790. int ret;
  791. u16 byteen_start, byteen_end, byen;
  792. u16 limit = 512;
  793. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  794. return -ENODEV;
  795. /* both size and indix must be 4 bytes align */
  796. if ((size & 3) || !size || (index & 3) || !data)
  797. return -EPERM;
  798. if ((u32)index + (u32)size > 0xffff)
  799. return -EPERM;
  800. byteen_start = byteen & BYTE_EN_START_MASK;
  801. byteen_end = byteen & BYTE_EN_END_MASK;
  802. byen = byteen_start | (byteen_start << 4);
  803. ret = set_registers(tp, index, type | byen, 4, data);
  804. if (ret < 0)
  805. goto error1;
  806. index += 4;
  807. data += 4;
  808. size -= 4;
  809. if (size) {
  810. size -= 4;
  811. while (size) {
  812. if (size > limit) {
  813. ret = set_registers(tp, index,
  814. type | BYTE_EN_DWORD,
  815. limit, data);
  816. if (ret < 0)
  817. goto error1;
  818. index += limit;
  819. data += limit;
  820. size -= limit;
  821. } else {
  822. ret = set_registers(tp, index,
  823. type | BYTE_EN_DWORD,
  824. size, data);
  825. if (ret < 0)
  826. goto error1;
  827. index += size;
  828. data += size;
  829. size = 0;
  830. break;
  831. }
  832. }
  833. byen = byteen_end | (byteen_end >> 4);
  834. ret = set_registers(tp, index, type | byen, 4, data);
  835. if (ret < 0)
  836. goto error1;
  837. }
  838. error1:
  839. if (ret == -ENODEV)
  840. rtl_set_unplug(tp);
  841. return ret;
  842. }
  843. static inline
  844. int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
  845. {
  846. return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
  847. }
  848. static inline
  849. int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
  850. {
  851. return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
  852. }
  853. static inline
  854. int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
  855. {
  856. return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
  857. }
  858. static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
  859. {
  860. __le32 data;
  861. generic_ocp_read(tp, index, sizeof(data), &data, type);
  862. return __le32_to_cpu(data);
  863. }
  864. static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
  865. {
  866. __le32 tmp = __cpu_to_le32(data);
  867. generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
  868. }
  869. static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
  870. {
  871. u32 data;
  872. __le32 tmp;
  873. u16 byen = BYTE_EN_WORD;
  874. u8 shift = index & 2;
  875. index &= ~3;
  876. byen <<= shift;
  877. generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen);
  878. data = __le32_to_cpu(tmp);
  879. data >>= (shift * 8);
  880. data &= 0xffff;
  881. return (u16)data;
  882. }
  883. static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
  884. {
  885. u32 mask = 0xffff;
  886. __le32 tmp;
  887. u16 byen = BYTE_EN_WORD;
  888. u8 shift = index & 2;
  889. data &= mask;
  890. if (index & 2) {
  891. byen <<= shift;
  892. mask <<= (shift * 8);
  893. data <<= (shift * 8);
  894. index &= ~3;
  895. }
  896. tmp = __cpu_to_le32(data);
  897. generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
  898. }
  899. static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
  900. {
  901. u32 data;
  902. __le32 tmp;
  903. u8 shift = index & 3;
  904. index &= ~3;
  905. generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
  906. data = __le32_to_cpu(tmp);
  907. data >>= (shift * 8);
  908. data &= 0xff;
  909. return (u8)data;
  910. }
  911. static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
  912. {
  913. u32 mask = 0xff;
  914. __le32 tmp;
  915. u16 byen = BYTE_EN_BYTE;
  916. u8 shift = index & 3;
  917. data &= mask;
  918. if (index & 3) {
  919. byen <<= shift;
  920. mask <<= (shift * 8);
  921. data <<= (shift * 8);
  922. index &= ~3;
  923. }
  924. tmp = __cpu_to_le32(data);
  925. generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
  926. }
  927. static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
  928. {
  929. u16 ocp_base, ocp_index;
  930. ocp_base = addr & 0xf000;
  931. if (ocp_base != tp->ocp_base) {
  932. ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
  933. tp->ocp_base = ocp_base;
  934. }
  935. ocp_index = (addr & 0x0fff) | 0xb000;
  936. return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
  937. }
  938. static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
  939. {
  940. u16 ocp_base, ocp_index;
  941. ocp_base = addr & 0xf000;
  942. if (ocp_base != tp->ocp_base) {
  943. ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
  944. tp->ocp_base = ocp_base;
  945. }
  946. ocp_index = (addr & 0x0fff) | 0xb000;
  947. ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
  948. }
  949. static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
  950. {
  951. ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
  952. }
  953. static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
  954. {
  955. return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
  956. }
  957. static void sram_write(struct r8152 *tp, u16 addr, u16 data)
  958. {
  959. ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
  960. ocp_reg_write(tp, OCP_SRAM_DATA, data);
  961. }
  962. static u16 sram_read(struct r8152 *tp, u16 addr)
  963. {
  964. ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
  965. return ocp_reg_read(tp, OCP_SRAM_DATA);
  966. }
  967. static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
  968. {
  969. struct r8152 *tp = netdev_priv(netdev);
  970. int ret;
  971. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  972. return -ENODEV;
  973. if (phy_id != R8152_PHY_ID)
  974. return -EINVAL;
  975. ret = r8152_mdio_read(tp, reg);
  976. return ret;
  977. }
  978. static
  979. void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
  980. {
  981. struct r8152 *tp = netdev_priv(netdev);
  982. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  983. return;
  984. if (phy_id != R8152_PHY_ID)
  985. return;
  986. r8152_mdio_write(tp, reg, val);
  987. }
  988. static int
  989. r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
  990. static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
  991. {
  992. struct r8152 *tp = netdev_priv(netdev);
  993. struct sockaddr *addr = p;
  994. int ret = -EADDRNOTAVAIL;
  995. if (!is_valid_ether_addr(addr->sa_data))
  996. goto out1;
  997. ret = usb_autopm_get_interface(tp->intf);
  998. if (ret < 0)
  999. goto out1;
  1000. mutex_lock(&tp->control);
  1001. memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
  1002. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  1003. pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
  1004. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  1005. mutex_unlock(&tp->control);
  1006. usb_autopm_put_interface(tp->intf);
  1007. out1:
  1008. return ret;
  1009. }
  1010. /* Devices containing proper chips can support a persistent
  1011. * host system provided MAC address.
  1012. * Examples of this are Dell TB15 and Dell WD15 docks
  1013. */
  1014. static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
  1015. {
  1016. acpi_status status;
  1017. struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
  1018. union acpi_object *obj;
  1019. int ret = -EINVAL;
  1020. u32 ocp_data;
  1021. unsigned char buf[6];
  1022. /* test for -AD variant of RTL8153 */
  1023. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
  1024. if ((ocp_data & AD_MASK) == 0x1000) {
  1025. /* test for MAC address pass-through bit */
  1026. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
  1027. if ((ocp_data & PASS_THRU_MASK) != 1) {
  1028. netif_dbg(tp, probe, tp->netdev,
  1029. "No efuse for RTL8153-AD MAC pass through\n");
  1030. return -ENODEV;
  1031. }
  1032. } else {
  1033. /* test for RTL8153-BND and RTL8153-BD */
  1034. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
  1035. if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) {
  1036. netif_dbg(tp, probe, tp->netdev,
  1037. "Invalid variant for MAC pass through\n");
  1038. return -ENODEV;
  1039. }
  1040. }
  1041. /* returns _AUXMAC_#AABBCCDDEEFF# */
  1042. status = acpi_evaluate_object(NULL, "\\_SB.AMAC", NULL, &buffer);
  1043. obj = (union acpi_object *)buffer.pointer;
  1044. if (!ACPI_SUCCESS(status))
  1045. return -ENODEV;
  1046. if (obj->type != ACPI_TYPE_BUFFER || obj->string.length != 0x17) {
  1047. netif_warn(tp, probe, tp->netdev,
  1048. "Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
  1049. obj->type, obj->string.length);
  1050. goto amacout;
  1051. }
  1052. if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
  1053. strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
  1054. netif_warn(tp, probe, tp->netdev,
  1055. "Invalid header when reading pass-thru MAC addr\n");
  1056. goto amacout;
  1057. }
  1058. ret = hex2bin(buf, obj->string.pointer + 9, 6);
  1059. if (!(ret == 0 && is_valid_ether_addr(buf))) {
  1060. netif_warn(tp, probe, tp->netdev,
  1061. "Invalid MAC for pass-thru MAC addr: %d, %pM\n",
  1062. ret, buf);
  1063. ret = -EINVAL;
  1064. goto amacout;
  1065. }
  1066. memcpy(sa->sa_data, buf, 6);
  1067. netif_info(tp, probe, tp->netdev,
  1068. "Using pass-thru MAC addr %pM\n", sa->sa_data);
  1069. amacout:
  1070. kfree(obj);
  1071. return ret;
  1072. }
  1073. static int determine_ethernet_addr(struct r8152 *tp, struct sockaddr *sa)
  1074. {
  1075. struct net_device *dev = tp->netdev;
  1076. int ret;
  1077. sa->sa_family = dev->type;
  1078. if (tp->version == RTL_VER_01) {
  1079. ret = pla_ocp_read(tp, PLA_IDR, 8, sa->sa_data);
  1080. } else {
  1081. /* if device doesn't support MAC pass through this will
  1082. * be expected to be non-zero
  1083. */
  1084. ret = vendor_mac_passthru_addr_read(tp, sa);
  1085. if (ret < 0)
  1086. ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa->sa_data);
  1087. }
  1088. if (ret < 0) {
  1089. netif_err(tp, probe, dev, "Get ether addr fail\n");
  1090. } else if (!is_valid_ether_addr(sa->sa_data)) {
  1091. netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
  1092. sa->sa_data);
  1093. eth_hw_addr_random(dev);
  1094. ether_addr_copy(sa->sa_data, dev->dev_addr);
  1095. netif_info(tp, probe, dev, "Random ether addr %pM\n",
  1096. sa->sa_data);
  1097. return 0;
  1098. }
  1099. return ret;
  1100. }
  1101. static int set_ethernet_addr(struct r8152 *tp)
  1102. {
  1103. struct net_device *dev = tp->netdev;
  1104. struct sockaddr sa;
  1105. int ret;
  1106. ret = determine_ethernet_addr(tp, &sa);
  1107. if (ret < 0)
  1108. return ret;
  1109. if (tp->version == RTL_VER_01)
  1110. ether_addr_copy(dev->dev_addr, sa.sa_data);
  1111. else
  1112. ret = rtl8152_set_mac_address(dev, &sa);
  1113. return ret;
  1114. }
  1115. static void read_bulk_callback(struct urb *urb)
  1116. {
  1117. struct net_device *netdev;
  1118. int status = urb->status;
  1119. struct rx_agg *agg;
  1120. struct r8152 *tp;
  1121. unsigned long flags;
  1122. agg = urb->context;
  1123. if (!agg)
  1124. return;
  1125. tp = agg->context;
  1126. if (!tp)
  1127. return;
  1128. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1129. return;
  1130. if (!test_bit(WORK_ENABLE, &tp->flags))
  1131. return;
  1132. netdev = tp->netdev;
  1133. /* When link down, the driver would cancel all bulks. */
  1134. /* This avoid the re-submitting bulk */
  1135. if (!netif_carrier_ok(netdev))
  1136. return;
  1137. usb_mark_last_busy(tp->udev);
  1138. switch (status) {
  1139. case 0:
  1140. if (urb->actual_length < ETH_ZLEN)
  1141. break;
  1142. spin_lock_irqsave(&tp->rx_lock, flags);
  1143. list_add_tail(&agg->list, &tp->rx_done);
  1144. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1145. napi_schedule(&tp->napi);
  1146. return;
  1147. case -ESHUTDOWN:
  1148. rtl_set_unplug(tp);
  1149. netif_device_detach(tp->netdev);
  1150. return;
  1151. case -ENOENT:
  1152. return; /* the urb is in unlink state */
  1153. case -ETIME:
  1154. if (net_ratelimit())
  1155. netdev_warn(netdev, "maybe reset is needed?\n");
  1156. break;
  1157. default:
  1158. if (net_ratelimit())
  1159. netdev_warn(netdev, "Rx status %d\n", status);
  1160. break;
  1161. }
  1162. r8152_submit_rx(tp, agg, GFP_ATOMIC);
  1163. }
  1164. static void write_bulk_callback(struct urb *urb)
  1165. {
  1166. struct net_device_stats *stats;
  1167. struct net_device *netdev;
  1168. struct tx_agg *agg;
  1169. struct r8152 *tp;
  1170. unsigned long flags;
  1171. int status = urb->status;
  1172. agg = urb->context;
  1173. if (!agg)
  1174. return;
  1175. tp = agg->context;
  1176. if (!tp)
  1177. return;
  1178. netdev = tp->netdev;
  1179. stats = &netdev->stats;
  1180. if (status) {
  1181. if (net_ratelimit())
  1182. netdev_warn(netdev, "Tx status %d\n", status);
  1183. stats->tx_errors += agg->skb_num;
  1184. } else {
  1185. stats->tx_packets += agg->skb_num;
  1186. stats->tx_bytes += agg->skb_len;
  1187. }
  1188. spin_lock_irqsave(&tp->tx_lock, flags);
  1189. list_add_tail(&agg->list, &tp->tx_free);
  1190. spin_unlock_irqrestore(&tp->tx_lock, flags);
  1191. usb_autopm_put_interface_async(tp->intf);
  1192. if (!netif_carrier_ok(netdev))
  1193. return;
  1194. if (!test_bit(WORK_ENABLE, &tp->flags))
  1195. return;
  1196. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1197. return;
  1198. if (!skb_queue_empty(&tp->tx_queue))
  1199. tasklet_schedule(&tp->tx_tl);
  1200. }
  1201. static void intr_callback(struct urb *urb)
  1202. {
  1203. struct r8152 *tp;
  1204. __le16 *d;
  1205. int status = urb->status;
  1206. int res;
  1207. tp = urb->context;
  1208. if (!tp)
  1209. return;
  1210. if (!test_bit(WORK_ENABLE, &tp->flags))
  1211. return;
  1212. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1213. return;
  1214. switch (status) {
  1215. case 0: /* success */
  1216. break;
  1217. case -ECONNRESET: /* unlink */
  1218. case -ESHUTDOWN:
  1219. netif_device_detach(tp->netdev);
  1220. /* fall through */
  1221. case -ENOENT:
  1222. case -EPROTO:
  1223. netif_info(tp, intr, tp->netdev,
  1224. "Stop submitting intr, status %d\n", status);
  1225. return;
  1226. case -EOVERFLOW:
  1227. netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
  1228. goto resubmit;
  1229. /* -EPIPE: should clear the halt */
  1230. default:
  1231. netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
  1232. goto resubmit;
  1233. }
  1234. d = urb->transfer_buffer;
  1235. if (INTR_LINK & __le16_to_cpu(d[0])) {
  1236. if (!netif_carrier_ok(tp->netdev)) {
  1237. set_bit(RTL8152_LINK_CHG, &tp->flags);
  1238. schedule_delayed_work(&tp->schedule, 0);
  1239. }
  1240. } else {
  1241. if (netif_carrier_ok(tp->netdev)) {
  1242. netif_stop_queue(tp->netdev);
  1243. set_bit(RTL8152_LINK_CHG, &tp->flags);
  1244. schedule_delayed_work(&tp->schedule, 0);
  1245. }
  1246. }
  1247. resubmit:
  1248. res = usb_submit_urb(urb, GFP_ATOMIC);
  1249. if (res == -ENODEV) {
  1250. rtl_set_unplug(tp);
  1251. netif_device_detach(tp->netdev);
  1252. } else if (res) {
  1253. netif_err(tp, intr, tp->netdev,
  1254. "can't resubmit intr, status %d\n", res);
  1255. }
  1256. }
  1257. static inline void *rx_agg_align(void *data)
  1258. {
  1259. return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
  1260. }
  1261. static inline void *tx_agg_align(void *data)
  1262. {
  1263. return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
  1264. }
  1265. static void free_rx_agg(struct r8152 *tp, struct rx_agg *agg)
  1266. {
  1267. list_del(&agg->info_list);
  1268. usb_free_urb(agg->urb);
  1269. put_page(agg->page);
  1270. kfree(agg);
  1271. atomic_dec(&tp->rx_count);
  1272. }
  1273. static struct rx_agg *alloc_rx_agg(struct r8152 *tp, gfp_t mflags)
  1274. {
  1275. struct net_device *netdev = tp->netdev;
  1276. int node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
  1277. unsigned int order = get_order(tp->rx_buf_sz);
  1278. struct rx_agg *rx_agg;
  1279. unsigned long flags;
  1280. rx_agg = kmalloc_node(sizeof(*rx_agg), mflags, node);
  1281. if (!rx_agg)
  1282. return NULL;
  1283. rx_agg->page = alloc_pages(mflags | __GFP_COMP, order);
  1284. if (!rx_agg->page)
  1285. goto free_rx;
  1286. rx_agg->buffer = page_address(rx_agg->page);
  1287. rx_agg->urb = usb_alloc_urb(0, mflags);
  1288. if (!rx_agg->urb)
  1289. goto free_buf;
  1290. rx_agg->context = tp;
  1291. INIT_LIST_HEAD(&rx_agg->list);
  1292. INIT_LIST_HEAD(&rx_agg->info_list);
  1293. spin_lock_irqsave(&tp->rx_lock, flags);
  1294. list_add_tail(&rx_agg->info_list, &tp->rx_info);
  1295. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1296. atomic_inc(&tp->rx_count);
  1297. return rx_agg;
  1298. free_buf:
  1299. __free_pages(rx_agg->page, order);
  1300. free_rx:
  1301. kfree(rx_agg);
  1302. return NULL;
  1303. }
  1304. static void free_all_mem(struct r8152 *tp)
  1305. {
  1306. struct rx_agg *agg, *agg_next;
  1307. unsigned long flags;
  1308. int i;
  1309. spin_lock_irqsave(&tp->rx_lock, flags);
  1310. list_for_each_entry_safe(agg, agg_next, &tp->rx_info, info_list)
  1311. free_rx_agg(tp, agg);
  1312. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1313. WARN_ON(atomic_read(&tp->rx_count));
  1314. for (i = 0; i < RTL8152_MAX_TX; i++) {
  1315. usb_free_urb(tp->tx_info[i].urb);
  1316. tp->tx_info[i].urb = NULL;
  1317. kfree(tp->tx_info[i].buffer);
  1318. tp->tx_info[i].buffer = NULL;
  1319. tp->tx_info[i].head = NULL;
  1320. }
  1321. usb_free_urb(tp->intr_urb);
  1322. tp->intr_urb = NULL;
  1323. kfree(tp->intr_buff);
  1324. tp->intr_buff = NULL;
  1325. }
  1326. static int alloc_all_mem(struct r8152 *tp)
  1327. {
  1328. struct net_device *netdev = tp->netdev;
  1329. struct usb_interface *intf = tp->intf;
  1330. struct usb_host_interface *alt = intf->cur_altsetting;
  1331. struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
  1332. int node, i;
  1333. node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
  1334. spin_lock_init(&tp->rx_lock);
  1335. spin_lock_init(&tp->tx_lock);
  1336. INIT_LIST_HEAD(&tp->rx_info);
  1337. INIT_LIST_HEAD(&tp->tx_free);
  1338. INIT_LIST_HEAD(&tp->rx_done);
  1339. skb_queue_head_init(&tp->tx_queue);
  1340. skb_queue_head_init(&tp->rx_queue);
  1341. atomic_set(&tp->rx_count, 0);
  1342. for (i = 0; i < RTL8152_MAX_RX; i++) {
  1343. if (!alloc_rx_agg(tp, GFP_KERNEL))
  1344. goto err1;
  1345. }
  1346. for (i = 0; i < RTL8152_MAX_TX; i++) {
  1347. struct urb *urb;
  1348. u8 *buf;
  1349. buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
  1350. if (!buf)
  1351. goto err1;
  1352. if (buf != tx_agg_align(buf)) {
  1353. kfree(buf);
  1354. buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
  1355. node);
  1356. if (!buf)
  1357. goto err1;
  1358. }
  1359. urb = usb_alloc_urb(0, GFP_KERNEL);
  1360. if (!urb) {
  1361. kfree(buf);
  1362. goto err1;
  1363. }
  1364. INIT_LIST_HEAD(&tp->tx_info[i].list);
  1365. tp->tx_info[i].context = tp;
  1366. tp->tx_info[i].urb = urb;
  1367. tp->tx_info[i].buffer = buf;
  1368. tp->tx_info[i].head = tx_agg_align(buf);
  1369. list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
  1370. }
  1371. tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
  1372. if (!tp->intr_urb)
  1373. goto err1;
  1374. tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
  1375. if (!tp->intr_buff)
  1376. goto err1;
  1377. tp->intr_interval = (int)ep_intr->desc.bInterval;
  1378. usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
  1379. tp->intr_buff, INTBUFSIZE, intr_callback,
  1380. tp, tp->intr_interval);
  1381. return 0;
  1382. err1:
  1383. free_all_mem(tp);
  1384. return -ENOMEM;
  1385. }
  1386. static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
  1387. {
  1388. struct tx_agg *agg = NULL;
  1389. unsigned long flags;
  1390. if (list_empty(&tp->tx_free))
  1391. return NULL;
  1392. spin_lock_irqsave(&tp->tx_lock, flags);
  1393. if (!list_empty(&tp->tx_free)) {
  1394. struct list_head *cursor;
  1395. cursor = tp->tx_free.next;
  1396. list_del_init(cursor);
  1397. agg = list_entry(cursor, struct tx_agg, list);
  1398. }
  1399. spin_unlock_irqrestore(&tp->tx_lock, flags);
  1400. return agg;
  1401. }
  1402. /* r8152_csum_workaround()
  1403. * The hw limites the value the transport offset. When the offset is out of the
  1404. * range, calculate the checksum by sw.
  1405. */
  1406. static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
  1407. struct sk_buff_head *list)
  1408. {
  1409. if (skb_shinfo(skb)->gso_size) {
  1410. netdev_features_t features = tp->netdev->features;
  1411. struct sk_buff_head seg_list;
  1412. struct sk_buff *segs, *nskb;
  1413. features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
  1414. segs = skb_gso_segment(skb, features);
  1415. if (IS_ERR(segs) || !segs)
  1416. goto drop;
  1417. __skb_queue_head_init(&seg_list);
  1418. do {
  1419. nskb = segs;
  1420. segs = segs->next;
  1421. nskb->next = NULL;
  1422. __skb_queue_tail(&seg_list, nskb);
  1423. } while (segs);
  1424. skb_queue_splice(&seg_list, list);
  1425. dev_kfree_skb(skb);
  1426. } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
  1427. if (skb_checksum_help(skb) < 0)
  1428. goto drop;
  1429. __skb_queue_head(list, skb);
  1430. } else {
  1431. struct net_device_stats *stats;
  1432. drop:
  1433. stats = &tp->netdev->stats;
  1434. stats->tx_dropped++;
  1435. dev_kfree_skb(skb);
  1436. }
  1437. }
  1438. /* msdn_giant_send_check()
  1439. * According to the document of microsoft, the TCP Pseudo Header excludes the
  1440. * packet length for IPv6 TCP large packets.
  1441. */
  1442. static int msdn_giant_send_check(struct sk_buff *skb)
  1443. {
  1444. const struct ipv6hdr *ipv6h;
  1445. struct tcphdr *th;
  1446. int ret;
  1447. ret = skb_cow_head(skb, 0);
  1448. if (ret)
  1449. return ret;
  1450. ipv6h = ipv6_hdr(skb);
  1451. th = tcp_hdr(skb);
  1452. th->check = 0;
  1453. th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
  1454. return ret;
  1455. }
  1456. static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
  1457. {
  1458. if (skb_vlan_tag_present(skb)) {
  1459. u32 opts2;
  1460. opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
  1461. desc->opts2 |= cpu_to_le32(opts2);
  1462. }
  1463. }
  1464. static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
  1465. {
  1466. u32 opts2 = le32_to_cpu(desc->opts2);
  1467. if (opts2 & RX_VLAN_TAG)
  1468. __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
  1469. swab16(opts2 & 0xffff));
  1470. }
  1471. static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
  1472. struct sk_buff *skb, u32 len, u32 transport_offset)
  1473. {
  1474. u32 mss = skb_shinfo(skb)->gso_size;
  1475. u32 opts1, opts2 = 0;
  1476. int ret = TX_CSUM_SUCCESS;
  1477. WARN_ON_ONCE(len > TX_LEN_MAX);
  1478. opts1 = len | TX_FS | TX_LS;
  1479. if (mss) {
  1480. if (transport_offset > GTTCPHO_MAX) {
  1481. netif_warn(tp, tx_err, tp->netdev,
  1482. "Invalid transport offset 0x%x for TSO\n",
  1483. transport_offset);
  1484. ret = TX_CSUM_TSO;
  1485. goto unavailable;
  1486. }
  1487. switch (vlan_get_protocol(skb)) {
  1488. case htons(ETH_P_IP):
  1489. opts1 |= GTSENDV4;
  1490. break;
  1491. case htons(ETH_P_IPV6):
  1492. if (msdn_giant_send_check(skb)) {
  1493. ret = TX_CSUM_TSO;
  1494. goto unavailable;
  1495. }
  1496. opts1 |= GTSENDV6;
  1497. break;
  1498. default:
  1499. WARN_ON_ONCE(1);
  1500. break;
  1501. }
  1502. opts1 |= transport_offset << GTTCPHO_SHIFT;
  1503. opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
  1504. } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
  1505. u8 ip_protocol;
  1506. if (transport_offset > TCPHO_MAX) {
  1507. netif_warn(tp, tx_err, tp->netdev,
  1508. "Invalid transport offset 0x%x\n",
  1509. transport_offset);
  1510. ret = TX_CSUM_NONE;
  1511. goto unavailable;
  1512. }
  1513. switch (vlan_get_protocol(skb)) {
  1514. case htons(ETH_P_IP):
  1515. opts2 |= IPV4_CS;
  1516. ip_protocol = ip_hdr(skb)->protocol;
  1517. break;
  1518. case htons(ETH_P_IPV6):
  1519. opts2 |= IPV6_CS;
  1520. ip_protocol = ipv6_hdr(skb)->nexthdr;
  1521. break;
  1522. default:
  1523. ip_protocol = IPPROTO_RAW;
  1524. break;
  1525. }
  1526. if (ip_protocol == IPPROTO_TCP)
  1527. opts2 |= TCP_CS;
  1528. else if (ip_protocol == IPPROTO_UDP)
  1529. opts2 |= UDP_CS;
  1530. else
  1531. WARN_ON_ONCE(1);
  1532. opts2 |= transport_offset << TCPHO_SHIFT;
  1533. }
  1534. desc->opts2 = cpu_to_le32(opts2);
  1535. desc->opts1 = cpu_to_le32(opts1);
  1536. unavailable:
  1537. return ret;
  1538. }
  1539. static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
  1540. {
  1541. struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
  1542. int remain, ret;
  1543. u8 *tx_data;
  1544. __skb_queue_head_init(&skb_head);
  1545. spin_lock(&tx_queue->lock);
  1546. skb_queue_splice_init(tx_queue, &skb_head);
  1547. spin_unlock(&tx_queue->lock);
  1548. tx_data = agg->head;
  1549. agg->skb_num = 0;
  1550. agg->skb_len = 0;
  1551. remain = agg_buf_sz;
  1552. while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
  1553. struct tx_desc *tx_desc;
  1554. struct sk_buff *skb;
  1555. unsigned int len;
  1556. u32 offset;
  1557. skb = __skb_dequeue(&skb_head);
  1558. if (!skb)
  1559. break;
  1560. len = skb->len + sizeof(*tx_desc);
  1561. if (len > remain) {
  1562. __skb_queue_head(&skb_head, skb);
  1563. break;
  1564. }
  1565. tx_data = tx_agg_align(tx_data);
  1566. tx_desc = (struct tx_desc *)tx_data;
  1567. offset = (u32)skb_transport_offset(skb);
  1568. if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
  1569. r8152_csum_workaround(tp, skb, &skb_head);
  1570. continue;
  1571. }
  1572. rtl_tx_vlan_tag(tx_desc, skb);
  1573. tx_data += sizeof(*tx_desc);
  1574. len = skb->len;
  1575. if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
  1576. struct net_device_stats *stats = &tp->netdev->stats;
  1577. stats->tx_dropped++;
  1578. dev_kfree_skb_any(skb);
  1579. tx_data -= sizeof(*tx_desc);
  1580. continue;
  1581. }
  1582. tx_data += len;
  1583. agg->skb_len += len;
  1584. agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1;
  1585. dev_kfree_skb_any(skb);
  1586. remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
  1587. if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
  1588. break;
  1589. }
  1590. if (!skb_queue_empty(&skb_head)) {
  1591. spin_lock(&tx_queue->lock);
  1592. skb_queue_splice(&skb_head, tx_queue);
  1593. spin_unlock(&tx_queue->lock);
  1594. }
  1595. netif_tx_lock(tp->netdev);
  1596. if (netif_queue_stopped(tp->netdev) &&
  1597. skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
  1598. netif_wake_queue(tp->netdev);
  1599. netif_tx_unlock(tp->netdev);
  1600. ret = usb_autopm_get_interface_async(tp->intf);
  1601. if (ret < 0)
  1602. goto out_tx_fill;
  1603. usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
  1604. agg->head, (int)(tx_data - (u8 *)agg->head),
  1605. (usb_complete_t)write_bulk_callback, agg);
  1606. ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
  1607. if (ret < 0)
  1608. usb_autopm_put_interface_async(tp->intf);
  1609. out_tx_fill:
  1610. return ret;
  1611. }
  1612. static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
  1613. {
  1614. u8 checksum = CHECKSUM_NONE;
  1615. u32 opts2, opts3;
  1616. if (!(tp->netdev->features & NETIF_F_RXCSUM))
  1617. goto return_result;
  1618. opts2 = le32_to_cpu(rx_desc->opts2);
  1619. opts3 = le32_to_cpu(rx_desc->opts3);
  1620. if (opts2 & RD_IPV4_CS) {
  1621. if (opts3 & IPF)
  1622. checksum = CHECKSUM_NONE;
  1623. else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
  1624. checksum = CHECKSUM_UNNECESSARY;
  1625. else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
  1626. checksum = CHECKSUM_UNNECESSARY;
  1627. } else if (opts2 & RD_IPV6_CS) {
  1628. if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
  1629. checksum = CHECKSUM_UNNECESSARY;
  1630. else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
  1631. checksum = CHECKSUM_UNNECESSARY;
  1632. }
  1633. return_result:
  1634. return checksum;
  1635. }
  1636. static inline bool rx_count_exceed(struct r8152 *tp)
  1637. {
  1638. return atomic_read(&tp->rx_count) > RTL8152_MAX_RX;
  1639. }
  1640. static inline int agg_offset(struct rx_agg *agg, void *addr)
  1641. {
  1642. return (int)(addr - agg->buffer);
  1643. }
  1644. static struct rx_agg *rtl_get_free_rx(struct r8152 *tp, gfp_t mflags)
  1645. {
  1646. struct rx_agg *agg, *agg_next, *agg_free = NULL;
  1647. unsigned long flags;
  1648. spin_lock_irqsave(&tp->rx_lock, flags);
  1649. list_for_each_entry_safe(agg, agg_next, &tp->rx_used, list) {
  1650. if (page_count(agg->page) == 1) {
  1651. if (!agg_free) {
  1652. list_del_init(&agg->list);
  1653. agg_free = agg;
  1654. continue;
  1655. }
  1656. if (rx_count_exceed(tp)) {
  1657. list_del_init(&agg->list);
  1658. free_rx_agg(tp, agg);
  1659. }
  1660. break;
  1661. }
  1662. }
  1663. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1664. if (!agg_free && atomic_read(&tp->rx_count) < tp->rx_pending)
  1665. agg_free = alloc_rx_agg(tp, mflags);
  1666. return agg_free;
  1667. }
  1668. static int rx_bottom(struct r8152 *tp, int budget)
  1669. {
  1670. unsigned long flags;
  1671. struct list_head *cursor, *next, rx_queue;
  1672. int ret = 0, work_done = 0;
  1673. struct napi_struct *napi = &tp->napi;
  1674. if (!skb_queue_empty(&tp->rx_queue)) {
  1675. while (work_done < budget) {
  1676. struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
  1677. struct net_device *netdev = tp->netdev;
  1678. struct net_device_stats *stats = &netdev->stats;
  1679. unsigned int pkt_len;
  1680. if (!skb)
  1681. break;
  1682. pkt_len = skb->len;
  1683. napi_gro_receive(napi, skb);
  1684. work_done++;
  1685. stats->rx_packets++;
  1686. stats->rx_bytes += pkt_len;
  1687. }
  1688. }
  1689. if (list_empty(&tp->rx_done))
  1690. goto out1;
  1691. INIT_LIST_HEAD(&rx_queue);
  1692. spin_lock_irqsave(&tp->rx_lock, flags);
  1693. list_splice_init(&tp->rx_done, &rx_queue);
  1694. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1695. list_for_each_safe(cursor, next, &rx_queue) {
  1696. struct rx_desc *rx_desc;
  1697. struct rx_agg *agg, *agg_free;
  1698. int len_used = 0;
  1699. struct urb *urb;
  1700. u8 *rx_data;
  1701. list_del_init(cursor);
  1702. agg = list_entry(cursor, struct rx_agg, list);
  1703. urb = agg->urb;
  1704. if (urb->actual_length < ETH_ZLEN)
  1705. goto submit;
  1706. agg_free = rtl_get_free_rx(tp, GFP_ATOMIC);
  1707. rx_desc = agg->buffer;
  1708. rx_data = agg->buffer;
  1709. len_used += sizeof(struct rx_desc);
  1710. while (urb->actual_length > len_used) {
  1711. struct net_device *netdev = tp->netdev;
  1712. struct net_device_stats *stats = &netdev->stats;
  1713. unsigned int pkt_len, rx_frag_head_sz;
  1714. struct sk_buff *skb;
  1715. /* limite the skb numbers for rx_queue */
  1716. if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000))
  1717. break;
  1718. pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
  1719. if (pkt_len < ETH_ZLEN)
  1720. break;
  1721. len_used += pkt_len;
  1722. if (urb->actual_length < len_used)
  1723. break;
  1724. pkt_len -= ETH_FCS_LEN;
  1725. rx_data += sizeof(struct rx_desc);
  1726. if (!agg_free || tp->rx_copybreak > pkt_len)
  1727. rx_frag_head_sz = pkt_len;
  1728. else
  1729. rx_frag_head_sz = tp->rx_copybreak;
  1730. skb = napi_alloc_skb(napi, rx_frag_head_sz);
  1731. if (!skb) {
  1732. stats->rx_dropped++;
  1733. goto find_next_rx;
  1734. }
  1735. skb->ip_summed = r8152_rx_csum(tp, rx_desc);
  1736. memcpy(skb->data, rx_data, rx_frag_head_sz);
  1737. skb_put(skb, rx_frag_head_sz);
  1738. pkt_len -= rx_frag_head_sz;
  1739. rx_data += rx_frag_head_sz;
  1740. if (pkt_len) {
  1741. skb_add_rx_frag(skb, 0, agg->page,
  1742. agg_offset(agg, rx_data),
  1743. pkt_len,
  1744. SKB_DATA_ALIGN(pkt_len));
  1745. get_page(agg->page);
  1746. }
  1747. skb->protocol = eth_type_trans(skb, netdev);
  1748. rtl_rx_vlan_tag(rx_desc, skb);
  1749. if (work_done < budget) {
  1750. work_done++;
  1751. stats->rx_packets++;
  1752. stats->rx_bytes += skb->len;
  1753. napi_gro_receive(napi, skb);
  1754. } else {
  1755. __skb_queue_tail(&tp->rx_queue, skb);
  1756. }
  1757. find_next_rx:
  1758. rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN);
  1759. rx_desc = (struct rx_desc *)rx_data;
  1760. len_used = agg_offset(agg, rx_data);
  1761. len_used += sizeof(struct rx_desc);
  1762. }
  1763. WARN_ON(!agg_free && page_count(agg->page) > 1);
  1764. if (agg_free) {
  1765. spin_lock_irqsave(&tp->rx_lock, flags);
  1766. if (page_count(agg->page) == 1) {
  1767. list_add(&agg_free->list, &tp->rx_used);
  1768. } else {
  1769. list_add_tail(&agg->list, &tp->rx_used);
  1770. agg = agg_free;
  1771. urb = agg->urb;
  1772. }
  1773. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1774. }
  1775. submit:
  1776. if (!ret) {
  1777. ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
  1778. } else {
  1779. urb->actual_length = 0;
  1780. list_add_tail(&agg->list, next);
  1781. }
  1782. }
  1783. if (!list_empty(&rx_queue)) {
  1784. spin_lock_irqsave(&tp->rx_lock, flags);
  1785. list_splice_tail(&rx_queue, &tp->rx_done);
  1786. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1787. }
  1788. out1:
  1789. return work_done;
  1790. }
  1791. static void tx_bottom(struct r8152 *tp)
  1792. {
  1793. int res;
  1794. do {
  1795. struct tx_agg *agg;
  1796. if (skb_queue_empty(&tp->tx_queue))
  1797. break;
  1798. agg = r8152_get_tx_agg(tp);
  1799. if (!agg)
  1800. break;
  1801. res = r8152_tx_agg_fill(tp, agg);
  1802. if (res) {
  1803. struct net_device *netdev = tp->netdev;
  1804. if (res == -ENODEV) {
  1805. rtl_set_unplug(tp);
  1806. netif_device_detach(netdev);
  1807. } else {
  1808. struct net_device_stats *stats = &netdev->stats;
  1809. unsigned long flags;
  1810. netif_warn(tp, tx_err, netdev,
  1811. "failed tx_urb %d\n", res);
  1812. stats->tx_dropped += agg->skb_num;
  1813. spin_lock_irqsave(&tp->tx_lock, flags);
  1814. list_add_tail(&agg->list, &tp->tx_free);
  1815. spin_unlock_irqrestore(&tp->tx_lock, flags);
  1816. }
  1817. }
  1818. } while (res == 0);
  1819. }
  1820. static void bottom_half(unsigned long data)
  1821. {
  1822. struct r8152 *tp;
  1823. tp = (struct r8152 *)data;
  1824. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1825. return;
  1826. if (!test_bit(WORK_ENABLE, &tp->flags))
  1827. return;
  1828. /* When link down, the driver would cancel all bulks. */
  1829. /* This avoid the re-submitting bulk */
  1830. if (!netif_carrier_ok(tp->netdev))
  1831. return;
  1832. clear_bit(SCHEDULE_TASKLET, &tp->flags);
  1833. tx_bottom(tp);
  1834. }
  1835. static int r8152_poll(struct napi_struct *napi, int budget)
  1836. {
  1837. struct r8152 *tp = container_of(napi, struct r8152, napi);
  1838. int work_done;
  1839. work_done = rx_bottom(tp, budget);
  1840. if (work_done < budget) {
  1841. if (!napi_complete_done(napi, work_done))
  1842. goto out;
  1843. if (!list_empty(&tp->rx_done))
  1844. napi_schedule(napi);
  1845. }
  1846. out:
  1847. return work_done;
  1848. }
  1849. static
  1850. int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
  1851. {
  1852. int ret;
  1853. /* The rx would be stopped, so skip submitting */
  1854. if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
  1855. !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
  1856. return 0;
  1857. usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
  1858. agg->buffer, tp->rx_buf_sz,
  1859. (usb_complete_t)read_bulk_callback, agg);
  1860. ret = usb_submit_urb(agg->urb, mem_flags);
  1861. if (ret == -ENODEV) {
  1862. rtl_set_unplug(tp);
  1863. netif_device_detach(tp->netdev);
  1864. } else if (ret) {
  1865. struct urb *urb = agg->urb;
  1866. unsigned long flags;
  1867. urb->actual_length = 0;
  1868. spin_lock_irqsave(&tp->rx_lock, flags);
  1869. list_add_tail(&agg->list, &tp->rx_done);
  1870. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1871. netif_err(tp, rx_err, tp->netdev,
  1872. "Couldn't submit rx[%p], ret = %d\n", agg, ret);
  1873. napi_schedule(&tp->napi);
  1874. }
  1875. return ret;
  1876. }
  1877. static void rtl_drop_queued_tx(struct r8152 *tp)
  1878. {
  1879. struct net_device_stats *stats = &tp->netdev->stats;
  1880. struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
  1881. struct sk_buff *skb;
  1882. if (skb_queue_empty(tx_queue))
  1883. return;
  1884. __skb_queue_head_init(&skb_head);
  1885. spin_lock_bh(&tx_queue->lock);
  1886. skb_queue_splice_init(tx_queue, &skb_head);
  1887. spin_unlock_bh(&tx_queue->lock);
  1888. while ((skb = __skb_dequeue(&skb_head))) {
  1889. dev_kfree_skb(skb);
  1890. stats->tx_dropped++;
  1891. }
  1892. }
  1893. static void rtl8152_tx_timeout(struct net_device *netdev)
  1894. {
  1895. struct r8152 *tp = netdev_priv(netdev);
  1896. netif_warn(tp, tx_err, netdev, "Tx timeout\n");
  1897. usb_queue_reset_device(tp->intf);
  1898. }
  1899. static void rtl8152_set_rx_mode(struct net_device *netdev)
  1900. {
  1901. struct r8152 *tp = netdev_priv(netdev);
  1902. if (netif_carrier_ok(netdev)) {
  1903. set_bit(RTL8152_SET_RX_MODE, &tp->flags);
  1904. schedule_delayed_work(&tp->schedule, 0);
  1905. }
  1906. }
  1907. static void _rtl8152_set_rx_mode(struct net_device *netdev)
  1908. {
  1909. struct r8152 *tp = netdev_priv(netdev);
  1910. u32 mc_filter[2]; /* Multicast hash filter */
  1911. __le32 tmp[2];
  1912. u32 ocp_data;
  1913. netif_stop_queue(netdev);
  1914. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  1915. ocp_data &= ~RCR_ACPT_ALL;
  1916. ocp_data |= RCR_AB | RCR_APM;
  1917. if (netdev->flags & IFF_PROMISC) {
  1918. /* Unconditionally log net taps. */
  1919. netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
  1920. ocp_data |= RCR_AM | RCR_AAP;
  1921. mc_filter[1] = 0xffffffff;
  1922. mc_filter[0] = 0xffffffff;
  1923. } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
  1924. (netdev->flags & IFF_ALLMULTI)) {
  1925. /* Too many to filter perfectly -- accept all multicasts. */
  1926. ocp_data |= RCR_AM;
  1927. mc_filter[1] = 0xffffffff;
  1928. mc_filter[0] = 0xffffffff;
  1929. } else {
  1930. struct netdev_hw_addr *ha;
  1931. mc_filter[1] = 0;
  1932. mc_filter[0] = 0;
  1933. netdev_for_each_mc_addr(ha, netdev) {
  1934. int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
  1935. mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
  1936. ocp_data |= RCR_AM;
  1937. }
  1938. }
  1939. tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
  1940. tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
  1941. pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
  1942. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  1943. netif_wake_queue(netdev);
  1944. }
  1945. static netdev_features_t
  1946. rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
  1947. netdev_features_t features)
  1948. {
  1949. u32 mss = skb_shinfo(skb)->gso_size;
  1950. int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
  1951. int offset = skb_transport_offset(skb);
  1952. if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
  1953. features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
  1954. else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
  1955. features &= ~NETIF_F_GSO_MASK;
  1956. return features;
  1957. }
  1958. static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
  1959. struct net_device *netdev)
  1960. {
  1961. struct r8152 *tp = netdev_priv(netdev);
  1962. skb_tx_timestamp(skb);
  1963. skb_queue_tail(&tp->tx_queue, skb);
  1964. if (!list_empty(&tp->tx_free)) {
  1965. if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  1966. set_bit(SCHEDULE_TASKLET, &tp->flags);
  1967. schedule_delayed_work(&tp->schedule, 0);
  1968. } else {
  1969. usb_mark_last_busy(tp->udev);
  1970. tasklet_schedule(&tp->tx_tl);
  1971. }
  1972. } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
  1973. netif_stop_queue(netdev);
  1974. }
  1975. return NETDEV_TX_OK;
  1976. }
  1977. static void r8152b_reset_packet_filter(struct r8152 *tp)
  1978. {
  1979. u32 ocp_data;
  1980. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
  1981. ocp_data &= ~FMC_FCR_MCU_EN;
  1982. ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
  1983. ocp_data |= FMC_FCR_MCU_EN;
  1984. ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
  1985. }
  1986. static void rtl8152_nic_reset(struct r8152 *tp)
  1987. {
  1988. int i;
  1989. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
  1990. for (i = 0; i < 1000; i++) {
  1991. if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
  1992. break;
  1993. usleep_range(100, 400);
  1994. }
  1995. }
  1996. static void set_tx_qlen(struct r8152 *tp)
  1997. {
  1998. struct net_device *netdev = tp->netdev;
  1999. tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN +
  2000. sizeof(struct tx_desc));
  2001. }
  2002. static inline u8 rtl8152_get_speed(struct r8152 *tp)
  2003. {
  2004. return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
  2005. }
  2006. static void rtl_set_eee_plus(struct r8152 *tp)
  2007. {
  2008. u32 ocp_data;
  2009. u8 speed;
  2010. speed = rtl8152_get_speed(tp);
  2011. if (speed & _10bps) {
  2012. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
  2013. ocp_data |= EEEP_CR_EEEP_TX;
  2014. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
  2015. } else {
  2016. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
  2017. ocp_data &= ~EEEP_CR_EEEP_TX;
  2018. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
  2019. }
  2020. }
  2021. static void rxdy_gated_en(struct r8152 *tp, bool enable)
  2022. {
  2023. u32 ocp_data;
  2024. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
  2025. if (enable)
  2026. ocp_data |= RXDY_GATED_EN;
  2027. else
  2028. ocp_data &= ~RXDY_GATED_EN;
  2029. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
  2030. }
  2031. static int rtl_start_rx(struct r8152 *tp)
  2032. {
  2033. struct rx_agg *agg, *agg_next;
  2034. struct list_head tmp_list;
  2035. unsigned long flags;
  2036. int ret = 0, i = 0;
  2037. INIT_LIST_HEAD(&tmp_list);
  2038. spin_lock_irqsave(&tp->rx_lock, flags);
  2039. INIT_LIST_HEAD(&tp->rx_done);
  2040. INIT_LIST_HEAD(&tp->rx_used);
  2041. list_splice_init(&tp->rx_info, &tmp_list);
  2042. spin_unlock_irqrestore(&tp->rx_lock, flags);
  2043. list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
  2044. INIT_LIST_HEAD(&agg->list);
  2045. /* Only RTL8152_MAX_RX rx_agg need to be submitted. */
  2046. if (++i > RTL8152_MAX_RX) {
  2047. spin_lock_irqsave(&tp->rx_lock, flags);
  2048. list_add_tail(&agg->list, &tp->rx_used);
  2049. spin_unlock_irqrestore(&tp->rx_lock, flags);
  2050. } else if (unlikely(ret < 0)) {
  2051. spin_lock_irqsave(&tp->rx_lock, flags);
  2052. list_add_tail(&agg->list, &tp->rx_done);
  2053. spin_unlock_irqrestore(&tp->rx_lock, flags);
  2054. } else {
  2055. ret = r8152_submit_rx(tp, agg, GFP_KERNEL);
  2056. }
  2057. }
  2058. spin_lock_irqsave(&tp->rx_lock, flags);
  2059. WARN_ON(!list_empty(&tp->rx_info));
  2060. list_splice(&tmp_list, &tp->rx_info);
  2061. spin_unlock_irqrestore(&tp->rx_lock, flags);
  2062. return ret;
  2063. }
  2064. static int rtl_stop_rx(struct r8152 *tp)
  2065. {
  2066. struct rx_agg *agg, *agg_next;
  2067. struct list_head tmp_list;
  2068. unsigned long flags;
  2069. INIT_LIST_HEAD(&tmp_list);
  2070. /* The usb_kill_urb() couldn't be used in atomic.
  2071. * Therefore, move the list of rx_info to a tmp one.
  2072. * Then, list_for_each_entry_safe could be used without
  2073. * spin lock.
  2074. */
  2075. spin_lock_irqsave(&tp->rx_lock, flags);
  2076. list_splice_init(&tp->rx_info, &tmp_list);
  2077. spin_unlock_irqrestore(&tp->rx_lock, flags);
  2078. list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
  2079. /* At least RTL8152_MAX_RX rx_agg have the page_count being
  2080. * equal to 1, so the other ones could be freed safely.
  2081. */
  2082. if (page_count(agg->page) > 1)
  2083. free_rx_agg(tp, agg);
  2084. else
  2085. usb_kill_urb(agg->urb);
  2086. }
  2087. /* Move back the list of temp to the rx_info */
  2088. spin_lock_irqsave(&tp->rx_lock, flags);
  2089. WARN_ON(!list_empty(&tp->rx_info));
  2090. list_splice(&tmp_list, &tp->rx_info);
  2091. spin_unlock_irqrestore(&tp->rx_lock, flags);
  2092. while (!skb_queue_empty(&tp->rx_queue))
  2093. dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
  2094. return 0;
  2095. }
  2096. static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp)
  2097. {
  2098. ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN,
  2099. OWN_UPDATE | OWN_CLEAR);
  2100. }
  2101. static int rtl_enable(struct r8152 *tp)
  2102. {
  2103. u32 ocp_data;
  2104. r8152b_reset_packet_filter(tp);
  2105. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
  2106. ocp_data |= CR_RE | CR_TE;
  2107. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
  2108. switch (tp->version) {
  2109. case RTL_VER_08:
  2110. case RTL_VER_09:
  2111. r8153b_rx_agg_chg_indicate(tp);
  2112. break;
  2113. default:
  2114. break;
  2115. }
  2116. rxdy_gated_en(tp, false);
  2117. return 0;
  2118. }
  2119. static int rtl8152_enable(struct r8152 *tp)
  2120. {
  2121. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2122. return -ENODEV;
  2123. set_tx_qlen(tp);
  2124. rtl_set_eee_plus(tp);
  2125. return rtl_enable(tp);
  2126. }
  2127. static void r8153_set_rx_early_timeout(struct r8152 *tp)
  2128. {
  2129. u32 ocp_data = tp->coalesce / 8;
  2130. switch (tp->version) {
  2131. case RTL_VER_03:
  2132. case RTL_VER_04:
  2133. case RTL_VER_05:
  2134. case RTL_VER_06:
  2135. ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
  2136. ocp_data);
  2137. break;
  2138. case RTL_VER_08:
  2139. case RTL_VER_09:
  2140. /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
  2141. * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns.
  2142. */
  2143. ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
  2144. 128 / 8);
  2145. ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
  2146. ocp_data);
  2147. break;
  2148. default:
  2149. break;
  2150. }
  2151. }
  2152. static void r8153_set_rx_early_size(struct r8152 *tp)
  2153. {
  2154. u32 ocp_data = tp->rx_buf_sz - rx_reserved_size(tp->netdev->mtu);
  2155. switch (tp->version) {
  2156. case RTL_VER_03:
  2157. case RTL_VER_04:
  2158. case RTL_VER_05:
  2159. case RTL_VER_06:
  2160. ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
  2161. ocp_data / 4);
  2162. break;
  2163. case RTL_VER_08:
  2164. case RTL_VER_09:
  2165. ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
  2166. ocp_data / 8);
  2167. break;
  2168. default:
  2169. WARN_ON_ONCE(1);
  2170. break;
  2171. }
  2172. }
  2173. static int rtl8153_enable(struct r8152 *tp)
  2174. {
  2175. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2176. return -ENODEV;
  2177. set_tx_qlen(tp);
  2178. rtl_set_eee_plus(tp);
  2179. r8153_set_rx_early_timeout(tp);
  2180. r8153_set_rx_early_size(tp);
  2181. return rtl_enable(tp);
  2182. }
  2183. static void rtl_disable(struct r8152 *tp)
  2184. {
  2185. u32 ocp_data;
  2186. int i;
  2187. if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
  2188. rtl_drop_queued_tx(tp);
  2189. return;
  2190. }
  2191. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  2192. ocp_data &= ~RCR_ACPT_ALL;
  2193. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  2194. rtl_drop_queued_tx(tp);
  2195. for (i = 0; i < RTL8152_MAX_TX; i++)
  2196. usb_kill_urb(tp->tx_info[i].urb);
  2197. rxdy_gated_en(tp, true);
  2198. for (i = 0; i < 1000; i++) {
  2199. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2200. if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
  2201. break;
  2202. usleep_range(1000, 2000);
  2203. }
  2204. for (i = 0; i < 1000; i++) {
  2205. if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
  2206. break;
  2207. usleep_range(1000, 2000);
  2208. }
  2209. rtl_stop_rx(tp);
  2210. rtl8152_nic_reset(tp);
  2211. }
  2212. static void r8152_power_cut_en(struct r8152 *tp, bool enable)
  2213. {
  2214. u32 ocp_data;
  2215. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
  2216. if (enable)
  2217. ocp_data |= POWER_CUT;
  2218. else
  2219. ocp_data &= ~POWER_CUT;
  2220. ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
  2221. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
  2222. ocp_data &= ~RESUME_INDICATE;
  2223. ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
  2224. }
  2225. static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
  2226. {
  2227. u32 ocp_data;
  2228. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
  2229. if (enable)
  2230. ocp_data |= CPCR_RX_VLAN;
  2231. else
  2232. ocp_data &= ~CPCR_RX_VLAN;
  2233. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
  2234. }
  2235. static int rtl8152_set_features(struct net_device *dev,
  2236. netdev_features_t features)
  2237. {
  2238. netdev_features_t changed = features ^ dev->features;
  2239. struct r8152 *tp = netdev_priv(dev);
  2240. int ret;
  2241. ret = usb_autopm_get_interface(tp->intf);
  2242. if (ret < 0)
  2243. goto out;
  2244. mutex_lock(&tp->control);
  2245. if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
  2246. if (features & NETIF_F_HW_VLAN_CTAG_RX)
  2247. rtl_rx_vlan_en(tp, true);
  2248. else
  2249. rtl_rx_vlan_en(tp, false);
  2250. }
  2251. mutex_unlock(&tp->control);
  2252. usb_autopm_put_interface(tp->intf);
  2253. out:
  2254. return ret;
  2255. }
  2256. #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
  2257. static u32 __rtl_get_wol(struct r8152 *tp)
  2258. {
  2259. u32 ocp_data;
  2260. u32 wolopts = 0;
  2261. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
  2262. if (ocp_data & LINK_ON_WAKE_EN)
  2263. wolopts |= WAKE_PHY;
  2264. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
  2265. if (ocp_data & UWF_EN)
  2266. wolopts |= WAKE_UCAST;
  2267. if (ocp_data & BWF_EN)
  2268. wolopts |= WAKE_BCAST;
  2269. if (ocp_data & MWF_EN)
  2270. wolopts |= WAKE_MCAST;
  2271. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
  2272. if (ocp_data & MAGIC_EN)
  2273. wolopts |= WAKE_MAGIC;
  2274. return wolopts;
  2275. }
  2276. static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
  2277. {
  2278. u32 ocp_data;
  2279. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  2280. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
  2281. ocp_data &= ~LINK_ON_WAKE_EN;
  2282. if (wolopts & WAKE_PHY)
  2283. ocp_data |= LINK_ON_WAKE_EN;
  2284. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
  2285. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
  2286. ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
  2287. if (wolopts & WAKE_UCAST)
  2288. ocp_data |= UWF_EN;
  2289. if (wolopts & WAKE_BCAST)
  2290. ocp_data |= BWF_EN;
  2291. if (wolopts & WAKE_MCAST)
  2292. ocp_data |= MWF_EN;
  2293. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
  2294. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  2295. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
  2296. ocp_data &= ~MAGIC_EN;
  2297. if (wolopts & WAKE_MAGIC)
  2298. ocp_data |= MAGIC_EN;
  2299. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
  2300. if (wolopts & WAKE_ANY)
  2301. device_set_wakeup_enable(&tp->udev->dev, true);
  2302. else
  2303. device_set_wakeup_enable(&tp->udev->dev, false);
  2304. }
  2305. static void r8153_u1u2en(struct r8152 *tp, bool enable)
  2306. {
  2307. u8 u1u2[8];
  2308. if (enable)
  2309. memset(u1u2, 0xff, sizeof(u1u2));
  2310. else
  2311. memset(u1u2, 0x00, sizeof(u1u2));
  2312. usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
  2313. }
  2314. static void r8153b_u1u2en(struct r8152 *tp, bool enable)
  2315. {
  2316. u32 ocp_data;
  2317. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG);
  2318. if (enable)
  2319. ocp_data |= LPM_U1U2_EN;
  2320. else
  2321. ocp_data &= ~LPM_U1U2_EN;
  2322. ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data);
  2323. }
  2324. static void r8153_u2p3en(struct r8152 *tp, bool enable)
  2325. {
  2326. u32 ocp_data;
  2327. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
  2328. if (enable)
  2329. ocp_data |= U2P3_ENABLE;
  2330. else
  2331. ocp_data &= ~U2P3_ENABLE;
  2332. ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
  2333. }
  2334. static void r8153b_ups_flags(struct r8152 *tp)
  2335. {
  2336. u32 ups_flags = 0;
  2337. if (tp->ups_info.green)
  2338. ups_flags |= UPS_FLAGS_EN_GREEN;
  2339. if (tp->ups_info.aldps)
  2340. ups_flags |= UPS_FLAGS_EN_ALDPS;
  2341. if (tp->ups_info.eee)
  2342. ups_flags |= UPS_FLAGS_EN_EEE;
  2343. if (tp->ups_info.flow_control)
  2344. ups_flags |= UPS_FLAGS_EN_FLOW_CTR;
  2345. if (tp->ups_info.eee_ckdiv)
  2346. ups_flags |= UPS_FLAGS_EN_EEE_CKDIV;
  2347. if (tp->ups_info.eee_cmod_lv)
  2348. ups_flags |= UPS_FLAGS_EEE_CMOD_LV_EN;
  2349. if (tp->ups_info._10m_ckdiv)
  2350. ups_flags |= UPS_FLAGS_EN_10M_CKDIV;
  2351. if (tp->ups_info.eee_plloff_100)
  2352. ups_flags |= UPS_FLAGS_EEE_PLLOFF_100;
  2353. if (tp->ups_info.eee_plloff_giga)
  2354. ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA;
  2355. if (tp->ups_info._250m_ckdiv)
  2356. ups_flags |= UPS_FLAGS_250M_CKDIV;
  2357. if (tp->ups_info.ctap_short_off)
  2358. ups_flags |= UPS_FLAGS_CTAP_SHORT_DIS;
  2359. switch (tp->ups_info.speed_duplex) {
  2360. case NWAY_10M_HALF:
  2361. ups_flags |= ups_flags_speed(1);
  2362. break;
  2363. case NWAY_10M_FULL:
  2364. ups_flags |= ups_flags_speed(2);
  2365. break;
  2366. case NWAY_100M_HALF:
  2367. ups_flags |= ups_flags_speed(3);
  2368. break;
  2369. case NWAY_100M_FULL:
  2370. ups_flags |= ups_flags_speed(4);
  2371. break;
  2372. case NWAY_1000M_FULL:
  2373. ups_flags |= ups_flags_speed(5);
  2374. break;
  2375. case FORCE_10M_HALF:
  2376. ups_flags |= ups_flags_speed(6);
  2377. break;
  2378. case FORCE_10M_FULL:
  2379. ups_flags |= ups_flags_speed(7);
  2380. break;
  2381. case FORCE_100M_HALF:
  2382. ups_flags |= ups_flags_speed(8);
  2383. break;
  2384. case FORCE_100M_FULL:
  2385. ups_flags |= ups_flags_speed(9);
  2386. break;
  2387. default:
  2388. break;
  2389. }
  2390. ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags);
  2391. }
  2392. static void r8153b_green_en(struct r8152 *tp, bool enable)
  2393. {
  2394. u16 data;
  2395. if (enable) {
  2396. sram_write(tp, 0x8045, 0); /* 10M abiq&ldvbias */
  2397. sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */
  2398. sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */
  2399. } else {
  2400. sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */
  2401. sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */
  2402. sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */
  2403. }
  2404. data = sram_read(tp, SRAM_GREEN_CFG);
  2405. data |= GREEN_ETH_EN;
  2406. sram_write(tp, SRAM_GREEN_CFG, data);
  2407. tp->ups_info.green = enable;
  2408. }
  2409. static u16 r8153_phy_status(struct r8152 *tp, u16 desired)
  2410. {
  2411. u16 data;
  2412. int i;
  2413. for (i = 0; i < 500; i++) {
  2414. data = ocp_reg_read(tp, OCP_PHY_STATUS);
  2415. data &= PHY_STAT_MASK;
  2416. if (desired) {
  2417. if (data == desired)
  2418. break;
  2419. } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN ||
  2420. data == PHY_STAT_EXT_INIT) {
  2421. break;
  2422. }
  2423. msleep(20);
  2424. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2425. break;
  2426. }
  2427. return data;
  2428. }
  2429. static void r8153b_ups_en(struct r8152 *tp, bool enable)
  2430. {
  2431. u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
  2432. if (enable) {
  2433. r8153b_ups_flags(tp);
  2434. ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
  2435. ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
  2436. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
  2437. ocp_data |= BIT(0);
  2438. ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
  2439. } else {
  2440. u16 data;
  2441. ocp_data &= ~(UPS_EN | USP_PREWAKE);
  2442. ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
  2443. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
  2444. ocp_data &= ~BIT(0);
  2445. ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
  2446. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
  2447. ocp_data &= ~PCUT_STATUS;
  2448. ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
  2449. data = r8153_phy_status(tp, 0);
  2450. switch (data) {
  2451. case PHY_STAT_PWRDN:
  2452. case PHY_STAT_EXT_INIT:
  2453. r8153b_green_en(tp,
  2454. test_bit(GREEN_ETHERNET, &tp->flags));
  2455. data = r8152_mdio_read(tp, MII_BMCR);
  2456. data &= ~BMCR_PDOWN;
  2457. data |= BMCR_RESET;
  2458. r8152_mdio_write(tp, MII_BMCR, data);
  2459. data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
  2460. /* fall through */
  2461. default:
  2462. if (data != PHY_STAT_LAN_ON)
  2463. netif_warn(tp, link, tp->netdev,
  2464. "PHY not ready");
  2465. break;
  2466. }
  2467. }
  2468. }
  2469. static void r8153_power_cut_en(struct r8152 *tp, bool enable)
  2470. {
  2471. u32 ocp_data;
  2472. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
  2473. if (enable)
  2474. ocp_data |= PWR_EN | PHASE2_EN;
  2475. else
  2476. ocp_data &= ~(PWR_EN | PHASE2_EN);
  2477. ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
  2478. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
  2479. ocp_data &= ~PCUT_STATUS;
  2480. ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
  2481. }
  2482. static void r8153b_power_cut_en(struct r8152 *tp, bool enable)
  2483. {
  2484. u32 ocp_data;
  2485. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
  2486. if (enable)
  2487. ocp_data |= PWR_EN | PHASE2_EN;
  2488. else
  2489. ocp_data &= ~PWR_EN;
  2490. ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
  2491. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
  2492. ocp_data &= ~PCUT_STATUS;
  2493. ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
  2494. }
  2495. static void r8153_queue_wake(struct r8152 *tp, bool enable)
  2496. {
  2497. u32 ocp_data;
  2498. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG);
  2499. if (enable)
  2500. ocp_data |= UPCOMING_RUNTIME_D3;
  2501. else
  2502. ocp_data &= ~UPCOMING_RUNTIME_D3;
  2503. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, ocp_data);
  2504. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG);
  2505. ocp_data &= ~LINK_CHG_EVENT;
  2506. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG, ocp_data);
  2507. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
  2508. ocp_data &= ~LINK_CHANGE_FLAG;
  2509. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
  2510. }
  2511. static bool rtl_can_wakeup(struct r8152 *tp)
  2512. {
  2513. struct usb_device *udev = tp->udev;
  2514. return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
  2515. }
  2516. static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
  2517. {
  2518. if (enable) {
  2519. u32 ocp_data;
  2520. __rtl_set_wol(tp, WAKE_ANY);
  2521. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  2522. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
  2523. ocp_data |= LINK_OFF_WAKE_EN;
  2524. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
  2525. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  2526. } else {
  2527. u32 ocp_data;
  2528. __rtl_set_wol(tp, tp->saved_wolopts);
  2529. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  2530. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
  2531. ocp_data &= ~LINK_OFF_WAKE_EN;
  2532. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
  2533. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  2534. }
  2535. }
  2536. static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
  2537. {
  2538. if (enable) {
  2539. r8153_u1u2en(tp, false);
  2540. r8153_u2p3en(tp, false);
  2541. rtl_runtime_suspend_enable(tp, true);
  2542. } else {
  2543. rtl_runtime_suspend_enable(tp, false);
  2544. switch (tp->version) {
  2545. case RTL_VER_03:
  2546. case RTL_VER_04:
  2547. break;
  2548. case RTL_VER_05:
  2549. case RTL_VER_06:
  2550. default:
  2551. r8153_u2p3en(tp, true);
  2552. break;
  2553. }
  2554. r8153_u1u2en(tp, true);
  2555. }
  2556. }
  2557. static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable)
  2558. {
  2559. if (enable) {
  2560. r8153_queue_wake(tp, true);
  2561. r8153b_u1u2en(tp, false);
  2562. r8153_u2p3en(tp, false);
  2563. rtl_runtime_suspend_enable(tp, true);
  2564. r8153b_ups_en(tp, true);
  2565. } else {
  2566. r8153b_ups_en(tp, false);
  2567. r8153_queue_wake(tp, false);
  2568. rtl_runtime_suspend_enable(tp, false);
  2569. r8153b_u1u2en(tp, true);
  2570. }
  2571. }
  2572. static void r8153_teredo_off(struct r8152 *tp)
  2573. {
  2574. u32 ocp_data;
  2575. switch (tp->version) {
  2576. case RTL_VER_01:
  2577. case RTL_VER_02:
  2578. case RTL_VER_03:
  2579. case RTL_VER_04:
  2580. case RTL_VER_05:
  2581. case RTL_VER_06:
  2582. case RTL_VER_07:
  2583. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
  2584. ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK |
  2585. OOB_TEREDO_EN);
  2586. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
  2587. break;
  2588. case RTL_VER_08:
  2589. case RTL_VER_09:
  2590. /* The bit 0 ~ 7 are relative with teredo settings. They are
  2591. * W1C (write 1 to clear), so set all 1 to disable it.
  2592. */
  2593. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff);
  2594. break;
  2595. default:
  2596. break;
  2597. }
  2598. ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
  2599. ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
  2600. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
  2601. }
  2602. static void rtl_reset_bmu(struct r8152 *tp)
  2603. {
  2604. u32 ocp_data;
  2605. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
  2606. ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
  2607. ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
  2608. ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
  2609. ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
  2610. }
  2611. static void r8152_aldps_en(struct r8152 *tp, bool enable)
  2612. {
  2613. if (enable) {
  2614. ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
  2615. LINKENA | DIS_SDSAVE);
  2616. } else {
  2617. ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
  2618. DIS_SDSAVE);
  2619. msleep(20);
  2620. }
  2621. }
  2622. static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
  2623. {
  2624. ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
  2625. ocp_reg_write(tp, OCP_EEE_DATA, reg);
  2626. ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
  2627. }
  2628. static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
  2629. {
  2630. u16 data;
  2631. r8152_mmd_indirect(tp, dev, reg);
  2632. data = ocp_reg_read(tp, OCP_EEE_DATA);
  2633. ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
  2634. return data;
  2635. }
  2636. static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
  2637. {
  2638. r8152_mmd_indirect(tp, dev, reg);
  2639. ocp_reg_write(tp, OCP_EEE_DATA, data);
  2640. ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
  2641. }
  2642. static void r8152_eee_en(struct r8152 *tp, bool enable)
  2643. {
  2644. u16 config1, config2, config3;
  2645. u32 ocp_data;
  2646. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  2647. config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
  2648. config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
  2649. config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
  2650. if (enable) {
  2651. ocp_data |= EEE_RX_EN | EEE_TX_EN;
  2652. config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
  2653. config1 |= sd_rise_time(1);
  2654. config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
  2655. config3 |= fast_snr(42);
  2656. } else {
  2657. ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
  2658. config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
  2659. RX_QUIET_EN);
  2660. config1 |= sd_rise_time(7);
  2661. config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
  2662. config3 |= fast_snr(511);
  2663. }
  2664. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
  2665. ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
  2666. ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
  2667. ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
  2668. }
  2669. static void r8153_eee_en(struct r8152 *tp, bool enable)
  2670. {
  2671. u32 ocp_data;
  2672. u16 config;
  2673. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  2674. config = ocp_reg_read(tp, OCP_EEE_CFG);
  2675. if (enable) {
  2676. ocp_data |= EEE_RX_EN | EEE_TX_EN;
  2677. config |= EEE10_EN;
  2678. } else {
  2679. ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
  2680. config &= ~EEE10_EN;
  2681. }
  2682. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
  2683. ocp_reg_write(tp, OCP_EEE_CFG, config);
  2684. tp->ups_info.eee = enable;
  2685. }
  2686. static void rtl_eee_enable(struct r8152 *tp, bool enable)
  2687. {
  2688. switch (tp->version) {
  2689. case RTL_VER_01:
  2690. case RTL_VER_02:
  2691. case RTL_VER_07:
  2692. if (enable) {
  2693. r8152_eee_en(tp, true);
  2694. r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
  2695. tp->eee_adv);
  2696. } else {
  2697. r8152_eee_en(tp, false);
  2698. r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
  2699. }
  2700. break;
  2701. case RTL_VER_03:
  2702. case RTL_VER_04:
  2703. case RTL_VER_05:
  2704. case RTL_VER_06:
  2705. case RTL_VER_08:
  2706. case RTL_VER_09:
  2707. if (enable) {
  2708. r8153_eee_en(tp, true);
  2709. ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv);
  2710. } else {
  2711. r8153_eee_en(tp, false);
  2712. ocp_reg_write(tp, OCP_EEE_ADV, 0);
  2713. }
  2714. break;
  2715. default:
  2716. break;
  2717. }
  2718. }
  2719. static void r8152b_enable_fc(struct r8152 *tp)
  2720. {
  2721. u16 anar;
  2722. anar = r8152_mdio_read(tp, MII_ADVERTISE);
  2723. anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  2724. r8152_mdio_write(tp, MII_ADVERTISE, anar);
  2725. tp->ups_info.flow_control = true;
  2726. }
  2727. static void rtl8152_disable(struct r8152 *tp)
  2728. {
  2729. r8152_aldps_en(tp, false);
  2730. rtl_disable(tp);
  2731. r8152_aldps_en(tp, true);
  2732. }
  2733. static void r8152b_hw_phy_cfg(struct r8152 *tp)
  2734. {
  2735. rtl_eee_enable(tp, tp->eee_en);
  2736. r8152_aldps_en(tp, true);
  2737. r8152b_enable_fc(tp);
  2738. set_bit(PHY_RESET, &tp->flags);
  2739. }
  2740. static void r8152b_exit_oob(struct r8152 *tp)
  2741. {
  2742. u32 ocp_data;
  2743. int i;
  2744. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  2745. ocp_data &= ~RCR_ACPT_ALL;
  2746. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  2747. rxdy_gated_en(tp, true);
  2748. r8153_teredo_off(tp);
  2749. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  2750. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
  2751. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2752. ocp_data &= ~NOW_IS_OOB;
  2753. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2754. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2755. ocp_data &= ~MCU_BORW_EN;
  2756. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2757. for (i = 0; i < 1000; i++) {
  2758. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2759. if (ocp_data & LINK_LIST_READY)
  2760. break;
  2761. usleep_range(1000, 2000);
  2762. }
  2763. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2764. ocp_data |= RE_INIT_LL;
  2765. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2766. for (i = 0; i < 1000; i++) {
  2767. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2768. if (ocp_data & LINK_LIST_READY)
  2769. break;
  2770. usleep_range(1000, 2000);
  2771. }
  2772. rtl8152_nic_reset(tp);
  2773. /* rx share fifo credit full threshold */
  2774. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
  2775. if (tp->udev->speed == USB_SPEED_FULL ||
  2776. tp->udev->speed == USB_SPEED_LOW) {
  2777. /* rx share fifo credit near full threshold */
  2778. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
  2779. RXFIFO_THR2_FULL);
  2780. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
  2781. RXFIFO_THR3_FULL);
  2782. } else {
  2783. /* rx share fifo credit near full threshold */
  2784. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
  2785. RXFIFO_THR2_HIGH);
  2786. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
  2787. RXFIFO_THR3_HIGH);
  2788. }
  2789. /* TX share fifo free credit full threshold */
  2790. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
  2791. ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
  2792. ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
  2793. ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
  2794. TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
  2795. rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
  2796. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
  2797. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
  2798. ocp_data |= TCR0_AUTO_FIFO;
  2799. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
  2800. }
  2801. static void r8152b_enter_oob(struct r8152 *tp)
  2802. {
  2803. u32 ocp_data;
  2804. int i;
  2805. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2806. ocp_data &= ~NOW_IS_OOB;
  2807. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2808. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
  2809. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
  2810. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
  2811. rtl_disable(tp);
  2812. for (i = 0; i < 1000; i++) {
  2813. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2814. if (ocp_data & LINK_LIST_READY)
  2815. break;
  2816. usleep_range(1000, 2000);
  2817. }
  2818. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2819. ocp_data |= RE_INIT_LL;
  2820. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2821. for (i = 0; i < 1000; i++) {
  2822. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2823. if (ocp_data & LINK_LIST_READY)
  2824. break;
  2825. usleep_range(1000, 2000);
  2826. }
  2827. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
  2828. rtl_rx_vlan_en(tp, true);
  2829. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
  2830. ocp_data |= ALDPS_PROXY_MODE;
  2831. ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
  2832. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2833. ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
  2834. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2835. rxdy_gated_en(tp, false);
  2836. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  2837. ocp_data |= RCR_APM | RCR_AM | RCR_AB;
  2838. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  2839. }
  2840. static int r8153_patch_request(struct r8152 *tp, bool request)
  2841. {
  2842. u16 data;
  2843. int i;
  2844. data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD);
  2845. if (request)
  2846. data |= PATCH_REQUEST;
  2847. else
  2848. data &= ~PATCH_REQUEST;
  2849. ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data);
  2850. for (i = 0; request && i < 5000; i++) {
  2851. usleep_range(1000, 2000);
  2852. if (ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)
  2853. break;
  2854. }
  2855. if (request && !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) {
  2856. netif_err(tp, drv, tp->netdev, "patch request fail\n");
  2857. r8153_patch_request(tp, false);
  2858. return -ETIME;
  2859. } else {
  2860. return 0;
  2861. }
  2862. }
  2863. static void r8153_aldps_en(struct r8152 *tp, bool enable)
  2864. {
  2865. u16 data;
  2866. data = ocp_reg_read(tp, OCP_POWER_CFG);
  2867. if (enable) {
  2868. data |= EN_ALDPS;
  2869. ocp_reg_write(tp, OCP_POWER_CFG, data);
  2870. } else {
  2871. int i;
  2872. data &= ~EN_ALDPS;
  2873. ocp_reg_write(tp, OCP_POWER_CFG, data);
  2874. for (i = 0; i < 20; i++) {
  2875. usleep_range(1000, 2000);
  2876. if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100)
  2877. break;
  2878. }
  2879. }
  2880. tp->ups_info.aldps = enable;
  2881. }
  2882. static void r8153_hw_phy_cfg(struct r8152 *tp)
  2883. {
  2884. u32 ocp_data;
  2885. u16 data;
  2886. /* disable ALDPS before updating the PHY parameters */
  2887. r8153_aldps_en(tp, false);
  2888. /* disable EEE before updating the PHY parameters */
  2889. rtl_eee_enable(tp, false);
  2890. if (tp->version == RTL_VER_03) {
  2891. data = ocp_reg_read(tp, OCP_EEE_CFG);
  2892. data &= ~CTAP_SHORT_EN;
  2893. ocp_reg_write(tp, OCP_EEE_CFG, data);
  2894. }
  2895. data = ocp_reg_read(tp, OCP_POWER_CFG);
  2896. data |= EEE_CLKDIV_EN;
  2897. ocp_reg_write(tp, OCP_POWER_CFG, data);
  2898. data = ocp_reg_read(tp, OCP_DOWN_SPEED);
  2899. data |= EN_10M_BGOFF;
  2900. ocp_reg_write(tp, OCP_DOWN_SPEED, data);
  2901. data = ocp_reg_read(tp, OCP_POWER_CFG);
  2902. data |= EN_10M_PLLOFF;
  2903. ocp_reg_write(tp, OCP_POWER_CFG, data);
  2904. sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
  2905. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
  2906. ocp_data |= PFM_PWM_SWITCH;
  2907. ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
  2908. /* Enable LPF corner auto tune */
  2909. sram_write(tp, SRAM_LPF_CFG, 0xf70f);
  2910. /* Adjust 10M Amplitude */
  2911. sram_write(tp, SRAM_10M_AMP1, 0x00af);
  2912. sram_write(tp, SRAM_10M_AMP2, 0x0208);
  2913. if (tp->eee_en)
  2914. rtl_eee_enable(tp, true);
  2915. r8153_aldps_en(tp, true);
  2916. r8152b_enable_fc(tp);
  2917. switch (tp->version) {
  2918. case RTL_VER_03:
  2919. case RTL_VER_04:
  2920. break;
  2921. case RTL_VER_05:
  2922. case RTL_VER_06:
  2923. default:
  2924. r8153_u2p3en(tp, true);
  2925. break;
  2926. }
  2927. set_bit(PHY_RESET, &tp->flags);
  2928. }
  2929. static u32 r8152_efuse_read(struct r8152 *tp, u8 addr)
  2930. {
  2931. u32 ocp_data;
  2932. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr);
  2933. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD);
  2934. ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9; /* data of bit16 */
  2935. ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA);
  2936. return ocp_data;
  2937. }
  2938. static void r8153b_hw_phy_cfg(struct r8152 *tp)
  2939. {
  2940. u32 ocp_data;
  2941. u16 data;
  2942. /* disable ALDPS before updating the PHY parameters */
  2943. r8153_aldps_en(tp, false);
  2944. /* disable EEE before updating the PHY parameters */
  2945. rtl_eee_enable(tp, false);
  2946. r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
  2947. data = sram_read(tp, SRAM_GREEN_CFG);
  2948. data |= R_TUNE_EN;
  2949. sram_write(tp, SRAM_GREEN_CFG, data);
  2950. data = ocp_reg_read(tp, OCP_NCTL_CFG);
  2951. data |= PGA_RETURN_EN;
  2952. ocp_reg_write(tp, OCP_NCTL_CFG, data);
  2953. /* ADC Bias Calibration:
  2954. * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
  2955. * bit (bit3) to rebuild the real 16-bit data. Write the data to the
  2956. * ADC ioffset.
  2957. */
  2958. ocp_data = r8152_efuse_read(tp, 0x7d);
  2959. data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7));
  2960. if (data != 0xffff)
  2961. ocp_reg_write(tp, OCP_ADC_IOFFSET, data);
  2962. /* ups mode tx-link-pulse timing adjustment:
  2963. * rg_saw_cnt = OCP reg 0xC426 Bit[13:0]
  2964. * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt
  2965. */
  2966. ocp_data = ocp_reg_read(tp, 0xc426);
  2967. ocp_data &= 0x3fff;
  2968. if (ocp_data) {
  2969. u32 swr_cnt_1ms_ini;
  2970. swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK;
  2971. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG);
  2972. ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini;
  2973. ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data);
  2974. }
  2975. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
  2976. ocp_data |= PFM_PWM_SWITCH;
  2977. ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
  2978. /* Advnace EEE */
  2979. if (!r8153_patch_request(tp, true)) {
  2980. data = ocp_reg_read(tp, OCP_POWER_CFG);
  2981. data |= EEE_CLKDIV_EN;
  2982. ocp_reg_write(tp, OCP_POWER_CFG, data);
  2983. tp->ups_info.eee_ckdiv = true;
  2984. data = ocp_reg_read(tp, OCP_DOWN_SPEED);
  2985. data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV;
  2986. ocp_reg_write(tp, OCP_DOWN_SPEED, data);
  2987. tp->ups_info.eee_cmod_lv = true;
  2988. tp->ups_info._10m_ckdiv = true;
  2989. tp->ups_info.eee_plloff_giga = true;
  2990. ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
  2991. ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5));
  2992. tp->ups_info._250m_ckdiv = true;
  2993. r8153_patch_request(tp, false);
  2994. }
  2995. if (tp->eee_en)
  2996. rtl_eee_enable(tp, true);
  2997. r8153_aldps_en(tp, true);
  2998. r8152b_enable_fc(tp);
  2999. set_bit(PHY_RESET, &tp->flags);
  3000. }
  3001. static void r8153_first_init(struct r8152 *tp)
  3002. {
  3003. u32 ocp_data;
  3004. int i;
  3005. rxdy_gated_en(tp, true);
  3006. r8153_teredo_off(tp);
  3007. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  3008. ocp_data &= ~RCR_ACPT_ALL;
  3009. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  3010. rtl8152_nic_reset(tp);
  3011. rtl_reset_bmu(tp);
  3012. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  3013. ocp_data &= ~NOW_IS_OOB;
  3014. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  3015. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  3016. ocp_data &= ~MCU_BORW_EN;
  3017. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  3018. for (i = 0; i < 1000; i++) {
  3019. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  3020. if (ocp_data & LINK_LIST_READY)
  3021. break;
  3022. usleep_range(1000, 2000);
  3023. }
  3024. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  3025. ocp_data |= RE_INIT_LL;
  3026. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  3027. for (i = 0; i < 1000; i++) {
  3028. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  3029. if (ocp_data & LINK_LIST_READY)
  3030. break;
  3031. usleep_range(1000, 2000);
  3032. }
  3033. rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
  3034. ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
  3035. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
  3036. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
  3037. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
  3038. ocp_data |= TCR0_AUTO_FIFO;
  3039. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
  3040. rtl8152_nic_reset(tp);
  3041. /* rx share fifo credit full threshold */
  3042. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
  3043. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
  3044. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
  3045. /* TX share fifo free credit full threshold */
  3046. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
  3047. }
  3048. static void r8153_enter_oob(struct r8152 *tp)
  3049. {
  3050. u32 ocp_data;
  3051. int i;
  3052. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  3053. ocp_data &= ~NOW_IS_OOB;
  3054. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  3055. rtl_disable(tp);
  3056. rtl_reset_bmu(tp);
  3057. for (i = 0; i < 1000; i++) {
  3058. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  3059. if (ocp_data & LINK_LIST_READY)
  3060. break;
  3061. usleep_range(1000, 2000);
  3062. }
  3063. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  3064. ocp_data |= RE_INIT_LL;
  3065. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  3066. for (i = 0; i < 1000; i++) {
  3067. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  3068. if (ocp_data & LINK_LIST_READY)
  3069. break;
  3070. usleep_range(1000, 2000);
  3071. }
  3072. ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
  3073. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
  3074. switch (tp->version) {
  3075. case RTL_VER_03:
  3076. case RTL_VER_04:
  3077. case RTL_VER_05:
  3078. case RTL_VER_06:
  3079. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
  3080. ocp_data &= ~TEREDO_WAKE_MASK;
  3081. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
  3082. break;
  3083. case RTL_VER_08:
  3084. case RTL_VER_09:
  3085. /* Clear teredo wake event. bit[15:8] is the teredo wakeup
  3086. * type. Set it to zero. bits[7:0] are the W1C bits about
  3087. * the events. Set them to all 1 to clear them.
  3088. */
  3089. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
  3090. break;
  3091. default:
  3092. break;
  3093. }
  3094. rtl_rx_vlan_en(tp, true);
  3095. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
  3096. ocp_data |= ALDPS_PROXY_MODE;
  3097. ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
  3098. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  3099. ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
  3100. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  3101. rxdy_gated_en(tp, false);
  3102. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  3103. ocp_data |= RCR_APM | RCR_AM | RCR_AB;
  3104. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  3105. }
  3106. static void rtl8153_disable(struct r8152 *tp)
  3107. {
  3108. r8153_aldps_en(tp, false);
  3109. rtl_disable(tp);
  3110. rtl_reset_bmu(tp);
  3111. r8153_aldps_en(tp, true);
  3112. }
  3113. static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
  3114. u32 advertising)
  3115. {
  3116. u16 bmcr;
  3117. int ret = 0;
  3118. if (autoneg == AUTONEG_DISABLE) {
  3119. if (duplex != DUPLEX_HALF && duplex != DUPLEX_FULL)
  3120. return -EINVAL;
  3121. switch (speed) {
  3122. case SPEED_10:
  3123. bmcr = BMCR_SPEED10;
  3124. if (duplex == DUPLEX_FULL) {
  3125. bmcr |= BMCR_FULLDPLX;
  3126. tp->ups_info.speed_duplex = FORCE_10M_FULL;
  3127. } else {
  3128. tp->ups_info.speed_duplex = FORCE_10M_HALF;
  3129. }
  3130. break;
  3131. case SPEED_100:
  3132. bmcr = BMCR_SPEED100;
  3133. if (duplex == DUPLEX_FULL) {
  3134. bmcr |= BMCR_FULLDPLX;
  3135. tp->ups_info.speed_duplex = FORCE_100M_FULL;
  3136. } else {
  3137. tp->ups_info.speed_duplex = FORCE_100M_HALF;
  3138. }
  3139. break;
  3140. case SPEED_1000:
  3141. if (tp->mii.supports_gmii) {
  3142. bmcr = BMCR_SPEED1000 | BMCR_FULLDPLX;
  3143. tp->ups_info.speed_duplex = NWAY_1000M_FULL;
  3144. break;
  3145. }
  3146. /* fall through */
  3147. default:
  3148. ret = -EINVAL;
  3149. goto out;
  3150. }
  3151. if (duplex == DUPLEX_FULL)
  3152. tp->mii.full_duplex = 1;
  3153. else
  3154. tp->mii.full_duplex = 0;
  3155. tp->mii.force_media = 1;
  3156. } else {
  3157. u16 anar, tmp1;
  3158. u32 support;
  3159. support = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
  3160. RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
  3161. if (tp->mii.supports_gmii)
  3162. support |= RTL_ADVERTISED_1000_FULL;
  3163. if (!(advertising & support))
  3164. return -EINVAL;
  3165. anar = r8152_mdio_read(tp, MII_ADVERTISE);
  3166. tmp1 = anar & ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
  3167. ADVERTISE_100HALF | ADVERTISE_100FULL);
  3168. if (advertising & RTL_ADVERTISED_10_HALF) {
  3169. tmp1 |= ADVERTISE_10HALF;
  3170. tp->ups_info.speed_duplex = NWAY_10M_HALF;
  3171. }
  3172. if (advertising & RTL_ADVERTISED_10_FULL) {
  3173. tmp1 |= ADVERTISE_10FULL;
  3174. tp->ups_info.speed_duplex = NWAY_10M_FULL;
  3175. }
  3176. if (advertising & RTL_ADVERTISED_100_HALF) {
  3177. tmp1 |= ADVERTISE_100HALF;
  3178. tp->ups_info.speed_duplex = NWAY_100M_HALF;
  3179. }
  3180. if (advertising & RTL_ADVERTISED_100_FULL) {
  3181. tmp1 |= ADVERTISE_100FULL;
  3182. tp->ups_info.speed_duplex = NWAY_100M_FULL;
  3183. }
  3184. if (anar != tmp1) {
  3185. r8152_mdio_write(tp, MII_ADVERTISE, tmp1);
  3186. tp->mii.advertising = tmp1;
  3187. }
  3188. if (tp->mii.supports_gmii) {
  3189. u16 gbcr;
  3190. gbcr = r8152_mdio_read(tp, MII_CTRL1000);
  3191. tmp1 = gbcr & ~(ADVERTISE_1000FULL |
  3192. ADVERTISE_1000HALF);
  3193. if (advertising & RTL_ADVERTISED_1000_FULL) {
  3194. tmp1 |= ADVERTISE_1000FULL;
  3195. tp->ups_info.speed_duplex = NWAY_1000M_FULL;
  3196. }
  3197. if (gbcr != tmp1)
  3198. r8152_mdio_write(tp, MII_CTRL1000, tmp1);
  3199. }
  3200. bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
  3201. tp->mii.force_media = 0;
  3202. }
  3203. if (test_and_clear_bit(PHY_RESET, &tp->flags))
  3204. bmcr |= BMCR_RESET;
  3205. r8152_mdio_write(tp, MII_BMCR, bmcr);
  3206. if (bmcr & BMCR_RESET) {
  3207. int i;
  3208. for (i = 0; i < 50; i++) {
  3209. msleep(20);
  3210. if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
  3211. break;
  3212. }
  3213. }
  3214. out:
  3215. return ret;
  3216. }
  3217. static void rtl8152_up(struct r8152 *tp)
  3218. {
  3219. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  3220. return;
  3221. r8152_aldps_en(tp, false);
  3222. r8152b_exit_oob(tp);
  3223. r8152_aldps_en(tp, true);
  3224. }
  3225. static void rtl8152_down(struct r8152 *tp)
  3226. {
  3227. if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
  3228. rtl_drop_queued_tx(tp);
  3229. return;
  3230. }
  3231. r8152_power_cut_en(tp, false);
  3232. r8152_aldps_en(tp, false);
  3233. r8152b_enter_oob(tp);
  3234. r8152_aldps_en(tp, true);
  3235. }
  3236. static void rtl8153_up(struct r8152 *tp)
  3237. {
  3238. u32 ocp_data;
  3239. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  3240. return;
  3241. r8153_u1u2en(tp, false);
  3242. r8153_u2p3en(tp, false);
  3243. r8153_aldps_en(tp, false);
  3244. r8153_first_init(tp);
  3245. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
  3246. ocp_data |= LANWAKE_CLR_EN;
  3247. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
  3248. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
  3249. ocp_data &= ~LANWAKE_PIN;
  3250. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);
  3251. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1);
  3252. ocp_data &= ~DELAY_PHY_PWR_CHG;
  3253. ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1, ocp_data);
  3254. r8153_aldps_en(tp, true);
  3255. switch (tp->version) {
  3256. case RTL_VER_03:
  3257. case RTL_VER_04:
  3258. break;
  3259. case RTL_VER_05:
  3260. case RTL_VER_06:
  3261. default:
  3262. r8153_u2p3en(tp, true);
  3263. break;
  3264. }
  3265. r8153_u1u2en(tp, true);
  3266. }
  3267. static void rtl8153_down(struct r8152 *tp)
  3268. {
  3269. u32 ocp_data;
  3270. if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
  3271. rtl_drop_queued_tx(tp);
  3272. return;
  3273. }
  3274. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
  3275. ocp_data &= ~LANWAKE_CLR_EN;
  3276. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
  3277. r8153_u1u2en(tp, false);
  3278. r8153_u2p3en(tp, false);
  3279. r8153_power_cut_en(tp, false);
  3280. r8153_aldps_en(tp, false);
  3281. r8153_enter_oob(tp);
  3282. r8153_aldps_en(tp, true);
  3283. }
  3284. static void rtl8153b_up(struct r8152 *tp)
  3285. {
  3286. u32 ocp_data;
  3287. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  3288. return;
  3289. r8153b_u1u2en(tp, false);
  3290. r8153_u2p3en(tp, false);
  3291. r8153_aldps_en(tp, false);
  3292. r8153_first_init(tp);
  3293. ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
  3294. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
  3295. ocp_data &= ~PLA_MCU_SPDWN_EN;
  3296. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
  3297. r8153_aldps_en(tp, true);
  3298. r8153b_u1u2en(tp, true);
  3299. }
  3300. static void rtl8153b_down(struct r8152 *tp)
  3301. {
  3302. u32 ocp_data;
  3303. if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
  3304. rtl_drop_queued_tx(tp);
  3305. return;
  3306. }
  3307. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
  3308. ocp_data |= PLA_MCU_SPDWN_EN;
  3309. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
  3310. r8153b_u1u2en(tp, false);
  3311. r8153_u2p3en(tp, false);
  3312. r8153b_power_cut_en(tp, false);
  3313. r8153_aldps_en(tp, false);
  3314. r8153_enter_oob(tp);
  3315. r8153_aldps_en(tp, true);
  3316. }
  3317. static bool rtl8152_in_nway(struct r8152 *tp)
  3318. {
  3319. u16 nway_state;
  3320. ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
  3321. tp->ocp_base = 0x2000;
  3322. ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */
  3323. nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
  3324. /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
  3325. if (nway_state & 0xc000)
  3326. return false;
  3327. else
  3328. return true;
  3329. }
  3330. static bool rtl8153_in_nway(struct r8152 *tp)
  3331. {
  3332. u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
  3333. if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
  3334. return false;
  3335. else
  3336. return true;
  3337. }
  3338. static void set_carrier(struct r8152 *tp)
  3339. {
  3340. struct net_device *netdev = tp->netdev;
  3341. struct napi_struct *napi = &tp->napi;
  3342. u8 speed;
  3343. speed = rtl8152_get_speed(tp);
  3344. if (speed & LINK_STATUS) {
  3345. if (!netif_carrier_ok(netdev)) {
  3346. tp->rtl_ops.enable(tp);
  3347. netif_stop_queue(netdev);
  3348. napi_disable(napi);
  3349. netif_carrier_on(netdev);
  3350. rtl_start_rx(tp);
  3351. clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
  3352. _rtl8152_set_rx_mode(netdev);
  3353. napi_enable(&tp->napi);
  3354. netif_wake_queue(netdev);
  3355. netif_info(tp, link, netdev, "carrier on\n");
  3356. } else if (netif_queue_stopped(netdev) &&
  3357. skb_queue_len(&tp->tx_queue) < tp->tx_qlen) {
  3358. netif_wake_queue(netdev);
  3359. }
  3360. } else {
  3361. if (netif_carrier_ok(netdev)) {
  3362. netif_carrier_off(netdev);
  3363. tasklet_disable(&tp->tx_tl);
  3364. napi_disable(napi);
  3365. tp->rtl_ops.disable(tp);
  3366. napi_enable(napi);
  3367. tasklet_enable(&tp->tx_tl);
  3368. netif_info(tp, link, netdev, "carrier off\n");
  3369. }
  3370. }
  3371. }
  3372. static void rtl_work_func_t(struct work_struct *work)
  3373. {
  3374. struct r8152 *tp = container_of(work, struct r8152, schedule.work);
  3375. /* If the device is unplugged or !netif_running(), the workqueue
  3376. * doesn't need to wake the device, and could return directly.
  3377. */
  3378. if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
  3379. return;
  3380. if (usb_autopm_get_interface(tp->intf) < 0)
  3381. return;
  3382. if (!test_bit(WORK_ENABLE, &tp->flags))
  3383. goto out1;
  3384. if (!mutex_trylock(&tp->control)) {
  3385. schedule_delayed_work(&tp->schedule, 0);
  3386. goto out1;
  3387. }
  3388. if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
  3389. set_carrier(tp);
  3390. if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
  3391. _rtl8152_set_rx_mode(tp->netdev);
  3392. /* don't schedule tasket before linking */
  3393. if (test_and_clear_bit(SCHEDULE_TASKLET, &tp->flags) &&
  3394. netif_carrier_ok(tp->netdev))
  3395. tasklet_schedule(&tp->tx_tl);
  3396. mutex_unlock(&tp->control);
  3397. out1:
  3398. usb_autopm_put_interface(tp->intf);
  3399. }
  3400. static void rtl_hw_phy_work_func_t(struct work_struct *work)
  3401. {
  3402. struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
  3403. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  3404. return;
  3405. if (usb_autopm_get_interface(tp->intf) < 0)
  3406. return;
  3407. mutex_lock(&tp->control);
  3408. tp->rtl_ops.hw_phy_cfg(tp);
  3409. rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex,
  3410. tp->advertising);
  3411. mutex_unlock(&tp->control);
  3412. usb_autopm_put_interface(tp->intf);
  3413. }
  3414. #ifdef CONFIG_PM_SLEEP
  3415. static int rtl_notifier(struct notifier_block *nb, unsigned long action,
  3416. void *data)
  3417. {
  3418. struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
  3419. switch (action) {
  3420. case PM_HIBERNATION_PREPARE:
  3421. case PM_SUSPEND_PREPARE:
  3422. usb_autopm_get_interface(tp->intf);
  3423. break;
  3424. case PM_POST_HIBERNATION:
  3425. case PM_POST_SUSPEND:
  3426. usb_autopm_put_interface(tp->intf);
  3427. break;
  3428. case PM_POST_RESTORE:
  3429. case PM_RESTORE_PREPARE:
  3430. default:
  3431. break;
  3432. }
  3433. return NOTIFY_DONE;
  3434. }
  3435. #endif
  3436. static int rtl8152_open(struct net_device *netdev)
  3437. {
  3438. struct r8152 *tp = netdev_priv(netdev);
  3439. int res = 0;
  3440. res = alloc_all_mem(tp);
  3441. if (res)
  3442. goto out;
  3443. res = usb_autopm_get_interface(tp->intf);
  3444. if (res < 0)
  3445. goto out_free;
  3446. mutex_lock(&tp->control);
  3447. tp->rtl_ops.up(tp);
  3448. netif_carrier_off(netdev);
  3449. netif_start_queue(netdev);
  3450. set_bit(WORK_ENABLE, &tp->flags);
  3451. res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
  3452. if (res) {
  3453. if (res == -ENODEV)
  3454. netif_device_detach(tp->netdev);
  3455. netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
  3456. res);
  3457. goto out_unlock;
  3458. }
  3459. napi_enable(&tp->napi);
  3460. tasklet_enable(&tp->tx_tl);
  3461. mutex_unlock(&tp->control);
  3462. usb_autopm_put_interface(tp->intf);
  3463. #ifdef CONFIG_PM_SLEEP
  3464. tp->pm_notifier.notifier_call = rtl_notifier;
  3465. register_pm_notifier(&tp->pm_notifier);
  3466. #endif
  3467. return 0;
  3468. out_unlock:
  3469. mutex_unlock(&tp->control);
  3470. usb_autopm_put_interface(tp->intf);
  3471. out_free:
  3472. free_all_mem(tp);
  3473. out:
  3474. return res;
  3475. }
  3476. static int rtl8152_close(struct net_device *netdev)
  3477. {
  3478. struct r8152 *tp = netdev_priv(netdev);
  3479. int res = 0;
  3480. #ifdef CONFIG_PM_SLEEP
  3481. unregister_pm_notifier(&tp->pm_notifier);
  3482. #endif
  3483. tasklet_disable(&tp->tx_tl);
  3484. clear_bit(WORK_ENABLE, &tp->flags);
  3485. usb_kill_urb(tp->intr_urb);
  3486. cancel_delayed_work_sync(&tp->schedule);
  3487. napi_disable(&tp->napi);
  3488. netif_stop_queue(netdev);
  3489. res = usb_autopm_get_interface(tp->intf);
  3490. if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
  3491. rtl_drop_queued_tx(tp);
  3492. rtl_stop_rx(tp);
  3493. } else {
  3494. mutex_lock(&tp->control);
  3495. tp->rtl_ops.down(tp);
  3496. mutex_unlock(&tp->control);
  3497. }
  3498. if (!res)
  3499. usb_autopm_put_interface(tp->intf);
  3500. free_all_mem(tp);
  3501. return res;
  3502. }
  3503. static void rtl_tally_reset(struct r8152 *tp)
  3504. {
  3505. u32 ocp_data;
  3506. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
  3507. ocp_data |= TALLY_RESET;
  3508. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
  3509. }
  3510. static void r8152b_init(struct r8152 *tp)
  3511. {
  3512. u32 ocp_data;
  3513. u16 data;
  3514. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  3515. return;
  3516. data = r8152_mdio_read(tp, MII_BMCR);
  3517. if (data & BMCR_PDOWN) {
  3518. data &= ~BMCR_PDOWN;
  3519. r8152_mdio_write(tp, MII_BMCR, data);
  3520. }
  3521. r8152_aldps_en(tp, false);
  3522. if (tp->version == RTL_VER_01) {
  3523. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
  3524. ocp_data &= ~LED_MODE_MASK;
  3525. ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
  3526. }
  3527. r8152_power_cut_en(tp, false);
  3528. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
  3529. ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
  3530. ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
  3531. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
  3532. ocp_data &= ~MCU_CLK_RATIO_MASK;
  3533. ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
  3534. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
  3535. ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
  3536. SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
  3537. ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
  3538. rtl_tally_reset(tp);
  3539. /* enable rx aggregation */
  3540. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
  3541. ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
  3542. ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
  3543. }
  3544. static void r8153_init(struct r8152 *tp)
  3545. {
  3546. u32 ocp_data;
  3547. u16 data;
  3548. int i;
  3549. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  3550. return;
  3551. r8153_u1u2en(tp, false);
  3552. for (i = 0; i < 500; i++) {
  3553. if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
  3554. AUTOLOAD_DONE)
  3555. break;
  3556. msleep(20);
  3557. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  3558. break;
  3559. }
  3560. data = r8153_phy_status(tp, 0);
  3561. if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
  3562. tp->version == RTL_VER_05)
  3563. ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
  3564. data = r8152_mdio_read(tp, MII_BMCR);
  3565. if (data & BMCR_PDOWN) {
  3566. data &= ~BMCR_PDOWN;
  3567. r8152_mdio_write(tp, MII_BMCR, data);
  3568. }
  3569. data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
  3570. r8153_u2p3en(tp, false);
  3571. if (tp->version == RTL_VER_04) {
  3572. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
  3573. ocp_data &= ~pwd_dn_scale_mask;
  3574. ocp_data |= pwd_dn_scale(96);
  3575. ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
  3576. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
  3577. ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
  3578. ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
  3579. } else if (tp->version == RTL_VER_05) {
  3580. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
  3581. ocp_data &= ~ECM_ALDPS;
  3582. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
  3583. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
  3584. if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
  3585. ocp_data &= ~DYNAMIC_BURST;
  3586. else
  3587. ocp_data |= DYNAMIC_BURST;
  3588. ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
  3589. } else if (tp->version == RTL_VER_06) {
  3590. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
  3591. if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
  3592. ocp_data &= ~DYNAMIC_BURST;
  3593. else
  3594. ocp_data |= DYNAMIC_BURST;
  3595. ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
  3596. }
  3597. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
  3598. ocp_data |= EP4_FULL_FC;
  3599. ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
  3600. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
  3601. ocp_data &= ~TIMER11_EN;
  3602. ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
  3603. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
  3604. ocp_data &= ~LED_MODE_MASK;
  3605. ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
  3606. ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
  3607. if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
  3608. ocp_data |= LPM_TIMER_500MS;
  3609. else
  3610. ocp_data |= LPM_TIMER_500US;
  3611. ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
  3612. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
  3613. ocp_data &= ~SEN_VAL_MASK;
  3614. ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
  3615. ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
  3616. ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
  3617. /* MAC clock speed down */
  3618. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0);
  3619. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0);
  3620. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0);
  3621. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0);
  3622. r8153_power_cut_en(tp, false);
  3623. r8153_u1u2en(tp, true);
  3624. usb_enable_lpm(tp->udev);
  3625. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
  3626. ocp_data |= LANWAKE_CLR_EN;
  3627. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
  3628. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
  3629. ocp_data &= ~LANWAKE_PIN;
  3630. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);
  3631. /* rx aggregation */
  3632. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
  3633. ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
  3634. if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
  3635. ocp_data |= RX_AGG_DISABLE;
  3636. ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
  3637. rtl_tally_reset(tp);
  3638. switch (tp->udev->speed) {
  3639. case USB_SPEED_SUPER:
  3640. case USB_SPEED_SUPER_PLUS:
  3641. tp->coalesce = COALESCE_SUPER;
  3642. break;
  3643. case USB_SPEED_HIGH:
  3644. tp->coalesce = COALESCE_HIGH;
  3645. break;
  3646. default:
  3647. tp->coalesce = COALESCE_SLOW;
  3648. break;
  3649. }
  3650. }
  3651. static void r8153b_init(struct r8152 *tp)
  3652. {
  3653. u32 ocp_data;
  3654. u16 data;
  3655. int i;
  3656. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  3657. return;
  3658. r8153b_u1u2en(tp, false);
  3659. for (i = 0; i < 500; i++) {
  3660. if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
  3661. AUTOLOAD_DONE)
  3662. break;
  3663. msleep(20);
  3664. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  3665. break;
  3666. }
  3667. data = r8153_phy_status(tp, 0);
  3668. data = r8152_mdio_read(tp, MII_BMCR);
  3669. if (data & BMCR_PDOWN) {
  3670. data &= ~BMCR_PDOWN;
  3671. r8152_mdio_write(tp, MII_BMCR, data);
  3672. }
  3673. data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
  3674. r8153_u2p3en(tp, false);
  3675. /* MSC timer = 0xfff * 8ms = 32760 ms */
  3676. ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
  3677. /* U1/U2/L1 idle timer. 500 us */
  3678. ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
  3679. r8153b_power_cut_en(tp, false);
  3680. r8153b_ups_en(tp, false);
  3681. r8153_queue_wake(tp, false);
  3682. rtl_runtime_suspend_enable(tp, false);
  3683. r8153b_u1u2en(tp, true);
  3684. usb_enable_lpm(tp->udev);
  3685. /* MAC clock speed down */
  3686. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
  3687. ocp_data |= MAC_CLK_SPDWN_EN;
  3688. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
  3689. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
  3690. ocp_data &= ~PLA_MCU_SPDWN_EN;
  3691. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
  3692. if (tp->version == RTL_VER_09) {
  3693. /* Disable Test IO for 32QFN */
  3694. if (ocp_read_byte(tp, MCU_TYPE_PLA, 0xdc00) & BIT(5)) {
  3695. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
  3696. ocp_data |= TEST_IO_OFF;
  3697. ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
  3698. }
  3699. }
  3700. set_bit(GREEN_ETHERNET, &tp->flags);
  3701. /* rx aggregation */
  3702. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
  3703. ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
  3704. ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
  3705. rtl_tally_reset(tp);
  3706. tp->coalesce = 15000; /* 15 us */
  3707. }
  3708. static int rtl8152_pre_reset(struct usb_interface *intf)
  3709. {
  3710. struct r8152 *tp = usb_get_intfdata(intf);
  3711. struct net_device *netdev;
  3712. if (!tp)
  3713. return 0;
  3714. netdev = tp->netdev;
  3715. if (!netif_running(netdev))
  3716. return 0;
  3717. netif_stop_queue(netdev);
  3718. tasklet_disable(&tp->tx_tl);
  3719. clear_bit(WORK_ENABLE, &tp->flags);
  3720. usb_kill_urb(tp->intr_urb);
  3721. cancel_delayed_work_sync(&tp->schedule);
  3722. napi_disable(&tp->napi);
  3723. if (netif_carrier_ok(netdev)) {
  3724. mutex_lock(&tp->control);
  3725. tp->rtl_ops.disable(tp);
  3726. mutex_unlock(&tp->control);
  3727. }
  3728. return 0;
  3729. }
  3730. static int rtl8152_post_reset(struct usb_interface *intf)
  3731. {
  3732. struct r8152 *tp = usb_get_intfdata(intf);
  3733. struct net_device *netdev;
  3734. struct sockaddr sa;
  3735. if (!tp)
  3736. return 0;
  3737. /* reset the MAC adddress in case of policy change */
  3738. if (determine_ethernet_addr(tp, &sa) >= 0) {
  3739. rtnl_lock();
  3740. dev_set_mac_address (tp->netdev, &sa, NULL);
  3741. rtnl_unlock();
  3742. }
  3743. netdev = tp->netdev;
  3744. if (!netif_running(netdev))
  3745. return 0;
  3746. set_bit(WORK_ENABLE, &tp->flags);
  3747. if (netif_carrier_ok(netdev)) {
  3748. mutex_lock(&tp->control);
  3749. tp->rtl_ops.enable(tp);
  3750. rtl_start_rx(tp);
  3751. _rtl8152_set_rx_mode(netdev);
  3752. mutex_unlock(&tp->control);
  3753. }
  3754. napi_enable(&tp->napi);
  3755. tasklet_enable(&tp->tx_tl);
  3756. netif_wake_queue(netdev);
  3757. usb_submit_urb(tp->intr_urb, GFP_KERNEL);
  3758. if (!list_empty(&tp->rx_done))
  3759. napi_schedule(&tp->napi);
  3760. return 0;
  3761. }
  3762. static bool delay_autosuspend(struct r8152 *tp)
  3763. {
  3764. bool sw_linking = !!netif_carrier_ok(tp->netdev);
  3765. bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
  3766. /* This means a linking change occurs and the driver doesn't detect it,
  3767. * yet. If the driver has disabled tx/rx and hw is linking on, the
  3768. * device wouldn't wake up by receiving any packet.
  3769. */
  3770. if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
  3771. return true;
  3772. /* If the linking down is occurred by nway, the device may miss the
  3773. * linking change event. And it wouldn't wake when linking on.
  3774. */
  3775. if (!sw_linking && tp->rtl_ops.in_nway(tp))
  3776. return true;
  3777. else if (!skb_queue_empty(&tp->tx_queue))
  3778. return true;
  3779. else
  3780. return false;
  3781. }
  3782. static int rtl8152_runtime_resume(struct r8152 *tp)
  3783. {
  3784. struct net_device *netdev = tp->netdev;
  3785. if (netif_running(netdev) && netdev->flags & IFF_UP) {
  3786. struct napi_struct *napi = &tp->napi;
  3787. tp->rtl_ops.autosuspend_en(tp, false);
  3788. napi_disable(napi);
  3789. set_bit(WORK_ENABLE, &tp->flags);
  3790. if (netif_carrier_ok(netdev)) {
  3791. if (rtl8152_get_speed(tp) & LINK_STATUS) {
  3792. rtl_start_rx(tp);
  3793. } else {
  3794. netif_carrier_off(netdev);
  3795. tp->rtl_ops.disable(tp);
  3796. netif_info(tp, link, netdev, "linking down\n");
  3797. }
  3798. }
  3799. napi_enable(napi);
  3800. clear_bit(SELECTIVE_SUSPEND, &tp->flags);
  3801. smp_mb__after_atomic();
  3802. if (!list_empty(&tp->rx_done))
  3803. napi_schedule(&tp->napi);
  3804. usb_submit_urb(tp->intr_urb, GFP_NOIO);
  3805. } else {
  3806. if (netdev->flags & IFF_UP)
  3807. tp->rtl_ops.autosuspend_en(tp, false);
  3808. clear_bit(SELECTIVE_SUSPEND, &tp->flags);
  3809. }
  3810. return 0;
  3811. }
  3812. static int rtl8152_system_resume(struct r8152 *tp)
  3813. {
  3814. struct net_device *netdev = tp->netdev;
  3815. netif_device_attach(netdev);
  3816. if (netif_running(netdev) && (netdev->flags & IFF_UP)) {
  3817. tp->rtl_ops.up(tp);
  3818. netif_carrier_off(netdev);
  3819. set_bit(WORK_ENABLE, &tp->flags);
  3820. usb_submit_urb(tp->intr_urb, GFP_NOIO);
  3821. }
  3822. return 0;
  3823. }
  3824. static int rtl8152_runtime_suspend(struct r8152 *tp)
  3825. {
  3826. struct net_device *netdev = tp->netdev;
  3827. int ret = 0;
  3828. set_bit(SELECTIVE_SUSPEND, &tp->flags);
  3829. smp_mb__after_atomic();
  3830. if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
  3831. u32 rcr = 0;
  3832. if (netif_carrier_ok(netdev)) {
  3833. u32 ocp_data;
  3834. rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  3835. ocp_data = rcr & ~RCR_ACPT_ALL;
  3836. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  3837. rxdy_gated_en(tp, true);
  3838. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
  3839. PLA_OOB_CTRL);
  3840. if (!(ocp_data & RXFIFO_EMPTY)) {
  3841. rxdy_gated_en(tp, false);
  3842. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
  3843. clear_bit(SELECTIVE_SUSPEND, &tp->flags);
  3844. smp_mb__after_atomic();
  3845. ret = -EBUSY;
  3846. goto out1;
  3847. }
  3848. }
  3849. clear_bit(WORK_ENABLE, &tp->flags);
  3850. usb_kill_urb(tp->intr_urb);
  3851. tp->rtl_ops.autosuspend_en(tp, true);
  3852. if (netif_carrier_ok(netdev)) {
  3853. struct napi_struct *napi = &tp->napi;
  3854. napi_disable(napi);
  3855. rtl_stop_rx(tp);
  3856. rxdy_gated_en(tp, false);
  3857. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
  3858. napi_enable(napi);
  3859. }
  3860. if (delay_autosuspend(tp)) {
  3861. rtl8152_runtime_resume(tp);
  3862. ret = -EBUSY;
  3863. }
  3864. }
  3865. out1:
  3866. return ret;
  3867. }
  3868. static int rtl8152_system_suspend(struct r8152 *tp)
  3869. {
  3870. struct net_device *netdev = tp->netdev;
  3871. netif_device_detach(netdev);
  3872. if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
  3873. struct napi_struct *napi = &tp->napi;
  3874. clear_bit(WORK_ENABLE, &tp->flags);
  3875. usb_kill_urb(tp->intr_urb);
  3876. tasklet_disable(&tp->tx_tl);
  3877. napi_disable(napi);
  3878. cancel_delayed_work_sync(&tp->schedule);
  3879. tp->rtl_ops.down(tp);
  3880. napi_enable(napi);
  3881. tasklet_enable(&tp->tx_tl);
  3882. }
  3883. return 0;
  3884. }
  3885. static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
  3886. {
  3887. struct r8152 *tp = usb_get_intfdata(intf);
  3888. int ret;
  3889. mutex_lock(&tp->control);
  3890. if (PMSG_IS_AUTO(message))
  3891. ret = rtl8152_runtime_suspend(tp);
  3892. else
  3893. ret = rtl8152_system_suspend(tp);
  3894. mutex_unlock(&tp->control);
  3895. return ret;
  3896. }
  3897. static int rtl8152_resume(struct usb_interface *intf)
  3898. {
  3899. struct r8152 *tp = usb_get_intfdata(intf);
  3900. int ret;
  3901. mutex_lock(&tp->control);
  3902. if (test_bit(SELECTIVE_SUSPEND, &tp->flags))
  3903. ret = rtl8152_runtime_resume(tp);
  3904. else
  3905. ret = rtl8152_system_resume(tp);
  3906. mutex_unlock(&tp->control);
  3907. return ret;
  3908. }
  3909. static int rtl8152_reset_resume(struct usb_interface *intf)
  3910. {
  3911. struct r8152 *tp = usb_get_intfdata(intf);
  3912. clear_bit(SELECTIVE_SUSPEND, &tp->flags);
  3913. tp->rtl_ops.init(tp);
  3914. queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
  3915. set_ethernet_addr(tp);
  3916. return rtl8152_resume(intf);
  3917. }
  3918. static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  3919. {
  3920. struct r8152 *tp = netdev_priv(dev);
  3921. if (usb_autopm_get_interface(tp->intf) < 0)
  3922. return;
  3923. if (!rtl_can_wakeup(tp)) {
  3924. wol->supported = 0;
  3925. wol->wolopts = 0;
  3926. } else {
  3927. mutex_lock(&tp->control);
  3928. wol->supported = WAKE_ANY;
  3929. wol->wolopts = __rtl_get_wol(tp);
  3930. mutex_unlock(&tp->control);
  3931. }
  3932. usb_autopm_put_interface(tp->intf);
  3933. }
  3934. static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  3935. {
  3936. struct r8152 *tp = netdev_priv(dev);
  3937. int ret;
  3938. if (!rtl_can_wakeup(tp))
  3939. return -EOPNOTSUPP;
  3940. if (wol->wolopts & ~WAKE_ANY)
  3941. return -EINVAL;
  3942. ret = usb_autopm_get_interface(tp->intf);
  3943. if (ret < 0)
  3944. goto out_set_wol;
  3945. mutex_lock(&tp->control);
  3946. __rtl_set_wol(tp, wol->wolopts);
  3947. tp->saved_wolopts = wol->wolopts & WAKE_ANY;
  3948. mutex_unlock(&tp->control);
  3949. usb_autopm_put_interface(tp->intf);
  3950. out_set_wol:
  3951. return ret;
  3952. }
  3953. static u32 rtl8152_get_msglevel(struct net_device *dev)
  3954. {
  3955. struct r8152 *tp = netdev_priv(dev);
  3956. return tp->msg_enable;
  3957. }
  3958. static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
  3959. {
  3960. struct r8152 *tp = netdev_priv(dev);
  3961. tp->msg_enable = value;
  3962. }
  3963. static void rtl8152_get_drvinfo(struct net_device *netdev,
  3964. struct ethtool_drvinfo *info)
  3965. {
  3966. struct r8152 *tp = netdev_priv(netdev);
  3967. strlcpy(info->driver, MODULENAME, sizeof(info->driver));
  3968. strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
  3969. usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
  3970. }
  3971. static
  3972. int rtl8152_get_link_ksettings(struct net_device *netdev,
  3973. struct ethtool_link_ksettings *cmd)
  3974. {
  3975. struct r8152 *tp = netdev_priv(netdev);
  3976. int ret;
  3977. if (!tp->mii.mdio_read)
  3978. return -EOPNOTSUPP;
  3979. ret = usb_autopm_get_interface(tp->intf);
  3980. if (ret < 0)
  3981. goto out;
  3982. mutex_lock(&tp->control);
  3983. mii_ethtool_get_link_ksettings(&tp->mii, cmd);
  3984. mutex_unlock(&tp->control);
  3985. usb_autopm_put_interface(tp->intf);
  3986. out:
  3987. return ret;
  3988. }
  3989. static int rtl8152_set_link_ksettings(struct net_device *dev,
  3990. const struct ethtool_link_ksettings *cmd)
  3991. {
  3992. struct r8152 *tp = netdev_priv(dev);
  3993. u32 advertising = 0;
  3994. int ret;
  3995. ret = usb_autopm_get_interface(tp->intf);
  3996. if (ret < 0)
  3997. goto out;
  3998. if (test_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
  3999. cmd->link_modes.advertising))
  4000. advertising |= RTL_ADVERTISED_10_HALF;
  4001. if (test_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
  4002. cmd->link_modes.advertising))
  4003. advertising |= RTL_ADVERTISED_10_FULL;
  4004. if (test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
  4005. cmd->link_modes.advertising))
  4006. advertising |= RTL_ADVERTISED_100_HALF;
  4007. if (test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
  4008. cmd->link_modes.advertising))
  4009. advertising |= RTL_ADVERTISED_100_FULL;
  4010. if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
  4011. cmd->link_modes.advertising))
  4012. advertising |= RTL_ADVERTISED_1000_HALF;
  4013. if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
  4014. cmd->link_modes.advertising))
  4015. advertising |= RTL_ADVERTISED_1000_FULL;
  4016. mutex_lock(&tp->control);
  4017. ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed,
  4018. cmd->base.duplex, advertising);
  4019. if (!ret) {
  4020. tp->autoneg = cmd->base.autoneg;
  4021. tp->speed = cmd->base.speed;
  4022. tp->duplex = cmd->base.duplex;
  4023. tp->advertising = advertising;
  4024. }
  4025. mutex_unlock(&tp->control);
  4026. usb_autopm_put_interface(tp->intf);
  4027. out:
  4028. return ret;
  4029. }
  4030. static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
  4031. "tx_packets",
  4032. "rx_packets",
  4033. "tx_errors",
  4034. "rx_errors",
  4035. "rx_missed",
  4036. "align_errors",
  4037. "tx_single_collisions",
  4038. "tx_multi_collisions",
  4039. "rx_unicast",
  4040. "rx_broadcast",
  4041. "rx_multicast",
  4042. "tx_aborted",
  4043. "tx_underrun",
  4044. };
  4045. static int rtl8152_get_sset_count(struct net_device *dev, int sset)
  4046. {
  4047. switch (sset) {
  4048. case ETH_SS_STATS:
  4049. return ARRAY_SIZE(rtl8152_gstrings);
  4050. default:
  4051. return -EOPNOTSUPP;
  4052. }
  4053. }
  4054. static void rtl8152_get_ethtool_stats(struct net_device *dev,
  4055. struct ethtool_stats *stats, u64 *data)
  4056. {
  4057. struct r8152 *tp = netdev_priv(dev);
  4058. struct tally_counter tally;
  4059. if (usb_autopm_get_interface(tp->intf) < 0)
  4060. return;
  4061. generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
  4062. usb_autopm_put_interface(tp->intf);
  4063. data[0] = le64_to_cpu(tally.tx_packets);
  4064. data[1] = le64_to_cpu(tally.rx_packets);
  4065. data[2] = le64_to_cpu(tally.tx_errors);
  4066. data[3] = le32_to_cpu(tally.rx_errors);
  4067. data[4] = le16_to_cpu(tally.rx_missed);
  4068. data[5] = le16_to_cpu(tally.align_errors);
  4069. data[6] = le32_to_cpu(tally.tx_one_collision);
  4070. data[7] = le32_to_cpu(tally.tx_multi_collision);
  4071. data[8] = le64_to_cpu(tally.rx_unicast);
  4072. data[9] = le64_to_cpu(tally.rx_broadcast);
  4073. data[10] = le32_to_cpu(tally.rx_multicast);
  4074. data[11] = le16_to_cpu(tally.tx_aborted);
  4075. data[12] = le16_to_cpu(tally.tx_underrun);
  4076. }
  4077. static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  4078. {
  4079. switch (stringset) {
  4080. case ETH_SS_STATS:
  4081. memcpy(data, rtl8152_gstrings, sizeof(rtl8152_gstrings));
  4082. break;
  4083. }
  4084. }
  4085. static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
  4086. {
  4087. u32 lp, adv, supported = 0;
  4088. u16 val;
  4089. val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
  4090. supported = mmd_eee_cap_to_ethtool_sup_t(val);
  4091. val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
  4092. adv = mmd_eee_adv_to_ethtool_adv_t(val);
  4093. val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
  4094. lp = mmd_eee_adv_to_ethtool_adv_t(val);
  4095. eee->eee_enabled = tp->eee_en;
  4096. eee->eee_active = !!(supported & adv & lp);
  4097. eee->supported = supported;
  4098. eee->advertised = tp->eee_adv;
  4099. eee->lp_advertised = lp;
  4100. return 0;
  4101. }
  4102. static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
  4103. {
  4104. u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
  4105. tp->eee_en = eee->eee_enabled;
  4106. tp->eee_adv = val;
  4107. rtl_eee_enable(tp, tp->eee_en);
  4108. return 0;
  4109. }
  4110. static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
  4111. {
  4112. u32 lp, adv, supported = 0;
  4113. u16 val;
  4114. val = ocp_reg_read(tp, OCP_EEE_ABLE);
  4115. supported = mmd_eee_cap_to_ethtool_sup_t(val);
  4116. val = ocp_reg_read(tp, OCP_EEE_ADV);
  4117. adv = mmd_eee_adv_to_ethtool_adv_t(val);
  4118. val = ocp_reg_read(tp, OCP_EEE_LPABLE);
  4119. lp = mmd_eee_adv_to_ethtool_adv_t(val);
  4120. eee->eee_enabled = tp->eee_en;
  4121. eee->eee_active = !!(supported & adv & lp);
  4122. eee->supported = supported;
  4123. eee->advertised = tp->eee_adv;
  4124. eee->lp_advertised = lp;
  4125. return 0;
  4126. }
  4127. static int
  4128. rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
  4129. {
  4130. struct r8152 *tp = netdev_priv(net);
  4131. int ret;
  4132. ret = usb_autopm_get_interface(tp->intf);
  4133. if (ret < 0)
  4134. goto out;
  4135. mutex_lock(&tp->control);
  4136. ret = tp->rtl_ops.eee_get(tp, edata);
  4137. mutex_unlock(&tp->control);
  4138. usb_autopm_put_interface(tp->intf);
  4139. out:
  4140. return ret;
  4141. }
  4142. static int
  4143. rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
  4144. {
  4145. struct r8152 *tp = netdev_priv(net);
  4146. int ret;
  4147. ret = usb_autopm_get_interface(tp->intf);
  4148. if (ret < 0)
  4149. goto out;
  4150. mutex_lock(&tp->control);
  4151. ret = tp->rtl_ops.eee_set(tp, edata);
  4152. if (!ret)
  4153. ret = mii_nway_restart(&tp->mii);
  4154. mutex_unlock(&tp->control);
  4155. usb_autopm_put_interface(tp->intf);
  4156. out:
  4157. return ret;
  4158. }
  4159. static int rtl8152_nway_reset(struct net_device *dev)
  4160. {
  4161. struct r8152 *tp = netdev_priv(dev);
  4162. int ret;
  4163. ret = usb_autopm_get_interface(tp->intf);
  4164. if (ret < 0)
  4165. goto out;
  4166. mutex_lock(&tp->control);
  4167. ret = mii_nway_restart(&tp->mii);
  4168. mutex_unlock(&tp->control);
  4169. usb_autopm_put_interface(tp->intf);
  4170. out:
  4171. return ret;
  4172. }
  4173. static int rtl8152_get_coalesce(struct net_device *netdev,
  4174. struct ethtool_coalesce *coalesce)
  4175. {
  4176. struct r8152 *tp = netdev_priv(netdev);
  4177. switch (tp->version) {
  4178. case RTL_VER_01:
  4179. case RTL_VER_02:
  4180. case RTL_VER_07:
  4181. return -EOPNOTSUPP;
  4182. default:
  4183. break;
  4184. }
  4185. coalesce->rx_coalesce_usecs = tp->coalesce;
  4186. return 0;
  4187. }
  4188. static int rtl8152_set_coalesce(struct net_device *netdev,
  4189. struct ethtool_coalesce *coalesce)
  4190. {
  4191. struct r8152 *tp = netdev_priv(netdev);
  4192. int ret;
  4193. switch (tp->version) {
  4194. case RTL_VER_01:
  4195. case RTL_VER_02:
  4196. case RTL_VER_07:
  4197. return -EOPNOTSUPP;
  4198. default:
  4199. break;
  4200. }
  4201. if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
  4202. return -EINVAL;
  4203. ret = usb_autopm_get_interface(tp->intf);
  4204. if (ret < 0)
  4205. return ret;
  4206. mutex_lock(&tp->control);
  4207. if (tp->coalesce != coalesce->rx_coalesce_usecs) {
  4208. tp->coalesce = coalesce->rx_coalesce_usecs;
  4209. if (netif_running(netdev) && netif_carrier_ok(netdev)) {
  4210. netif_stop_queue(netdev);
  4211. napi_disable(&tp->napi);
  4212. tp->rtl_ops.disable(tp);
  4213. tp->rtl_ops.enable(tp);
  4214. rtl_start_rx(tp);
  4215. clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
  4216. _rtl8152_set_rx_mode(netdev);
  4217. napi_enable(&tp->napi);
  4218. netif_wake_queue(netdev);
  4219. }
  4220. }
  4221. mutex_unlock(&tp->control);
  4222. usb_autopm_put_interface(tp->intf);
  4223. return ret;
  4224. }
  4225. static int rtl8152_get_tunable(struct net_device *netdev,
  4226. const struct ethtool_tunable *tunable, void *d)
  4227. {
  4228. struct r8152 *tp = netdev_priv(netdev);
  4229. switch (tunable->id) {
  4230. case ETHTOOL_RX_COPYBREAK:
  4231. *(u32 *)d = tp->rx_copybreak;
  4232. break;
  4233. default:
  4234. return -EOPNOTSUPP;
  4235. }
  4236. return 0;
  4237. }
  4238. static int rtl8152_set_tunable(struct net_device *netdev,
  4239. const struct ethtool_tunable *tunable,
  4240. const void *d)
  4241. {
  4242. struct r8152 *tp = netdev_priv(netdev);
  4243. u32 val;
  4244. switch (tunable->id) {
  4245. case ETHTOOL_RX_COPYBREAK:
  4246. val = *(u32 *)d;
  4247. if (val < ETH_ZLEN) {
  4248. netif_err(tp, rx_err, netdev,
  4249. "Invalid rx copy break value\n");
  4250. return -EINVAL;
  4251. }
  4252. if (tp->rx_copybreak != val) {
  4253. if (netdev->flags & IFF_UP) {
  4254. mutex_lock(&tp->control);
  4255. napi_disable(&tp->napi);
  4256. tp->rx_copybreak = val;
  4257. napi_enable(&tp->napi);
  4258. mutex_unlock(&tp->control);
  4259. } else {
  4260. tp->rx_copybreak = val;
  4261. }
  4262. }
  4263. break;
  4264. default:
  4265. return -EOPNOTSUPP;
  4266. }
  4267. return 0;
  4268. }
  4269. static void rtl8152_get_ringparam(struct net_device *netdev,
  4270. struct ethtool_ringparam *ring)
  4271. {
  4272. struct r8152 *tp = netdev_priv(netdev);
  4273. ring->rx_max_pending = RTL8152_RX_MAX_PENDING;
  4274. ring->rx_pending = tp->rx_pending;
  4275. }
  4276. static int rtl8152_set_ringparam(struct net_device *netdev,
  4277. struct ethtool_ringparam *ring)
  4278. {
  4279. struct r8152 *tp = netdev_priv(netdev);
  4280. if (ring->rx_pending < (RTL8152_MAX_RX * 2))
  4281. return -EINVAL;
  4282. if (tp->rx_pending != ring->rx_pending) {
  4283. if (netdev->flags & IFF_UP) {
  4284. mutex_lock(&tp->control);
  4285. napi_disable(&tp->napi);
  4286. tp->rx_pending = ring->rx_pending;
  4287. napi_enable(&tp->napi);
  4288. mutex_unlock(&tp->control);
  4289. } else {
  4290. tp->rx_pending = ring->rx_pending;
  4291. }
  4292. }
  4293. return 0;
  4294. }
  4295. static const struct ethtool_ops ops = {
  4296. .get_drvinfo = rtl8152_get_drvinfo,
  4297. .get_link = ethtool_op_get_link,
  4298. .nway_reset = rtl8152_nway_reset,
  4299. .get_msglevel = rtl8152_get_msglevel,
  4300. .set_msglevel = rtl8152_set_msglevel,
  4301. .get_wol = rtl8152_get_wol,
  4302. .set_wol = rtl8152_set_wol,
  4303. .get_strings = rtl8152_get_strings,
  4304. .get_sset_count = rtl8152_get_sset_count,
  4305. .get_ethtool_stats = rtl8152_get_ethtool_stats,
  4306. .get_coalesce = rtl8152_get_coalesce,
  4307. .set_coalesce = rtl8152_set_coalesce,
  4308. .get_eee = rtl_ethtool_get_eee,
  4309. .set_eee = rtl_ethtool_set_eee,
  4310. .get_link_ksettings = rtl8152_get_link_ksettings,
  4311. .set_link_ksettings = rtl8152_set_link_ksettings,
  4312. .get_tunable = rtl8152_get_tunable,
  4313. .set_tunable = rtl8152_set_tunable,
  4314. .get_ringparam = rtl8152_get_ringparam,
  4315. .set_ringparam = rtl8152_set_ringparam,
  4316. };
  4317. static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
  4318. {
  4319. struct r8152 *tp = netdev_priv(netdev);
  4320. struct mii_ioctl_data *data = if_mii(rq);
  4321. int res;
  4322. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  4323. return -ENODEV;
  4324. res = usb_autopm_get_interface(tp->intf);
  4325. if (res < 0)
  4326. goto out;
  4327. switch (cmd) {
  4328. case SIOCGMIIPHY:
  4329. data->phy_id = R8152_PHY_ID; /* Internal PHY */
  4330. break;
  4331. case SIOCGMIIREG:
  4332. mutex_lock(&tp->control);
  4333. data->val_out = r8152_mdio_read(tp, data->reg_num);
  4334. mutex_unlock(&tp->control);
  4335. break;
  4336. case SIOCSMIIREG:
  4337. if (!capable(CAP_NET_ADMIN)) {
  4338. res = -EPERM;
  4339. break;
  4340. }
  4341. mutex_lock(&tp->control);
  4342. r8152_mdio_write(tp, data->reg_num, data->val_in);
  4343. mutex_unlock(&tp->control);
  4344. break;
  4345. default:
  4346. res = -EOPNOTSUPP;
  4347. }
  4348. usb_autopm_put_interface(tp->intf);
  4349. out:
  4350. return res;
  4351. }
  4352. static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
  4353. {
  4354. struct r8152 *tp = netdev_priv(dev);
  4355. int ret;
  4356. switch (tp->version) {
  4357. case RTL_VER_01:
  4358. case RTL_VER_02:
  4359. case RTL_VER_07:
  4360. dev->mtu = new_mtu;
  4361. return 0;
  4362. default:
  4363. break;
  4364. }
  4365. ret = usb_autopm_get_interface(tp->intf);
  4366. if (ret < 0)
  4367. return ret;
  4368. mutex_lock(&tp->control);
  4369. dev->mtu = new_mtu;
  4370. if (netif_running(dev)) {
  4371. u32 rms = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
  4372. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rms);
  4373. if (netif_carrier_ok(dev))
  4374. r8153_set_rx_early_size(tp);
  4375. }
  4376. mutex_unlock(&tp->control);
  4377. usb_autopm_put_interface(tp->intf);
  4378. return ret;
  4379. }
  4380. static const struct net_device_ops rtl8152_netdev_ops = {
  4381. .ndo_open = rtl8152_open,
  4382. .ndo_stop = rtl8152_close,
  4383. .ndo_do_ioctl = rtl8152_ioctl,
  4384. .ndo_start_xmit = rtl8152_start_xmit,
  4385. .ndo_tx_timeout = rtl8152_tx_timeout,
  4386. .ndo_set_features = rtl8152_set_features,
  4387. .ndo_set_rx_mode = rtl8152_set_rx_mode,
  4388. .ndo_set_mac_address = rtl8152_set_mac_address,
  4389. .ndo_change_mtu = rtl8152_change_mtu,
  4390. .ndo_validate_addr = eth_validate_addr,
  4391. .ndo_features_check = rtl8152_features_check,
  4392. };
  4393. static void rtl8152_unload(struct r8152 *tp)
  4394. {
  4395. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  4396. return;
  4397. if (tp->version != RTL_VER_01)
  4398. r8152_power_cut_en(tp, true);
  4399. }
  4400. static void rtl8153_unload(struct r8152 *tp)
  4401. {
  4402. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  4403. return;
  4404. r8153_power_cut_en(tp, false);
  4405. }
  4406. static void rtl8153b_unload(struct r8152 *tp)
  4407. {
  4408. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  4409. return;
  4410. r8153b_power_cut_en(tp, false);
  4411. }
  4412. static int rtl_ops_init(struct r8152 *tp)
  4413. {
  4414. struct rtl_ops *ops = &tp->rtl_ops;
  4415. int ret = 0;
  4416. switch (tp->version) {
  4417. case RTL_VER_01:
  4418. case RTL_VER_02:
  4419. case RTL_VER_07:
  4420. ops->init = r8152b_init;
  4421. ops->enable = rtl8152_enable;
  4422. ops->disable = rtl8152_disable;
  4423. ops->up = rtl8152_up;
  4424. ops->down = rtl8152_down;
  4425. ops->unload = rtl8152_unload;
  4426. ops->eee_get = r8152_get_eee;
  4427. ops->eee_set = r8152_set_eee;
  4428. ops->in_nway = rtl8152_in_nway;
  4429. ops->hw_phy_cfg = r8152b_hw_phy_cfg;
  4430. ops->autosuspend_en = rtl_runtime_suspend_enable;
  4431. tp->rx_buf_sz = 16 * 1024;
  4432. tp->eee_en = true;
  4433. tp->eee_adv = MDIO_EEE_100TX;
  4434. break;
  4435. case RTL_VER_03:
  4436. case RTL_VER_04:
  4437. case RTL_VER_05:
  4438. case RTL_VER_06:
  4439. ops->init = r8153_init;
  4440. ops->enable = rtl8153_enable;
  4441. ops->disable = rtl8153_disable;
  4442. ops->up = rtl8153_up;
  4443. ops->down = rtl8153_down;
  4444. ops->unload = rtl8153_unload;
  4445. ops->eee_get = r8153_get_eee;
  4446. ops->eee_set = r8152_set_eee;
  4447. ops->in_nway = rtl8153_in_nway;
  4448. ops->hw_phy_cfg = r8153_hw_phy_cfg;
  4449. ops->autosuspend_en = rtl8153_runtime_enable;
  4450. if (tp->udev->speed < USB_SPEED_SUPER)
  4451. tp->rx_buf_sz = 16 * 1024;
  4452. else
  4453. tp->rx_buf_sz = 32 * 1024;
  4454. tp->eee_en = true;
  4455. tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
  4456. break;
  4457. case RTL_VER_08:
  4458. case RTL_VER_09:
  4459. ops->init = r8153b_init;
  4460. ops->enable = rtl8153_enable;
  4461. ops->disable = rtl8153_disable;
  4462. ops->up = rtl8153b_up;
  4463. ops->down = rtl8153b_down;
  4464. ops->unload = rtl8153b_unload;
  4465. ops->eee_get = r8153_get_eee;
  4466. ops->eee_set = r8152_set_eee;
  4467. ops->in_nway = rtl8153_in_nway;
  4468. ops->hw_phy_cfg = r8153b_hw_phy_cfg;
  4469. ops->autosuspend_en = rtl8153b_runtime_enable;
  4470. tp->rx_buf_sz = 32 * 1024;
  4471. tp->eee_en = true;
  4472. tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
  4473. break;
  4474. default:
  4475. ret = -ENODEV;
  4476. netif_err(tp, probe, tp->netdev, "Unknown Device\n");
  4477. break;
  4478. }
  4479. return ret;
  4480. }
  4481. static u8 rtl_get_version(struct usb_interface *intf)
  4482. {
  4483. struct usb_device *udev = interface_to_usbdev(intf);
  4484. u32 ocp_data = 0;
  4485. __le32 *tmp;
  4486. u8 version;
  4487. int ret;
  4488. tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
  4489. if (!tmp)
  4490. return 0;
  4491. ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
  4492. RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
  4493. PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500);
  4494. if (ret > 0)
  4495. ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK;
  4496. kfree(tmp);
  4497. switch (ocp_data) {
  4498. case 0x4c00:
  4499. version = RTL_VER_01;
  4500. break;
  4501. case 0x4c10:
  4502. version = RTL_VER_02;
  4503. break;
  4504. case 0x5c00:
  4505. version = RTL_VER_03;
  4506. break;
  4507. case 0x5c10:
  4508. version = RTL_VER_04;
  4509. break;
  4510. case 0x5c20:
  4511. version = RTL_VER_05;
  4512. break;
  4513. case 0x5c30:
  4514. version = RTL_VER_06;
  4515. break;
  4516. case 0x4800:
  4517. version = RTL_VER_07;
  4518. break;
  4519. case 0x6000:
  4520. version = RTL_VER_08;
  4521. break;
  4522. case 0x6010:
  4523. version = RTL_VER_09;
  4524. break;
  4525. default:
  4526. version = RTL_VER_UNKNOWN;
  4527. dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data);
  4528. break;
  4529. }
  4530. dev_dbg(&intf->dev, "Detected version 0x%04x\n", version);
  4531. return version;
  4532. }
  4533. static int rtl8152_probe(struct usb_interface *intf,
  4534. const struct usb_device_id *id)
  4535. {
  4536. struct usb_device *udev = interface_to_usbdev(intf);
  4537. u8 version = rtl_get_version(intf);
  4538. struct r8152 *tp;
  4539. struct net_device *netdev;
  4540. int ret;
  4541. if (version == RTL_VER_UNKNOWN)
  4542. return -ENODEV;
  4543. if (udev->actconfig->desc.bConfigurationValue != 1) {
  4544. usb_driver_set_configuration(udev, 1);
  4545. return -ENODEV;
  4546. }
  4547. if (intf->cur_altsetting->desc.bNumEndpoints < 3)
  4548. return -ENODEV;
  4549. usb_reset_device(udev);
  4550. netdev = alloc_etherdev(sizeof(struct r8152));
  4551. if (!netdev) {
  4552. dev_err(&intf->dev, "Out of memory\n");
  4553. return -ENOMEM;
  4554. }
  4555. SET_NETDEV_DEV(netdev, &intf->dev);
  4556. tp = netdev_priv(netdev);
  4557. tp->msg_enable = 0x7FFF;
  4558. tp->udev = udev;
  4559. tp->netdev = netdev;
  4560. tp->intf = intf;
  4561. tp->version = version;
  4562. switch (version) {
  4563. case RTL_VER_01:
  4564. case RTL_VER_02:
  4565. case RTL_VER_07:
  4566. tp->mii.supports_gmii = 0;
  4567. break;
  4568. default:
  4569. tp->mii.supports_gmii = 1;
  4570. break;
  4571. }
  4572. ret = rtl_ops_init(tp);
  4573. if (ret)
  4574. goto out;
  4575. mutex_init(&tp->control);
  4576. INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
  4577. INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
  4578. tasklet_init(&tp->tx_tl, bottom_half, (unsigned long)tp);
  4579. tasklet_disable(&tp->tx_tl);
  4580. netdev->netdev_ops = &rtl8152_netdev_ops;
  4581. netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
  4582. netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
  4583. NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
  4584. NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
  4585. NETIF_F_HW_VLAN_CTAG_TX;
  4586. netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
  4587. NETIF_F_TSO | NETIF_F_FRAGLIST |
  4588. NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
  4589. NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
  4590. netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
  4591. NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
  4592. NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
  4593. if (tp->version == RTL_VER_01) {
  4594. netdev->features &= ~NETIF_F_RXCSUM;
  4595. netdev->hw_features &= ~NETIF_F_RXCSUM;
  4596. }
  4597. if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial &&
  4598. (!strcmp(udev->serial, "000001000000") || !strcmp(udev->serial, "000002000000"))) {
  4599. dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation");
  4600. set_bit(DELL_TB_RX_AGG_BUG, &tp->flags);
  4601. }
  4602. netdev->ethtool_ops = &ops;
  4603. netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
  4604. /* MTU range: 68 - 1500 or 9194 */
  4605. netdev->min_mtu = ETH_MIN_MTU;
  4606. switch (tp->version) {
  4607. case RTL_VER_01:
  4608. case RTL_VER_02:
  4609. netdev->max_mtu = ETH_DATA_LEN;
  4610. break;
  4611. default:
  4612. netdev->max_mtu = RTL8153_MAX_MTU;
  4613. break;
  4614. }
  4615. tp->mii.dev = netdev;
  4616. tp->mii.mdio_read = read_mii_word;
  4617. tp->mii.mdio_write = write_mii_word;
  4618. tp->mii.phy_id_mask = 0x3f;
  4619. tp->mii.reg_num_mask = 0x1f;
  4620. tp->mii.phy_id = R8152_PHY_ID;
  4621. tp->autoneg = AUTONEG_ENABLE;
  4622. tp->speed = SPEED_100;
  4623. tp->advertising = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
  4624. RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
  4625. if (tp->mii.supports_gmii) {
  4626. tp->speed = SPEED_1000;
  4627. tp->advertising |= RTL_ADVERTISED_1000_FULL;
  4628. }
  4629. tp->duplex = DUPLEX_FULL;
  4630. tp->rx_copybreak = RTL8152_RXFG_HEADSZ;
  4631. tp->rx_pending = 10 * RTL8152_MAX_RX;
  4632. intf->needs_remote_wakeup = 1;
  4633. if (!rtl_can_wakeup(tp))
  4634. __rtl_set_wol(tp, 0);
  4635. else
  4636. tp->saved_wolopts = __rtl_get_wol(tp);
  4637. tp->rtl_ops.init(tp);
  4638. queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
  4639. set_ethernet_addr(tp);
  4640. usb_set_intfdata(intf, tp);
  4641. netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
  4642. ret = register_netdev(netdev);
  4643. if (ret != 0) {
  4644. netif_err(tp, probe, netdev, "couldn't register the device\n");
  4645. goto out1;
  4646. }
  4647. if (tp->saved_wolopts)
  4648. device_set_wakeup_enable(&udev->dev, true);
  4649. else
  4650. device_set_wakeup_enable(&udev->dev, false);
  4651. netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
  4652. return 0;
  4653. out1:
  4654. tasklet_kill(&tp->tx_tl);
  4655. usb_set_intfdata(intf, NULL);
  4656. out:
  4657. free_netdev(netdev);
  4658. return ret;
  4659. }
  4660. static void rtl8152_disconnect(struct usb_interface *intf)
  4661. {
  4662. struct r8152 *tp = usb_get_intfdata(intf);
  4663. usb_set_intfdata(intf, NULL);
  4664. if (tp) {
  4665. rtl_set_unplug(tp);
  4666. unregister_netdev(tp->netdev);
  4667. tasklet_kill(&tp->tx_tl);
  4668. cancel_delayed_work_sync(&tp->hw_phy_work);
  4669. tp->rtl_ops.unload(tp);
  4670. free_netdev(tp->netdev);
  4671. }
  4672. }
  4673. #define REALTEK_USB_DEVICE(vend, prod) \
  4674. .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
  4675. USB_DEVICE_ID_MATCH_INT_CLASS, \
  4676. .idVendor = (vend), \
  4677. .idProduct = (prod), \
  4678. .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
  4679. }, \
  4680. { \
  4681. .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
  4682. USB_DEVICE_ID_MATCH_DEVICE, \
  4683. .idVendor = (vend), \
  4684. .idProduct = (prod), \
  4685. .bInterfaceClass = USB_CLASS_COMM, \
  4686. .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
  4687. .bInterfaceProtocol = USB_CDC_PROTO_NONE
  4688. /* table of devices that work with this driver */
  4689. static const struct usb_device_id rtl8152_table[] = {
  4690. {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050)},
  4691. {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
  4692. {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
  4693. {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab)},
  4694. {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6)},
  4695. {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0927)},
  4696. {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
  4697. {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)},
  4698. {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3062)},
  4699. {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3069)},
  4700. {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)},
  4701. {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x720c)},
  4702. {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7214)},
  4703. {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x721e)},
  4704. {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0xa387)},
  4705. {REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041)},
  4706. {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)},
  4707. {REALTEK_USB_DEVICE(VENDOR_ID_TPLINK, 0x0601)},
  4708. {}
  4709. };
  4710. MODULE_DEVICE_TABLE(usb, rtl8152_table);
  4711. static struct usb_driver rtl8152_driver = {
  4712. .name = MODULENAME,
  4713. .id_table = rtl8152_table,
  4714. .probe = rtl8152_probe,
  4715. .disconnect = rtl8152_disconnect,
  4716. .suspend = rtl8152_suspend,
  4717. .resume = rtl8152_resume,
  4718. .reset_resume = rtl8152_reset_resume,
  4719. .pre_reset = rtl8152_pre_reset,
  4720. .post_reset = rtl8152_post_reset,
  4721. .supports_autosuspend = 1,
  4722. .disable_hub_initiated_lpm = 1,
  4723. };
  4724. module_usb_driver(rtl8152_driver);
  4725. MODULE_AUTHOR(DRIVER_AUTHOR);
  4726. MODULE_DESCRIPTION(DRIVER_DESC);
  4727. MODULE_LICENSE("GPL");
  4728. MODULE_VERSION(DRIVER_VERSION);