ax88179_178a.c 44 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * ASIX AX88179/178A USB 3.0/2.0 to Gigabit Ethernet Devices
  4. *
  5. * Copyright (C) 2011-2013 ASIX
  6. */
  7. #include <linux/module.h>
  8. #include <linux/etherdevice.h>
  9. #include <linux/mii.h>
  10. #include <linux/usb.h>
  11. #include <linux/crc32.h>
  12. #include <linux/usb/usbnet.h>
  13. #include <uapi/linux/mdio.h>
  14. #include <linux/mdio.h>
  15. #define AX88179_PHY_ID 0x03
  16. #define AX_EEPROM_LEN 0x100
  17. #define AX88179_EEPROM_MAGIC 0x17900b95
  18. #define AX_MCAST_FLTSIZE 8
  19. #define AX_MAX_MCAST 64
  20. #define AX_INT_PPLS_LINK ((u32)BIT(16))
  21. #define AX_RXHDR_L4_TYPE_MASK 0x1c
  22. #define AX_RXHDR_L4_TYPE_UDP 4
  23. #define AX_RXHDR_L4_TYPE_TCP 16
  24. #define AX_RXHDR_L3CSUM_ERR 2
  25. #define AX_RXHDR_L4CSUM_ERR 1
  26. #define AX_RXHDR_CRC_ERR ((u32)BIT(29))
  27. #define AX_RXHDR_DROP_ERR ((u32)BIT(31))
  28. #define AX_ACCESS_MAC 0x01
  29. #define AX_ACCESS_PHY 0x02
  30. #define AX_ACCESS_EEPROM 0x04
  31. #define AX_ACCESS_EFUS 0x05
  32. #define AX_PAUSE_WATERLVL_HIGH 0x54
  33. #define AX_PAUSE_WATERLVL_LOW 0x55
  34. #define PHYSICAL_LINK_STATUS 0x02
  35. #define AX_USB_SS 0x04
  36. #define AX_USB_HS 0x02
  37. #define GENERAL_STATUS 0x03
  38. /* Check AX88179 version. UA1:Bit2 = 0, UA2:Bit2 = 1 */
  39. #define AX_SECLD 0x04
  40. #define AX_SROM_ADDR 0x07
  41. #define AX_SROM_CMD 0x0a
  42. #define EEP_RD 0x04
  43. #define EEP_BUSY 0x10
  44. #define AX_SROM_DATA_LOW 0x08
  45. #define AX_SROM_DATA_HIGH 0x09
  46. #define AX_RX_CTL 0x0b
  47. #define AX_RX_CTL_DROPCRCERR 0x0100
  48. #define AX_RX_CTL_IPE 0x0200
  49. #define AX_RX_CTL_START 0x0080
  50. #define AX_RX_CTL_AP 0x0020
  51. #define AX_RX_CTL_AM 0x0010
  52. #define AX_RX_CTL_AB 0x0008
  53. #define AX_RX_CTL_AMALL 0x0002
  54. #define AX_RX_CTL_PRO 0x0001
  55. #define AX_RX_CTL_STOP 0x0000
  56. #define AX_NODE_ID 0x10
  57. #define AX_MULFLTARY 0x16
  58. #define AX_MEDIUM_STATUS_MODE 0x22
  59. #define AX_MEDIUM_GIGAMODE 0x01
  60. #define AX_MEDIUM_FULL_DUPLEX 0x02
  61. #define AX_MEDIUM_EN_125MHZ 0x08
  62. #define AX_MEDIUM_RXFLOW_CTRLEN 0x10
  63. #define AX_MEDIUM_TXFLOW_CTRLEN 0x20
  64. #define AX_MEDIUM_RECEIVE_EN 0x100
  65. #define AX_MEDIUM_PS 0x200
  66. #define AX_MEDIUM_JUMBO_EN 0x8040
  67. #define AX_MONITOR_MOD 0x24
  68. #define AX_MONITOR_MODE_RWLC 0x02
  69. #define AX_MONITOR_MODE_RWMP 0x04
  70. #define AX_MONITOR_MODE_PMEPOL 0x20
  71. #define AX_MONITOR_MODE_PMETYPE 0x40
  72. #define AX_GPIO_CTRL 0x25
  73. #define AX_GPIO_CTRL_GPIO3EN 0x80
  74. #define AX_GPIO_CTRL_GPIO2EN 0x40
  75. #define AX_GPIO_CTRL_GPIO1EN 0x20
  76. #define AX_PHYPWR_RSTCTL 0x26
  77. #define AX_PHYPWR_RSTCTL_BZ 0x0010
  78. #define AX_PHYPWR_RSTCTL_IPRL 0x0020
  79. #define AX_PHYPWR_RSTCTL_AT 0x1000
  80. #define AX_RX_BULKIN_QCTRL 0x2e
  81. #define AX_CLK_SELECT 0x33
  82. #define AX_CLK_SELECT_BCS 0x01
  83. #define AX_CLK_SELECT_ACS 0x02
  84. #define AX_CLK_SELECT_ULR 0x08
  85. #define AX_RXCOE_CTL 0x34
  86. #define AX_RXCOE_IP 0x01
  87. #define AX_RXCOE_TCP 0x02
  88. #define AX_RXCOE_UDP 0x04
  89. #define AX_RXCOE_TCPV6 0x20
  90. #define AX_RXCOE_UDPV6 0x40
  91. #define AX_TXCOE_CTL 0x35
  92. #define AX_TXCOE_IP 0x01
  93. #define AX_TXCOE_TCP 0x02
  94. #define AX_TXCOE_UDP 0x04
  95. #define AX_TXCOE_TCPV6 0x20
  96. #define AX_TXCOE_UDPV6 0x40
  97. #define AX_LEDCTRL 0x73
  98. #define GMII_PHY_PHYSR 0x11
  99. #define GMII_PHY_PHYSR_SMASK 0xc000
  100. #define GMII_PHY_PHYSR_GIGA 0x8000
  101. #define GMII_PHY_PHYSR_100 0x4000
  102. #define GMII_PHY_PHYSR_FULL 0x2000
  103. #define GMII_PHY_PHYSR_LINK 0x400
  104. #define GMII_LED_ACT 0x1a
  105. #define GMII_LED_ACTIVE_MASK 0xff8f
  106. #define GMII_LED0_ACTIVE BIT(4)
  107. #define GMII_LED1_ACTIVE BIT(5)
  108. #define GMII_LED2_ACTIVE BIT(6)
  109. #define GMII_LED_LINK 0x1c
  110. #define GMII_LED_LINK_MASK 0xf888
  111. #define GMII_LED0_LINK_10 BIT(0)
  112. #define GMII_LED0_LINK_100 BIT(1)
  113. #define GMII_LED0_LINK_1000 BIT(2)
  114. #define GMII_LED1_LINK_10 BIT(4)
  115. #define GMII_LED1_LINK_100 BIT(5)
  116. #define GMII_LED1_LINK_1000 BIT(6)
  117. #define GMII_LED2_LINK_10 BIT(8)
  118. #define GMII_LED2_LINK_100 BIT(9)
  119. #define GMII_LED2_LINK_1000 BIT(10)
  120. #define LED0_ACTIVE BIT(0)
  121. #define LED0_LINK_10 BIT(1)
  122. #define LED0_LINK_100 BIT(2)
  123. #define LED0_LINK_1000 BIT(3)
  124. #define LED0_FD BIT(4)
  125. #define LED0_USB3_MASK 0x001f
  126. #define LED1_ACTIVE BIT(5)
  127. #define LED1_LINK_10 BIT(6)
  128. #define LED1_LINK_100 BIT(7)
  129. #define LED1_LINK_1000 BIT(8)
  130. #define LED1_FD BIT(9)
  131. #define LED1_USB3_MASK 0x03e0
  132. #define LED2_ACTIVE BIT(10)
  133. #define LED2_LINK_1000 BIT(13)
  134. #define LED2_LINK_100 BIT(12)
  135. #define LED2_LINK_10 BIT(11)
  136. #define LED2_FD BIT(14)
  137. #define LED_VALID BIT(15)
  138. #define LED2_USB3_MASK 0x7c00
  139. #define GMII_PHYPAGE 0x1e
  140. #define GMII_PHY_PAGE_SELECT 0x1f
  141. #define GMII_PHY_PGSEL_EXT 0x0007
  142. #define GMII_PHY_PGSEL_PAGE0 0x0000
  143. #define GMII_PHY_PGSEL_PAGE3 0x0003
  144. #define GMII_PHY_PGSEL_PAGE5 0x0005
  145. struct ax88179_data {
  146. u8 eee_enabled;
  147. u8 eee_active;
  148. u16 rxctl;
  149. u16 reserved;
  150. };
  151. struct ax88179_int_data {
  152. __le32 intdata1;
  153. __le32 intdata2;
  154. };
  155. static const struct {
  156. unsigned char ctrl, timer_l, timer_h, size, ifg;
  157. } AX88179_BULKIN_SIZE[] = {
  158. {7, 0x4f, 0, 0x12, 0xff},
  159. {7, 0x20, 3, 0x16, 0xff},
  160. {7, 0xae, 7, 0x18, 0xff},
  161. {7, 0xcc, 0x4c, 0x18, 8},
  162. };
  163. static int __ax88179_read_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index,
  164. u16 size, void *data, int in_pm)
  165. {
  166. int ret;
  167. int (*fn)(struct usbnet *, u8, u8, u16, u16, void *, u16);
  168. BUG_ON(!dev);
  169. if (!in_pm)
  170. fn = usbnet_read_cmd;
  171. else
  172. fn = usbnet_read_cmd_nopm;
  173. ret = fn(dev, cmd, USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  174. value, index, data, size);
  175. if (unlikely(ret < 0))
  176. netdev_warn(dev->net, "Failed to read reg index 0x%04x: %d\n",
  177. index, ret);
  178. return ret;
  179. }
  180. static int __ax88179_write_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index,
  181. u16 size, void *data, int in_pm)
  182. {
  183. int ret;
  184. int (*fn)(struct usbnet *, u8, u8, u16, u16, const void *, u16);
  185. BUG_ON(!dev);
  186. if (!in_pm)
  187. fn = usbnet_write_cmd;
  188. else
  189. fn = usbnet_write_cmd_nopm;
  190. ret = fn(dev, cmd, USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  191. value, index, data, size);
  192. if (unlikely(ret < 0))
  193. netdev_warn(dev->net, "Failed to write reg index 0x%04x: %d\n",
  194. index, ret);
  195. return ret;
  196. }
  197. static void ax88179_write_cmd_async(struct usbnet *dev, u8 cmd, u16 value,
  198. u16 index, u16 size, void *data)
  199. {
  200. u16 buf;
  201. if (2 == size) {
  202. buf = *((u16 *)data);
  203. cpu_to_le16s(&buf);
  204. usbnet_write_cmd_async(dev, cmd, USB_DIR_OUT | USB_TYPE_VENDOR |
  205. USB_RECIP_DEVICE, value, index, &buf,
  206. size);
  207. } else {
  208. usbnet_write_cmd_async(dev, cmd, USB_DIR_OUT | USB_TYPE_VENDOR |
  209. USB_RECIP_DEVICE, value, index, data,
  210. size);
  211. }
  212. }
  213. static int ax88179_read_cmd_nopm(struct usbnet *dev, u8 cmd, u16 value,
  214. u16 index, u16 size, void *data)
  215. {
  216. int ret;
  217. if (2 == size) {
  218. u16 buf;
  219. ret = __ax88179_read_cmd(dev, cmd, value, index, size, &buf, 1);
  220. le16_to_cpus(&buf);
  221. *((u16 *)data) = buf;
  222. } else if (4 == size) {
  223. u32 buf;
  224. ret = __ax88179_read_cmd(dev, cmd, value, index, size, &buf, 1);
  225. le32_to_cpus(&buf);
  226. *((u32 *)data) = buf;
  227. } else {
  228. ret = __ax88179_read_cmd(dev, cmd, value, index, size, data, 1);
  229. }
  230. return ret;
  231. }
  232. static int ax88179_write_cmd_nopm(struct usbnet *dev, u8 cmd, u16 value,
  233. u16 index, u16 size, void *data)
  234. {
  235. int ret;
  236. if (2 == size) {
  237. u16 buf;
  238. buf = *((u16 *)data);
  239. cpu_to_le16s(&buf);
  240. ret = __ax88179_write_cmd(dev, cmd, value, index,
  241. size, &buf, 1);
  242. } else {
  243. ret = __ax88179_write_cmd(dev, cmd, value, index,
  244. size, data, 1);
  245. }
  246. return ret;
  247. }
  248. static int ax88179_read_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index,
  249. u16 size, void *data)
  250. {
  251. int ret;
  252. if (2 == size) {
  253. u16 buf = 0;
  254. ret = __ax88179_read_cmd(dev, cmd, value, index, size, &buf, 0);
  255. le16_to_cpus(&buf);
  256. *((u16 *)data) = buf;
  257. } else if (4 == size) {
  258. u32 buf = 0;
  259. ret = __ax88179_read_cmd(dev, cmd, value, index, size, &buf, 0);
  260. le32_to_cpus(&buf);
  261. *((u32 *)data) = buf;
  262. } else {
  263. ret = __ax88179_read_cmd(dev, cmd, value, index, size, data, 0);
  264. }
  265. return ret;
  266. }
  267. static int ax88179_write_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index,
  268. u16 size, void *data)
  269. {
  270. int ret;
  271. if (2 == size) {
  272. u16 buf;
  273. buf = *((u16 *)data);
  274. cpu_to_le16s(&buf);
  275. ret = __ax88179_write_cmd(dev, cmd, value, index,
  276. size, &buf, 0);
  277. } else {
  278. ret = __ax88179_write_cmd(dev, cmd, value, index,
  279. size, data, 0);
  280. }
  281. return ret;
  282. }
  283. static void ax88179_status(struct usbnet *dev, struct urb *urb)
  284. {
  285. struct ax88179_int_data *event;
  286. u32 link;
  287. if (urb->actual_length < 8)
  288. return;
  289. event = urb->transfer_buffer;
  290. le32_to_cpus((void *)&event->intdata1);
  291. link = (((__force u32)event->intdata1) & AX_INT_PPLS_LINK) >> 16;
  292. if (netif_carrier_ok(dev->net) != link) {
  293. usbnet_link_change(dev, link, 1);
  294. netdev_info(dev->net, "ax88179 - Link status is: %d\n", link);
  295. }
  296. }
  297. static int ax88179_mdio_read(struct net_device *netdev, int phy_id, int loc)
  298. {
  299. struct usbnet *dev = netdev_priv(netdev);
  300. u16 res;
  301. ax88179_read_cmd(dev, AX_ACCESS_PHY, phy_id, (__u16)loc, 2, &res);
  302. return res;
  303. }
  304. static void ax88179_mdio_write(struct net_device *netdev, int phy_id, int loc,
  305. int val)
  306. {
  307. struct usbnet *dev = netdev_priv(netdev);
  308. u16 res = (u16) val;
  309. ax88179_write_cmd(dev, AX_ACCESS_PHY, phy_id, (__u16)loc, 2, &res);
  310. }
  311. static inline int ax88179_phy_mmd_indirect(struct usbnet *dev, u16 prtad,
  312. u16 devad)
  313. {
  314. u16 tmp16;
  315. int ret;
  316. tmp16 = devad;
  317. ret = ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  318. MII_MMD_CTRL, 2, &tmp16);
  319. tmp16 = prtad;
  320. ret = ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  321. MII_MMD_DATA, 2, &tmp16);
  322. tmp16 = devad | MII_MMD_CTRL_NOINCR;
  323. ret = ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  324. MII_MMD_CTRL, 2, &tmp16);
  325. return ret;
  326. }
  327. static int
  328. ax88179_phy_read_mmd_indirect(struct usbnet *dev, u16 prtad, u16 devad)
  329. {
  330. int ret;
  331. u16 tmp16;
  332. ax88179_phy_mmd_indirect(dev, prtad, devad);
  333. ret = ax88179_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  334. MII_MMD_DATA, 2, &tmp16);
  335. if (ret < 0)
  336. return ret;
  337. return tmp16;
  338. }
  339. static int
  340. ax88179_phy_write_mmd_indirect(struct usbnet *dev, u16 prtad, u16 devad,
  341. u16 data)
  342. {
  343. int ret;
  344. ax88179_phy_mmd_indirect(dev, prtad, devad);
  345. ret = ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  346. MII_MMD_DATA, 2, &data);
  347. if (ret < 0)
  348. return ret;
  349. return 0;
  350. }
  351. static int ax88179_suspend(struct usb_interface *intf, pm_message_t message)
  352. {
  353. struct usbnet *dev = usb_get_intfdata(intf);
  354. u16 tmp16;
  355. u8 tmp8;
  356. usbnet_suspend(intf, message);
  357. /* Disable RX path */
  358. ax88179_read_cmd_nopm(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
  359. 2, 2, &tmp16);
  360. tmp16 &= ~AX_MEDIUM_RECEIVE_EN;
  361. ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
  362. 2, 2, &tmp16);
  363. /* Force bulk-in zero length */
  364. ax88179_read_cmd_nopm(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL,
  365. 2, 2, &tmp16);
  366. tmp16 |= AX_PHYPWR_RSTCTL_BZ | AX_PHYPWR_RSTCTL_IPRL;
  367. ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL,
  368. 2, 2, &tmp16);
  369. /* change clock */
  370. tmp8 = 0;
  371. ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp8);
  372. /* Configure RX control register => stop operation */
  373. tmp16 = AX_RX_CTL_STOP;
  374. ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, &tmp16);
  375. return 0;
  376. }
  377. /* This function is used to enable the autodetach function. */
  378. /* This function is determined by offset 0x43 of EEPROM */
  379. static int ax88179_auto_detach(struct usbnet *dev, int in_pm)
  380. {
  381. u16 tmp16;
  382. u8 tmp8;
  383. int (*fnr)(struct usbnet *, u8, u16, u16, u16, void *);
  384. int (*fnw)(struct usbnet *, u8, u16, u16, u16, void *);
  385. if (!in_pm) {
  386. fnr = ax88179_read_cmd;
  387. fnw = ax88179_write_cmd;
  388. } else {
  389. fnr = ax88179_read_cmd_nopm;
  390. fnw = ax88179_write_cmd_nopm;
  391. }
  392. if (fnr(dev, AX_ACCESS_EEPROM, 0x43, 1, 2, &tmp16) < 0)
  393. return 0;
  394. if ((tmp16 == 0xFFFF) || (!(tmp16 & 0x0100)))
  395. return 0;
  396. /* Enable Auto Detach bit */
  397. tmp8 = 0;
  398. fnr(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp8);
  399. tmp8 |= AX_CLK_SELECT_ULR;
  400. fnw(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp8);
  401. fnr(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, &tmp16);
  402. tmp16 |= AX_PHYPWR_RSTCTL_AT;
  403. fnw(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, &tmp16);
  404. return 0;
  405. }
  406. static int ax88179_resume(struct usb_interface *intf)
  407. {
  408. struct usbnet *dev = usb_get_intfdata(intf);
  409. u16 tmp16;
  410. u8 tmp8;
  411. usbnet_link_change(dev, 0, 0);
  412. /* Power up ethernet PHY */
  413. tmp16 = 0;
  414. ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL,
  415. 2, 2, &tmp16);
  416. udelay(1000);
  417. tmp16 = AX_PHYPWR_RSTCTL_IPRL;
  418. ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL,
  419. 2, 2, &tmp16);
  420. msleep(200);
  421. /* Ethernet PHY Auto Detach*/
  422. ax88179_auto_detach(dev, 1);
  423. /* Enable clock */
  424. ax88179_read_cmd_nopm(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp8);
  425. tmp8 |= AX_CLK_SELECT_ACS | AX_CLK_SELECT_BCS;
  426. ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp8);
  427. msleep(100);
  428. /* Configure RX control register => start operation */
  429. tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START |
  430. AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB;
  431. ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, &tmp16);
  432. return usbnet_resume(intf);
  433. }
  434. static void
  435. ax88179_get_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo)
  436. {
  437. struct usbnet *dev = netdev_priv(net);
  438. u8 opt;
  439. if (ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD,
  440. 1, 1, &opt) < 0) {
  441. wolinfo->supported = 0;
  442. wolinfo->wolopts = 0;
  443. return;
  444. }
  445. wolinfo->supported = WAKE_PHY | WAKE_MAGIC;
  446. wolinfo->wolopts = 0;
  447. if (opt & AX_MONITOR_MODE_RWLC)
  448. wolinfo->wolopts |= WAKE_PHY;
  449. if (opt & AX_MONITOR_MODE_RWMP)
  450. wolinfo->wolopts |= WAKE_MAGIC;
  451. }
  452. static int
  453. ax88179_set_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo)
  454. {
  455. struct usbnet *dev = netdev_priv(net);
  456. u8 opt = 0;
  457. if (wolinfo->wolopts & ~(WAKE_PHY | WAKE_MAGIC))
  458. return -EINVAL;
  459. if (wolinfo->wolopts & WAKE_PHY)
  460. opt |= AX_MONITOR_MODE_RWLC;
  461. if (wolinfo->wolopts & WAKE_MAGIC)
  462. opt |= AX_MONITOR_MODE_RWMP;
  463. if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD,
  464. 1, 1, &opt) < 0)
  465. return -EINVAL;
  466. return 0;
  467. }
  468. static int ax88179_get_eeprom_len(struct net_device *net)
  469. {
  470. return AX_EEPROM_LEN;
  471. }
  472. static int
  473. ax88179_get_eeprom(struct net_device *net, struct ethtool_eeprom *eeprom,
  474. u8 *data)
  475. {
  476. struct usbnet *dev = netdev_priv(net);
  477. u16 *eeprom_buff;
  478. int first_word, last_word;
  479. int i, ret;
  480. if (eeprom->len == 0)
  481. return -EINVAL;
  482. eeprom->magic = AX88179_EEPROM_MAGIC;
  483. first_word = eeprom->offset >> 1;
  484. last_word = (eeprom->offset + eeprom->len - 1) >> 1;
  485. eeprom_buff = kmalloc_array(last_word - first_word + 1, sizeof(u16),
  486. GFP_KERNEL);
  487. if (!eeprom_buff)
  488. return -ENOMEM;
  489. /* ax88179/178A returns 2 bytes from eeprom on read */
  490. for (i = first_word; i <= last_word; i++) {
  491. ret = __ax88179_read_cmd(dev, AX_ACCESS_EEPROM, i, 1, 2,
  492. &eeprom_buff[i - first_word],
  493. 0);
  494. if (ret < 0) {
  495. kfree(eeprom_buff);
  496. return -EIO;
  497. }
  498. }
  499. memcpy(data, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
  500. kfree(eeprom_buff);
  501. return 0;
  502. }
  503. static int ax88179_get_link_ksettings(struct net_device *net,
  504. struct ethtool_link_ksettings *cmd)
  505. {
  506. struct usbnet *dev = netdev_priv(net);
  507. mii_ethtool_get_link_ksettings(&dev->mii, cmd);
  508. return 0;
  509. }
  510. static int ax88179_set_link_ksettings(struct net_device *net,
  511. const struct ethtool_link_ksettings *cmd)
  512. {
  513. struct usbnet *dev = netdev_priv(net);
  514. return mii_ethtool_set_link_ksettings(&dev->mii, cmd);
  515. }
  516. static int
  517. ax88179_ethtool_get_eee(struct usbnet *dev, struct ethtool_eee *data)
  518. {
  519. int val;
  520. /* Get Supported EEE */
  521. val = ax88179_phy_read_mmd_indirect(dev, MDIO_PCS_EEE_ABLE,
  522. MDIO_MMD_PCS);
  523. if (val < 0)
  524. return val;
  525. data->supported = mmd_eee_cap_to_ethtool_sup_t(val);
  526. /* Get advertisement EEE */
  527. val = ax88179_phy_read_mmd_indirect(dev, MDIO_AN_EEE_ADV,
  528. MDIO_MMD_AN);
  529. if (val < 0)
  530. return val;
  531. data->advertised = mmd_eee_adv_to_ethtool_adv_t(val);
  532. /* Get LP advertisement EEE */
  533. val = ax88179_phy_read_mmd_indirect(dev, MDIO_AN_EEE_LPABLE,
  534. MDIO_MMD_AN);
  535. if (val < 0)
  536. return val;
  537. data->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(val);
  538. return 0;
  539. }
  540. static int
  541. ax88179_ethtool_set_eee(struct usbnet *dev, struct ethtool_eee *data)
  542. {
  543. u16 tmp16 = ethtool_adv_to_mmd_eee_adv_t(data->advertised);
  544. return ax88179_phy_write_mmd_indirect(dev, MDIO_AN_EEE_ADV,
  545. MDIO_MMD_AN, tmp16);
  546. }
  547. static int ax88179_chk_eee(struct usbnet *dev)
  548. {
  549. struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
  550. struct ax88179_data *priv = (struct ax88179_data *)dev->data;
  551. mii_ethtool_gset(&dev->mii, &ecmd);
  552. if (ecmd.duplex & DUPLEX_FULL) {
  553. int eee_lp, eee_cap, eee_adv;
  554. u32 lp, cap, adv, supported = 0;
  555. eee_cap = ax88179_phy_read_mmd_indirect(dev,
  556. MDIO_PCS_EEE_ABLE,
  557. MDIO_MMD_PCS);
  558. if (eee_cap < 0) {
  559. priv->eee_active = 0;
  560. return false;
  561. }
  562. cap = mmd_eee_cap_to_ethtool_sup_t(eee_cap);
  563. if (!cap) {
  564. priv->eee_active = 0;
  565. return false;
  566. }
  567. eee_lp = ax88179_phy_read_mmd_indirect(dev,
  568. MDIO_AN_EEE_LPABLE,
  569. MDIO_MMD_AN);
  570. if (eee_lp < 0) {
  571. priv->eee_active = 0;
  572. return false;
  573. }
  574. eee_adv = ax88179_phy_read_mmd_indirect(dev,
  575. MDIO_AN_EEE_ADV,
  576. MDIO_MMD_AN);
  577. if (eee_adv < 0) {
  578. priv->eee_active = 0;
  579. return false;
  580. }
  581. adv = mmd_eee_adv_to_ethtool_adv_t(eee_adv);
  582. lp = mmd_eee_adv_to_ethtool_adv_t(eee_lp);
  583. supported = (ecmd.speed == SPEED_1000) ?
  584. SUPPORTED_1000baseT_Full :
  585. SUPPORTED_100baseT_Full;
  586. if (!(lp & adv & supported)) {
  587. priv->eee_active = 0;
  588. return false;
  589. }
  590. priv->eee_active = 1;
  591. return true;
  592. }
  593. priv->eee_active = 0;
  594. return false;
  595. }
  596. static void ax88179_disable_eee(struct usbnet *dev)
  597. {
  598. u16 tmp16;
  599. tmp16 = GMII_PHY_PGSEL_PAGE3;
  600. ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  601. GMII_PHY_PAGE_SELECT, 2, &tmp16);
  602. tmp16 = 0x3246;
  603. ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  604. MII_PHYADDR, 2, &tmp16);
  605. tmp16 = GMII_PHY_PGSEL_PAGE0;
  606. ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  607. GMII_PHY_PAGE_SELECT, 2, &tmp16);
  608. }
  609. static void ax88179_enable_eee(struct usbnet *dev)
  610. {
  611. u16 tmp16;
  612. tmp16 = GMII_PHY_PGSEL_PAGE3;
  613. ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  614. GMII_PHY_PAGE_SELECT, 2, &tmp16);
  615. tmp16 = 0x3247;
  616. ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  617. MII_PHYADDR, 2, &tmp16);
  618. tmp16 = GMII_PHY_PGSEL_PAGE5;
  619. ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  620. GMII_PHY_PAGE_SELECT, 2, &tmp16);
  621. tmp16 = 0x0680;
  622. ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  623. MII_BMSR, 2, &tmp16);
  624. tmp16 = GMII_PHY_PGSEL_PAGE0;
  625. ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  626. GMII_PHY_PAGE_SELECT, 2, &tmp16);
  627. }
  628. static int ax88179_get_eee(struct net_device *net, struct ethtool_eee *edata)
  629. {
  630. struct usbnet *dev = netdev_priv(net);
  631. struct ax88179_data *priv = (struct ax88179_data *)dev->data;
  632. edata->eee_enabled = priv->eee_enabled;
  633. edata->eee_active = priv->eee_active;
  634. return ax88179_ethtool_get_eee(dev, edata);
  635. }
  636. static int ax88179_set_eee(struct net_device *net, struct ethtool_eee *edata)
  637. {
  638. struct usbnet *dev = netdev_priv(net);
  639. struct ax88179_data *priv = (struct ax88179_data *)dev->data;
  640. int ret = -EOPNOTSUPP;
  641. priv->eee_enabled = edata->eee_enabled;
  642. if (!priv->eee_enabled) {
  643. ax88179_disable_eee(dev);
  644. } else {
  645. priv->eee_enabled = ax88179_chk_eee(dev);
  646. if (!priv->eee_enabled)
  647. return -EOPNOTSUPP;
  648. ax88179_enable_eee(dev);
  649. }
  650. ret = ax88179_ethtool_set_eee(dev, edata);
  651. if (ret)
  652. return ret;
  653. mii_nway_restart(&dev->mii);
  654. usbnet_link_change(dev, 0, 0);
  655. return ret;
  656. }
  657. static int ax88179_ioctl(struct net_device *net, struct ifreq *rq, int cmd)
  658. {
  659. struct usbnet *dev = netdev_priv(net);
  660. return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
  661. }
  662. static const struct ethtool_ops ax88179_ethtool_ops = {
  663. .get_link = ethtool_op_get_link,
  664. .get_msglevel = usbnet_get_msglevel,
  665. .set_msglevel = usbnet_set_msglevel,
  666. .get_wol = ax88179_get_wol,
  667. .set_wol = ax88179_set_wol,
  668. .get_eeprom_len = ax88179_get_eeprom_len,
  669. .get_eeprom = ax88179_get_eeprom,
  670. .get_eee = ax88179_get_eee,
  671. .set_eee = ax88179_set_eee,
  672. .nway_reset = usbnet_nway_reset,
  673. .get_link_ksettings = ax88179_get_link_ksettings,
  674. .set_link_ksettings = ax88179_set_link_ksettings,
  675. };
  676. static void ax88179_set_multicast(struct net_device *net)
  677. {
  678. struct usbnet *dev = netdev_priv(net);
  679. struct ax88179_data *data = (struct ax88179_data *)dev->data;
  680. u8 *m_filter = ((u8 *)dev->data) + 12;
  681. data->rxctl = (AX_RX_CTL_START | AX_RX_CTL_AB | AX_RX_CTL_IPE);
  682. if (net->flags & IFF_PROMISC) {
  683. data->rxctl |= AX_RX_CTL_PRO;
  684. } else if (net->flags & IFF_ALLMULTI ||
  685. netdev_mc_count(net) > AX_MAX_MCAST) {
  686. data->rxctl |= AX_RX_CTL_AMALL;
  687. } else if (netdev_mc_empty(net)) {
  688. /* just broadcast and directed */
  689. } else {
  690. /* We use the 20 byte dev->data for our 8 byte filter buffer
  691. * to avoid allocating memory that is tricky to free later
  692. */
  693. u32 crc_bits;
  694. struct netdev_hw_addr *ha;
  695. memset(m_filter, 0, AX_MCAST_FLTSIZE);
  696. netdev_for_each_mc_addr(ha, net) {
  697. crc_bits = ether_crc(ETH_ALEN, ha->addr) >> 26;
  698. *(m_filter + (crc_bits >> 3)) |= (1 << (crc_bits & 7));
  699. }
  700. ax88179_write_cmd_async(dev, AX_ACCESS_MAC, AX_MULFLTARY,
  701. AX_MCAST_FLTSIZE, AX_MCAST_FLTSIZE,
  702. m_filter);
  703. data->rxctl |= AX_RX_CTL_AM;
  704. }
  705. ax88179_write_cmd_async(dev, AX_ACCESS_MAC, AX_RX_CTL,
  706. 2, 2, &data->rxctl);
  707. }
  708. static int
  709. ax88179_set_features(struct net_device *net, netdev_features_t features)
  710. {
  711. u8 tmp;
  712. struct usbnet *dev = netdev_priv(net);
  713. netdev_features_t changed = net->features ^ features;
  714. if (changed & NETIF_F_IP_CSUM) {
  715. ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, &tmp);
  716. tmp ^= AX_TXCOE_TCP | AX_TXCOE_UDP;
  717. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, &tmp);
  718. }
  719. if (changed & NETIF_F_IPV6_CSUM) {
  720. ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, &tmp);
  721. tmp ^= AX_TXCOE_TCPV6 | AX_TXCOE_UDPV6;
  722. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, &tmp);
  723. }
  724. if (changed & NETIF_F_RXCSUM) {
  725. ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, &tmp);
  726. tmp ^= AX_RXCOE_IP | AX_RXCOE_TCP | AX_RXCOE_UDP |
  727. AX_RXCOE_TCPV6 | AX_RXCOE_UDPV6;
  728. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, &tmp);
  729. }
  730. return 0;
  731. }
  732. static int ax88179_change_mtu(struct net_device *net, int new_mtu)
  733. {
  734. struct usbnet *dev = netdev_priv(net);
  735. u16 tmp16;
  736. net->mtu = new_mtu;
  737. dev->hard_mtu = net->mtu + net->hard_header_len;
  738. if (net->mtu > 1500) {
  739. ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
  740. 2, 2, &tmp16);
  741. tmp16 |= AX_MEDIUM_JUMBO_EN;
  742. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
  743. 2, 2, &tmp16);
  744. } else {
  745. ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
  746. 2, 2, &tmp16);
  747. tmp16 &= ~AX_MEDIUM_JUMBO_EN;
  748. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
  749. 2, 2, &tmp16);
  750. }
  751. /* max qlen depend on hard_mtu and rx_urb_size */
  752. usbnet_update_max_qlen(dev);
  753. return 0;
  754. }
  755. static int ax88179_set_mac_addr(struct net_device *net, void *p)
  756. {
  757. struct usbnet *dev = netdev_priv(net);
  758. struct sockaddr *addr = p;
  759. int ret;
  760. if (netif_running(net))
  761. return -EBUSY;
  762. if (!is_valid_ether_addr(addr->sa_data))
  763. return -EADDRNOTAVAIL;
  764. memcpy(net->dev_addr, addr->sa_data, ETH_ALEN);
  765. /* Set the MAC address */
  766. ret = ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, ETH_ALEN,
  767. ETH_ALEN, net->dev_addr);
  768. if (ret < 0)
  769. return ret;
  770. return 0;
  771. }
  772. static const struct net_device_ops ax88179_netdev_ops = {
  773. .ndo_open = usbnet_open,
  774. .ndo_stop = usbnet_stop,
  775. .ndo_start_xmit = usbnet_start_xmit,
  776. .ndo_tx_timeout = usbnet_tx_timeout,
  777. .ndo_get_stats64 = usbnet_get_stats64,
  778. .ndo_change_mtu = ax88179_change_mtu,
  779. .ndo_set_mac_address = ax88179_set_mac_addr,
  780. .ndo_validate_addr = eth_validate_addr,
  781. .ndo_do_ioctl = ax88179_ioctl,
  782. .ndo_set_rx_mode = ax88179_set_multicast,
  783. .ndo_set_features = ax88179_set_features,
  784. };
  785. static int ax88179_check_eeprom(struct usbnet *dev)
  786. {
  787. u8 i, buf, eeprom[20];
  788. u16 csum, delay = HZ / 10;
  789. unsigned long jtimeout;
  790. /* Read EEPROM content */
  791. for (i = 0; i < 6; i++) {
  792. buf = i;
  793. if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_SROM_ADDR,
  794. 1, 1, &buf) < 0)
  795. return -EINVAL;
  796. buf = EEP_RD;
  797. if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_SROM_CMD,
  798. 1, 1, &buf) < 0)
  799. return -EINVAL;
  800. jtimeout = jiffies + delay;
  801. do {
  802. ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_SROM_CMD,
  803. 1, 1, &buf);
  804. if (time_after(jiffies, jtimeout))
  805. return -EINVAL;
  806. } while (buf & EEP_BUSY);
  807. __ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_SROM_DATA_LOW,
  808. 2, 2, &eeprom[i * 2], 0);
  809. if ((i == 0) && (eeprom[0] == 0xFF))
  810. return -EINVAL;
  811. }
  812. csum = eeprom[6] + eeprom[7] + eeprom[8] + eeprom[9];
  813. csum = (csum >> 8) + (csum & 0xff);
  814. if ((csum + eeprom[10]) != 0xff)
  815. return -EINVAL;
  816. return 0;
  817. }
  818. static int ax88179_check_efuse(struct usbnet *dev, u16 *ledmode)
  819. {
  820. u8 i;
  821. u8 efuse[64];
  822. u16 csum = 0;
  823. if (ax88179_read_cmd(dev, AX_ACCESS_EFUS, 0, 64, 64, efuse) < 0)
  824. return -EINVAL;
  825. if (*efuse == 0xFF)
  826. return -EINVAL;
  827. for (i = 0; i < 64; i++)
  828. csum = csum + efuse[i];
  829. while (csum > 255)
  830. csum = (csum & 0x00FF) + ((csum >> 8) & 0x00FF);
  831. if (csum != 0xFF)
  832. return -EINVAL;
  833. *ledmode = (efuse[51] << 8) | efuse[52];
  834. return 0;
  835. }
  836. static int ax88179_convert_old_led(struct usbnet *dev, u16 *ledvalue)
  837. {
  838. u16 led;
  839. /* Loaded the old eFuse LED Mode */
  840. if (ax88179_read_cmd(dev, AX_ACCESS_EEPROM, 0x3C, 1, 2, &led) < 0)
  841. return -EINVAL;
  842. led >>= 8;
  843. switch (led) {
  844. case 0xFF:
  845. led = LED0_ACTIVE | LED1_LINK_10 | LED1_LINK_100 |
  846. LED1_LINK_1000 | LED2_ACTIVE | LED2_LINK_10 |
  847. LED2_LINK_100 | LED2_LINK_1000 | LED_VALID;
  848. break;
  849. case 0xFE:
  850. led = LED0_ACTIVE | LED1_LINK_1000 | LED2_LINK_100 | LED_VALID;
  851. break;
  852. case 0xFD:
  853. led = LED0_ACTIVE | LED1_LINK_1000 | LED2_LINK_100 |
  854. LED2_LINK_10 | LED_VALID;
  855. break;
  856. case 0xFC:
  857. led = LED0_ACTIVE | LED1_ACTIVE | LED1_LINK_1000 | LED2_ACTIVE |
  858. LED2_LINK_100 | LED2_LINK_10 | LED_VALID;
  859. break;
  860. default:
  861. led = LED0_ACTIVE | LED1_LINK_10 | LED1_LINK_100 |
  862. LED1_LINK_1000 | LED2_ACTIVE | LED2_LINK_10 |
  863. LED2_LINK_100 | LED2_LINK_1000 | LED_VALID;
  864. break;
  865. }
  866. *ledvalue = led;
  867. return 0;
  868. }
  869. static int ax88179_led_setting(struct usbnet *dev)
  870. {
  871. u8 ledfd, value = 0;
  872. u16 tmp, ledact, ledlink, ledvalue = 0, delay = HZ / 10;
  873. unsigned long jtimeout;
  874. /* Check AX88179 version. UA1 or UA2*/
  875. ax88179_read_cmd(dev, AX_ACCESS_MAC, GENERAL_STATUS, 1, 1, &value);
  876. if (!(value & AX_SECLD)) { /* UA1 */
  877. value = AX_GPIO_CTRL_GPIO3EN | AX_GPIO_CTRL_GPIO2EN |
  878. AX_GPIO_CTRL_GPIO1EN;
  879. if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_GPIO_CTRL,
  880. 1, 1, &value) < 0)
  881. return -EINVAL;
  882. }
  883. /* Check EEPROM */
  884. if (!ax88179_check_eeprom(dev)) {
  885. value = 0x42;
  886. if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_SROM_ADDR,
  887. 1, 1, &value) < 0)
  888. return -EINVAL;
  889. value = EEP_RD;
  890. if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_SROM_CMD,
  891. 1, 1, &value) < 0)
  892. return -EINVAL;
  893. jtimeout = jiffies + delay;
  894. do {
  895. ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_SROM_CMD,
  896. 1, 1, &value);
  897. if (time_after(jiffies, jtimeout))
  898. return -EINVAL;
  899. } while (value & EEP_BUSY);
  900. ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_SROM_DATA_HIGH,
  901. 1, 1, &value);
  902. ledvalue = (value << 8);
  903. ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_SROM_DATA_LOW,
  904. 1, 1, &value);
  905. ledvalue |= value;
  906. /* load internal ROM for defaule setting */
  907. if ((ledvalue == 0xFFFF) || ((ledvalue & LED_VALID) == 0))
  908. ax88179_convert_old_led(dev, &ledvalue);
  909. } else if (!ax88179_check_efuse(dev, &ledvalue)) {
  910. if ((ledvalue == 0xFFFF) || ((ledvalue & LED_VALID) == 0))
  911. ax88179_convert_old_led(dev, &ledvalue);
  912. } else {
  913. ax88179_convert_old_led(dev, &ledvalue);
  914. }
  915. tmp = GMII_PHY_PGSEL_EXT;
  916. ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  917. GMII_PHY_PAGE_SELECT, 2, &tmp);
  918. tmp = 0x2c;
  919. ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  920. GMII_PHYPAGE, 2, &tmp);
  921. ax88179_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  922. GMII_LED_ACT, 2, &ledact);
  923. ax88179_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  924. GMII_LED_LINK, 2, &ledlink);
  925. ledact &= GMII_LED_ACTIVE_MASK;
  926. ledlink &= GMII_LED_LINK_MASK;
  927. if (ledvalue & LED0_ACTIVE)
  928. ledact |= GMII_LED0_ACTIVE;
  929. if (ledvalue & LED1_ACTIVE)
  930. ledact |= GMII_LED1_ACTIVE;
  931. if (ledvalue & LED2_ACTIVE)
  932. ledact |= GMII_LED2_ACTIVE;
  933. if (ledvalue & LED0_LINK_10)
  934. ledlink |= GMII_LED0_LINK_10;
  935. if (ledvalue & LED1_LINK_10)
  936. ledlink |= GMII_LED1_LINK_10;
  937. if (ledvalue & LED2_LINK_10)
  938. ledlink |= GMII_LED2_LINK_10;
  939. if (ledvalue & LED0_LINK_100)
  940. ledlink |= GMII_LED0_LINK_100;
  941. if (ledvalue & LED1_LINK_100)
  942. ledlink |= GMII_LED1_LINK_100;
  943. if (ledvalue & LED2_LINK_100)
  944. ledlink |= GMII_LED2_LINK_100;
  945. if (ledvalue & LED0_LINK_1000)
  946. ledlink |= GMII_LED0_LINK_1000;
  947. if (ledvalue & LED1_LINK_1000)
  948. ledlink |= GMII_LED1_LINK_1000;
  949. if (ledvalue & LED2_LINK_1000)
  950. ledlink |= GMII_LED2_LINK_1000;
  951. tmp = ledact;
  952. ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  953. GMII_LED_ACT, 2, &tmp);
  954. tmp = ledlink;
  955. ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  956. GMII_LED_LINK, 2, &tmp);
  957. tmp = GMII_PHY_PGSEL_PAGE0;
  958. ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  959. GMII_PHY_PAGE_SELECT, 2, &tmp);
  960. /* LED full duplex setting */
  961. ledfd = 0;
  962. if (ledvalue & LED0_FD)
  963. ledfd |= 0x01;
  964. else if ((ledvalue & LED0_USB3_MASK) == 0)
  965. ledfd |= 0x02;
  966. if (ledvalue & LED1_FD)
  967. ledfd |= 0x04;
  968. else if ((ledvalue & LED1_USB3_MASK) == 0)
  969. ledfd |= 0x08;
  970. if (ledvalue & LED2_FD)
  971. ledfd |= 0x10;
  972. else if ((ledvalue & LED2_USB3_MASK) == 0)
  973. ledfd |= 0x20;
  974. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_LEDCTRL, 1, 1, &ledfd);
  975. return 0;
  976. }
  977. static int ax88179_bind(struct usbnet *dev, struct usb_interface *intf)
  978. {
  979. u8 buf[5];
  980. u16 *tmp16;
  981. u8 *tmp;
  982. struct ax88179_data *ax179_data = (struct ax88179_data *)dev->data;
  983. struct ethtool_eee eee_data;
  984. usbnet_get_endpoints(dev, intf);
  985. tmp16 = (u16 *)buf;
  986. tmp = (u8 *)buf;
  987. memset(ax179_data, 0, sizeof(*ax179_data));
  988. /* Power up ethernet PHY */
  989. *tmp16 = 0;
  990. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16);
  991. *tmp16 = AX_PHYPWR_RSTCTL_IPRL;
  992. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16);
  993. msleep(200);
  994. *tmp = AX_CLK_SELECT_ACS | AX_CLK_SELECT_BCS;
  995. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, tmp);
  996. msleep(100);
  997. ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, ETH_ALEN,
  998. ETH_ALEN, dev->net->dev_addr);
  999. memcpy(dev->net->perm_addr, dev->net->dev_addr, ETH_ALEN);
  1000. /* RX bulk configuration */
  1001. memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5);
  1002. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp);
  1003. dev->rx_urb_size = 1024 * 20;
  1004. *tmp = 0x34;
  1005. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_LOW, 1, 1, tmp);
  1006. *tmp = 0x52;
  1007. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_HIGH,
  1008. 1, 1, tmp);
  1009. dev->net->netdev_ops = &ax88179_netdev_ops;
  1010. dev->net->ethtool_ops = &ax88179_ethtool_ops;
  1011. dev->net->needed_headroom = 8;
  1012. dev->net->max_mtu = 4088;
  1013. /* Initialize MII structure */
  1014. dev->mii.dev = dev->net;
  1015. dev->mii.mdio_read = ax88179_mdio_read;
  1016. dev->mii.mdio_write = ax88179_mdio_write;
  1017. dev->mii.phy_id_mask = 0xff;
  1018. dev->mii.reg_num_mask = 0xff;
  1019. dev->mii.phy_id = 0x03;
  1020. dev->mii.supports_gmii = 1;
  1021. dev->net->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
  1022. NETIF_F_RXCSUM;
  1023. dev->net->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
  1024. NETIF_F_RXCSUM;
  1025. /* Enable checksum offload */
  1026. *tmp = AX_RXCOE_IP | AX_RXCOE_TCP | AX_RXCOE_UDP |
  1027. AX_RXCOE_TCPV6 | AX_RXCOE_UDPV6;
  1028. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, tmp);
  1029. *tmp = AX_TXCOE_IP | AX_TXCOE_TCP | AX_TXCOE_UDP |
  1030. AX_TXCOE_TCPV6 | AX_TXCOE_UDPV6;
  1031. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, tmp);
  1032. /* Configure RX control register => start operation */
  1033. *tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START |
  1034. AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB;
  1035. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, tmp16);
  1036. *tmp = AX_MONITOR_MODE_PMETYPE | AX_MONITOR_MODE_PMEPOL |
  1037. AX_MONITOR_MODE_RWMP;
  1038. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD, 1, 1, tmp);
  1039. /* Configure default medium type => giga */
  1040. *tmp16 = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN |
  1041. AX_MEDIUM_RXFLOW_CTRLEN | AX_MEDIUM_FULL_DUPLEX |
  1042. AX_MEDIUM_GIGAMODE;
  1043. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
  1044. 2, 2, tmp16);
  1045. ax88179_led_setting(dev);
  1046. ax179_data->eee_enabled = 0;
  1047. ax179_data->eee_active = 0;
  1048. ax88179_disable_eee(dev);
  1049. ax88179_ethtool_get_eee(dev, &eee_data);
  1050. eee_data.advertised = 0;
  1051. ax88179_ethtool_set_eee(dev, &eee_data);
  1052. /* Restart autoneg */
  1053. mii_nway_restart(&dev->mii);
  1054. usbnet_link_change(dev, 0, 0);
  1055. return 0;
  1056. }
  1057. static void ax88179_unbind(struct usbnet *dev, struct usb_interface *intf)
  1058. {
  1059. u16 tmp16;
  1060. /* Configure RX control register => stop operation */
  1061. tmp16 = AX_RX_CTL_STOP;
  1062. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, &tmp16);
  1063. tmp16 = 0;
  1064. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp16);
  1065. /* Power down ethernet PHY */
  1066. tmp16 = 0;
  1067. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, &tmp16);
  1068. }
  1069. static void
  1070. ax88179_rx_checksum(struct sk_buff *skb, u32 *pkt_hdr)
  1071. {
  1072. skb->ip_summed = CHECKSUM_NONE;
  1073. /* checksum error bit is set */
  1074. if ((*pkt_hdr & AX_RXHDR_L3CSUM_ERR) ||
  1075. (*pkt_hdr & AX_RXHDR_L4CSUM_ERR))
  1076. return;
  1077. /* It must be a TCP or UDP packet with a valid checksum */
  1078. if (((*pkt_hdr & AX_RXHDR_L4_TYPE_MASK) == AX_RXHDR_L4_TYPE_TCP) ||
  1079. ((*pkt_hdr & AX_RXHDR_L4_TYPE_MASK) == AX_RXHDR_L4_TYPE_UDP))
  1080. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1081. }
  1082. static int ax88179_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
  1083. {
  1084. struct sk_buff *ax_skb;
  1085. int pkt_cnt;
  1086. u32 rx_hdr;
  1087. u16 hdr_off;
  1088. u32 *pkt_hdr;
  1089. /* This check is no longer done by usbnet */
  1090. if (skb->len < dev->net->hard_header_len)
  1091. return 0;
  1092. skb_trim(skb, skb->len - 4);
  1093. rx_hdr = get_unaligned_le32(skb_tail_pointer(skb));
  1094. pkt_cnt = (u16)rx_hdr;
  1095. hdr_off = (u16)(rx_hdr >> 16);
  1096. pkt_hdr = (u32 *)(skb->data + hdr_off);
  1097. while (pkt_cnt--) {
  1098. u16 pkt_len;
  1099. le32_to_cpus(pkt_hdr);
  1100. pkt_len = (*pkt_hdr >> 16) & 0x1fff;
  1101. /* Check CRC or runt packet */
  1102. if ((*pkt_hdr & AX_RXHDR_CRC_ERR) ||
  1103. (*pkt_hdr & AX_RXHDR_DROP_ERR)) {
  1104. skb_pull(skb, (pkt_len + 7) & 0xFFF8);
  1105. pkt_hdr++;
  1106. continue;
  1107. }
  1108. if (pkt_cnt == 0) {
  1109. skb->len = pkt_len;
  1110. /* Skip IP alignment pseudo header */
  1111. skb_pull(skb, 2);
  1112. skb_set_tail_pointer(skb, skb->len);
  1113. skb->truesize = pkt_len + sizeof(struct sk_buff);
  1114. ax88179_rx_checksum(skb, pkt_hdr);
  1115. return 1;
  1116. }
  1117. ax_skb = skb_clone(skb, GFP_ATOMIC);
  1118. if (ax_skb) {
  1119. ax_skb->len = pkt_len;
  1120. /* Skip IP alignment pseudo header */
  1121. skb_pull(ax_skb, 2);
  1122. skb_set_tail_pointer(ax_skb, ax_skb->len);
  1123. ax_skb->truesize = pkt_len + sizeof(struct sk_buff);
  1124. ax88179_rx_checksum(ax_skb, pkt_hdr);
  1125. usbnet_skb_return(dev, ax_skb);
  1126. } else {
  1127. return 0;
  1128. }
  1129. skb_pull(skb, (pkt_len + 7) & 0xFFF8);
  1130. pkt_hdr++;
  1131. }
  1132. return 1;
  1133. }
  1134. static struct sk_buff *
  1135. ax88179_tx_fixup(struct usbnet *dev, struct sk_buff *skb, gfp_t flags)
  1136. {
  1137. u32 tx_hdr1, tx_hdr2;
  1138. int frame_size = dev->maxpacket;
  1139. int mss = skb_shinfo(skb)->gso_size;
  1140. int headroom;
  1141. void *ptr;
  1142. tx_hdr1 = skb->len;
  1143. tx_hdr2 = mss;
  1144. if (((skb->len + 8) % frame_size) == 0)
  1145. tx_hdr2 |= 0x80008000; /* Enable padding */
  1146. headroom = skb_headroom(skb) - 8;
  1147. if ((skb_header_cloned(skb) || headroom < 0) &&
  1148. pskb_expand_head(skb, headroom < 0 ? 8 : 0, 0, GFP_ATOMIC)) {
  1149. dev_kfree_skb_any(skb);
  1150. return NULL;
  1151. }
  1152. ptr = skb_push(skb, 8);
  1153. put_unaligned_le32(tx_hdr1, ptr);
  1154. put_unaligned_le32(tx_hdr2, ptr + 4);
  1155. return skb;
  1156. }
  1157. static int ax88179_link_reset(struct usbnet *dev)
  1158. {
  1159. struct ax88179_data *ax179_data = (struct ax88179_data *)dev->data;
  1160. u8 tmp[5], link_sts;
  1161. u16 mode, tmp16, delay = HZ / 10;
  1162. u32 tmp32 = 0x40000000;
  1163. unsigned long jtimeout;
  1164. jtimeout = jiffies + delay;
  1165. while (tmp32 & 0x40000000) {
  1166. mode = 0;
  1167. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, &mode);
  1168. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2,
  1169. &ax179_data->rxctl);
  1170. /*link up, check the usb device control TX FIFO full or empty*/
  1171. ax88179_read_cmd(dev, 0x81, 0x8c, 0, 4, &tmp32);
  1172. if (time_after(jiffies, jtimeout))
  1173. return 0;
  1174. }
  1175. mode = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN |
  1176. AX_MEDIUM_RXFLOW_CTRLEN;
  1177. ax88179_read_cmd(dev, AX_ACCESS_MAC, PHYSICAL_LINK_STATUS,
  1178. 1, 1, &link_sts);
  1179. ax88179_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  1180. GMII_PHY_PHYSR, 2, &tmp16);
  1181. if (!(tmp16 & GMII_PHY_PHYSR_LINK)) {
  1182. return 0;
  1183. } else if (GMII_PHY_PHYSR_GIGA == (tmp16 & GMII_PHY_PHYSR_SMASK)) {
  1184. mode |= AX_MEDIUM_GIGAMODE | AX_MEDIUM_EN_125MHZ;
  1185. if (dev->net->mtu > 1500)
  1186. mode |= AX_MEDIUM_JUMBO_EN;
  1187. if (link_sts & AX_USB_SS)
  1188. memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5);
  1189. else if (link_sts & AX_USB_HS)
  1190. memcpy(tmp, &AX88179_BULKIN_SIZE[1], 5);
  1191. else
  1192. memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5);
  1193. } else if (GMII_PHY_PHYSR_100 == (tmp16 & GMII_PHY_PHYSR_SMASK)) {
  1194. mode |= AX_MEDIUM_PS;
  1195. if (link_sts & (AX_USB_SS | AX_USB_HS))
  1196. memcpy(tmp, &AX88179_BULKIN_SIZE[2], 5);
  1197. else
  1198. memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5);
  1199. } else {
  1200. memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5);
  1201. }
  1202. /* RX bulk configuration */
  1203. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp);
  1204. dev->rx_urb_size = (1024 * (tmp[3] + 2));
  1205. if (tmp16 & GMII_PHY_PHYSR_FULL)
  1206. mode |= AX_MEDIUM_FULL_DUPLEX;
  1207. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
  1208. 2, 2, &mode);
  1209. ax179_data->eee_enabled = ax88179_chk_eee(dev);
  1210. netif_carrier_on(dev->net);
  1211. return 0;
  1212. }
  1213. static int ax88179_reset(struct usbnet *dev)
  1214. {
  1215. u8 buf[5];
  1216. u16 *tmp16;
  1217. u8 *tmp;
  1218. struct ax88179_data *ax179_data = (struct ax88179_data *)dev->data;
  1219. struct ethtool_eee eee_data;
  1220. tmp16 = (u16 *)buf;
  1221. tmp = (u8 *)buf;
  1222. /* Power up ethernet PHY */
  1223. *tmp16 = 0;
  1224. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16);
  1225. *tmp16 = AX_PHYPWR_RSTCTL_IPRL;
  1226. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16);
  1227. msleep(200);
  1228. *tmp = AX_CLK_SELECT_ACS | AX_CLK_SELECT_BCS;
  1229. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, tmp);
  1230. msleep(100);
  1231. /* Ethernet PHY Auto Detach*/
  1232. ax88179_auto_detach(dev, 0);
  1233. ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, ETH_ALEN, ETH_ALEN,
  1234. dev->net->dev_addr);
  1235. /* RX bulk configuration */
  1236. memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5);
  1237. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp);
  1238. dev->rx_urb_size = 1024 * 20;
  1239. *tmp = 0x34;
  1240. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_LOW, 1, 1, tmp);
  1241. *tmp = 0x52;
  1242. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_HIGH,
  1243. 1, 1, tmp);
  1244. dev->net->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
  1245. NETIF_F_RXCSUM;
  1246. dev->net->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
  1247. NETIF_F_RXCSUM;
  1248. /* Enable checksum offload */
  1249. *tmp = AX_RXCOE_IP | AX_RXCOE_TCP | AX_RXCOE_UDP |
  1250. AX_RXCOE_TCPV6 | AX_RXCOE_UDPV6;
  1251. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, tmp);
  1252. *tmp = AX_TXCOE_IP | AX_TXCOE_TCP | AX_TXCOE_UDP |
  1253. AX_TXCOE_TCPV6 | AX_TXCOE_UDPV6;
  1254. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, tmp);
  1255. /* Configure RX control register => start operation */
  1256. *tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START |
  1257. AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB;
  1258. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, tmp16);
  1259. *tmp = AX_MONITOR_MODE_PMETYPE | AX_MONITOR_MODE_PMEPOL |
  1260. AX_MONITOR_MODE_RWMP;
  1261. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD, 1, 1, tmp);
  1262. /* Configure default medium type => giga */
  1263. *tmp16 = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN |
  1264. AX_MEDIUM_RXFLOW_CTRLEN | AX_MEDIUM_FULL_DUPLEX |
  1265. AX_MEDIUM_GIGAMODE;
  1266. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
  1267. 2, 2, tmp16);
  1268. ax88179_led_setting(dev);
  1269. ax179_data->eee_enabled = 0;
  1270. ax179_data->eee_active = 0;
  1271. ax88179_disable_eee(dev);
  1272. ax88179_ethtool_get_eee(dev, &eee_data);
  1273. eee_data.advertised = 0;
  1274. ax88179_ethtool_set_eee(dev, &eee_data);
  1275. /* Restart autoneg */
  1276. mii_nway_restart(&dev->mii);
  1277. usbnet_link_change(dev, 0, 0);
  1278. return 0;
  1279. }
  1280. static int ax88179_stop(struct usbnet *dev)
  1281. {
  1282. u16 tmp16;
  1283. ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
  1284. 2, 2, &tmp16);
  1285. tmp16 &= ~AX_MEDIUM_RECEIVE_EN;
  1286. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
  1287. 2, 2, &tmp16);
  1288. return 0;
  1289. }
  1290. static const struct driver_info ax88179_info = {
  1291. .description = "ASIX AX88179 USB 3.0 Gigabit Ethernet",
  1292. .bind = ax88179_bind,
  1293. .unbind = ax88179_unbind,
  1294. .status = ax88179_status,
  1295. .link_reset = ax88179_link_reset,
  1296. .reset = ax88179_reset,
  1297. .stop = ax88179_stop,
  1298. .flags = FLAG_ETHER | FLAG_FRAMING_AX,
  1299. .rx_fixup = ax88179_rx_fixup,
  1300. .tx_fixup = ax88179_tx_fixup,
  1301. };
  1302. static const struct driver_info ax88178a_info = {
  1303. .description = "ASIX AX88178A USB 2.0 Gigabit Ethernet",
  1304. .bind = ax88179_bind,
  1305. .unbind = ax88179_unbind,
  1306. .status = ax88179_status,
  1307. .link_reset = ax88179_link_reset,
  1308. .reset = ax88179_reset,
  1309. .stop = ax88179_stop,
  1310. .flags = FLAG_ETHER | FLAG_FRAMING_AX,
  1311. .rx_fixup = ax88179_rx_fixup,
  1312. .tx_fixup = ax88179_tx_fixup,
  1313. };
  1314. static const struct driver_info cypress_GX3_info = {
  1315. .description = "Cypress GX3 SuperSpeed to Gigabit Ethernet Controller",
  1316. .bind = ax88179_bind,
  1317. .unbind = ax88179_unbind,
  1318. .status = ax88179_status,
  1319. .link_reset = ax88179_link_reset,
  1320. .reset = ax88179_reset,
  1321. .stop = ax88179_stop,
  1322. .flags = FLAG_ETHER | FLAG_FRAMING_AX,
  1323. .rx_fixup = ax88179_rx_fixup,
  1324. .tx_fixup = ax88179_tx_fixup,
  1325. };
  1326. static const struct driver_info dlink_dub1312_info = {
  1327. .description = "D-Link DUB-1312 USB 3.0 to Gigabit Ethernet Adapter",
  1328. .bind = ax88179_bind,
  1329. .unbind = ax88179_unbind,
  1330. .status = ax88179_status,
  1331. .link_reset = ax88179_link_reset,
  1332. .reset = ax88179_reset,
  1333. .stop = ax88179_stop,
  1334. .flags = FLAG_ETHER | FLAG_FRAMING_AX,
  1335. .rx_fixup = ax88179_rx_fixup,
  1336. .tx_fixup = ax88179_tx_fixup,
  1337. };
  1338. static const struct driver_info sitecom_info = {
  1339. .description = "Sitecom USB 3.0 to Gigabit Adapter",
  1340. .bind = ax88179_bind,
  1341. .unbind = ax88179_unbind,
  1342. .status = ax88179_status,
  1343. .link_reset = ax88179_link_reset,
  1344. .reset = ax88179_reset,
  1345. .stop = ax88179_stop,
  1346. .flags = FLAG_ETHER | FLAG_FRAMING_AX,
  1347. .rx_fixup = ax88179_rx_fixup,
  1348. .tx_fixup = ax88179_tx_fixup,
  1349. };
  1350. static const struct driver_info samsung_info = {
  1351. .description = "Samsung USB Ethernet Adapter",
  1352. .bind = ax88179_bind,
  1353. .unbind = ax88179_unbind,
  1354. .status = ax88179_status,
  1355. .link_reset = ax88179_link_reset,
  1356. .reset = ax88179_reset,
  1357. .stop = ax88179_stop,
  1358. .flags = FLAG_ETHER | FLAG_FRAMING_AX,
  1359. .rx_fixup = ax88179_rx_fixup,
  1360. .tx_fixup = ax88179_tx_fixup,
  1361. };
  1362. static const struct driver_info lenovo_info = {
  1363. .description = "Lenovo OneLinkDock Gigabit LAN",
  1364. .bind = ax88179_bind,
  1365. .unbind = ax88179_unbind,
  1366. .status = ax88179_status,
  1367. .link_reset = ax88179_link_reset,
  1368. .reset = ax88179_reset,
  1369. .stop = ax88179_stop,
  1370. .flags = FLAG_ETHER | FLAG_FRAMING_AX,
  1371. .rx_fixup = ax88179_rx_fixup,
  1372. .tx_fixup = ax88179_tx_fixup,
  1373. };
  1374. static const struct driver_info belkin_info = {
  1375. .description = "Belkin USB Ethernet Adapter",
  1376. .bind = ax88179_bind,
  1377. .unbind = ax88179_unbind,
  1378. .status = ax88179_status,
  1379. .link_reset = ax88179_link_reset,
  1380. .reset = ax88179_reset,
  1381. .stop = ax88179_stop,
  1382. .flags = FLAG_ETHER | FLAG_FRAMING_AX,
  1383. .rx_fixup = ax88179_rx_fixup,
  1384. .tx_fixup = ax88179_tx_fixup,
  1385. };
  1386. static const struct usb_device_id products[] = {
  1387. {
  1388. /* ASIX AX88179 10/100/1000 */
  1389. USB_DEVICE(0x0b95, 0x1790),
  1390. .driver_info = (unsigned long)&ax88179_info,
  1391. }, {
  1392. /* ASIX AX88178A 10/100/1000 */
  1393. USB_DEVICE(0x0b95, 0x178a),
  1394. .driver_info = (unsigned long)&ax88178a_info,
  1395. }, {
  1396. /* Cypress GX3 SuperSpeed to Gigabit Ethernet Bridge Controller */
  1397. USB_DEVICE(0x04b4, 0x3610),
  1398. .driver_info = (unsigned long)&cypress_GX3_info,
  1399. }, {
  1400. /* D-Link DUB-1312 USB 3.0 to Gigabit Ethernet Adapter */
  1401. USB_DEVICE(0x2001, 0x4a00),
  1402. .driver_info = (unsigned long)&dlink_dub1312_info,
  1403. }, {
  1404. /* Sitecom USB 3.0 to Gigabit Adapter */
  1405. USB_DEVICE(0x0df6, 0x0072),
  1406. .driver_info = (unsigned long)&sitecom_info,
  1407. }, {
  1408. /* Samsung USB Ethernet Adapter */
  1409. USB_DEVICE(0x04e8, 0xa100),
  1410. .driver_info = (unsigned long)&samsung_info,
  1411. }, {
  1412. /* Lenovo OneLinkDock Gigabit LAN */
  1413. USB_DEVICE(0x17ef, 0x304b),
  1414. .driver_info = (unsigned long)&lenovo_info,
  1415. }, {
  1416. /* Belkin B2B128 USB 3.0 Hub + Gigabit Ethernet Adapter */
  1417. USB_DEVICE(0x050d, 0x0128),
  1418. .driver_info = (unsigned long)&belkin_info,
  1419. },
  1420. { },
  1421. };
  1422. MODULE_DEVICE_TABLE(usb, products);
  1423. static struct usb_driver ax88179_178a_driver = {
  1424. .name = "ax88179_178a",
  1425. .id_table = products,
  1426. .probe = usbnet_probe,
  1427. .suspend = ax88179_suspend,
  1428. .resume = ax88179_resume,
  1429. .reset_resume = ax88179_resume,
  1430. .disconnect = usbnet_disconnect,
  1431. .supports_autosuspend = 1,
  1432. .disable_hub_initiated_lpm = 1,
  1433. };
  1434. module_usb_driver(ax88179_178a_driver);
  1435. MODULE_DESCRIPTION("ASIX AX88179/178A based USB 3.0/2.0 Gigabit Ethernet Devices");
  1436. MODULE_LICENSE("GPL");