sungem_phy.c 30 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * PHY drivers for the sungem ethernet driver.
  4. *
  5. * This file could be shared with other drivers.
  6. *
  7. * (c) 2002-2007, Benjamin Herrenscmidt (benh@kernel.crashing.org)
  8. *
  9. * TODO:
  10. * - Add support for PHYs that provide an IRQ line
  11. * - Eventually moved the entire polling state machine in
  12. * there (out of the eth driver), so that it can easily be
  13. * skipped on PHYs that implement it in hardware.
  14. * - On LXT971 & BCM5201, Apple uses some chip specific regs
  15. * to read the link status. Figure out why and if it makes
  16. * sense to do the same (magic aneg ?)
  17. * - Apple has some additional power management code for some
  18. * Broadcom PHYs that they "hide" from the OpenSource version
  19. * of darwin, still need to reverse engineer that
  20. */
  21. #include <linux/module.h>
  22. #include <linux/kernel.h>
  23. #include <linux/types.h>
  24. #include <linux/netdevice.h>
  25. #include <linux/etherdevice.h>
  26. #include <linux/mii.h>
  27. #include <linux/ethtool.h>
  28. #include <linux/delay.h>
  29. #ifdef CONFIG_PPC_PMAC
  30. #include <asm/prom.h>
  31. #endif
  32. #include <linux/sungem_phy.h>
  33. /* Link modes of the BCM5400 PHY */
  34. static const int phy_BCM5400_link_table[8][3] = {
  35. { 0, 0, 0 }, /* No link */
  36. { 0, 0, 0 }, /* 10BT Half Duplex */
  37. { 1, 0, 0 }, /* 10BT Full Duplex */
  38. { 0, 1, 0 }, /* 100BT Half Duplex */
  39. { 0, 1, 0 }, /* 100BT Half Duplex */
  40. { 1, 1, 0 }, /* 100BT Full Duplex*/
  41. { 1, 0, 1 }, /* 1000BT */
  42. { 1, 0, 1 }, /* 1000BT */
  43. };
  44. static inline int __sungem_phy_read(struct mii_phy* phy, int id, int reg)
  45. {
  46. return phy->mdio_read(phy->dev, id, reg);
  47. }
  48. static inline void __sungem_phy_write(struct mii_phy* phy, int id, int reg, int val)
  49. {
  50. phy->mdio_write(phy->dev, id, reg, val);
  51. }
  52. static inline int sungem_phy_read(struct mii_phy* phy, int reg)
  53. {
  54. return phy->mdio_read(phy->dev, phy->mii_id, reg);
  55. }
  56. static inline void sungem_phy_write(struct mii_phy* phy, int reg, int val)
  57. {
  58. phy->mdio_write(phy->dev, phy->mii_id, reg, val);
  59. }
  60. static int reset_one_mii_phy(struct mii_phy* phy, int phy_id)
  61. {
  62. u16 val;
  63. int limit = 10000;
  64. val = __sungem_phy_read(phy, phy_id, MII_BMCR);
  65. val &= ~(BMCR_ISOLATE | BMCR_PDOWN);
  66. val |= BMCR_RESET;
  67. __sungem_phy_write(phy, phy_id, MII_BMCR, val);
  68. udelay(100);
  69. while (--limit) {
  70. val = __sungem_phy_read(phy, phy_id, MII_BMCR);
  71. if ((val & BMCR_RESET) == 0)
  72. break;
  73. udelay(10);
  74. }
  75. if ((val & BMCR_ISOLATE) && limit > 0)
  76. __sungem_phy_write(phy, phy_id, MII_BMCR, val & ~BMCR_ISOLATE);
  77. return limit <= 0;
  78. }
  79. static int bcm5201_init(struct mii_phy* phy)
  80. {
  81. u16 data;
  82. data = sungem_phy_read(phy, MII_BCM5201_MULTIPHY);
  83. data &= ~MII_BCM5201_MULTIPHY_SUPERISOLATE;
  84. sungem_phy_write(phy, MII_BCM5201_MULTIPHY, data);
  85. sungem_phy_write(phy, MII_BCM5201_INTERRUPT, 0);
  86. return 0;
  87. }
  88. static int bcm5201_suspend(struct mii_phy* phy)
  89. {
  90. sungem_phy_write(phy, MII_BCM5201_INTERRUPT, 0);
  91. sungem_phy_write(phy, MII_BCM5201_MULTIPHY, MII_BCM5201_MULTIPHY_SUPERISOLATE);
  92. return 0;
  93. }
  94. static int bcm5221_init(struct mii_phy* phy)
  95. {
  96. u16 data;
  97. data = sungem_phy_read(phy, MII_BCM5221_TEST);
  98. sungem_phy_write(phy, MII_BCM5221_TEST,
  99. data | MII_BCM5221_TEST_ENABLE_SHADOWS);
  100. data = sungem_phy_read(phy, MII_BCM5221_SHDOW_AUX_STAT2);
  101. sungem_phy_write(phy, MII_BCM5221_SHDOW_AUX_STAT2,
  102. data | MII_BCM5221_SHDOW_AUX_STAT2_APD);
  103. data = sungem_phy_read(phy, MII_BCM5221_SHDOW_AUX_MODE4);
  104. sungem_phy_write(phy, MII_BCM5221_SHDOW_AUX_MODE4,
  105. data | MII_BCM5221_SHDOW_AUX_MODE4_CLKLOPWR);
  106. data = sungem_phy_read(phy, MII_BCM5221_TEST);
  107. sungem_phy_write(phy, MII_BCM5221_TEST,
  108. data & ~MII_BCM5221_TEST_ENABLE_SHADOWS);
  109. return 0;
  110. }
  111. static int bcm5221_suspend(struct mii_phy* phy)
  112. {
  113. u16 data;
  114. data = sungem_phy_read(phy, MII_BCM5221_TEST);
  115. sungem_phy_write(phy, MII_BCM5221_TEST,
  116. data | MII_BCM5221_TEST_ENABLE_SHADOWS);
  117. data = sungem_phy_read(phy, MII_BCM5221_SHDOW_AUX_MODE4);
  118. sungem_phy_write(phy, MII_BCM5221_SHDOW_AUX_MODE4,
  119. data | MII_BCM5221_SHDOW_AUX_MODE4_IDDQMODE);
  120. return 0;
  121. }
  122. static int bcm5241_init(struct mii_phy* phy)
  123. {
  124. u16 data;
  125. data = sungem_phy_read(phy, MII_BCM5221_TEST);
  126. sungem_phy_write(phy, MII_BCM5221_TEST,
  127. data | MII_BCM5221_TEST_ENABLE_SHADOWS);
  128. data = sungem_phy_read(phy, MII_BCM5221_SHDOW_AUX_STAT2);
  129. sungem_phy_write(phy, MII_BCM5221_SHDOW_AUX_STAT2,
  130. data | MII_BCM5221_SHDOW_AUX_STAT2_APD);
  131. data = sungem_phy_read(phy, MII_BCM5221_SHDOW_AUX_MODE4);
  132. sungem_phy_write(phy, MII_BCM5221_SHDOW_AUX_MODE4,
  133. data & ~MII_BCM5241_SHDOW_AUX_MODE4_STANDBYPWR);
  134. data = sungem_phy_read(phy, MII_BCM5221_TEST);
  135. sungem_phy_write(phy, MII_BCM5221_TEST,
  136. data & ~MII_BCM5221_TEST_ENABLE_SHADOWS);
  137. return 0;
  138. }
  139. static int bcm5241_suspend(struct mii_phy* phy)
  140. {
  141. u16 data;
  142. data = sungem_phy_read(phy, MII_BCM5221_TEST);
  143. sungem_phy_write(phy, MII_BCM5221_TEST,
  144. data | MII_BCM5221_TEST_ENABLE_SHADOWS);
  145. data = sungem_phy_read(phy, MII_BCM5221_SHDOW_AUX_MODE4);
  146. sungem_phy_write(phy, MII_BCM5221_SHDOW_AUX_MODE4,
  147. data | MII_BCM5241_SHDOW_AUX_MODE4_STANDBYPWR);
  148. return 0;
  149. }
  150. static int bcm5400_init(struct mii_phy* phy)
  151. {
  152. u16 data;
  153. /* Configure for gigabit full duplex */
  154. data = sungem_phy_read(phy, MII_BCM5400_AUXCONTROL);
  155. data |= MII_BCM5400_AUXCONTROL_PWR10BASET;
  156. sungem_phy_write(phy, MII_BCM5400_AUXCONTROL, data);
  157. data = sungem_phy_read(phy, MII_BCM5400_GB_CONTROL);
  158. data |= MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP;
  159. sungem_phy_write(phy, MII_BCM5400_GB_CONTROL, data);
  160. udelay(100);
  161. /* Reset and configure cascaded 10/100 PHY */
  162. (void)reset_one_mii_phy(phy, 0x1f);
  163. data = __sungem_phy_read(phy, 0x1f, MII_BCM5201_MULTIPHY);
  164. data |= MII_BCM5201_MULTIPHY_SERIALMODE;
  165. __sungem_phy_write(phy, 0x1f, MII_BCM5201_MULTIPHY, data);
  166. data = sungem_phy_read(phy, MII_BCM5400_AUXCONTROL);
  167. data &= ~MII_BCM5400_AUXCONTROL_PWR10BASET;
  168. sungem_phy_write(phy, MII_BCM5400_AUXCONTROL, data);
  169. return 0;
  170. }
  171. static int bcm5400_suspend(struct mii_phy* phy)
  172. {
  173. #if 0 /* Commented out in Darwin... someone has those dawn docs ? */
  174. sungem_phy_write(phy, MII_BMCR, BMCR_PDOWN);
  175. #endif
  176. return 0;
  177. }
  178. static int bcm5401_init(struct mii_phy* phy)
  179. {
  180. u16 data;
  181. int rev;
  182. rev = sungem_phy_read(phy, MII_PHYSID2) & 0x000f;
  183. if (rev == 0 || rev == 3) {
  184. /* Some revisions of 5401 appear to need this
  185. * initialisation sequence to disable, according
  186. * to OF, "tap power management"
  187. *
  188. * WARNING ! OF and Darwin don't agree on the
  189. * register addresses. OF seem to interpret the
  190. * register numbers below as decimal
  191. *
  192. * Note: This should (and does) match tg3_init_5401phy_dsp
  193. * in the tg3.c driver. -DaveM
  194. */
  195. sungem_phy_write(phy, 0x18, 0x0c20);
  196. sungem_phy_write(phy, 0x17, 0x0012);
  197. sungem_phy_write(phy, 0x15, 0x1804);
  198. sungem_phy_write(phy, 0x17, 0x0013);
  199. sungem_phy_write(phy, 0x15, 0x1204);
  200. sungem_phy_write(phy, 0x17, 0x8006);
  201. sungem_phy_write(phy, 0x15, 0x0132);
  202. sungem_phy_write(phy, 0x17, 0x8006);
  203. sungem_phy_write(phy, 0x15, 0x0232);
  204. sungem_phy_write(phy, 0x17, 0x201f);
  205. sungem_phy_write(phy, 0x15, 0x0a20);
  206. }
  207. /* Configure for gigabit full duplex */
  208. data = sungem_phy_read(phy, MII_BCM5400_GB_CONTROL);
  209. data |= MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP;
  210. sungem_phy_write(phy, MII_BCM5400_GB_CONTROL, data);
  211. udelay(10);
  212. /* Reset and configure cascaded 10/100 PHY */
  213. (void)reset_one_mii_phy(phy, 0x1f);
  214. data = __sungem_phy_read(phy, 0x1f, MII_BCM5201_MULTIPHY);
  215. data |= MII_BCM5201_MULTIPHY_SERIALMODE;
  216. __sungem_phy_write(phy, 0x1f, MII_BCM5201_MULTIPHY, data);
  217. return 0;
  218. }
  219. static int bcm5401_suspend(struct mii_phy* phy)
  220. {
  221. #if 0 /* Commented out in Darwin... someone has those dawn docs ? */
  222. sungem_phy_write(phy, MII_BMCR, BMCR_PDOWN);
  223. #endif
  224. return 0;
  225. }
  226. static int bcm5411_init(struct mii_phy* phy)
  227. {
  228. u16 data;
  229. /* Here's some more Apple black magic to setup
  230. * some voltage stuffs.
  231. */
  232. sungem_phy_write(phy, 0x1c, 0x8c23);
  233. sungem_phy_write(phy, 0x1c, 0x8ca3);
  234. sungem_phy_write(phy, 0x1c, 0x8c23);
  235. /* Here, Apple seems to want to reset it, do
  236. * it as well
  237. */
  238. sungem_phy_write(phy, MII_BMCR, BMCR_RESET);
  239. sungem_phy_write(phy, MII_BMCR, 0x1340);
  240. data = sungem_phy_read(phy, MII_BCM5400_GB_CONTROL);
  241. data |= MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP;
  242. sungem_phy_write(phy, MII_BCM5400_GB_CONTROL, data);
  243. udelay(10);
  244. /* Reset and configure cascaded 10/100 PHY */
  245. (void)reset_one_mii_phy(phy, 0x1f);
  246. return 0;
  247. }
  248. static int genmii_setup_aneg(struct mii_phy *phy, u32 advertise)
  249. {
  250. u16 ctl, adv;
  251. phy->autoneg = 1;
  252. phy->speed = SPEED_10;
  253. phy->duplex = DUPLEX_HALF;
  254. phy->pause = 0;
  255. phy->advertising = advertise;
  256. /* Setup standard advertise */
  257. adv = sungem_phy_read(phy, MII_ADVERTISE);
  258. adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
  259. if (advertise & ADVERTISED_10baseT_Half)
  260. adv |= ADVERTISE_10HALF;
  261. if (advertise & ADVERTISED_10baseT_Full)
  262. adv |= ADVERTISE_10FULL;
  263. if (advertise & ADVERTISED_100baseT_Half)
  264. adv |= ADVERTISE_100HALF;
  265. if (advertise & ADVERTISED_100baseT_Full)
  266. adv |= ADVERTISE_100FULL;
  267. sungem_phy_write(phy, MII_ADVERTISE, adv);
  268. /* Start/Restart aneg */
  269. ctl = sungem_phy_read(phy, MII_BMCR);
  270. ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
  271. sungem_phy_write(phy, MII_BMCR, ctl);
  272. return 0;
  273. }
  274. static int genmii_setup_forced(struct mii_phy *phy, int speed, int fd)
  275. {
  276. u16 ctl;
  277. phy->autoneg = 0;
  278. phy->speed = speed;
  279. phy->duplex = fd;
  280. phy->pause = 0;
  281. ctl = sungem_phy_read(phy, MII_BMCR);
  282. ctl &= ~(BMCR_FULLDPLX|BMCR_SPEED100|BMCR_ANENABLE);
  283. /* First reset the PHY */
  284. sungem_phy_write(phy, MII_BMCR, ctl | BMCR_RESET);
  285. /* Select speed & duplex */
  286. switch(speed) {
  287. case SPEED_10:
  288. break;
  289. case SPEED_100:
  290. ctl |= BMCR_SPEED100;
  291. break;
  292. case SPEED_1000:
  293. default:
  294. return -EINVAL;
  295. }
  296. if (fd == DUPLEX_FULL)
  297. ctl |= BMCR_FULLDPLX;
  298. sungem_phy_write(phy, MII_BMCR, ctl);
  299. return 0;
  300. }
  301. static int genmii_poll_link(struct mii_phy *phy)
  302. {
  303. u16 status;
  304. (void)sungem_phy_read(phy, MII_BMSR);
  305. status = sungem_phy_read(phy, MII_BMSR);
  306. if ((status & BMSR_LSTATUS) == 0)
  307. return 0;
  308. if (phy->autoneg && !(status & BMSR_ANEGCOMPLETE))
  309. return 0;
  310. return 1;
  311. }
  312. static int genmii_read_link(struct mii_phy *phy)
  313. {
  314. u16 lpa;
  315. if (phy->autoneg) {
  316. lpa = sungem_phy_read(phy, MII_LPA);
  317. if (lpa & (LPA_10FULL | LPA_100FULL))
  318. phy->duplex = DUPLEX_FULL;
  319. else
  320. phy->duplex = DUPLEX_HALF;
  321. if (lpa & (LPA_100FULL | LPA_100HALF))
  322. phy->speed = SPEED_100;
  323. else
  324. phy->speed = SPEED_10;
  325. phy->pause = 0;
  326. }
  327. /* On non-aneg, we assume what we put in BMCR is the speed,
  328. * though magic-aneg shouldn't prevent this case from occurring
  329. */
  330. return 0;
  331. }
  332. static int generic_suspend(struct mii_phy* phy)
  333. {
  334. sungem_phy_write(phy, MII_BMCR, BMCR_PDOWN);
  335. return 0;
  336. }
  337. static int bcm5421_init(struct mii_phy* phy)
  338. {
  339. u16 data;
  340. unsigned int id;
  341. id = (sungem_phy_read(phy, MII_PHYSID1) << 16 | sungem_phy_read(phy, MII_PHYSID2));
  342. /* Revision 0 of 5421 needs some fixups */
  343. if (id == 0x002060e0) {
  344. /* This is borrowed from MacOS
  345. */
  346. sungem_phy_write(phy, 0x18, 0x1007);
  347. data = sungem_phy_read(phy, 0x18);
  348. sungem_phy_write(phy, 0x18, data | 0x0400);
  349. sungem_phy_write(phy, 0x18, 0x0007);
  350. data = sungem_phy_read(phy, 0x18);
  351. sungem_phy_write(phy, 0x18, data | 0x0800);
  352. sungem_phy_write(phy, 0x17, 0x000a);
  353. data = sungem_phy_read(phy, 0x15);
  354. sungem_phy_write(phy, 0x15, data | 0x0200);
  355. }
  356. /* Pick up some init code from OF for K2 version */
  357. if ((id & 0xfffffff0) == 0x002062e0) {
  358. sungem_phy_write(phy, 4, 0x01e1);
  359. sungem_phy_write(phy, 9, 0x0300);
  360. }
  361. /* Check if we can enable automatic low power */
  362. #ifdef CONFIG_PPC_PMAC
  363. if (phy->platform_data) {
  364. struct device_node *np = of_get_parent(phy->platform_data);
  365. int can_low_power = 1;
  366. if (np == NULL || of_get_property(np, "no-autolowpower", NULL))
  367. can_low_power = 0;
  368. if (can_low_power) {
  369. /* Enable automatic low-power */
  370. sungem_phy_write(phy, 0x1c, 0x9002);
  371. sungem_phy_write(phy, 0x1c, 0xa821);
  372. sungem_phy_write(phy, 0x1c, 0x941d);
  373. }
  374. }
  375. #endif /* CONFIG_PPC_PMAC */
  376. return 0;
  377. }
  378. static int bcm54xx_setup_aneg(struct mii_phy *phy, u32 advertise)
  379. {
  380. u16 ctl, adv;
  381. phy->autoneg = 1;
  382. phy->speed = SPEED_10;
  383. phy->duplex = DUPLEX_HALF;
  384. phy->pause = 0;
  385. phy->advertising = advertise;
  386. /* Setup standard advertise */
  387. adv = sungem_phy_read(phy, MII_ADVERTISE);
  388. adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
  389. if (advertise & ADVERTISED_10baseT_Half)
  390. adv |= ADVERTISE_10HALF;
  391. if (advertise & ADVERTISED_10baseT_Full)
  392. adv |= ADVERTISE_10FULL;
  393. if (advertise & ADVERTISED_100baseT_Half)
  394. adv |= ADVERTISE_100HALF;
  395. if (advertise & ADVERTISED_100baseT_Full)
  396. adv |= ADVERTISE_100FULL;
  397. if (advertise & ADVERTISED_Pause)
  398. adv |= ADVERTISE_PAUSE_CAP;
  399. if (advertise & ADVERTISED_Asym_Pause)
  400. adv |= ADVERTISE_PAUSE_ASYM;
  401. sungem_phy_write(phy, MII_ADVERTISE, adv);
  402. /* Setup 1000BT advertise */
  403. adv = sungem_phy_read(phy, MII_1000BASETCONTROL);
  404. adv &= ~(MII_1000BASETCONTROL_FULLDUPLEXCAP|MII_1000BASETCONTROL_HALFDUPLEXCAP);
  405. if (advertise & SUPPORTED_1000baseT_Half)
  406. adv |= MII_1000BASETCONTROL_HALFDUPLEXCAP;
  407. if (advertise & SUPPORTED_1000baseT_Full)
  408. adv |= MII_1000BASETCONTROL_FULLDUPLEXCAP;
  409. sungem_phy_write(phy, MII_1000BASETCONTROL, adv);
  410. /* Start/Restart aneg */
  411. ctl = sungem_phy_read(phy, MII_BMCR);
  412. ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
  413. sungem_phy_write(phy, MII_BMCR, ctl);
  414. return 0;
  415. }
  416. static int bcm54xx_setup_forced(struct mii_phy *phy, int speed, int fd)
  417. {
  418. u16 ctl;
  419. phy->autoneg = 0;
  420. phy->speed = speed;
  421. phy->duplex = fd;
  422. phy->pause = 0;
  423. ctl = sungem_phy_read(phy, MII_BMCR);
  424. ctl &= ~(BMCR_FULLDPLX|BMCR_SPEED100|BMCR_SPD2|BMCR_ANENABLE);
  425. /* First reset the PHY */
  426. sungem_phy_write(phy, MII_BMCR, ctl | BMCR_RESET);
  427. /* Select speed & duplex */
  428. switch(speed) {
  429. case SPEED_10:
  430. break;
  431. case SPEED_100:
  432. ctl |= BMCR_SPEED100;
  433. break;
  434. case SPEED_1000:
  435. ctl |= BMCR_SPD2;
  436. }
  437. if (fd == DUPLEX_FULL)
  438. ctl |= BMCR_FULLDPLX;
  439. // XXX Should we set the sungem to GII now on 1000BT ?
  440. sungem_phy_write(phy, MII_BMCR, ctl);
  441. return 0;
  442. }
  443. static int bcm54xx_read_link(struct mii_phy *phy)
  444. {
  445. int link_mode;
  446. u16 val;
  447. if (phy->autoneg) {
  448. val = sungem_phy_read(phy, MII_BCM5400_AUXSTATUS);
  449. link_mode = ((val & MII_BCM5400_AUXSTATUS_LINKMODE_MASK) >>
  450. MII_BCM5400_AUXSTATUS_LINKMODE_SHIFT);
  451. phy->duplex = phy_BCM5400_link_table[link_mode][0] ?
  452. DUPLEX_FULL : DUPLEX_HALF;
  453. phy->speed = phy_BCM5400_link_table[link_mode][2] ?
  454. SPEED_1000 :
  455. (phy_BCM5400_link_table[link_mode][1] ?
  456. SPEED_100 : SPEED_10);
  457. val = sungem_phy_read(phy, MII_LPA);
  458. phy->pause = (phy->duplex == DUPLEX_FULL) &&
  459. ((val & LPA_PAUSE) != 0);
  460. }
  461. /* On non-aneg, we assume what we put in BMCR is the speed,
  462. * though magic-aneg shouldn't prevent this case from occurring
  463. */
  464. return 0;
  465. }
  466. static int marvell88e1111_init(struct mii_phy* phy)
  467. {
  468. u16 rev;
  469. /* magic init sequence for rev 0 */
  470. rev = sungem_phy_read(phy, MII_PHYSID2) & 0x000f;
  471. if (rev == 0) {
  472. sungem_phy_write(phy, 0x1d, 0x000a);
  473. sungem_phy_write(phy, 0x1e, 0x0821);
  474. sungem_phy_write(phy, 0x1d, 0x0006);
  475. sungem_phy_write(phy, 0x1e, 0x8600);
  476. sungem_phy_write(phy, 0x1d, 0x000b);
  477. sungem_phy_write(phy, 0x1e, 0x0100);
  478. sungem_phy_write(phy, 0x1d, 0x0004);
  479. sungem_phy_write(phy, 0x1e, 0x4850);
  480. }
  481. return 0;
  482. }
  483. #define BCM5421_MODE_MASK (1 << 5)
  484. static int bcm5421_poll_link(struct mii_phy* phy)
  485. {
  486. u32 phy_reg;
  487. int mode;
  488. /* find out in what mode we are */
  489. sungem_phy_write(phy, MII_NCONFIG, 0x1000);
  490. phy_reg = sungem_phy_read(phy, MII_NCONFIG);
  491. mode = (phy_reg & BCM5421_MODE_MASK) >> 5;
  492. if ( mode == BCM54XX_COPPER)
  493. return genmii_poll_link(phy);
  494. /* try to find out whether we have a link */
  495. sungem_phy_write(phy, MII_NCONFIG, 0x2000);
  496. phy_reg = sungem_phy_read(phy, MII_NCONFIG);
  497. if (phy_reg & 0x0020)
  498. return 0;
  499. else
  500. return 1;
  501. }
  502. static int bcm5421_read_link(struct mii_phy* phy)
  503. {
  504. u32 phy_reg;
  505. int mode;
  506. /* find out in what mode we are */
  507. sungem_phy_write(phy, MII_NCONFIG, 0x1000);
  508. phy_reg = sungem_phy_read(phy, MII_NCONFIG);
  509. mode = (phy_reg & BCM5421_MODE_MASK ) >> 5;
  510. if ( mode == BCM54XX_COPPER)
  511. return bcm54xx_read_link(phy);
  512. phy->speed = SPEED_1000;
  513. /* find out whether we are running half- or full duplex */
  514. sungem_phy_write(phy, MII_NCONFIG, 0x2000);
  515. phy_reg = sungem_phy_read(phy, MII_NCONFIG);
  516. if ( (phy_reg & 0x0080) >> 7)
  517. phy->duplex |= DUPLEX_HALF;
  518. else
  519. phy->duplex |= DUPLEX_FULL;
  520. return 0;
  521. }
  522. static int bcm5421_enable_fiber(struct mii_phy* phy, int autoneg)
  523. {
  524. /* enable fiber mode */
  525. sungem_phy_write(phy, MII_NCONFIG, 0x9020);
  526. /* LEDs active in both modes, autosense prio = fiber */
  527. sungem_phy_write(phy, MII_NCONFIG, 0x945f);
  528. if (!autoneg) {
  529. /* switch off fibre autoneg */
  530. sungem_phy_write(phy, MII_NCONFIG, 0xfc01);
  531. sungem_phy_write(phy, 0x0b, 0x0004);
  532. }
  533. phy->autoneg = autoneg;
  534. return 0;
  535. }
  536. #define BCM5461_FIBER_LINK (1 << 2)
  537. #define BCM5461_MODE_MASK (3 << 1)
  538. static int bcm5461_poll_link(struct mii_phy* phy)
  539. {
  540. u32 phy_reg;
  541. int mode;
  542. /* find out in what mode we are */
  543. sungem_phy_write(phy, MII_NCONFIG, 0x7c00);
  544. phy_reg = sungem_phy_read(phy, MII_NCONFIG);
  545. mode = (phy_reg & BCM5461_MODE_MASK ) >> 1;
  546. if ( mode == BCM54XX_COPPER)
  547. return genmii_poll_link(phy);
  548. /* find out whether we have a link */
  549. sungem_phy_write(phy, MII_NCONFIG, 0x7000);
  550. phy_reg = sungem_phy_read(phy, MII_NCONFIG);
  551. if (phy_reg & BCM5461_FIBER_LINK)
  552. return 1;
  553. else
  554. return 0;
  555. }
  556. #define BCM5461_FIBER_DUPLEX (1 << 3)
  557. static int bcm5461_read_link(struct mii_phy* phy)
  558. {
  559. u32 phy_reg;
  560. int mode;
  561. /* find out in what mode we are */
  562. sungem_phy_write(phy, MII_NCONFIG, 0x7c00);
  563. phy_reg = sungem_phy_read(phy, MII_NCONFIG);
  564. mode = (phy_reg & BCM5461_MODE_MASK ) >> 1;
  565. if ( mode == BCM54XX_COPPER) {
  566. return bcm54xx_read_link(phy);
  567. }
  568. phy->speed = SPEED_1000;
  569. /* find out whether we are running half- or full duplex */
  570. sungem_phy_write(phy, MII_NCONFIG, 0x7000);
  571. phy_reg = sungem_phy_read(phy, MII_NCONFIG);
  572. if (phy_reg & BCM5461_FIBER_DUPLEX)
  573. phy->duplex |= DUPLEX_FULL;
  574. else
  575. phy->duplex |= DUPLEX_HALF;
  576. return 0;
  577. }
  578. static int bcm5461_enable_fiber(struct mii_phy* phy, int autoneg)
  579. {
  580. /* select fiber mode, enable 1000 base-X registers */
  581. sungem_phy_write(phy, MII_NCONFIG, 0xfc0b);
  582. if (autoneg) {
  583. /* enable fiber with no autonegotiation */
  584. sungem_phy_write(phy, MII_ADVERTISE, 0x01e0);
  585. sungem_phy_write(phy, MII_BMCR, 0x1140);
  586. } else {
  587. /* enable fiber with autonegotiation */
  588. sungem_phy_write(phy, MII_BMCR, 0x0140);
  589. }
  590. phy->autoneg = autoneg;
  591. return 0;
  592. }
  593. static int marvell_setup_aneg(struct mii_phy *phy, u32 advertise)
  594. {
  595. u16 ctl, adv;
  596. phy->autoneg = 1;
  597. phy->speed = SPEED_10;
  598. phy->duplex = DUPLEX_HALF;
  599. phy->pause = 0;
  600. phy->advertising = advertise;
  601. /* Setup standard advertise */
  602. adv = sungem_phy_read(phy, MII_ADVERTISE);
  603. adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
  604. if (advertise & ADVERTISED_10baseT_Half)
  605. adv |= ADVERTISE_10HALF;
  606. if (advertise & ADVERTISED_10baseT_Full)
  607. adv |= ADVERTISE_10FULL;
  608. if (advertise & ADVERTISED_100baseT_Half)
  609. adv |= ADVERTISE_100HALF;
  610. if (advertise & ADVERTISED_100baseT_Full)
  611. adv |= ADVERTISE_100FULL;
  612. if (advertise & ADVERTISED_Pause)
  613. adv |= ADVERTISE_PAUSE_CAP;
  614. if (advertise & ADVERTISED_Asym_Pause)
  615. adv |= ADVERTISE_PAUSE_ASYM;
  616. sungem_phy_write(phy, MII_ADVERTISE, adv);
  617. /* Setup 1000BT advertise & enable crossover detect
  618. * XXX How do we advertise 1000BT ? Darwin source is
  619. * confusing here, they read from specific control and
  620. * write to control... Someone has specs for those
  621. * beasts ?
  622. */
  623. adv = sungem_phy_read(phy, MII_M1011_PHY_SPEC_CONTROL);
  624. adv |= MII_M1011_PHY_SPEC_CONTROL_AUTO_MDIX;
  625. adv &= ~(MII_1000BASETCONTROL_FULLDUPLEXCAP |
  626. MII_1000BASETCONTROL_HALFDUPLEXCAP);
  627. if (advertise & SUPPORTED_1000baseT_Half)
  628. adv |= MII_1000BASETCONTROL_HALFDUPLEXCAP;
  629. if (advertise & SUPPORTED_1000baseT_Full)
  630. adv |= MII_1000BASETCONTROL_FULLDUPLEXCAP;
  631. sungem_phy_write(phy, MII_1000BASETCONTROL, adv);
  632. /* Start/Restart aneg */
  633. ctl = sungem_phy_read(phy, MII_BMCR);
  634. ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
  635. sungem_phy_write(phy, MII_BMCR, ctl);
  636. return 0;
  637. }
  638. static int marvell_setup_forced(struct mii_phy *phy, int speed, int fd)
  639. {
  640. u16 ctl, ctl2;
  641. phy->autoneg = 0;
  642. phy->speed = speed;
  643. phy->duplex = fd;
  644. phy->pause = 0;
  645. ctl = sungem_phy_read(phy, MII_BMCR);
  646. ctl &= ~(BMCR_FULLDPLX|BMCR_SPEED100|BMCR_SPD2|BMCR_ANENABLE);
  647. ctl |= BMCR_RESET;
  648. /* Select speed & duplex */
  649. switch(speed) {
  650. case SPEED_10:
  651. break;
  652. case SPEED_100:
  653. ctl |= BMCR_SPEED100;
  654. break;
  655. /* I'm not sure about the one below, again, Darwin source is
  656. * quite confusing and I lack chip specs
  657. */
  658. case SPEED_1000:
  659. ctl |= BMCR_SPD2;
  660. }
  661. if (fd == DUPLEX_FULL)
  662. ctl |= BMCR_FULLDPLX;
  663. /* Disable crossover. Again, the way Apple does it is strange,
  664. * though I don't assume they are wrong ;)
  665. */
  666. ctl2 = sungem_phy_read(phy, MII_M1011_PHY_SPEC_CONTROL);
  667. ctl2 &= ~(MII_M1011_PHY_SPEC_CONTROL_MANUAL_MDIX |
  668. MII_M1011_PHY_SPEC_CONTROL_AUTO_MDIX |
  669. MII_1000BASETCONTROL_FULLDUPLEXCAP |
  670. MII_1000BASETCONTROL_HALFDUPLEXCAP);
  671. if (speed == SPEED_1000)
  672. ctl2 |= (fd == DUPLEX_FULL) ?
  673. MII_1000BASETCONTROL_FULLDUPLEXCAP :
  674. MII_1000BASETCONTROL_HALFDUPLEXCAP;
  675. sungem_phy_write(phy, MII_1000BASETCONTROL, ctl2);
  676. // XXX Should we set the sungem to GII now on 1000BT ?
  677. sungem_phy_write(phy, MII_BMCR, ctl);
  678. return 0;
  679. }
  680. static int marvell_read_link(struct mii_phy *phy)
  681. {
  682. u16 status, pmask;
  683. if (phy->autoneg) {
  684. status = sungem_phy_read(phy, MII_M1011_PHY_SPEC_STATUS);
  685. if ((status & MII_M1011_PHY_SPEC_STATUS_RESOLVED) == 0)
  686. return -EAGAIN;
  687. if (status & MII_M1011_PHY_SPEC_STATUS_1000)
  688. phy->speed = SPEED_1000;
  689. else if (status & MII_M1011_PHY_SPEC_STATUS_100)
  690. phy->speed = SPEED_100;
  691. else
  692. phy->speed = SPEED_10;
  693. if (status & MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX)
  694. phy->duplex = DUPLEX_FULL;
  695. else
  696. phy->duplex = DUPLEX_HALF;
  697. pmask = MII_M1011_PHY_SPEC_STATUS_TX_PAUSE |
  698. MII_M1011_PHY_SPEC_STATUS_RX_PAUSE;
  699. phy->pause = (status & pmask) == pmask;
  700. }
  701. /* On non-aneg, we assume what we put in BMCR is the speed,
  702. * though magic-aneg shouldn't prevent this case from occurring
  703. */
  704. return 0;
  705. }
  706. #define MII_BASIC_FEATURES \
  707. (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \
  708. SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \
  709. SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII | \
  710. SUPPORTED_Pause)
  711. /* On gigabit capable PHYs, we advertise Pause support but not asym pause
  712. * support for now as I'm not sure it's supported and Darwin doesn't do
  713. * it neither. --BenH.
  714. */
  715. #define MII_GBIT_FEATURES \
  716. (MII_BASIC_FEATURES | \
  717. SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)
  718. /* Broadcom BCM 5201 */
  719. static const struct mii_phy_ops bcm5201_phy_ops = {
  720. .init = bcm5201_init,
  721. .suspend = bcm5201_suspend,
  722. .setup_aneg = genmii_setup_aneg,
  723. .setup_forced = genmii_setup_forced,
  724. .poll_link = genmii_poll_link,
  725. .read_link = genmii_read_link,
  726. };
  727. static struct mii_phy_def bcm5201_phy_def = {
  728. .phy_id = 0x00406210,
  729. .phy_id_mask = 0xfffffff0,
  730. .name = "BCM5201",
  731. .features = MII_BASIC_FEATURES,
  732. .magic_aneg = 1,
  733. .ops = &bcm5201_phy_ops
  734. };
  735. /* Broadcom BCM 5221 */
  736. static const struct mii_phy_ops bcm5221_phy_ops = {
  737. .suspend = bcm5221_suspend,
  738. .init = bcm5221_init,
  739. .setup_aneg = genmii_setup_aneg,
  740. .setup_forced = genmii_setup_forced,
  741. .poll_link = genmii_poll_link,
  742. .read_link = genmii_read_link,
  743. };
  744. static struct mii_phy_def bcm5221_phy_def = {
  745. .phy_id = 0x004061e0,
  746. .phy_id_mask = 0xfffffff0,
  747. .name = "BCM5221",
  748. .features = MII_BASIC_FEATURES,
  749. .magic_aneg = 1,
  750. .ops = &bcm5221_phy_ops
  751. };
  752. /* Broadcom BCM 5241 */
  753. static const struct mii_phy_ops bcm5241_phy_ops = {
  754. .suspend = bcm5241_suspend,
  755. .init = bcm5241_init,
  756. .setup_aneg = genmii_setup_aneg,
  757. .setup_forced = genmii_setup_forced,
  758. .poll_link = genmii_poll_link,
  759. .read_link = genmii_read_link,
  760. };
  761. static struct mii_phy_def bcm5241_phy_def = {
  762. .phy_id = 0x0143bc30,
  763. .phy_id_mask = 0xfffffff0,
  764. .name = "BCM5241",
  765. .features = MII_BASIC_FEATURES,
  766. .magic_aneg = 1,
  767. .ops = &bcm5241_phy_ops
  768. };
  769. /* Broadcom BCM 5400 */
  770. static const struct mii_phy_ops bcm5400_phy_ops = {
  771. .init = bcm5400_init,
  772. .suspend = bcm5400_suspend,
  773. .setup_aneg = bcm54xx_setup_aneg,
  774. .setup_forced = bcm54xx_setup_forced,
  775. .poll_link = genmii_poll_link,
  776. .read_link = bcm54xx_read_link,
  777. };
  778. static struct mii_phy_def bcm5400_phy_def = {
  779. .phy_id = 0x00206040,
  780. .phy_id_mask = 0xfffffff0,
  781. .name = "BCM5400",
  782. .features = MII_GBIT_FEATURES,
  783. .magic_aneg = 1,
  784. .ops = &bcm5400_phy_ops
  785. };
  786. /* Broadcom BCM 5401 */
  787. static const struct mii_phy_ops bcm5401_phy_ops = {
  788. .init = bcm5401_init,
  789. .suspend = bcm5401_suspend,
  790. .setup_aneg = bcm54xx_setup_aneg,
  791. .setup_forced = bcm54xx_setup_forced,
  792. .poll_link = genmii_poll_link,
  793. .read_link = bcm54xx_read_link,
  794. };
  795. static struct mii_phy_def bcm5401_phy_def = {
  796. .phy_id = 0x00206050,
  797. .phy_id_mask = 0xfffffff0,
  798. .name = "BCM5401",
  799. .features = MII_GBIT_FEATURES,
  800. .magic_aneg = 1,
  801. .ops = &bcm5401_phy_ops
  802. };
  803. /* Broadcom BCM 5411 */
  804. static const struct mii_phy_ops bcm5411_phy_ops = {
  805. .init = bcm5411_init,
  806. .suspend = generic_suspend,
  807. .setup_aneg = bcm54xx_setup_aneg,
  808. .setup_forced = bcm54xx_setup_forced,
  809. .poll_link = genmii_poll_link,
  810. .read_link = bcm54xx_read_link,
  811. };
  812. static struct mii_phy_def bcm5411_phy_def = {
  813. .phy_id = 0x00206070,
  814. .phy_id_mask = 0xfffffff0,
  815. .name = "BCM5411",
  816. .features = MII_GBIT_FEATURES,
  817. .magic_aneg = 1,
  818. .ops = &bcm5411_phy_ops
  819. };
  820. /* Broadcom BCM 5421 */
  821. static const struct mii_phy_ops bcm5421_phy_ops = {
  822. .init = bcm5421_init,
  823. .suspend = generic_suspend,
  824. .setup_aneg = bcm54xx_setup_aneg,
  825. .setup_forced = bcm54xx_setup_forced,
  826. .poll_link = bcm5421_poll_link,
  827. .read_link = bcm5421_read_link,
  828. .enable_fiber = bcm5421_enable_fiber,
  829. };
  830. static struct mii_phy_def bcm5421_phy_def = {
  831. .phy_id = 0x002060e0,
  832. .phy_id_mask = 0xfffffff0,
  833. .name = "BCM5421",
  834. .features = MII_GBIT_FEATURES,
  835. .magic_aneg = 1,
  836. .ops = &bcm5421_phy_ops
  837. };
  838. /* Broadcom BCM 5421 built-in K2 */
  839. static const struct mii_phy_ops bcm5421k2_phy_ops = {
  840. .init = bcm5421_init,
  841. .suspend = generic_suspend,
  842. .setup_aneg = bcm54xx_setup_aneg,
  843. .setup_forced = bcm54xx_setup_forced,
  844. .poll_link = genmii_poll_link,
  845. .read_link = bcm54xx_read_link,
  846. };
  847. static struct mii_phy_def bcm5421k2_phy_def = {
  848. .phy_id = 0x002062e0,
  849. .phy_id_mask = 0xfffffff0,
  850. .name = "BCM5421-K2",
  851. .features = MII_GBIT_FEATURES,
  852. .magic_aneg = 1,
  853. .ops = &bcm5421k2_phy_ops
  854. };
  855. static const struct mii_phy_ops bcm5461_phy_ops = {
  856. .init = bcm5421_init,
  857. .suspend = generic_suspend,
  858. .setup_aneg = bcm54xx_setup_aneg,
  859. .setup_forced = bcm54xx_setup_forced,
  860. .poll_link = bcm5461_poll_link,
  861. .read_link = bcm5461_read_link,
  862. .enable_fiber = bcm5461_enable_fiber,
  863. };
  864. static struct mii_phy_def bcm5461_phy_def = {
  865. .phy_id = 0x002060c0,
  866. .phy_id_mask = 0xfffffff0,
  867. .name = "BCM5461",
  868. .features = MII_GBIT_FEATURES,
  869. .magic_aneg = 1,
  870. .ops = &bcm5461_phy_ops
  871. };
  872. /* Broadcom BCM 5462 built-in Vesta */
  873. static const struct mii_phy_ops bcm5462V_phy_ops = {
  874. .init = bcm5421_init,
  875. .suspend = generic_suspend,
  876. .setup_aneg = bcm54xx_setup_aneg,
  877. .setup_forced = bcm54xx_setup_forced,
  878. .poll_link = genmii_poll_link,
  879. .read_link = bcm54xx_read_link,
  880. };
  881. static struct mii_phy_def bcm5462V_phy_def = {
  882. .phy_id = 0x002060d0,
  883. .phy_id_mask = 0xfffffff0,
  884. .name = "BCM5462-Vesta",
  885. .features = MII_GBIT_FEATURES,
  886. .magic_aneg = 1,
  887. .ops = &bcm5462V_phy_ops
  888. };
  889. /* Marvell 88E1101 amd 88E1111 */
  890. static const struct mii_phy_ops marvell88e1101_phy_ops = {
  891. .suspend = generic_suspend,
  892. .setup_aneg = marvell_setup_aneg,
  893. .setup_forced = marvell_setup_forced,
  894. .poll_link = genmii_poll_link,
  895. .read_link = marvell_read_link
  896. };
  897. static const struct mii_phy_ops marvell88e1111_phy_ops = {
  898. .init = marvell88e1111_init,
  899. .suspend = generic_suspend,
  900. .setup_aneg = marvell_setup_aneg,
  901. .setup_forced = marvell_setup_forced,
  902. .poll_link = genmii_poll_link,
  903. .read_link = marvell_read_link
  904. };
  905. /* two revs in darwin for the 88e1101 ... I could use a datasheet
  906. * to get the proper names...
  907. */
  908. static struct mii_phy_def marvell88e1101v1_phy_def = {
  909. .phy_id = 0x01410c20,
  910. .phy_id_mask = 0xfffffff0,
  911. .name = "Marvell 88E1101v1",
  912. .features = MII_GBIT_FEATURES,
  913. .magic_aneg = 1,
  914. .ops = &marvell88e1101_phy_ops
  915. };
  916. static struct mii_phy_def marvell88e1101v2_phy_def = {
  917. .phy_id = 0x01410c60,
  918. .phy_id_mask = 0xfffffff0,
  919. .name = "Marvell 88E1101v2",
  920. .features = MII_GBIT_FEATURES,
  921. .magic_aneg = 1,
  922. .ops = &marvell88e1101_phy_ops
  923. };
  924. static struct mii_phy_def marvell88e1111_phy_def = {
  925. .phy_id = 0x01410cc0,
  926. .phy_id_mask = 0xfffffff0,
  927. .name = "Marvell 88E1111",
  928. .features = MII_GBIT_FEATURES,
  929. .magic_aneg = 1,
  930. .ops = &marvell88e1111_phy_ops
  931. };
  932. /* Generic implementation for most 10/100 PHYs */
  933. static const struct mii_phy_ops generic_phy_ops = {
  934. .setup_aneg = genmii_setup_aneg,
  935. .setup_forced = genmii_setup_forced,
  936. .poll_link = genmii_poll_link,
  937. .read_link = genmii_read_link
  938. };
  939. static struct mii_phy_def genmii_phy_def = {
  940. .phy_id = 0x00000000,
  941. .phy_id_mask = 0x00000000,
  942. .name = "Generic MII",
  943. .features = MII_BASIC_FEATURES,
  944. .magic_aneg = 0,
  945. .ops = &generic_phy_ops
  946. };
  947. static struct mii_phy_def* mii_phy_table[] = {
  948. &bcm5201_phy_def,
  949. &bcm5221_phy_def,
  950. &bcm5241_phy_def,
  951. &bcm5400_phy_def,
  952. &bcm5401_phy_def,
  953. &bcm5411_phy_def,
  954. &bcm5421_phy_def,
  955. &bcm5421k2_phy_def,
  956. &bcm5461_phy_def,
  957. &bcm5462V_phy_def,
  958. &marvell88e1101v1_phy_def,
  959. &marvell88e1101v2_phy_def,
  960. &marvell88e1111_phy_def,
  961. &genmii_phy_def,
  962. NULL
  963. };
  964. int sungem_phy_probe(struct mii_phy *phy, int mii_id)
  965. {
  966. int rc;
  967. u32 id;
  968. struct mii_phy_def* def;
  969. int i;
  970. /* We do not reset the mii_phy structure as the driver
  971. * may re-probe the PHY regulary
  972. */
  973. phy->mii_id = mii_id;
  974. /* Take PHY out of isloate mode and reset it. */
  975. rc = reset_one_mii_phy(phy, mii_id);
  976. if (rc)
  977. goto fail;
  978. /* Read ID and find matching entry */
  979. id = (sungem_phy_read(phy, MII_PHYSID1) << 16 | sungem_phy_read(phy, MII_PHYSID2));
  980. printk(KERN_DEBUG KBUILD_MODNAME ": " "PHY ID: %x, addr: %x\n",
  981. id, mii_id);
  982. for (i=0; (def = mii_phy_table[i]) != NULL; i++)
  983. if ((id & def->phy_id_mask) == def->phy_id)
  984. break;
  985. /* Should never be NULL (we have a generic entry), but... */
  986. if (def == NULL)
  987. goto fail;
  988. phy->def = def;
  989. return 0;
  990. fail:
  991. phy->speed = 0;
  992. phy->duplex = 0;
  993. phy->pause = 0;
  994. phy->advertising = 0;
  995. return -ENODEV;
  996. }
  997. EXPORT_SYMBOL(sungem_phy_probe);
  998. MODULE_LICENSE("GPL");