dp83tc811.c 8.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Driver for the Texas Instruments DP83TC811 PHY
  4. *
  5. * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
  6. *
  7. */
  8. #include <linux/ethtool.h>
  9. #include <linux/etherdevice.h>
  10. #include <linux/kernel.h>
  11. #include <linux/mii.h>
  12. #include <linux/module.h>
  13. #include <linux/of.h>
  14. #include <linux/phy.h>
  15. #include <linux/netdevice.h>
  16. #define DP83TC811_PHY_ID 0x2000a253
  17. #define DP83811_DEVADDR 0x1f
  18. #define MII_DP83811_SGMII_CTRL 0x09
  19. #define MII_DP83811_INT_STAT1 0x12
  20. #define MII_DP83811_INT_STAT2 0x13
  21. #define MII_DP83811_INT_STAT3 0x18
  22. #define MII_DP83811_RESET_CTRL 0x1f
  23. #define DP83811_HW_RESET BIT(15)
  24. #define DP83811_SW_RESET BIT(14)
  25. /* INT_STAT1 bits */
  26. #define DP83811_RX_ERR_HF_INT_EN BIT(0)
  27. #define DP83811_MS_TRAINING_INT_EN BIT(1)
  28. #define DP83811_ANEG_COMPLETE_INT_EN BIT(2)
  29. #define DP83811_ESD_EVENT_INT_EN BIT(3)
  30. #define DP83811_WOL_INT_EN BIT(4)
  31. #define DP83811_LINK_STAT_INT_EN BIT(5)
  32. #define DP83811_ENERGY_DET_INT_EN BIT(6)
  33. #define DP83811_LINK_QUAL_INT_EN BIT(7)
  34. /* INT_STAT2 bits */
  35. #define DP83811_JABBER_DET_INT_EN BIT(0)
  36. #define DP83811_POLARITY_INT_EN BIT(1)
  37. #define DP83811_SLEEP_MODE_INT_EN BIT(2)
  38. #define DP83811_OVERTEMP_INT_EN BIT(3)
  39. #define DP83811_OVERVOLTAGE_INT_EN BIT(6)
  40. #define DP83811_UNDERVOLTAGE_INT_EN BIT(7)
  41. /* INT_STAT3 bits */
  42. #define DP83811_LPS_INT_EN BIT(0)
  43. #define DP83811_NO_FRAME_INT_EN BIT(3)
  44. #define DP83811_POR_DONE_INT_EN BIT(4)
  45. #define MII_DP83811_RXSOP1 0x04a5
  46. #define MII_DP83811_RXSOP2 0x04a6
  47. #define MII_DP83811_RXSOP3 0x04a7
  48. /* WoL Registers */
  49. #define MII_DP83811_WOL_CFG 0x04a0
  50. #define MII_DP83811_WOL_STAT 0x04a1
  51. #define MII_DP83811_WOL_DA1 0x04a2
  52. #define MII_DP83811_WOL_DA2 0x04a3
  53. #define MII_DP83811_WOL_DA3 0x04a4
  54. /* WoL bits */
  55. #define DP83811_WOL_MAGIC_EN BIT(0)
  56. #define DP83811_WOL_SECURE_ON BIT(5)
  57. #define DP83811_WOL_EN BIT(7)
  58. #define DP83811_WOL_INDICATION_SEL BIT(8)
  59. #define DP83811_WOL_CLR_INDICATION BIT(11)
  60. /* SGMII CTRL bits */
  61. #define DP83811_TDR_AUTO BIT(8)
  62. #define DP83811_SGMII_EN BIT(12)
  63. #define DP83811_SGMII_AUTO_NEG_EN BIT(13)
  64. #define DP83811_SGMII_TX_ERR_DIS BIT(14)
  65. #define DP83811_SGMII_SOFT_RESET BIT(15)
  66. static int dp83811_ack_interrupt(struct phy_device *phydev)
  67. {
  68. int err;
  69. err = phy_read(phydev, MII_DP83811_INT_STAT1);
  70. if (err < 0)
  71. return err;
  72. err = phy_read(phydev, MII_DP83811_INT_STAT2);
  73. if (err < 0)
  74. return err;
  75. err = phy_read(phydev, MII_DP83811_INT_STAT3);
  76. if (err < 0)
  77. return err;
  78. return 0;
  79. }
  80. static int dp83811_set_wol(struct phy_device *phydev,
  81. struct ethtool_wolinfo *wol)
  82. {
  83. struct net_device *ndev = phydev->attached_dev;
  84. const u8 *mac;
  85. u16 value;
  86. if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE)) {
  87. mac = (const u8 *)ndev->dev_addr;
  88. if (!is_valid_ether_addr(mac))
  89. return -EINVAL;
  90. /* MAC addresses start with byte 5, but stored in mac[0].
  91. * 811 PHYs store bytes 4|5, 2|3, 0|1
  92. */
  93. phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_DA1,
  94. (mac[1] << 8) | mac[0]);
  95. phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_DA2,
  96. (mac[3] << 8) | mac[2]);
  97. phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_DA3,
  98. (mac[5] << 8) | mac[4]);
  99. value = phy_read_mmd(phydev, DP83811_DEVADDR,
  100. MII_DP83811_WOL_CFG);
  101. if (wol->wolopts & WAKE_MAGIC)
  102. value |= DP83811_WOL_MAGIC_EN;
  103. else
  104. value &= ~DP83811_WOL_MAGIC_EN;
  105. if (wol->wolopts & WAKE_MAGICSECURE) {
  106. phy_write_mmd(phydev, DP83811_DEVADDR,
  107. MII_DP83811_RXSOP1,
  108. (wol->sopass[1] << 8) | wol->sopass[0]);
  109. phy_write_mmd(phydev, DP83811_DEVADDR,
  110. MII_DP83811_RXSOP2,
  111. (wol->sopass[3] << 8) | wol->sopass[2]);
  112. phy_write_mmd(phydev, DP83811_DEVADDR,
  113. MII_DP83811_RXSOP3,
  114. (wol->sopass[5] << 8) | wol->sopass[4]);
  115. value |= DP83811_WOL_SECURE_ON;
  116. } else {
  117. value &= ~DP83811_WOL_SECURE_ON;
  118. }
  119. value |= (DP83811_WOL_EN | DP83811_WOL_INDICATION_SEL |
  120. DP83811_WOL_CLR_INDICATION);
  121. phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG,
  122. value);
  123. } else {
  124. phy_clear_bits_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG,
  125. DP83811_WOL_EN);
  126. }
  127. return 0;
  128. }
  129. static void dp83811_get_wol(struct phy_device *phydev,
  130. struct ethtool_wolinfo *wol)
  131. {
  132. u16 sopass_val;
  133. int value;
  134. wol->supported = (WAKE_MAGIC | WAKE_MAGICSECURE);
  135. wol->wolopts = 0;
  136. value = phy_read_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG);
  137. if (value & DP83811_WOL_MAGIC_EN)
  138. wol->wolopts |= WAKE_MAGIC;
  139. if (value & DP83811_WOL_SECURE_ON) {
  140. sopass_val = phy_read_mmd(phydev, DP83811_DEVADDR,
  141. MII_DP83811_RXSOP1);
  142. wol->sopass[0] = (sopass_val & 0xff);
  143. wol->sopass[1] = (sopass_val >> 8);
  144. sopass_val = phy_read_mmd(phydev, DP83811_DEVADDR,
  145. MII_DP83811_RXSOP2);
  146. wol->sopass[2] = (sopass_val & 0xff);
  147. wol->sopass[3] = (sopass_val >> 8);
  148. sopass_val = phy_read_mmd(phydev, DP83811_DEVADDR,
  149. MII_DP83811_RXSOP3);
  150. wol->sopass[4] = (sopass_val & 0xff);
  151. wol->sopass[5] = (sopass_val >> 8);
  152. wol->wolopts |= WAKE_MAGICSECURE;
  153. }
  154. /* WoL is not enabled so set wolopts to 0 */
  155. if (!(value & DP83811_WOL_EN))
  156. wol->wolopts = 0;
  157. }
  158. static int dp83811_config_intr(struct phy_device *phydev)
  159. {
  160. int misr_status, err;
  161. if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
  162. misr_status = phy_read(phydev, MII_DP83811_INT_STAT1);
  163. if (misr_status < 0)
  164. return misr_status;
  165. misr_status |= (DP83811_RX_ERR_HF_INT_EN |
  166. DP83811_MS_TRAINING_INT_EN |
  167. DP83811_ANEG_COMPLETE_INT_EN |
  168. DP83811_ESD_EVENT_INT_EN |
  169. DP83811_WOL_INT_EN |
  170. DP83811_LINK_STAT_INT_EN |
  171. DP83811_ENERGY_DET_INT_EN |
  172. DP83811_LINK_QUAL_INT_EN);
  173. err = phy_write(phydev, MII_DP83811_INT_STAT1, misr_status);
  174. if (err < 0)
  175. return err;
  176. misr_status = phy_read(phydev, MII_DP83811_INT_STAT2);
  177. if (misr_status < 0)
  178. return misr_status;
  179. misr_status |= (DP83811_JABBER_DET_INT_EN |
  180. DP83811_POLARITY_INT_EN |
  181. DP83811_SLEEP_MODE_INT_EN |
  182. DP83811_OVERTEMP_INT_EN |
  183. DP83811_OVERVOLTAGE_INT_EN |
  184. DP83811_UNDERVOLTAGE_INT_EN);
  185. err = phy_write(phydev, MII_DP83811_INT_STAT2, misr_status);
  186. if (err < 0)
  187. return err;
  188. misr_status = phy_read(phydev, MII_DP83811_INT_STAT3);
  189. if (misr_status < 0)
  190. return misr_status;
  191. misr_status |= (DP83811_LPS_INT_EN |
  192. DP83811_NO_FRAME_INT_EN |
  193. DP83811_POR_DONE_INT_EN);
  194. err = phy_write(phydev, MII_DP83811_INT_STAT3, misr_status);
  195. } else {
  196. err = phy_write(phydev, MII_DP83811_INT_STAT1, 0);
  197. if (err < 0)
  198. return err;
  199. err = phy_write(phydev, MII_DP83811_INT_STAT2, 0);
  200. if (err < 0)
  201. return err;
  202. err = phy_write(phydev, MII_DP83811_INT_STAT3, 0);
  203. }
  204. return err;
  205. }
  206. static int dp83811_config_aneg(struct phy_device *phydev)
  207. {
  208. int value, err;
  209. if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
  210. value = phy_read(phydev, MII_DP83811_SGMII_CTRL);
  211. if (phydev->autoneg == AUTONEG_ENABLE) {
  212. err = phy_write(phydev, MII_DP83811_SGMII_CTRL,
  213. (DP83811_SGMII_AUTO_NEG_EN | value));
  214. if (err < 0)
  215. return err;
  216. } else {
  217. err = phy_write(phydev, MII_DP83811_SGMII_CTRL,
  218. (~DP83811_SGMII_AUTO_NEG_EN & value));
  219. if (err < 0)
  220. return err;
  221. }
  222. }
  223. return genphy_config_aneg(phydev);
  224. }
  225. static int dp83811_config_init(struct phy_device *phydev)
  226. {
  227. int value, err;
  228. value = phy_read(phydev, MII_DP83811_SGMII_CTRL);
  229. if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
  230. err = phy_write(phydev, MII_DP83811_SGMII_CTRL,
  231. (DP83811_SGMII_EN | value));
  232. } else {
  233. err = phy_write(phydev, MII_DP83811_SGMII_CTRL,
  234. (~DP83811_SGMII_EN & value));
  235. }
  236. if (err < 0)
  237. return err;
  238. value = DP83811_WOL_MAGIC_EN | DP83811_WOL_SECURE_ON | DP83811_WOL_EN;
  239. return phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG,
  240. value);
  241. }
  242. static int dp83811_phy_reset(struct phy_device *phydev)
  243. {
  244. int err;
  245. err = phy_write(phydev, MII_DP83811_RESET_CTRL, DP83811_HW_RESET);
  246. if (err < 0)
  247. return err;
  248. return 0;
  249. }
  250. static int dp83811_suspend(struct phy_device *phydev)
  251. {
  252. int value;
  253. value = phy_read_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG);
  254. if (!(value & DP83811_WOL_EN))
  255. genphy_suspend(phydev);
  256. return 0;
  257. }
  258. static int dp83811_resume(struct phy_device *phydev)
  259. {
  260. genphy_resume(phydev);
  261. phy_set_bits_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG,
  262. DP83811_WOL_CLR_INDICATION);
  263. return 0;
  264. }
  265. static struct phy_driver dp83811_driver[] = {
  266. {
  267. .phy_id = DP83TC811_PHY_ID,
  268. .phy_id_mask = 0xfffffff0,
  269. .name = "TI DP83TC811",
  270. /* PHY_BASIC_FEATURES */
  271. .config_init = dp83811_config_init,
  272. .config_aneg = dp83811_config_aneg,
  273. .soft_reset = dp83811_phy_reset,
  274. .get_wol = dp83811_get_wol,
  275. .set_wol = dp83811_set_wol,
  276. .ack_interrupt = dp83811_ack_interrupt,
  277. .config_intr = dp83811_config_intr,
  278. .suspend = dp83811_suspend,
  279. .resume = dp83811_resume,
  280. },
  281. };
  282. module_phy_driver(dp83811_driver);
  283. static struct mdio_device_id __maybe_unused dp83811_tbl[] = {
  284. { DP83TC811_PHY_ID, 0xfffffff0 },
  285. { },
  286. };
  287. MODULE_DEVICE_TABLE(mdio, dp83811_tbl);
  288. MODULE_DESCRIPTION("Texas Instruments DP83TC811 PHY driver");
  289. MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
  290. MODULE_LICENSE("GPL");