emac.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
  3. */
  4. /* Qualcomm Technologies, Inc. EMAC Gigabit Ethernet Driver */
  5. #include <linux/if_ether.h>
  6. #include <linux/if_vlan.h>
  7. #include <linux/interrupt.h>
  8. #include <linux/io.h>
  9. #include <linux/module.h>
  10. #include <linux/of.h>
  11. #include <linux/of_net.h>
  12. #include <linux/of_device.h>
  13. #include <linux/phy.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/acpi.h>
  16. #include "emac.h"
  17. #include "emac-mac.h"
  18. #include "emac-phy.h"
  19. #include "emac-sgmii.h"
  20. #define EMAC_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
  21. NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP)
  22. #define EMAC_RRD_SIZE 4
  23. /* The RRD size if timestamping is enabled: */
  24. #define EMAC_TS_RRD_SIZE 6
  25. #define EMAC_TPD_SIZE 4
  26. #define EMAC_RFD_SIZE 2
  27. #define REG_MAC_RX_STATUS_BIN EMAC_RXMAC_STATC_REG0
  28. #define REG_MAC_RX_STATUS_END EMAC_RXMAC_STATC_REG22
  29. #define REG_MAC_TX_STATUS_BIN EMAC_TXMAC_STATC_REG0
  30. #define REG_MAC_TX_STATUS_END EMAC_TXMAC_STATC_REG24
  31. #define RXQ0_NUM_RFD_PREF_DEF 8
  32. #define TXQ0_NUM_TPD_PREF_DEF 5
  33. #define EMAC_PREAMBLE_DEF 7
  34. #define DMAR_DLY_CNT_DEF 15
  35. #define DMAW_DLY_CNT_DEF 4
  36. #define IMR_NORMAL_MASK (ISR_ERROR | ISR_OVER | ISR_TX_PKT)
  37. #define ISR_TX_PKT (\
  38. TX_PKT_INT |\
  39. TX_PKT_INT1 |\
  40. TX_PKT_INT2 |\
  41. TX_PKT_INT3)
  42. #define ISR_OVER (\
  43. RFD0_UR_INT |\
  44. RFD1_UR_INT |\
  45. RFD2_UR_INT |\
  46. RFD3_UR_INT |\
  47. RFD4_UR_INT |\
  48. RXF_OF_INT |\
  49. TXF_UR_INT)
  50. #define ISR_ERROR (\
  51. DMAR_TO_INT |\
  52. DMAW_TO_INT |\
  53. TXQ_TO_INT)
  54. /* in sync with enum emac_clk_id */
  55. static const char * const emac_clk_name[] = {
  56. "axi_clk", "cfg_ahb_clk", "high_speed_clk", "mdio_clk", "tx_clk",
  57. "rx_clk", "sys_clk"
  58. };
  59. void emac_reg_update32(void __iomem *addr, u32 mask, u32 val)
  60. {
  61. u32 data = readl(addr);
  62. writel(((data & ~mask) | val), addr);
  63. }
  64. /* reinitialize */
  65. int emac_reinit_locked(struct emac_adapter *adpt)
  66. {
  67. int ret;
  68. mutex_lock(&adpt->reset_lock);
  69. emac_mac_down(adpt);
  70. emac_sgmii_reset(adpt);
  71. ret = emac_mac_up(adpt);
  72. mutex_unlock(&adpt->reset_lock);
  73. return ret;
  74. }
  75. /* NAPI */
  76. static int emac_napi_rtx(struct napi_struct *napi, int budget)
  77. {
  78. struct emac_rx_queue *rx_q =
  79. container_of(napi, struct emac_rx_queue, napi);
  80. struct emac_adapter *adpt = netdev_priv(rx_q->netdev);
  81. struct emac_irq *irq = rx_q->irq;
  82. int work_done = 0;
  83. emac_mac_rx_process(adpt, rx_q, &work_done, budget);
  84. if (work_done < budget) {
  85. napi_complete_done(napi, work_done);
  86. irq->mask |= rx_q->intr;
  87. writel(irq->mask, adpt->base + EMAC_INT_MASK);
  88. }
  89. return work_done;
  90. }
  91. /* Transmit the packet */
  92. static int emac_start_xmit(struct sk_buff *skb, struct net_device *netdev)
  93. {
  94. struct emac_adapter *adpt = netdev_priv(netdev);
  95. return emac_mac_tx_buf_send(adpt, &adpt->tx_q, skb);
  96. }
  97. static irqreturn_t emac_isr(int _irq, void *data)
  98. {
  99. struct emac_irq *irq = data;
  100. struct emac_adapter *adpt =
  101. container_of(irq, struct emac_adapter, irq);
  102. struct emac_rx_queue *rx_q = &adpt->rx_q;
  103. u32 isr, status;
  104. /* disable the interrupt */
  105. writel(0, adpt->base + EMAC_INT_MASK);
  106. isr = readl_relaxed(adpt->base + EMAC_INT_STATUS);
  107. status = isr & irq->mask;
  108. if (status == 0)
  109. goto exit;
  110. if (status & ISR_ERROR) {
  111. net_err_ratelimited("%s: error interrupt 0x%lx\n",
  112. adpt->netdev->name, status & ISR_ERROR);
  113. /* reset MAC */
  114. schedule_work(&adpt->work_thread);
  115. }
  116. /* Schedule the napi for receive queue with interrupt
  117. * status bit set
  118. */
  119. if (status & rx_q->intr) {
  120. if (napi_schedule_prep(&rx_q->napi)) {
  121. irq->mask &= ~rx_q->intr;
  122. __napi_schedule(&rx_q->napi);
  123. }
  124. }
  125. if (status & TX_PKT_INT)
  126. emac_mac_tx_process(adpt, &adpt->tx_q);
  127. if (status & ISR_OVER)
  128. net_warn_ratelimited("%s: TX/RX overflow interrupt\n",
  129. adpt->netdev->name);
  130. exit:
  131. /* enable the interrupt */
  132. writel(irq->mask, adpt->base + EMAC_INT_MASK);
  133. return IRQ_HANDLED;
  134. }
  135. /* Configure VLAN tag strip/insert feature */
  136. static int emac_set_features(struct net_device *netdev,
  137. netdev_features_t features)
  138. {
  139. netdev_features_t changed = features ^ netdev->features;
  140. struct emac_adapter *adpt = netdev_priv(netdev);
  141. /* We only need to reprogram the hardware if the VLAN tag features
  142. * have changed, and if it's already running.
  143. */
  144. if (!(changed & (NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX)))
  145. return 0;
  146. if (!netif_running(netdev))
  147. return 0;
  148. /* emac_mac_mode_config() uses netdev->features to configure the EMAC,
  149. * so make sure it's set first.
  150. */
  151. netdev->features = features;
  152. return emac_reinit_locked(adpt);
  153. }
  154. /* Configure Multicast and Promiscuous modes */
  155. static void emac_rx_mode_set(struct net_device *netdev)
  156. {
  157. struct emac_adapter *adpt = netdev_priv(netdev);
  158. struct netdev_hw_addr *ha;
  159. emac_mac_mode_config(adpt);
  160. /* update multicast address filtering */
  161. emac_mac_multicast_addr_clear(adpt);
  162. netdev_for_each_mc_addr(ha, netdev)
  163. emac_mac_multicast_addr_set(adpt, ha->addr);
  164. }
  165. /* Change the Maximum Transfer Unit (MTU) */
  166. static int emac_change_mtu(struct net_device *netdev, int new_mtu)
  167. {
  168. struct emac_adapter *adpt = netdev_priv(netdev);
  169. netif_info(adpt, hw, adpt->netdev,
  170. "changing MTU from %d to %d\n", netdev->mtu,
  171. new_mtu);
  172. netdev->mtu = new_mtu;
  173. if (netif_running(netdev))
  174. return emac_reinit_locked(adpt);
  175. return 0;
  176. }
  177. /* Called when the network interface is made active */
  178. static int emac_open(struct net_device *netdev)
  179. {
  180. struct emac_adapter *adpt = netdev_priv(netdev);
  181. struct emac_irq *irq = &adpt->irq;
  182. int ret;
  183. ret = request_irq(irq->irq, emac_isr, 0, "emac-core0", irq);
  184. if (ret) {
  185. netdev_err(adpt->netdev, "could not request emac-core0 irq\n");
  186. return ret;
  187. }
  188. /* allocate rx/tx dma buffer & descriptors */
  189. ret = emac_mac_rx_tx_rings_alloc_all(adpt);
  190. if (ret) {
  191. netdev_err(adpt->netdev, "error allocating rx/tx rings\n");
  192. free_irq(irq->irq, irq);
  193. return ret;
  194. }
  195. ret = emac_sgmii_open(adpt);
  196. if (ret) {
  197. emac_mac_rx_tx_rings_free_all(adpt);
  198. free_irq(irq->irq, irq);
  199. return ret;
  200. }
  201. ret = emac_mac_up(adpt);
  202. if (ret) {
  203. emac_mac_rx_tx_rings_free_all(adpt);
  204. free_irq(irq->irq, irq);
  205. emac_sgmii_close(adpt);
  206. return ret;
  207. }
  208. return 0;
  209. }
  210. /* Called when the network interface is disabled */
  211. static int emac_close(struct net_device *netdev)
  212. {
  213. struct emac_adapter *adpt = netdev_priv(netdev);
  214. mutex_lock(&adpt->reset_lock);
  215. emac_sgmii_close(adpt);
  216. emac_mac_down(adpt);
  217. emac_mac_rx_tx_rings_free_all(adpt);
  218. free_irq(adpt->irq.irq, &adpt->irq);
  219. mutex_unlock(&adpt->reset_lock);
  220. return 0;
  221. }
  222. /* Respond to a TX hang */
  223. static void emac_tx_timeout(struct net_device *netdev)
  224. {
  225. struct emac_adapter *adpt = netdev_priv(netdev);
  226. schedule_work(&adpt->work_thread);
  227. }
  228. /* IOCTL support for the interface */
  229. static int emac_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
  230. {
  231. if (!netif_running(netdev))
  232. return -EINVAL;
  233. if (!netdev->phydev)
  234. return -ENODEV;
  235. return phy_mii_ioctl(netdev->phydev, ifr, cmd);
  236. }
  237. /**
  238. * emac_update_hw_stats - read the EMAC stat registers
  239. *
  240. * Reads the stats registers and write the values to adpt->stats.
  241. *
  242. * adpt->stats.lock must be held while calling this function,
  243. * and while reading from adpt->stats.
  244. */
  245. void emac_update_hw_stats(struct emac_adapter *adpt)
  246. {
  247. struct emac_stats *stats = &adpt->stats;
  248. u64 *stats_itr = &adpt->stats.rx_ok;
  249. void __iomem *base = adpt->base;
  250. unsigned int addr;
  251. addr = REG_MAC_RX_STATUS_BIN;
  252. while (addr <= REG_MAC_RX_STATUS_END) {
  253. *stats_itr += readl_relaxed(base + addr);
  254. stats_itr++;
  255. addr += sizeof(u32);
  256. }
  257. /* additional rx status */
  258. stats->rx_crc_align += readl_relaxed(base + EMAC_RXMAC_STATC_REG23);
  259. stats->rx_jabbers += readl_relaxed(base + EMAC_RXMAC_STATC_REG24);
  260. /* update tx status */
  261. addr = REG_MAC_TX_STATUS_BIN;
  262. stats_itr = &stats->tx_ok;
  263. while (addr <= REG_MAC_TX_STATUS_END) {
  264. *stats_itr += readl_relaxed(base + addr);
  265. stats_itr++;
  266. addr += sizeof(u32);
  267. }
  268. /* additional tx status */
  269. stats->tx_col += readl_relaxed(base + EMAC_TXMAC_STATC_REG25);
  270. }
  271. /* Provide network statistics info for the interface */
  272. static void emac_get_stats64(struct net_device *netdev,
  273. struct rtnl_link_stats64 *net_stats)
  274. {
  275. struct emac_adapter *adpt = netdev_priv(netdev);
  276. struct emac_stats *stats = &adpt->stats;
  277. spin_lock(&stats->lock);
  278. emac_update_hw_stats(adpt);
  279. /* return parsed statistics */
  280. net_stats->rx_packets = stats->rx_ok;
  281. net_stats->tx_packets = stats->tx_ok;
  282. net_stats->rx_bytes = stats->rx_byte_cnt;
  283. net_stats->tx_bytes = stats->tx_byte_cnt;
  284. net_stats->multicast = stats->rx_mcast;
  285. net_stats->collisions = stats->tx_1_col + stats->tx_2_col * 2 +
  286. stats->tx_late_col + stats->tx_abort_col;
  287. net_stats->rx_errors = stats->rx_frag + stats->rx_fcs_err +
  288. stats->rx_len_err + stats->rx_sz_ov +
  289. stats->rx_align_err;
  290. net_stats->rx_fifo_errors = stats->rx_rxf_ov;
  291. net_stats->rx_length_errors = stats->rx_len_err;
  292. net_stats->rx_crc_errors = stats->rx_fcs_err;
  293. net_stats->rx_frame_errors = stats->rx_align_err;
  294. net_stats->rx_over_errors = stats->rx_rxf_ov;
  295. net_stats->rx_missed_errors = stats->rx_rxf_ov;
  296. net_stats->tx_errors = stats->tx_late_col + stats->tx_abort_col +
  297. stats->tx_underrun + stats->tx_trunc;
  298. net_stats->tx_fifo_errors = stats->tx_underrun;
  299. net_stats->tx_aborted_errors = stats->tx_abort_col;
  300. net_stats->tx_window_errors = stats->tx_late_col;
  301. spin_unlock(&stats->lock);
  302. }
  303. static const struct net_device_ops emac_netdev_ops = {
  304. .ndo_open = emac_open,
  305. .ndo_stop = emac_close,
  306. .ndo_validate_addr = eth_validate_addr,
  307. .ndo_start_xmit = emac_start_xmit,
  308. .ndo_set_mac_address = eth_mac_addr,
  309. .ndo_change_mtu = emac_change_mtu,
  310. .ndo_do_ioctl = emac_ioctl,
  311. .ndo_tx_timeout = emac_tx_timeout,
  312. .ndo_get_stats64 = emac_get_stats64,
  313. .ndo_set_features = emac_set_features,
  314. .ndo_set_rx_mode = emac_rx_mode_set,
  315. };
  316. /* Watchdog task routine, called to reinitialize the EMAC */
  317. static void emac_work_thread(struct work_struct *work)
  318. {
  319. struct emac_adapter *adpt =
  320. container_of(work, struct emac_adapter, work_thread);
  321. emac_reinit_locked(adpt);
  322. }
  323. /* Initialize various data structures */
  324. static void emac_init_adapter(struct emac_adapter *adpt)
  325. {
  326. u32 reg;
  327. adpt->rrd_size = EMAC_RRD_SIZE;
  328. adpt->tpd_size = EMAC_TPD_SIZE;
  329. adpt->rfd_size = EMAC_RFD_SIZE;
  330. /* descriptors */
  331. adpt->tx_desc_cnt = EMAC_DEF_TX_DESCS;
  332. adpt->rx_desc_cnt = EMAC_DEF_RX_DESCS;
  333. /* dma */
  334. adpt->dma_order = emac_dma_ord_out;
  335. adpt->dmar_block = emac_dma_req_4096;
  336. adpt->dmaw_block = emac_dma_req_128;
  337. adpt->dmar_dly_cnt = DMAR_DLY_CNT_DEF;
  338. adpt->dmaw_dly_cnt = DMAW_DLY_CNT_DEF;
  339. adpt->tpd_burst = TXQ0_NUM_TPD_PREF_DEF;
  340. adpt->rfd_burst = RXQ0_NUM_RFD_PREF_DEF;
  341. /* irq moderator */
  342. reg = ((EMAC_DEF_RX_IRQ_MOD >> 1) << IRQ_MODERATOR2_INIT_SHFT) |
  343. ((EMAC_DEF_TX_IRQ_MOD >> 1) << IRQ_MODERATOR_INIT_SHFT);
  344. adpt->irq_mod = reg;
  345. /* others */
  346. adpt->preamble = EMAC_PREAMBLE_DEF;
  347. /* default to automatic flow control */
  348. adpt->automatic = true;
  349. /* Disable single-pause-frame mode by default */
  350. adpt->single_pause_mode = false;
  351. }
  352. /* Get the clock */
  353. static int emac_clks_get(struct platform_device *pdev,
  354. struct emac_adapter *adpt)
  355. {
  356. unsigned int i;
  357. for (i = 0; i < EMAC_CLK_CNT; i++) {
  358. struct clk *clk = devm_clk_get(&pdev->dev, emac_clk_name[i]);
  359. if (IS_ERR(clk)) {
  360. dev_err(&pdev->dev,
  361. "could not claim clock %s (error=%li)\n",
  362. emac_clk_name[i], PTR_ERR(clk));
  363. return PTR_ERR(clk);
  364. }
  365. adpt->clk[i] = clk;
  366. }
  367. return 0;
  368. }
  369. /* Initialize clocks */
  370. static int emac_clks_phase1_init(struct platform_device *pdev,
  371. struct emac_adapter *adpt)
  372. {
  373. int ret;
  374. /* On ACPI platforms, clocks are controlled by firmware and/or
  375. * ACPI, not by drivers.
  376. */
  377. if (has_acpi_companion(&pdev->dev))
  378. return 0;
  379. ret = emac_clks_get(pdev, adpt);
  380. if (ret)
  381. return ret;
  382. ret = clk_prepare_enable(adpt->clk[EMAC_CLK_AXI]);
  383. if (ret)
  384. return ret;
  385. ret = clk_prepare_enable(adpt->clk[EMAC_CLK_CFG_AHB]);
  386. if (ret)
  387. goto disable_clk_axi;
  388. ret = clk_set_rate(adpt->clk[EMAC_CLK_HIGH_SPEED], 19200000);
  389. if (ret)
  390. goto disable_clk_cfg_ahb;
  391. ret = clk_prepare_enable(adpt->clk[EMAC_CLK_HIGH_SPEED]);
  392. if (ret)
  393. goto disable_clk_cfg_ahb;
  394. return 0;
  395. disable_clk_cfg_ahb:
  396. clk_disable_unprepare(adpt->clk[EMAC_CLK_CFG_AHB]);
  397. disable_clk_axi:
  398. clk_disable_unprepare(adpt->clk[EMAC_CLK_AXI]);
  399. return ret;
  400. }
  401. /* Enable clocks; needs emac_clks_phase1_init to be called before */
  402. static int emac_clks_phase2_init(struct platform_device *pdev,
  403. struct emac_adapter *adpt)
  404. {
  405. int ret;
  406. if (has_acpi_companion(&pdev->dev))
  407. return 0;
  408. ret = clk_set_rate(adpt->clk[EMAC_CLK_TX], 125000000);
  409. if (ret)
  410. return ret;
  411. ret = clk_prepare_enable(adpt->clk[EMAC_CLK_TX]);
  412. if (ret)
  413. return ret;
  414. ret = clk_set_rate(adpt->clk[EMAC_CLK_HIGH_SPEED], 125000000);
  415. if (ret)
  416. return ret;
  417. ret = clk_set_rate(adpt->clk[EMAC_CLK_MDIO], 25000000);
  418. if (ret)
  419. return ret;
  420. ret = clk_prepare_enable(adpt->clk[EMAC_CLK_MDIO]);
  421. if (ret)
  422. return ret;
  423. ret = clk_prepare_enable(adpt->clk[EMAC_CLK_RX]);
  424. if (ret)
  425. return ret;
  426. return clk_prepare_enable(adpt->clk[EMAC_CLK_SYS]);
  427. }
  428. static void emac_clks_teardown(struct emac_adapter *adpt)
  429. {
  430. unsigned int i;
  431. for (i = 0; i < EMAC_CLK_CNT; i++)
  432. clk_disable_unprepare(adpt->clk[i]);
  433. }
  434. /* Get the resources */
  435. static int emac_probe_resources(struct platform_device *pdev,
  436. struct emac_adapter *adpt)
  437. {
  438. struct net_device *netdev = adpt->netdev;
  439. char maddr[ETH_ALEN];
  440. int ret = 0;
  441. /* get mac address */
  442. if (device_get_mac_address(&pdev->dev, maddr, ETH_ALEN))
  443. ether_addr_copy(netdev->dev_addr, maddr);
  444. else
  445. eth_hw_addr_random(netdev);
  446. /* Core 0 interrupt */
  447. ret = platform_get_irq(pdev, 0);
  448. if (ret < 0)
  449. return ret;
  450. adpt->irq.irq = ret;
  451. /* base register address */
  452. adpt->base = devm_platform_ioremap_resource(pdev, 0);
  453. if (IS_ERR(adpt->base))
  454. return PTR_ERR(adpt->base);
  455. /* CSR register address */
  456. adpt->csr = devm_platform_ioremap_resource(pdev, 1);
  457. if (IS_ERR(adpt->csr))
  458. return PTR_ERR(adpt->csr);
  459. netdev->base_addr = (unsigned long)adpt->base;
  460. return 0;
  461. }
  462. static const struct of_device_id emac_dt_match[] = {
  463. {
  464. .compatible = "qcom,fsm9900-emac",
  465. },
  466. {}
  467. };
  468. MODULE_DEVICE_TABLE(of, emac_dt_match);
  469. #if IS_ENABLED(CONFIG_ACPI)
  470. static const struct acpi_device_id emac_acpi_match[] = {
  471. {
  472. .id = "QCOM8070",
  473. },
  474. {}
  475. };
  476. MODULE_DEVICE_TABLE(acpi, emac_acpi_match);
  477. #endif
  478. static int emac_probe(struct platform_device *pdev)
  479. {
  480. struct net_device *netdev;
  481. struct emac_adapter *adpt;
  482. struct emac_sgmii *phy;
  483. u16 devid, revid;
  484. u32 reg;
  485. int ret;
  486. /* The TPD buffer address is limited to:
  487. * 1. PTP: 45bits. (Driver doesn't support yet.)
  488. * 2. NON-PTP: 46bits.
  489. */
  490. ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(46));
  491. if (ret) {
  492. dev_err(&pdev->dev, "could not set DMA mask\n");
  493. return ret;
  494. }
  495. netdev = alloc_etherdev(sizeof(struct emac_adapter));
  496. if (!netdev)
  497. return -ENOMEM;
  498. dev_set_drvdata(&pdev->dev, netdev);
  499. SET_NETDEV_DEV(netdev, &pdev->dev);
  500. emac_set_ethtool_ops(netdev);
  501. adpt = netdev_priv(netdev);
  502. adpt->netdev = netdev;
  503. adpt->msg_enable = EMAC_MSG_DEFAULT;
  504. phy = &adpt->phy;
  505. atomic_set(&phy->decode_error_count, 0);
  506. mutex_init(&adpt->reset_lock);
  507. spin_lock_init(&adpt->stats.lock);
  508. adpt->irq.mask = RX_PKT_INT0 | IMR_NORMAL_MASK;
  509. ret = emac_probe_resources(pdev, adpt);
  510. if (ret)
  511. goto err_undo_netdev;
  512. /* initialize clocks */
  513. ret = emac_clks_phase1_init(pdev, adpt);
  514. if (ret) {
  515. dev_err(&pdev->dev, "could not initialize clocks\n");
  516. goto err_undo_netdev;
  517. }
  518. netdev->watchdog_timeo = EMAC_WATCHDOG_TIME;
  519. netdev->irq = adpt->irq.irq;
  520. netdev->netdev_ops = &emac_netdev_ops;
  521. emac_init_adapter(adpt);
  522. /* init external phy */
  523. ret = emac_phy_config(pdev, adpt);
  524. if (ret)
  525. goto err_undo_clocks;
  526. /* init internal sgmii phy */
  527. ret = emac_sgmii_config(pdev, adpt);
  528. if (ret)
  529. goto err_undo_mdiobus;
  530. /* enable clocks */
  531. ret = emac_clks_phase2_init(pdev, adpt);
  532. if (ret) {
  533. dev_err(&pdev->dev, "could not initialize clocks\n");
  534. goto err_undo_mdiobus;
  535. }
  536. /* set hw features */
  537. netdev->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_RXCSUM |
  538. NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
  539. NETIF_F_HW_VLAN_CTAG_TX;
  540. netdev->hw_features = netdev->features;
  541. netdev->vlan_features |= NETIF_F_SG | NETIF_F_HW_CSUM |
  542. NETIF_F_TSO | NETIF_F_TSO6;
  543. /* MTU range: 46 - 9194 */
  544. netdev->min_mtu = EMAC_MIN_ETH_FRAME_SIZE -
  545. (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
  546. netdev->max_mtu = EMAC_MAX_ETH_FRAME_SIZE -
  547. (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
  548. INIT_WORK(&adpt->work_thread, emac_work_thread);
  549. /* Initialize queues */
  550. emac_mac_rx_tx_ring_init_all(pdev, adpt);
  551. netif_napi_add(netdev, &adpt->rx_q.napi, emac_napi_rtx,
  552. NAPI_POLL_WEIGHT);
  553. ret = register_netdev(netdev);
  554. if (ret) {
  555. dev_err(&pdev->dev, "could not register net device\n");
  556. goto err_undo_napi;
  557. }
  558. reg = readl_relaxed(adpt->base + EMAC_DMA_MAS_CTRL);
  559. devid = (reg & DEV_ID_NUM_BMSK) >> DEV_ID_NUM_SHFT;
  560. revid = (reg & DEV_REV_NUM_BMSK) >> DEV_REV_NUM_SHFT;
  561. reg = readl_relaxed(adpt->base + EMAC_CORE_HW_VERSION);
  562. netif_info(adpt, probe, netdev,
  563. "hardware id %d.%d, hardware version %d.%d.%d\n",
  564. devid, revid,
  565. (reg & MAJOR_BMSK) >> MAJOR_SHFT,
  566. (reg & MINOR_BMSK) >> MINOR_SHFT,
  567. (reg & STEP_BMSK) >> STEP_SHFT);
  568. return 0;
  569. err_undo_napi:
  570. netif_napi_del(&adpt->rx_q.napi);
  571. err_undo_mdiobus:
  572. put_device(&adpt->phydev->mdio.dev);
  573. mdiobus_unregister(adpt->mii_bus);
  574. err_undo_clocks:
  575. emac_clks_teardown(adpt);
  576. err_undo_netdev:
  577. free_netdev(netdev);
  578. return ret;
  579. }
  580. static int emac_remove(struct platform_device *pdev)
  581. {
  582. struct net_device *netdev = dev_get_drvdata(&pdev->dev);
  583. struct emac_adapter *adpt = netdev_priv(netdev);
  584. unregister_netdev(netdev);
  585. netif_napi_del(&adpt->rx_q.napi);
  586. emac_clks_teardown(adpt);
  587. put_device(&adpt->phydev->mdio.dev);
  588. mdiobus_unregister(adpt->mii_bus);
  589. if (adpt->phy.digital)
  590. iounmap(adpt->phy.digital);
  591. iounmap(adpt->phy.base);
  592. free_netdev(netdev);
  593. return 0;
  594. }
  595. static void emac_shutdown(struct platform_device *pdev)
  596. {
  597. struct net_device *netdev = dev_get_drvdata(&pdev->dev);
  598. struct emac_adapter *adpt = netdev_priv(netdev);
  599. if (netdev->flags & IFF_UP) {
  600. /* Closing the SGMII turns off its interrupts */
  601. emac_sgmii_close(adpt);
  602. /* Resetting the MAC turns off all DMA and its interrupts */
  603. emac_mac_reset(adpt);
  604. }
  605. }
  606. static struct platform_driver emac_platform_driver = {
  607. .probe = emac_probe,
  608. .remove = emac_remove,
  609. .driver = {
  610. .name = "qcom-emac",
  611. .of_match_table = emac_dt_match,
  612. .acpi_match_table = ACPI_PTR(emac_acpi_match),
  613. },
  614. .shutdown = emac_shutdown,
  615. };
  616. module_platform_driver(emac_platform_driver);
  617. MODULE_LICENSE("GPL v2");
  618. MODULE_ALIAS("platform:qcom-emac");