dnet.h 6.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Dave DNET Ethernet Controller driver
  4. *
  5. * Copyright (C) 2008 Dave S.r.l. <www.dave.eu>
  6. */
  7. #ifndef _DNET_H
  8. #define _DNET_H
  9. #define DRV_NAME "dnet"
  10. #define DRV_VERSION "0.9.1"
  11. #define PFX DRV_NAME ": "
  12. /* Register access macros */
  13. #define dnet_writel(port, value, reg) \
  14. writel((value), (port)->regs + DNET_##reg)
  15. #define dnet_readl(port, reg) readl((port)->regs + DNET_##reg)
  16. /* ALL DNET FIFO REGISTERS */
  17. #define DNET_RX_LEN_FIFO 0x000 /* RX_LEN_FIFO */
  18. #define DNET_RX_DATA_FIFO 0x004 /* RX_DATA_FIFO */
  19. #define DNET_TX_LEN_FIFO 0x008 /* TX_LEN_FIFO */
  20. #define DNET_TX_DATA_FIFO 0x00C /* TX_DATA_FIFO */
  21. /* ALL DNET CONTROL/STATUS REGISTERS OFFSETS */
  22. #define DNET_VERCAPS 0x100 /* VERCAPS */
  23. #define DNET_INTR_SRC 0x104 /* INTR_SRC */
  24. #define DNET_INTR_ENB 0x108 /* INTR_ENB */
  25. #define DNET_RX_STATUS 0x10C /* RX_STATUS */
  26. #define DNET_TX_STATUS 0x110 /* TX_STATUS */
  27. #define DNET_RX_FRAMES_CNT 0x114 /* RX_FRAMES_CNT */
  28. #define DNET_TX_FRAMES_CNT 0x118 /* TX_FRAMES_CNT */
  29. #define DNET_RX_FIFO_TH 0x11C /* RX_FIFO_TH */
  30. #define DNET_TX_FIFO_TH 0x120 /* TX_FIFO_TH */
  31. #define DNET_SYS_CTL 0x124 /* SYS_CTL */
  32. #define DNET_PAUSE_TMR 0x128 /* PAUSE_TMR */
  33. #define DNET_RX_FIFO_WCNT 0x12C /* RX_FIFO_WCNT */
  34. #define DNET_TX_FIFO_WCNT 0x130 /* TX_FIFO_WCNT */
  35. /* ALL DNET MAC REGISTERS */
  36. #define DNET_MACREG_DATA 0x200 /* Mac-Reg Data */
  37. #define DNET_MACREG_ADDR 0x204 /* Mac-Reg Addr */
  38. /* ALL DNET RX STATISTICS COUNTERS */
  39. #define DNET_RX_PKT_IGNR_CNT 0x300
  40. #define DNET_RX_LEN_CHK_ERR_CNT 0x304
  41. #define DNET_RX_LNG_FRM_CNT 0x308
  42. #define DNET_RX_SHRT_FRM_CNT 0x30C
  43. #define DNET_RX_IPG_VIOL_CNT 0x310
  44. #define DNET_RX_CRC_ERR_CNT 0x314
  45. #define DNET_RX_OK_PKT_CNT 0x318
  46. #define DNET_RX_CTL_FRM_CNT 0x31C
  47. #define DNET_RX_PAUSE_FRM_CNT 0x320
  48. #define DNET_RX_MULTICAST_CNT 0x324
  49. #define DNET_RX_BROADCAST_CNT 0x328
  50. #define DNET_RX_VLAN_TAG_CNT 0x32C
  51. #define DNET_RX_PRE_SHRINK_CNT 0x330
  52. #define DNET_RX_DRIB_NIB_CNT 0x334
  53. #define DNET_RX_UNSUP_OPCD_CNT 0x338
  54. #define DNET_RX_BYTE_CNT 0x33C
  55. /* DNET TX STATISTICS COUNTERS */
  56. #define DNET_TX_UNICAST_CNT 0x400
  57. #define DNET_TX_PAUSE_FRM_CNT 0x404
  58. #define DNET_TX_MULTICAST_CNT 0x408
  59. #define DNET_TX_BRDCAST_CNT 0x40C
  60. #define DNET_TX_VLAN_TAG_CNT 0x410
  61. #define DNET_TX_BAD_FCS_CNT 0x414
  62. #define DNET_TX_JUMBO_CNT 0x418
  63. #define DNET_TX_BYTE_CNT 0x41C
  64. /* SOME INTERNAL MAC-CORE REGISTER */
  65. #define DNET_INTERNAL_MODE_REG 0x0
  66. #define DNET_INTERNAL_RXTX_CONTROL_REG 0x2
  67. #define DNET_INTERNAL_MAX_PKT_SIZE_REG 0x4
  68. #define DNET_INTERNAL_IGP_REG 0x8
  69. #define DNET_INTERNAL_MAC_ADDR_0_REG 0xa
  70. #define DNET_INTERNAL_MAC_ADDR_1_REG 0xc
  71. #define DNET_INTERNAL_MAC_ADDR_2_REG 0xe
  72. #define DNET_INTERNAL_TX_RX_STS_REG 0x12
  73. #define DNET_INTERNAL_GMII_MNG_CTL_REG 0x14
  74. #define DNET_INTERNAL_GMII_MNG_DAT_REG 0x16
  75. #define DNET_INTERNAL_GMII_MNG_CMD_FIN (1 << 14)
  76. #define DNET_INTERNAL_WRITE (1 << 31)
  77. /* MAC-CORE REGISTER FIELDS */
  78. /* MAC-CORE MODE REGISTER FIELDS */
  79. #define DNET_INTERNAL_MODE_GBITEN (1 << 0)
  80. #define DNET_INTERNAL_MODE_FCEN (1 << 1)
  81. #define DNET_INTERNAL_MODE_RXEN (1 << 2)
  82. #define DNET_INTERNAL_MODE_TXEN (1 << 3)
  83. /* MAC-CORE RXTX CONTROL REGISTER FIELDS */
  84. #define DNET_INTERNAL_RXTX_CONTROL_RXSHORTFRAME (1 << 8)
  85. #define DNET_INTERNAL_RXTX_CONTROL_RXBROADCAST (1 << 7)
  86. #define DNET_INTERNAL_RXTX_CONTROL_RXMULTICAST (1 << 4)
  87. #define DNET_INTERNAL_RXTX_CONTROL_RXPAUSE (1 << 3)
  88. #define DNET_INTERNAL_RXTX_CONTROL_DISTXFCS (1 << 2)
  89. #define DNET_INTERNAL_RXTX_CONTROL_DISCFXFCS (1 << 1)
  90. #define DNET_INTERNAL_RXTX_CONTROL_ENPROMISC (1 << 0)
  91. #define DNET_INTERNAL_RXTX_CONTROL_DROPCONTROL (1 << 6)
  92. #define DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP (1 << 5)
  93. /* SYSTEM CONTROL REGISTER FIELDS */
  94. #define DNET_SYS_CTL_IGNORENEXTPKT (1 << 0)
  95. #define DNET_SYS_CTL_SENDPAUSE (1 << 2)
  96. #define DNET_SYS_CTL_RXFIFOFLUSH (1 << 3)
  97. #define DNET_SYS_CTL_TXFIFOFLUSH (1 << 4)
  98. /* TX STATUS REGISTER FIELDS */
  99. #define DNET_TX_STATUS_FIFO_ALMOST_EMPTY (1 << 2)
  100. #define DNET_TX_STATUS_FIFO_ALMOST_FULL (1 << 1)
  101. /* INTERRUPT SOURCE REGISTER FIELDS */
  102. #define DNET_INTR_SRC_TX_PKTSENT (1 << 0)
  103. #define DNET_INTR_SRC_TX_FIFOAF (1 << 1)
  104. #define DNET_INTR_SRC_TX_FIFOAE (1 << 2)
  105. #define DNET_INTR_SRC_TX_DISCFRM (1 << 3)
  106. #define DNET_INTR_SRC_TX_FIFOFULL (1 << 4)
  107. #define DNET_INTR_SRC_RX_CMDFIFOAF (1 << 8)
  108. #define DNET_INTR_SRC_RX_CMDFIFOFF (1 << 9)
  109. #define DNET_INTR_SRC_RX_DATAFIFOFF (1 << 10)
  110. #define DNET_INTR_SRC_TX_SUMMARY (1 << 16)
  111. #define DNET_INTR_SRC_RX_SUMMARY (1 << 17)
  112. #define DNET_INTR_SRC_PHY (1 << 19)
  113. /* INTERRUPT ENABLE REGISTER FIELDS */
  114. #define DNET_INTR_ENB_TX_PKTSENT (1 << 0)
  115. #define DNET_INTR_ENB_TX_FIFOAF (1 << 1)
  116. #define DNET_INTR_ENB_TX_FIFOAE (1 << 2)
  117. #define DNET_INTR_ENB_TX_DISCFRM (1 << 3)
  118. #define DNET_INTR_ENB_TX_FIFOFULL (1 << 4)
  119. #define DNET_INTR_ENB_RX_PKTRDY (1 << 8)
  120. #define DNET_INTR_ENB_RX_FIFOAF (1 << 9)
  121. #define DNET_INTR_ENB_RX_FIFOERR (1 << 10)
  122. #define DNET_INTR_ENB_RX_ERROR (1 << 11)
  123. #define DNET_INTR_ENB_RX_FIFOFULL (1 << 12)
  124. #define DNET_INTR_ENB_RX_FIFOAE (1 << 13)
  125. #define DNET_INTR_ENB_TX_SUMMARY (1 << 16)
  126. #define DNET_INTR_ENB_RX_SUMMARY (1 << 17)
  127. #define DNET_INTR_ENB_GLOBAL_ENABLE (1 << 18)
  128. /* default values:
  129. * almost empty = less than one full sized ethernet frame (no jumbo) inside
  130. * the fifo almost full = can write less than one full sized ethernet frame
  131. * (no jumbo) inside the fifo
  132. */
  133. #define DNET_CFG_TX_FIFO_FULL_THRES 25
  134. #define DNET_CFG_RX_FIFO_FULL_THRES 20
  135. /*
  136. * Capabilities. Used by the driver to know the capabilities that the ethernet
  137. * controller inside the FPGA have.
  138. */
  139. #define DNET_HAS_MDIO (1 << 0)
  140. #define DNET_HAS_IRQ (1 << 1)
  141. #define DNET_HAS_GIGABIT (1 << 2)
  142. #define DNET_HAS_DMA (1 << 3)
  143. #define DNET_HAS_MII (1 << 4) /* or GMII */
  144. #define DNET_HAS_RMII (1 << 5) /* or RGMII */
  145. #define DNET_CAPS_MASK 0xFFFF
  146. #define DNET_FIFO_SIZE 1024 /* 1K x 32 bit */
  147. #define DNET_FIFO_TX_DATA_AF_TH (DNET_FIFO_SIZE - 384) /* 384 = 1536 / 4 */
  148. #define DNET_FIFO_TX_DATA_AE_TH 384
  149. #define DNET_FIFO_RX_CMD_AF_TH (1 << 16) /* just one frame inside the FIFO */
  150. /*
  151. * Hardware-collected statistics.
  152. */
  153. struct dnet_stats {
  154. u32 rx_pkt_ignr;
  155. u32 rx_len_chk_err;
  156. u32 rx_lng_frm;
  157. u32 rx_shrt_frm;
  158. u32 rx_ipg_viol;
  159. u32 rx_crc_err;
  160. u32 rx_ok_pkt;
  161. u32 rx_ctl_frm;
  162. u32 rx_pause_frm;
  163. u32 rx_multicast;
  164. u32 rx_broadcast;
  165. u32 rx_vlan_tag;
  166. u32 rx_pre_shrink;
  167. u32 rx_drib_nib;
  168. u32 rx_unsup_opcd;
  169. u32 rx_byte;
  170. u32 tx_unicast;
  171. u32 tx_pause_frm;
  172. u32 tx_multicast;
  173. u32 tx_brdcast;
  174. u32 tx_vlan_tag;
  175. u32 tx_bad_fcs;
  176. u32 tx_jumbo;
  177. u32 tx_byte;
  178. };
  179. struct dnet {
  180. void __iomem *regs;
  181. spinlock_t lock;
  182. struct platform_device *pdev;
  183. struct net_device *dev;
  184. struct dnet_stats hw_stats;
  185. unsigned int capabilities; /* read from FPGA */
  186. struct napi_struct napi;
  187. /* PHY stuff */
  188. struct mii_bus *mii_bus;
  189. unsigned int link;
  190. unsigned int speed;
  191. unsigned int duplex;
  192. };
  193. #endif /* _DNET_H */