lan9303-core.c 39 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2017 Pengutronix, Juergen Borleis <kernel@pengutronix.de>
  4. */
  5. #include <linux/kernel.h>
  6. #include <linux/module.h>
  7. #include <linux/gpio/consumer.h>
  8. #include <linux/regmap.h>
  9. #include <linux/mutex.h>
  10. #include <linux/mii.h>
  11. #include <linux/phy.h>
  12. #include <linux/if_bridge.h>
  13. #include <linux/etherdevice.h>
  14. #include "lan9303.h"
  15. #define LAN9303_NUM_PORTS 3
  16. /* 13.2 System Control and Status Registers
  17. * Multiply register number by 4 to get address offset.
  18. */
  19. #define LAN9303_CHIP_REV 0x14
  20. # define LAN9303_CHIP_ID 0x9303
  21. #define LAN9303_IRQ_CFG 0x15
  22. # define LAN9303_IRQ_CFG_IRQ_ENABLE BIT(8)
  23. # define LAN9303_IRQ_CFG_IRQ_POL BIT(4)
  24. # define LAN9303_IRQ_CFG_IRQ_TYPE BIT(0)
  25. #define LAN9303_INT_STS 0x16
  26. # define LAN9303_INT_STS_PHY_INT2 BIT(27)
  27. # define LAN9303_INT_STS_PHY_INT1 BIT(26)
  28. #define LAN9303_INT_EN 0x17
  29. # define LAN9303_INT_EN_PHY_INT2_EN BIT(27)
  30. # define LAN9303_INT_EN_PHY_INT1_EN BIT(26)
  31. #define LAN9303_HW_CFG 0x1D
  32. # define LAN9303_HW_CFG_READY BIT(27)
  33. # define LAN9303_HW_CFG_AMDX_EN_PORT2 BIT(26)
  34. # define LAN9303_HW_CFG_AMDX_EN_PORT1 BIT(25)
  35. #define LAN9303_PMI_DATA 0x29
  36. #define LAN9303_PMI_ACCESS 0x2A
  37. # define LAN9303_PMI_ACCESS_PHY_ADDR(x) (((x) & 0x1f) << 11)
  38. # define LAN9303_PMI_ACCESS_MIIRINDA(x) (((x) & 0x1f) << 6)
  39. # define LAN9303_PMI_ACCESS_MII_BUSY BIT(0)
  40. # define LAN9303_PMI_ACCESS_MII_WRITE BIT(1)
  41. #define LAN9303_MANUAL_FC_1 0x68
  42. #define LAN9303_MANUAL_FC_2 0x69
  43. #define LAN9303_MANUAL_FC_0 0x6a
  44. #define LAN9303_SWITCH_CSR_DATA 0x6b
  45. #define LAN9303_SWITCH_CSR_CMD 0x6c
  46. #define LAN9303_SWITCH_CSR_CMD_BUSY BIT(31)
  47. #define LAN9303_SWITCH_CSR_CMD_RW BIT(30)
  48. #define LAN9303_SWITCH_CSR_CMD_LANES (BIT(19) | BIT(18) | BIT(17) | BIT(16))
  49. #define LAN9303_VIRT_PHY_BASE 0x70
  50. #define LAN9303_VIRT_SPECIAL_CTRL 0x77
  51. #define LAN9303_VIRT_SPECIAL_TURBO BIT(10) /*Turbo MII Enable*/
  52. /*13.4 Switch Fabric Control and Status Registers
  53. * Accessed indirectly via SWITCH_CSR_CMD, SWITCH_CSR_DATA.
  54. */
  55. #define LAN9303_SW_DEV_ID 0x0000
  56. #define LAN9303_SW_RESET 0x0001
  57. #define LAN9303_SW_RESET_RESET BIT(0)
  58. #define LAN9303_SW_IMR 0x0004
  59. #define LAN9303_SW_IPR 0x0005
  60. #define LAN9303_MAC_VER_ID_0 0x0400
  61. #define LAN9303_MAC_RX_CFG_0 0x0401
  62. # define LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES BIT(1)
  63. # define LAN9303_MAC_RX_CFG_X_RX_ENABLE BIT(0)
  64. #define LAN9303_MAC_RX_UNDSZE_CNT_0 0x0410
  65. #define LAN9303_MAC_RX_64_CNT_0 0x0411
  66. #define LAN9303_MAC_RX_127_CNT_0 0x0412
  67. #define LAN9303_MAC_RX_255_CNT_0 0x413
  68. #define LAN9303_MAC_RX_511_CNT_0 0x0414
  69. #define LAN9303_MAC_RX_1023_CNT_0 0x0415
  70. #define LAN9303_MAC_RX_MAX_CNT_0 0x0416
  71. #define LAN9303_MAC_RX_OVRSZE_CNT_0 0x0417
  72. #define LAN9303_MAC_RX_PKTOK_CNT_0 0x0418
  73. #define LAN9303_MAC_RX_CRCERR_CNT_0 0x0419
  74. #define LAN9303_MAC_RX_MULCST_CNT_0 0x041a
  75. #define LAN9303_MAC_RX_BRDCST_CNT_0 0x041b
  76. #define LAN9303_MAC_RX_PAUSE_CNT_0 0x041c
  77. #define LAN9303_MAC_RX_FRAG_CNT_0 0x041d
  78. #define LAN9303_MAC_RX_JABB_CNT_0 0x041e
  79. #define LAN9303_MAC_RX_ALIGN_CNT_0 0x041f
  80. #define LAN9303_MAC_RX_PKTLEN_CNT_0 0x0420
  81. #define LAN9303_MAC_RX_GOODPKTLEN_CNT_0 0x0421
  82. #define LAN9303_MAC_RX_SYMBL_CNT_0 0x0422
  83. #define LAN9303_MAC_RX_CTLFRM_CNT_0 0x0423
  84. #define LAN9303_MAC_TX_CFG_0 0x0440
  85. # define LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT (21 << 2)
  86. # define LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE BIT(1)
  87. # define LAN9303_MAC_TX_CFG_X_TX_ENABLE BIT(0)
  88. #define LAN9303_MAC_TX_DEFER_CNT_0 0x0451
  89. #define LAN9303_MAC_TX_PAUSE_CNT_0 0x0452
  90. #define LAN9303_MAC_TX_PKTOK_CNT_0 0x0453
  91. #define LAN9303_MAC_TX_64_CNT_0 0x0454
  92. #define LAN9303_MAC_TX_127_CNT_0 0x0455
  93. #define LAN9303_MAC_TX_255_CNT_0 0x0456
  94. #define LAN9303_MAC_TX_511_CNT_0 0x0457
  95. #define LAN9303_MAC_TX_1023_CNT_0 0x0458
  96. #define LAN9303_MAC_TX_MAX_CNT_0 0x0459
  97. #define LAN9303_MAC_TX_UNDSZE_CNT_0 0x045a
  98. #define LAN9303_MAC_TX_PKTLEN_CNT_0 0x045c
  99. #define LAN9303_MAC_TX_BRDCST_CNT_0 0x045d
  100. #define LAN9303_MAC_TX_MULCST_CNT_0 0x045e
  101. #define LAN9303_MAC_TX_LATECOL_0 0x045f
  102. #define LAN9303_MAC_TX_EXCOL_CNT_0 0x0460
  103. #define LAN9303_MAC_TX_SNGLECOL_CNT_0 0x0461
  104. #define LAN9303_MAC_TX_MULTICOL_CNT_0 0x0462
  105. #define LAN9303_MAC_TX_TOTALCOL_CNT_0 0x0463
  106. #define LAN9303_MAC_VER_ID_1 0x0800
  107. #define LAN9303_MAC_RX_CFG_1 0x0801
  108. #define LAN9303_MAC_TX_CFG_1 0x0840
  109. #define LAN9303_MAC_VER_ID_2 0x0c00
  110. #define LAN9303_MAC_RX_CFG_2 0x0c01
  111. #define LAN9303_MAC_TX_CFG_2 0x0c40
  112. #define LAN9303_SWE_ALR_CMD 0x1800
  113. # define LAN9303_ALR_CMD_MAKE_ENTRY BIT(2)
  114. # define LAN9303_ALR_CMD_GET_FIRST BIT(1)
  115. # define LAN9303_ALR_CMD_GET_NEXT BIT(0)
  116. #define LAN9303_SWE_ALR_WR_DAT_0 0x1801
  117. #define LAN9303_SWE_ALR_WR_DAT_1 0x1802
  118. # define LAN9303_ALR_DAT1_VALID BIT(26)
  119. # define LAN9303_ALR_DAT1_END_OF_TABL BIT(25)
  120. # define LAN9303_ALR_DAT1_AGE_OVERRID BIT(25)
  121. # define LAN9303_ALR_DAT1_STATIC BIT(24)
  122. # define LAN9303_ALR_DAT1_PORT_BITOFFS 16
  123. # define LAN9303_ALR_DAT1_PORT_MASK (7 << LAN9303_ALR_DAT1_PORT_BITOFFS)
  124. #define LAN9303_SWE_ALR_RD_DAT_0 0x1805
  125. #define LAN9303_SWE_ALR_RD_DAT_1 0x1806
  126. #define LAN9303_SWE_ALR_CMD_STS 0x1808
  127. # define ALR_STS_MAKE_PEND BIT(0)
  128. #define LAN9303_SWE_VLAN_CMD 0x180b
  129. # define LAN9303_SWE_VLAN_CMD_RNW BIT(5)
  130. # define LAN9303_SWE_VLAN_CMD_PVIDNVLAN BIT(4)
  131. #define LAN9303_SWE_VLAN_WR_DATA 0x180c
  132. #define LAN9303_SWE_VLAN_RD_DATA 0x180e
  133. # define LAN9303_SWE_VLAN_MEMBER_PORT2 BIT(17)
  134. # define LAN9303_SWE_VLAN_UNTAG_PORT2 BIT(16)
  135. # define LAN9303_SWE_VLAN_MEMBER_PORT1 BIT(15)
  136. # define LAN9303_SWE_VLAN_UNTAG_PORT1 BIT(14)
  137. # define LAN9303_SWE_VLAN_MEMBER_PORT0 BIT(13)
  138. # define LAN9303_SWE_VLAN_UNTAG_PORT0 BIT(12)
  139. #define LAN9303_SWE_VLAN_CMD_STS 0x1810
  140. #define LAN9303_SWE_GLB_INGRESS_CFG 0x1840
  141. # define LAN9303_SWE_GLB_INGR_IGMP_TRAP BIT(7)
  142. # define LAN9303_SWE_GLB_INGR_IGMP_PORT(p) BIT(10 + p)
  143. #define LAN9303_SWE_PORT_STATE 0x1843
  144. # define LAN9303_SWE_PORT_STATE_FORWARDING_PORT2 (0)
  145. # define LAN9303_SWE_PORT_STATE_LEARNING_PORT2 BIT(5)
  146. # define LAN9303_SWE_PORT_STATE_BLOCKING_PORT2 BIT(4)
  147. # define LAN9303_SWE_PORT_STATE_FORWARDING_PORT1 (0)
  148. # define LAN9303_SWE_PORT_STATE_LEARNING_PORT1 BIT(3)
  149. # define LAN9303_SWE_PORT_STATE_BLOCKING_PORT1 BIT(2)
  150. # define LAN9303_SWE_PORT_STATE_FORWARDING_PORT0 (0)
  151. # define LAN9303_SWE_PORT_STATE_LEARNING_PORT0 BIT(1)
  152. # define LAN9303_SWE_PORT_STATE_BLOCKING_PORT0 BIT(0)
  153. # define LAN9303_SWE_PORT_STATE_DISABLED_PORT0 (3)
  154. #define LAN9303_SWE_PORT_MIRROR 0x1846
  155. # define LAN9303_SWE_PORT_MIRROR_SNIFF_ALL BIT(8)
  156. # define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT2 BIT(7)
  157. # define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT1 BIT(6)
  158. # define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT0 BIT(5)
  159. # define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT2 BIT(4)
  160. # define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT1 BIT(3)
  161. # define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT0 BIT(2)
  162. # define LAN9303_SWE_PORT_MIRROR_ENABLE_RX_MIRRORING BIT(1)
  163. # define LAN9303_SWE_PORT_MIRROR_ENABLE_TX_MIRRORING BIT(0)
  164. # define LAN9303_SWE_PORT_MIRROR_DISABLED 0
  165. #define LAN9303_SWE_INGRESS_PORT_TYPE 0x1847
  166. #define LAN9303_SWE_INGRESS_PORT_TYPE_VLAN 3
  167. #define LAN9303_BM_CFG 0x1c00
  168. #define LAN9303_BM_EGRSS_PORT_TYPE 0x1c0c
  169. # define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT2 (BIT(17) | BIT(16))
  170. # define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT1 (BIT(9) | BIT(8))
  171. # define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT0 (BIT(1) | BIT(0))
  172. #define LAN9303_SWITCH_PORT_REG(port, reg0) (0x400 * (port) + (reg0))
  173. /* the built-in PHYs are of type LAN911X */
  174. #define MII_LAN911X_SPECIAL_MODES 0x12
  175. #define MII_LAN911X_SPECIAL_CONTROL_STATUS 0x1f
  176. static const struct regmap_range lan9303_valid_regs[] = {
  177. regmap_reg_range(0x14, 0x17), /* misc, interrupt */
  178. regmap_reg_range(0x19, 0x19), /* endian test */
  179. regmap_reg_range(0x1d, 0x1d), /* hardware config */
  180. regmap_reg_range(0x23, 0x24), /* general purpose timer */
  181. regmap_reg_range(0x27, 0x27), /* counter */
  182. regmap_reg_range(0x29, 0x2a), /* PMI index regs */
  183. regmap_reg_range(0x68, 0x6a), /* flow control */
  184. regmap_reg_range(0x6b, 0x6c), /* switch fabric indirect regs */
  185. regmap_reg_range(0x6d, 0x6f), /* misc */
  186. regmap_reg_range(0x70, 0x77), /* virtual phy */
  187. regmap_reg_range(0x78, 0x7a), /* GPIO */
  188. regmap_reg_range(0x7c, 0x7e), /* MAC & reset */
  189. regmap_reg_range(0x80, 0xb7), /* switch fabric direct regs (wr only) */
  190. };
  191. static const struct regmap_range lan9303_reserved_ranges[] = {
  192. regmap_reg_range(0x00, 0x13),
  193. regmap_reg_range(0x18, 0x18),
  194. regmap_reg_range(0x1a, 0x1c),
  195. regmap_reg_range(0x1e, 0x22),
  196. regmap_reg_range(0x25, 0x26),
  197. regmap_reg_range(0x28, 0x28),
  198. regmap_reg_range(0x2b, 0x67),
  199. regmap_reg_range(0x7b, 0x7b),
  200. regmap_reg_range(0x7f, 0x7f),
  201. regmap_reg_range(0xb8, 0xff),
  202. };
  203. const struct regmap_access_table lan9303_register_set = {
  204. .yes_ranges = lan9303_valid_regs,
  205. .n_yes_ranges = ARRAY_SIZE(lan9303_valid_regs),
  206. .no_ranges = lan9303_reserved_ranges,
  207. .n_no_ranges = ARRAY_SIZE(lan9303_reserved_ranges),
  208. };
  209. EXPORT_SYMBOL(lan9303_register_set);
  210. static int lan9303_read(struct regmap *regmap, unsigned int offset, u32 *reg)
  211. {
  212. int ret, i;
  213. /* we can lose arbitration for the I2C case, because the device
  214. * tries to detect and read an external EEPROM after reset and acts as
  215. * a master on the shared I2C bus itself. This conflicts with our
  216. * attempts to access the device as a slave at the same moment.
  217. */
  218. for (i = 0; i < 5; i++) {
  219. ret = regmap_read(regmap, offset, reg);
  220. if (!ret)
  221. return 0;
  222. if (ret != -EAGAIN)
  223. break;
  224. msleep(500);
  225. }
  226. return -EIO;
  227. }
  228. static int lan9303_read_wait(struct lan9303 *chip, int offset, u32 mask)
  229. {
  230. int i;
  231. for (i = 0; i < 25; i++) {
  232. u32 reg;
  233. int ret;
  234. ret = lan9303_read(chip->regmap, offset, &reg);
  235. if (ret) {
  236. dev_err(chip->dev, "%s failed to read offset %d: %d\n",
  237. __func__, offset, ret);
  238. return ret;
  239. }
  240. if (!(reg & mask))
  241. return 0;
  242. usleep_range(1000, 2000);
  243. }
  244. return -ETIMEDOUT;
  245. }
  246. static int lan9303_virt_phy_reg_read(struct lan9303 *chip, int regnum)
  247. {
  248. int ret;
  249. u32 val;
  250. if (regnum > MII_EXPANSION)
  251. return -EINVAL;
  252. ret = lan9303_read(chip->regmap, LAN9303_VIRT_PHY_BASE + regnum, &val);
  253. if (ret)
  254. return ret;
  255. return val & 0xffff;
  256. }
  257. static int lan9303_virt_phy_reg_write(struct lan9303 *chip, int regnum, u16 val)
  258. {
  259. if (regnum > MII_EXPANSION)
  260. return -EINVAL;
  261. return regmap_write(chip->regmap, LAN9303_VIRT_PHY_BASE + regnum, val);
  262. }
  263. static int lan9303_indirect_phy_wait_for_completion(struct lan9303 *chip)
  264. {
  265. return lan9303_read_wait(chip, LAN9303_PMI_ACCESS,
  266. LAN9303_PMI_ACCESS_MII_BUSY);
  267. }
  268. static int lan9303_indirect_phy_read(struct lan9303 *chip, int addr, int regnum)
  269. {
  270. int ret;
  271. u32 val;
  272. val = LAN9303_PMI_ACCESS_PHY_ADDR(addr);
  273. val |= LAN9303_PMI_ACCESS_MIIRINDA(regnum);
  274. mutex_lock(&chip->indirect_mutex);
  275. ret = lan9303_indirect_phy_wait_for_completion(chip);
  276. if (ret)
  277. goto on_error;
  278. /* start the MII read cycle */
  279. ret = regmap_write(chip->regmap, LAN9303_PMI_ACCESS, val);
  280. if (ret)
  281. goto on_error;
  282. ret = lan9303_indirect_phy_wait_for_completion(chip);
  283. if (ret)
  284. goto on_error;
  285. /* read the result of this operation */
  286. ret = lan9303_read(chip->regmap, LAN9303_PMI_DATA, &val);
  287. if (ret)
  288. goto on_error;
  289. mutex_unlock(&chip->indirect_mutex);
  290. return val & 0xffff;
  291. on_error:
  292. mutex_unlock(&chip->indirect_mutex);
  293. return ret;
  294. }
  295. static int lan9303_indirect_phy_write(struct lan9303 *chip, int addr,
  296. int regnum, u16 val)
  297. {
  298. int ret;
  299. u32 reg;
  300. reg = LAN9303_PMI_ACCESS_PHY_ADDR(addr);
  301. reg |= LAN9303_PMI_ACCESS_MIIRINDA(regnum);
  302. reg |= LAN9303_PMI_ACCESS_MII_WRITE;
  303. mutex_lock(&chip->indirect_mutex);
  304. ret = lan9303_indirect_phy_wait_for_completion(chip);
  305. if (ret)
  306. goto on_error;
  307. /* write the data first... */
  308. ret = regmap_write(chip->regmap, LAN9303_PMI_DATA, val);
  309. if (ret)
  310. goto on_error;
  311. /* ...then start the MII write cycle */
  312. ret = regmap_write(chip->regmap, LAN9303_PMI_ACCESS, reg);
  313. on_error:
  314. mutex_unlock(&chip->indirect_mutex);
  315. return ret;
  316. }
  317. const struct lan9303_phy_ops lan9303_indirect_phy_ops = {
  318. .phy_read = lan9303_indirect_phy_read,
  319. .phy_write = lan9303_indirect_phy_write,
  320. };
  321. EXPORT_SYMBOL_GPL(lan9303_indirect_phy_ops);
  322. static int lan9303_switch_wait_for_completion(struct lan9303 *chip)
  323. {
  324. return lan9303_read_wait(chip, LAN9303_SWITCH_CSR_CMD,
  325. LAN9303_SWITCH_CSR_CMD_BUSY);
  326. }
  327. static int lan9303_write_switch_reg(struct lan9303 *chip, u16 regnum, u32 val)
  328. {
  329. u32 reg;
  330. int ret;
  331. reg = regnum;
  332. reg |= LAN9303_SWITCH_CSR_CMD_LANES;
  333. reg |= LAN9303_SWITCH_CSR_CMD_BUSY;
  334. mutex_lock(&chip->indirect_mutex);
  335. ret = lan9303_switch_wait_for_completion(chip);
  336. if (ret)
  337. goto on_error;
  338. ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_DATA, val);
  339. if (ret) {
  340. dev_err(chip->dev, "Failed to write csr data reg: %d\n", ret);
  341. goto on_error;
  342. }
  343. /* trigger write */
  344. ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_CMD, reg);
  345. if (ret)
  346. dev_err(chip->dev, "Failed to write csr command reg: %d\n",
  347. ret);
  348. on_error:
  349. mutex_unlock(&chip->indirect_mutex);
  350. return ret;
  351. }
  352. static int lan9303_read_switch_reg(struct lan9303 *chip, u16 regnum, u32 *val)
  353. {
  354. u32 reg;
  355. int ret;
  356. reg = regnum;
  357. reg |= LAN9303_SWITCH_CSR_CMD_LANES;
  358. reg |= LAN9303_SWITCH_CSR_CMD_RW;
  359. reg |= LAN9303_SWITCH_CSR_CMD_BUSY;
  360. mutex_lock(&chip->indirect_mutex);
  361. ret = lan9303_switch_wait_for_completion(chip);
  362. if (ret)
  363. goto on_error;
  364. /* trigger read */
  365. ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_CMD, reg);
  366. if (ret) {
  367. dev_err(chip->dev, "Failed to write csr command reg: %d\n",
  368. ret);
  369. goto on_error;
  370. }
  371. ret = lan9303_switch_wait_for_completion(chip);
  372. if (ret)
  373. goto on_error;
  374. ret = lan9303_read(chip->regmap, LAN9303_SWITCH_CSR_DATA, val);
  375. if (ret)
  376. dev_err(chip->dev, "Failed to read csr data reg: %d\n", ret);
  377. on_error:
  378. mutex_unlock(&chip->indirect_mutex);
  379. return ret;
  380. }
  381. static int lan9303_write_switch_reg_mask(struct lan9303 *chip, u16 regnum,
  382. u32 val, u32 mask)
  383. {
  384. int ret;
  385. u32 reg;
  386. ret = lan9303_read_switch_reg(chip, regnum, &reg);
  387. if (ret)
  388. return ret;
  389. reg = (reg & ~mask) | val;
  390. return lan9303_write_switch_reg(chip, regnum, reg);
  391. }
  392. static int lan9303_write_switch_port(struct lan9303 *chip, int port,
  393. u16 regnum, u32 val)
  394. {
  395. return lan9303_write_switch_reg(
  396. chip, LAN9303_SWITCH_PORT_REG(port, regnum), val);
  397. }
  398. static int lan9303_read_switch_port(struct lan9303 *chip, int port,
  399. u16 regnum, u32 *val)
  400. {
  401. return lan9303_read_switch_reg(
  402. chip, LAN9303_SWITCH_PORT_REG(port, regnum), val);
  403. }
  404. static int lan9303_detect_phy_setup(struct lan9303 *chip)
  405. {
  406. int reg;
  407. /* Calculate chip->phy_addr_base:
  408. * Depending on the 'phy_addr_sel_strap' setting, the three phys are
  409. * using IDs 0-1-2 or IDs 1-2-3. We cannot read back the
  410. * 'phy_addr_sel_strap' setting directly, so we need a test, which
  411. * configuration is active:
  412. * Special reg 18 of phy 3 reads as 0x0000, if 'phy_addr_sel_strap' is 0
  413. * and the IDs are 0-1-2, else it contains something different from
  414. * 0x0000, which means 'phy_addr_sel_strap' is 1 and the IDs are 1-2-3.
  415. * 0xffff is returned on MDIO read with no response.
  416. */
  417. reg = chip->ops->phy_read(chip, 3, MII_LAN911X_SPECIAL_MODES);
  418. if (reg < 0) {
  419. dev_err(chip->dev, "Failed to detect phy config: %d\n", reg);
  420. return reg;
  421. }
  422. chip->phy_addr_base = reg != 0 && reg != 0xffff;
  423. dev_dbg(chip->dev, "Phy setup '%s' detected\n",
  424. chip->phy_addr_base ? "1-2-3" : "0-1-2");
  425. return 0;
  426. }
  427. /* Map ALR-port bits to port bitmap, and back */
  428. static const int alrport_2_portmap[] = {1, 2, 4, 0, 3, 5, 6, 7 };
  429. static const int portmap_2_alrport[] = {3, 0, 1, 4, 2, 5, 6, 7 };
  430. /* Return pointer to first free ALR cache entry, return NULL if none */
  431. static struct lan9303_alr_cache_entry *
  432. lan9303_alr_cache_find_free(struct lan9303 *chip)
  433. {
  434. int i;
  435. struct lan9303_alr_cache_entry *entr = chip->alr_cache;
  436. for (i = 0; i < LAN9303_NUM_ALR_RECORDS; i++, entr++)
  437. if (entr->port_map == 0)
  438. return entr;
  439. return NULL;
  440. }
  441. /* Return pointer to ALR cache entry matching MAC address */
  442. static struct lan9303_alr_cache_entry *
  443. lan9303_alr_cache_find_mac(struct lan9303 *chip, const u8 *mac_addr)
  444. {
  445. int i;
  446. struct lan9303_alr_cache_entry *entr = chip->alr_cache;
  447. BUILD_BUG_ON_MSG(sizeof(struct lan9303_alr_cache_entry) & 1,
  448. "ether_addr_equal require u16 alignment");
  449. for (i = 0; i < LAN9303_NUM_ALR_RECORDS; i++, entr++)
  450. if (ether_addr_equal(entr->mac_addr, mac_addr))
  451. return entr;
  452. return NULL;
  453. }
  454. static int lan9303_csr_reg_wait(struct lan9303 *chip, int regno, u32 mask)
  455. {
  456. int i;
  457. for (i = 0; i < 25; i++) {
  458. u32 reg;
  459. lan9303_read_switch_reg(chip, regno, &reg);
  460. if (!(reg & mask))
  461. return 0;
  462. usleep_range(1000, 2000);
  463. }
  464. return -ETIMEDOUT;
  465. }
  466. static int lan9303_alr_make_entry_raw(struct lan9303 *chip, u32 dat0, u32 dat1)
  467. {
  468. lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_WR_DAT_0, dat0);
  469. lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_WR_DAT_1, dat1);
  470. lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD,
  471. LAN9303_ALR_CMD_MAKE_ENTRY);
  472. lan9303_csr_reg_wait(chip, LAN9303_SWE_ALR_CMD_STS, ALR_STS_MAKE_PEND);
  473. lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 0);
  474. return 0;
  475. }
  476. typedef int alr_loop_cb_t(struct lan9303 *chip, u32 dat0, u32 dat1,
  477. int portmap, void *ctx);
  478. static int lan9303_alr_loop(struct lan9303 *chip, alr_loop_cb_t *cb, void *ctx)
  479. {
  480. int ret = 0, i;
  481. mutex_lock(&chip->alr_mutex);
  482. lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD,
  483. LAN9303_ALR_CMD_GET_FIRST);
  484. lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 0);
  485. for (i = 1; i < LAN9303_NUM_ALR_RECORDS; i++) {
  486. u32 dat0, dat1;
  487. int alrport, portmap;
  488. lan9303_read_switch_reg(chip, LAN9303_SWE_ALR_RD_DAT_0, &dat0);
  489. lan9303_read_switch_reg(chip, LAN9303_SWE_ALR_RD_DAT_1, &dat1);
  490. if (dat1 & LAN9303_ALR_DAT1_END_OF_TABL)
  491. break;
  492. alrport = (dat1 & LAN9303_ALR_DAT1_PORT_MASK) >>
  493. LAN9303_ALR_DAT1_PORT_BITOFFS;
  494. portmap = alrport_2_portmap[alrport];
  495. ret = cb(chip, dat0, dat1, portmap, ctx);
  496. if (ret)
  497. break;
  498. lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD,
  499. LAN9303_ALR_CMD_GET_NEXT);
  500. lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 0);
  501. }
  502. mutex_unlock(&chip->alr_mutex);
  503. return ret;
  504. }
  505. static void alr_reg_to_mac(u32 dat0, u32 dat1, u8 mac[6])
  506. {
  507. mac[0] = (dat0 >> 0) & 0xff;
  508. mac[1] = (dat0 >> 8) & 0xff;
  509. mac[2] = (dat0 >> 16) & 0xff;
  510. mac[3] = (dat0 >> 24) & 0xff;
  511. mac[4] = (dat1 >> 0) & 0xff;
  512. mac[5] = (dat1 >> 8) & 0xff;
  513. }
  514. struct del_port_learned_ctx {
  515. int port;
  516. };
  517. /* Clear learned (non-static) entry on given port */
  518. static int alr_loop_cb_del_port_learned(struct lan9303 *chip, u32 dat0,
  519. u32 dat1, int portmap, void *ctx)
  520. {
  521. struct del_port_learned_ctx *del_ctx = ctx;
  522. int port = del_ctx->port;
  523. if (((BIT(port) & portmap) == 0) || (dat1 & LAN9303_ALR_DAT1_STATIC))
  524. return 0;
  525. /* learned entries has only one port, we can just delete */
  526. dat1 &= ~LAN9303_ALR_DAT1_VALID; /* delete entry */
  527. lan9303_alr_make_entry_raw(chip, dat0, dat1);
  528. return 0;
  529. }
  530. struct port_fdb_dump_ctx {
  531. int port;
  532. void *data;
  533. dsa_fdb_dump_cb_t *cb;
  534. };
  535. static int alr_loop_cb_fdb_port_dump(struct lan9303 *chip, u32 dat0,
  536. u32 dat1, int portmap, void *ctx)
  537. {
  538. struct port_fdb_dump_ctx *dump_ctx = ctx;
  539. u8 mac[ETH_ALEN];
  540. bool is_static;
  541. if ((BIT(dump_ctx->port) & portmap) == 0)
  542. return 0;
  543. alr_reg_to_mac(dat0, dat1, mac);
  544. is_static = !!(dat1 & LAN9303_ALR_DAT1_STATIC);
  545. return dump_ctx->cb(mac, 0, is_static, dump_ctx->data);
  546. }
  547. /* Set a static ALR entry. Delete entry if port_map is zero */
  548. static void lan9303_alr_set_entry(struct lan9303 *chip, const u8 *mac,
  549. u8 port_map, bool stp_override)
  550. {
  551. u32 dat0, dat1, alr_port;
  552. dev_dbg(chip->dev, "%s(%pM, %d)\n", __func__, mac, port_map);
  553. dat1 = LAN9303_ALR_DAT1_STATIC;
  554. if (port_map)
  555. dat1 |= LAN9303_ALR_DAT1_VALID;
  556. /* otherwise no ports: delete entry */
  557. if (stp_override)
  558. dat1 |= LAN9303_ALR_DAT1_AGE_OVERRID;
  559. alr_port = portmap_2_alrport[port_map & 7];
  560. dat1 &= ~LAN9303_ALR_DAT1_PORT_MASK;
  561. dat1 |= alr_port << LAN9303_ALR_DAT1_PORT_BITOFFS;
  562. dat0 = 0;
  563. dat0 |= (mac[0] << 0);
  564. dat0 |= (mac[1] << 8);
  565. dat0 |= (mac[2] << 16);
  566. dat0 |= (mac[3] << 24);
  567. dat1 |= (mac[4] << 0);
  568. dat1 |= (mac[5] << 8);
  569. lan9303_alr_make_entry_raw(chip, dat0, dat1);
  570. }
  571. /* Add port to static ALR entry, create new static entry if needed */
  572. static int lan9303_alr_add_port(struct lan9303 *chip, const u8 *mac, int port,
  573. bool stp_override)
  574. {
  575. struct lan9303_alr_cache_entry *entr;
  576. mutex_lock(&chip->alr_mutex);
  577. entr = lan9303_alr_cache_find_mac(chip, mac);
  578. if (!entr) { /*New entry */
  579. entr = lan9303_alr_cache_find_free(chip);
  580. if (!entr) {
  581. mutex_unlock(&chip->alr_mutex);
  582. return -ENOSPC;
  583. }
  584. ether_addr_copy(entr->mac_addr, mac);
  585. }
  586. entr->port_map |= BIT(port);
  587. entr->stp_override = stp_override;
  588. lan9303_alr_set_entry(chip, mac, entr->port_map, stp_override);
  589. mutex_unlock(&chip->alr_mutex);
  590. return 0;
  591. }
  592. /* Delete static port from ALR entry, delete entry if last port */
  593. static int lan9303_alr_del_port(struct lan9303 *chip, const u8 *mac, int port)
  594. {
  595. struct lan9303_alr_cache_entry *entr;
  596. mutex_lock(&chip->alr_mutex);
  597. entr = lan9303_alr_cache_find_mac(chip, mac);
  598. if (!entr)
  599. goto out; /* no static entry found */
  600. entr->port_map &= ~BIT(port);
  601. if (entr->port_map == 0) /* zero means its free again */
  602. eth_zero_addr(entr->mac_addr);
  603. lan9303_alr_set_entry(chip, mac, entr->port_map, entr->stp_override);
  604. out:
  605. mutex_unlock(&chip->alr_mutex);
  606. return 0;
  607. }
  608. static int lan9303_disable_processing_port(struct lan9303 *chip,
  609. unsigned int port)
  610. {
  611. int ret;
  612. /* disable RX, but keep register reset default values else */
  613. ret = lan9303_write_switch_port(chip, port, LAN9303_MAC_RX_CFG_0,
  614. LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES);
  615. if (ret)
  616. return ret;
  617. /* disable TX, but keep register reset default values else */
  618. return lan9303_write_switch_port(chip, port, LAN9303_MAC_TX_CFG_0,
  619. LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT |
  620. LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE);
  621. }
  622. static int lan9303_enable_processing_port(struct lan9303 *chip,
  623. unsigned int port)
  624. {
  625. int ret;
  626. /* enable RX and keep register reset default values else */
  627. ret = lan9303_write_switch_port(chip, port, LAN9303_MAC_RX_CFG_0,
  628. LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES |
  629. LAN9303_MAC_RX_CFG_X_RX_ENABLE);
  630. if (ret)
  631. return ret;
  632. /* enable TX and keep register reset default values else */
  633. return lan9303_write_switch_port(chip, port, LAN9303_MAC_TX_CFG_0,
  634. LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT |
  635. LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE |
  636. LAN9303_MAC_TX_CFG_X_TX_ENABLE);
  637. }
  638. /* forward special tagged packets from port 0 to port 1 *or* port 2 */
  639. static int lan9303_setup_tagging(struct lan9303 *chip)
  640. {
  641. int ret;
  642. u32 val;
  643. /* enable defining the destination port via special VLAN tagging
  644. * for port 0
  645. */
  646. ret = lan9303_write_switch_reg(chip, LAN9303_SWE_INGRESS_PORT_TYPE,
  647. LAN9303_SWE_INGRESS_PORT_TYPE_VLAN);
  648. if (ret)
  649. return ret;
  650. /* tag incoming packets at port 1 and 2 on their way to port 0 to be
  651. * able to discover their source port
  652. */
  653. val = LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT0;
  654. return lan9303_write_switch_reg(chip, LAN9303_BM_EGRSS_PORT_TYPE, val);
  655. }
  656. /* We want a special working switch:
  657. * - do not forward packets between port 1 and 2
  658. * - forward everything from port 1 to port 0
  659. * - forward everything from port 2 to port 0
  660. */
  661. static int lan9303_separate_ports(struct lan9303 *chip)
  662. {
  663. int ret;
  664. lan9303_alr_del_port(chip, eth_stp_addr, 0);
  665. ret = lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_MIRROR,
  666. LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT0 |
  667. LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT1 |
  668. LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT2 |
  669. LAN9303_SWE_PORT_MIRROR_ENABLE_RX_MIRRORING |
  670. LAN9303_SWE_PORT_MIRROR_SNIFF_ALL);
  671. if (ret)
  672. return ret;
  673. /* prevent port 1 and 2 from forwarding packets by their own */
  674. return lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_STATE,
  675. LAN9303_SWE_PORT_STATE_FORWARDING_PORT0 |
  676. LAN9303_SWE_PORT_STATE_BLOCKING_PORT1 |
  677. LAN9303_SWE_PORT_STATE_BLOCKING_PORT2);
  678. }
  679. static void lan9303_bridge_ports(struct lan9303 *chip)
  680. {
  681. /* ports bridged: remove mirroring */
  682. lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_MIRROR,
  683. LAN9303_SWE_PORT_MIRROR_DISABLED);
  684. lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_STATE,
  685. chip->swe_port_state);
  686. lan9303_alr_add_port(chip, eth_stp_addr, 0, true);
  687. }
  688. static void lan9303_handle_reset(struct lan9303 *chip)
  689. {
  690. if (!chip->reset_gpio)
  691. return;
  692. if (chip->reset_duration != 0)
  693. msleep(chip->reset_duration);
  694. /* release (deassert) reset and activate the device */
  695. gpiod_set_value_cansleep(chip->reset_gpio, 0);
  696. }
  697. /* stop processing packets for all ports */
  698. static int lan9303_disable_processing(struct lan9303 *chip)
  699. {
  700. int p;
  701. for (p = 1; p < LAN9303_NUM_PORTS; p++) {
  702. int ret = lan9303_disable_processing_port(chip, p);
  703. if (ret)
  704. return ret;
  705. }
  706. return 0;
  707. }
  708. static int lan9303_check_device(struct lan9303 *chip)
  709. {
  710. int ret;
  711. u32 reg;
  712. ret = lan9303_read(chip->regmap, LAN9303_CHIP_REV, &reg);
  713. if (ret) {
  714. dev_err(chip->dev, "failed to read chip revision register: %d\n",
  715. ret);
  716. if (!chip->reset_gpio) {
  717. dev_dbg(chip->dev,
  718. "hint: maybe failed due to missing reset GPIO\n");
  719. }
  720. return ret;
  721. }
  722. if ((reg >> 16) != LAN9303_CHIP_ID) {
  723. dev_err(chip->dev, "expecting LAN9303 chip, but found: %X\n",
  724. reg >> 16);
  725. return -ENODEV;
  726. }
  727. /* The default state of the LAN9303 device is to forward packets between
  728. * all ports (if not configured differently by an external EEPROM).
  729. * The initial state of a DSA device must be forwarding packets only
  730. * between the external and the internal ports and no forwarding
  731. * between the external ports. In preparation we stop packet handling
  732. * at all for now until the LAN9303 device is re-programmed accordingly.
  733. */
  734. ret = lan9303_disable_processing(chip);
  735. if (ret)
  736. dev_warn(chip->dev, "failed to disable switching %d\n", ret);
  737. dev_info(chip->dev, "Found LAN9303 rev. %u\n", reg & 0xffff);
  738. ret = lan9303_detect_phy_setup(chip);
  739. if (ret) {
  740. dev_err(chip->dev,
  741. "failed to discover phy bootstrap setup: %d\n", ret);
  742. return ret;
  743. }
  744. return 0;
  745. }
  746. /* ---------------------------- DSA -----------------------------------*/
  747. static enum dsa_tag_protocol lan9303_get_tag_protocol(struct dsa_switch *ds,
  748. int port)
  749. {
  750. return DSA_TAG_PROTO_LAN9303;
  751. }
  752. static int lan9303_setup(struct dsa_switch *ds)
  753. {
  754. struct lan9303 *chip = ds->priv;
  755. int ret;
  756. /* Make sure that port 0 is the cpu port */
  757. if (!dsa_is_cpu_port(ds, 0)) {
  758. dev_err(chip->dev, "port 0 is not the CPU port\n");
  759. return -EINVAL;
  760. }
  761. ret = lan9303_setup_tagging(chip);
  762. if (ret)
  763. dev_err(chip->dev, "failed to setup port tagging %d\n", ret);
  764. ret = lan9303_separate_ports(chip);
  765. if (ret)
  766. dev_err(chip->dev, "failed to separate ports %d\n", ret);
  767. ret = lan9303_enable_processing_port(chip, 0);
  768. if (ret)
  769. dev_err(chip->dev, "failed to re-enable switching %d\n", ret);
  770. /* Trap IGMP to port 0 */
  771. ret = lan9303_write_switch_reg_mask(chip, LAN9303_SWE_GLB_INGRESS_CFG,
  772. LAN9303_SWE_GLB_INGR_IGMP_TRAP |
  773. LAN9303_SWE_GLB_INGR_IGMP_PORT(0),
  774. LAN9303_SWE_GLB_INGR_IGMP_PORT(1) |
  775. LAN9303_SWE_GLB_INGR_IGMP_PORT(2));
  776. if (ret)
  777. dev_err(chip->dev, "failed to setup IGMP trap %d\n", ret);
  778. return 0;
  779. }
  780. struct lan9303_mib_desc {
  781. unsigned int offset; /* offset of first MAC */
  782. const char *name;
  783. };
  784. static const struct lan9303_mib_desc lan9303_mib[] = {
  785. { .offset = LAN9303_MAC_RX_BRDCST_CNT_0, .name = "RxBroad", },
  786. { .offset = LAN9303_MAC_RX_PAUSE_CNT_0, .name = "RxPause", },
  787. { .offset = LAN9303_MAC_RX_MULCST_CNT_0, .name = "RxMulti", },
  788. { .offset = LAN9303_MAC_RX_PKTOK_CNT_0, .name = "RxOk", },
  789. { .offset = LAN9303_MAC_RX_CRCERR_CNT_0, .name = "RxCrcErr", },
  790. { .offset = LAN9303_MAC_RX_ALIGN_CNT_0, .name = "RxAlignErr", },
  791. { .offset = LAN9303_MAC_RX_JABB_CNT_0, .name = "RxJabber", },
  792. { .offset = LAN9303_MAC_RX_FRAG_CNT_0, .name = "RxFragment", },
  793. { .offset = LAN9303_MAC_RX_64_CNT_0, .name = "Rx64Byte", },
  794. { .offset = LAN9303_MAC_RX_127_CNT_0, .name = "Rx128Byte", },
  795. { .offset = LAN9303_MAC_RX_255_CNT_0, .name = "Rx256Byte", },
  796. { .offset = LAN9303_MAC_RX_511_CNT_0, .name = "Rx512Byte", },
  797. { .offset = LAN9303_MAC_RX_1023_CNT_0, .name = "Rx1024Byte", },
  798. { .offset = LAN9303_MAC_RX_MAX_CNT_0, .name = "RxMaxByte", },
  799. { .offset = LAN9303_MAC_RX_PKTLEN_CNT_0, .name = "RxByteCnt", },
  800. { .offset = LAN9303_MAC_RX_SYMBL_CNT_0, .name = "RxSymbolCnt", },
  801. { .offset = LAN9303_MAC_RX_CTLFRM_CNT_0, .name = "RxCfs", },
  802. { .offset = LAN9303_MAC_RX_OVRSZE_CNT_0, .name = "RxOverFlow", },
  803. { .offset = LAN9303_MAC_TX_UNDSZE_CNT_0, .name = "TxShort", },
  804. { .offset = LAN9303_MAC_TX_BRDCST_CNT_0, .name = "TxBroad", },
  805. { .offset = LAN9303_MAC_TX_PAUSE_CNT_0, .name = "TxPause", },
  806. { .offset = LAN9303_MAC_TX_MULCST_CNT_0, .name = "TxMulti", },
  807. { .offset = LAN9303_MAC_RX_UNDSZE_CNT_0, .name = "TxUnderRun", },
  808. { .offset = LAN9303_MAC_TX_64_CNT_0, .name = "Tx64Byte", },
  809. { .offset = LAN9303_MAC_TX_127_CNT_0, .name = "Tx128Byte", },
  810. { .offset = LAN9303_MAC_TX_255_CNT_0, .name = "Tx256Byte", },
  811. { .offset = LAN9303_MAC_TX_511_CNT_0, .name = "Tx512Byte", },
  812. { .offset = LAN9303_MAC_TX_1023_CNT_0, .name = "Tx1024Byte", },
  813. { .offset = LAN9303_MAC_TX_MAX_CNT_0, .name = "TxMaxByte", },
  814. { .offset = LAN9303_MAC_TX_PKTLEN_CNT_0, .name = "TxByteCnt", },
  815. { .offset = LAN9303_MAC_TX_PKTOK_CNT_0, .name = "TxOk", },
  816. { .offset = LAN9303_MAC_TX_TOTALCOL_CNT_0, .name = "TxCollision", },
  817. { .offset = LAN9303_MAC_TX_MULTICOL_CNT_0, .name = "TxMultiCol", },
  818. { .offset = LAN9303_MAC_TX_SNGLECOL_CNT_0, .name = "TxSingleCol", },
  819. { .offset = LAN9303_MAC_TX_EXCOL_CNT_0, .name = "TxExcCol", },
  820. { .offset = LAN9303_MAC_TX_DEFER_CNT_0, .name = "TxDefer", },
  821. { .offset = LAN9303_MAC_TX_LATECOL_0, .name = "TxLateCol", },
  822. };
  823. static void lan9303_get_strings(struct dsa_switch *ds, int port,
  824. u32 stringset, uint8_t *data)
  825. {
  826. unsigned int u;
  827. if (stringset != ETH_SS_STATS)
  828. return;
  829. for (u = 0; u < ARRAY_SIZE(lan9303_mib); u++) {
  830. strncpy(data + u * ETH_GSTRING_LEN, lan9303_mib[u].name,
  831. ETH_GSTRING_LEN);
  832. }
  833. }
  834. static void lan9303_get_ethtool_stats(struct dsa_switch *ds, int port,
  835. uint64_t *data)
  836. {
  837. struct lan9303 *chip = ds->priv;
  838. unsigned int u;
  839. for (u = 0; u < ARRAY_SIZE(lan9303_mib); u++) {
  840. u32 reg;
  841. int ret;
  842. ret = lan9303_read_switch_port(
  843. chip, port, lan9303_mib[u].offset, &reg);
  844. if (ret)
  845. dev_warn(chip->dev, "Reading status port %d reg %u failed\n",
  846. port, lan9303_mib[u].offset);
  847. data[u] = reg;
  848. }
  849. }
  850. static int lan9303_get_sset_count(struct dsa_switch *ds, int port, int sset)
  851. {
  852. if (sset != ETH_SS_STATS)
  853. return 0;
  854. return ARRAY_SIZE(lan9303_mib);
  855. }
  856. static int lan9303_phy_read(struct dsa_switch *ds, int phy, int regnum)
  857. {
  858. struct lan9303 *chip = ds->priv;
  859. int phy_base = chip->phy_addr_base;
  860. if (phy == phy_base)
  861. return lan9303_virt_phy_reg_read(chip, regnum);
  862. if (phy > phy_base + 2)
  863. return -ENODEV;
  864. return chip->ops->phy_read(chip, phy, regnum);
  865. }
  866. static int lan9303_phy_write(struct dsa_switch *ds, int phy, int regnum,
  867. u16 val)
  868. {
  869. struct lan9303 *chip = ds->priv;
  870. int phy_base = chip->phy_addr_base;
  871. if (phy == phy_base)
  872. return lan9303_virt_phy_reg_write(chip, regnum, val);
  873. if (phy > phy_base + 2)
  874. return -ENODEV;
  875. return chip->ops->phy_write(chip, phy, regnum, val);
  876. }
  877. static void lan9303_adjust_link(struct dsa_switch *ds, int port,
  878. struct phy_device *phydev)
  879. {
  880. struct lan9303 *chip = ds->priv;
  881. int ctl, res;
  882. if (!phy_is_pseudo_fixed_link(phydev))
  883. return;
  884. ctl = lan9303_phy_read(ds, port, MII_BMCR);
  885. ctl &= ~BMCR_ANENABLE;
  886. if (phydev->speed == SPEED_100)
  887. ctl |= BMCR_SPEED100;
  888. else if (phydev->speed == SPEED_10)
  889. ctl &= ~BMCR_SPEED100;
  890. else
  891. dev_err(ds->dev, "unsupported speed: %d\n", phydev->speed);
  892. if (phydev->duplex == DUPLEX_FULL)
  893. ctl |= BMCR_FULLDPLX;
  894. else
  895. ctl &= ~BMCR_FULLDPLX;
  896. res = lan9303_phy_write(ds, port, MII_BMCR, ctl);
  897. if (port == chip->phy_addr_base) {
  898. /* Virtual Phy: Remove Turbo 200Mbit mode */
  899. lan9303_read(chip->regmap, LAN9303_VIRT_SPECIAL_CTRL, &ctl);
  900. ctl &= ~LAN9303_VIRT_SPECIAL_TURBO;
  901. res = regmap_write(chip->regmap,
  902. LAN9303_VIRT_SPECIAL_CTRL, ctl);
  903. }
  904. }
  905. static int lan9303_port_enable(struct dsa_switch *ds, int port,
  906. struct phy_device *phy)
  907. {
  908. struct lan9303 *chip = ds->priv;
  909. if (!dsa_is_user_port(ds, port))
  910. return 0;
  911. return lan9303_enable_processing_port(chip, port);
  912. }
  913. static void lan9303_port_disable(struct dsa_switch *ds, int port)
  914. {
  915. struct lan9303 *chip = ds->priv;
  916. if (!dsa_is_user_port(ds, port))
  917. return;
  918. lan9303_disable_processing_port(chip, port);
  919. lan9303_phy_write(ds, chip->phy_addr_base + port, MII_BMCR, BMCR_PDOWN);
  920. }
  921. static int lan9303_port_bridge_join(struct dsa_switch *ds, int port,
  922. struct net_device *br)
  923. {
  924. struct lan9303 *chip = ds->priv;
  925. dev_dbg(chip->dev, "%s(port %d)\n", __func__, port);
  926. if (dsa_to_port(ds, 1)->bridge_dev == dsa_to_port(ds, 2)->bridge_dev) {
  927. lan9303_bridge_ports(chip);
  928. chip->is_bridged = true; /* unleash stp_state_set() */
  929. }
  930. return 0;
  931. }
  932. static void lan9303_port_bridge_leave(struct dsa_switch *ds, int port,
  933. struct net_device *br)
  934. {
  935. struct lan9303 *chip = ds->priv;
  936. dev_dbg(chip->dev, "%s(port %d)\n", __func__, port);
  937. if (chip->is_bridged) {
  938. lan9303_separate_ports(chip);
  939. chip->is_bridged = false;
  940. }
  941. }
  942. static void lan9303_port_stp_state_set(struct dsa_switch *ds, int port,
  943. u8 state)
  944. {
  945. int portmask, portstate;
  946. struct lan9303 *chip = ds->priv;
  947. dev_dbg(chip->dev, "%s(port %d, state %d)\n",
  948. __func__, port, state);
  949. switch (state) {
  950. case BR_STATE_DISABLED:
  951. portstate = LAN9303_SWE_PORT_STATE_DISABLED_PORT0;
  952. break;
  953. case BR_STATE_BLOCKING:
  954. case BR_STATE_LISTENING:
  955. portstate = LAN9303_SWE_PORT_STATE_BLOCKING_PORT0;
  956. break;
  957. case BR_STATE_LEARNING:
  958. portstate = LAN9303_SWE_PORT_STATE_LEARNING_PORT0;
  959. break;
  960. case BR_STATE_FORWARDING:
  961. portstate = LAN9303_SWE_PORT_STATE_FORWARDING_PORT0;
  962. break;
  963. default:
  964. portstate = LAN9303_SWE_PORT_STATE_DISABLED_PORT0;
  965. dev_err(chip->dev, "unknown stp state: port %d, state %d\n",
  966. port, state);
  967. }
  968. portmask = 0x3 << (port * 2);
  969. portstate <<= (port * 2);
  970. chip->swe_port_state = (chip->swe_port_state & ~portmask) | portstate;
  971. if (chip->is_bridged)
  972. lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_STATE,
  973. chip->swe_port_state);
  974. /* else: touching SWE_PORT_STATE would break port separation */
  975. }
  976. static void lan9303_port_fast_age(struct dsa_switch *ds, int port)
  977. {
  978. struct lan9303 *chip = ds->priv;
  979. struct del_port_learned_ctx del_ctx = {
  980. .port = port,
  981. };
  982. dev_dbg(chip->dev, "%s(%d)\n", __func__, port);
  983. lan9303_alr_loop(chip, alr_loop_cb_del_port_learned, &del_ctx);
  984. }
  985. static int lan9303_port_fdb_add(struct dsa_switch *ds, int port,
  986. const unsigned char *addr, u16 vid)
  987. {
  988. struct lan9303 *chip = ds->priv;
  989. dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, addr, vid);
  990. if (vid)
  991. return -EOPNOTSUPP;
  992. return lan9303_alr_add_port(chip, addr, port, false);
  993. }
  994. static int lan9303_port_fdb_del(struct dsa_switch *ds, int port,
  995. const unsigned char *addr, u16 vid)
  996. {
  997. struct lan9303 *chip = ds->priv;
  998. dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, addr, vid);
  999. if (vid)
  1000. return -EOPNOTSUPP;
  1001. lan9303_alr_del_port(chip, addr, port);
  1002. return 0;
  1003. }
  1004. static int lan9303_port_fdb_dump(struct dsa_switch *ds, int port,
  1005. dsa_fdb_dump_cb_t *cb, void *data)
  1006. {
  1007. struct lan9303 *chip = ds->priv;
  1008. struct port_fdb_dump_ctx dump_ctx = {
  1009. .port = port,
  1010. .data = data,
  1011. .cb = cb,
  1012. };
  1013. dev_dbg(chip->dev, "%s(%d)\n", __func__, port);
  1014. return lan9303_alr_loop(chip, alr_loop_cb_fdb_port_dump, &dump_ctx);
  1015. }
  1016. static int lan9303_port_mdb_prepare(struct dsa_switch *ds, int port,
  1017. const struct switchdev_obj_port_mdb *mdb)
  1018. {
  1019. struct lan9303 *chip = ds->priv;
  1020. dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, mdb->addr,
  1021. mdb->vid);
  1022. if (mdb->vid)
  1023. return -EOPNOTSUPP;
  1024. if (lan9303_alr_cache_find_mac(chip, mdb->addr))
  1025. return 0;
  1026. if (!lan9303_alr_cache_find_free(chip))
  1027. return -ENOSPC;
  1028. return 0;
  1029. }
  1030. static void lan9303_port_mdb_add(struct dsa_switch *ds, int port,
  1031. const struct switchdev_obj_port_mdb *mdb)
  1032. {
  1033. struct lan9303 *chip = ds->priv;
  1034. dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, mdb->addr,
  1035. mdb->vid);
  1036. lan9303_alr_add_port(chip, mdb->addr, port, false);
  1037. }
  1038. static int lan9303_port_mdb_del(struct dsa_switch *ds, int port,
  1039. const struct switchdev_obj_port_mdb *mdb)
  1040. {
  1041. struct lan9303 *chip = ds->priv;
  1042. dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, mdb->addr,
  1043. mdb->vid);
  1044. if (mdb->vid)
  1045. return -EOPNOTSUPP;
  1046. lan9303_alr_del_port(chip, mdb->addr, port);
  1047. return 0;
  1048. }
  1049. static const struct dsa_switch_ops lan9303_switch_ops = {
  1050. .get_tag_protocol = lan9303_get_tag_protocol,
  1051. .setup = lan9303_setup,
  1052. .get_strings = lan9303_get_strings,
  1053. .phy_read = lan9303_phy_read,
  1054. .phy_write = lan9303_phy_write,
  1055. .adjust_link = lan9303_adjust_link,
  1056. .get_ethtool_stats = lan9303_get_ethtool_stats,
  1057. .get_sset_count = lan9303_get_sset_count,
  1058. .port_enable = lan9303_port_enable,
  1059. .port_disable = lan9303_port_disable,
  1060. .port_bridge_join = lan9303_port_bridge_join,
  1061. .port_bridge_leave = lan9303_port_bridge_leave,
  1062. .port_stp_state_set = lan9303_port_stp_state_set,
  1063. .port_fast_age = lan9303_port_fast_age,
  1064. .port_fdb_add = lan9303_port_fdb_add,
  1065. .port_fdb_del = lan9303_port_fdb_del,
  1066. .port_fdb_dump = lan9303_port_fdb_dump,
  1067. .port_mdb_prepare = lan9303_port_mdb_prepare,
  1068. .port_mdb_add = lan9303_port_mdb_add,
  1069. .port_mdb_del = lan9303_port_mdb_del,
  1070. };
  1071. static int lan9303_register_switch(struct lan9303 *chip)
  1072. {
  1073. int base;
  1074. chip->ds = dsa_switch_alloc(chip->dev, LAN9303_NUM_PORTS);
  1075. if (!chip->ds)
  1076. return -ENOMEM;
  1077. chip->ds->priv = chip;
  1078. chip->ds->ops = &lan9303_switch_ops;
  1079. base = chip->phy_addr_base;
  1080. chip->ds->phys_mii_mask = GENMASK(LAN9303_NUM_PORTS - 1 + base, base);
  1081. return dsa_register_switch(chip->ds);
  1082. }
  1083. static int lan9303_probe_reset_gpio(struct lan9303 *chip,
  1084. struct device_node *np)
  1085. {
  1086. chip->reset_gpio = devm_gpiod_get_optional(chip->dev, "reset",
  1087. GPIOD_OUT_LOW);
  1088. if (IS_ERR(chip->reset_gpio))
  1089. return PTR_ERR(chip->reset_gpio);
  1090. if (!chip->reset_gpio) {
  1091. dev_dbg(chip->dev, "No reset GPIO defined\n");
  1092. return 0;
  1093. }
  1094. chip->reset_duration = 200;
  1095. if (np) {
  1096. of_property_read_u32(np, "reset-duration",
  1097. &chip->reset_duration);
  1098. } else {
  1099. dev_dbg(chip->dev, "reset duration defaults to 200 ms\n");
  1100. }
  1101. /* A sane reset duration should not be longer than 1s */
  1102. if (chip->reset_duration > 1000)
  1103. chip->reset_duration = 1000;
  1104. return 0;
  1105. }
  1106. int lan9303_probe(struct lan9303 *chip, struct device_node *np)
  1107. {
  1108. int ret;
  1109. mutex_init(&chip->indirect_mutex);
  1110. mutex_init(&chip->alr_mutex);
  1111. ret = lan9303_probe_reset_gpio(chip, np);
  1112. if (ret)
  1113. return ret;
  1114. lan9303_handle_reset(chip);
  1115. ret = lan9303_check_device(chip);
  1116. if (ret)
  1117. return ret;
  1118. ret = lan9303_register_switch(chip);
  1119. if (ret) {
  1120. dev_dbg(chip->dev, "Failed to register switch: %d\n", ret);
  1121. return ret;
  1122. }
  1123. return 0;
  1124. }
  1125. EXPORT_SYMBOL(lan9303_probe);
  1126. int lan9303_remove(struct lan9303 *chip)
  1127. {
  1128. int rc;
  1129. rc = lan9303_disable_processing(chip);
  1130. if (rc != 0)
  1131. dev_warn(chip->dev, "shutting down failed\n");
  1132. dsa_unregister_switch(chip->ds);
  1133. /* assert reset to the whole device to prevent it from doing anything */
  1134. gpiod_set_value_cansleep(chip->reset_gpio, 1);
  1135. gpiod_unexport(chip->reset_gpio);
  1136. return 0;
  1137. }
  1138. EXPORT_SYMBOL(lan9303_remove);
  1139. MODULE_AUTHOR("Juergen Borleis <kernel@pengutronix.de>");
  1140. MODULE_DESCRIPTION("Core driver for SMSC/Microchip LAN9303 three port ethernet switch");
  1141. MODULE_LICENSE("GPL v2");