b53_serdes.h 4.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
  2. /*
  3. * Northstar Plus switch SerDes/SGMII PHY definitions
  4. *
  5. * Copyright (C) 2018 Florian Fainelli <f.fainelli@gmail.com>
  6. */
  7. #include <linux/phy.h>
  8. #include <linux/types.h>
  9. /* Non-standard page used to access SerDes PHY registers on NorthStar Plus */
  10. #define B53_SERDES_PAGE 0x16
  11. #define B53_SERDES_BLKADDR 0x3e
  12. #define B53_SERDES_LANE 0x3c
  13. #define B53_SERDES_ID0 0x20
  14. #define SERDES_ID0_MODEL_MASK 0x3f
  15. #define SERDES_ID0_REV_NUM_SHIFT 11
  16. #define SERDES_ID0_REV_NUM_MASK 0x7
  17. #define SERDES_ID0_REV_LETTER_SHIFT 14
  18. #define B53_SERDES_MII_REG(x) (0x20 + (x) * 2)
  19. #define B53_SERDES_DIGITAL_CONTROL(x) (0x1e + (x) * 2)
  20. #define B53_SERDES_DIGITAL_STATUS 0x28
  21. /* SERDES_DIGITAL_CONTROL1 */
  22. #define FIBER_MODE_1000X BIT(0)
  23. #define TBI_INTERFACE BIT(1)
  24. #define SIGNAL_DETECT_EN BIT(2)
  25. #define INVERT_SIGNAL_DETECT BIT(3)
  26. #define AUTODET_EN BIT(4)
  27. #define SGMII_MASTER_MODE BIT(5)
  28. #define DISABLE_DLL_PWRDOWN BIT(6)
  29. #define CRC_CHECKER_DIS BIT(7)
  30. #define COMMA_DET_EN BIT(8)
  31. #define ZERO_COMMA_DET_EN BIT(9)
  32. #define REMOTE_LOOPBACK BIT(10)
  33. #define SEL_RX_PKTS_FOR_CNTR BIT(11)
  34. #define MASTER_MDIO_PHY_SEL BIT(13)
  35. #define DISABLE_SIGNAL_DETECT_FLT BIT(14)
  36. /* SERDES_DIGITAL_CONTROL2 */
  37. #define EN_PARALLEL_DET BIT(0)
  38. #define DIS_FALSE_LINK BIT(1)
  39. #define FLT_FORCE_LINK BIT(2)
  40. #define EN_AUTONEG_ERR_TIMER BIT(3)
  41. #define DIS_REMOTE_FAULT_SENSING BIT(4)
  42. #define FORCE_XMIT_DATA BIT(5)
  43. #define AUTONEG_FAST_TIMERS BIT(6)
  44. #define DIS_CARRIER_EXTEND BIT(7)
  45. #define DIS_TRRR_GENERATION BIT(8)
  46. #define BYPASS_PCS_RX BIT(9)
  47. #define BYPASS_PCS_TX BIT(10)
  48. #define TEST_CNTR_EN BIT(11)
  49. #define TX_PACKET_SEQ_TEST BIT(12)
  50. #define TX_IDLE_JAM_SEQ_TEST BIT(13)
  51. #define CLR_BER_CNTR BIT(14)
  52. /* SERDES_DIGITAL_CONTROL3 */
  53. #define TX_FIFO_RST BIT(0)
  54. #define FIFO_ELAST_TX_RX_SHIFT 1
  55. #define FIFO_ELAST_TX_RX_5K 0
  56. #define FIFO_ELAST_TX_RX_10K 1
  57. #define FIFO_ELAST_TX_RX_13_5K 2
  58. #define FIFO_ELAST_TX_RX_18_5K 3
  59. #define BLOCK_TXEN_MODE BIT(9)
  60. #define JAM_FALSE_CARRIER_MODE BIT(10)
  61. #define EXT_PHY_CRS_MODE BIT(11)
  62. #define INVERT_EXT_PHY_CRS BIT(12)
  63. #define DISABLE_TX_CRS BIT(13)
  64. /* SERDES_DIGITAL_STATUS */
  65. #define SGMII_MODE BIT(0)
  66. #define LINK_STATUS BIT(1)
  67. #define DUPLEX_STATUS BIT(2)
  68. #define SPEED_STATUS_SHIFT 3
  69. #define SPEED_STATUS_10 0
  70. #define SPEED_STATUS_100 1
  71. #define SPEED_STATUS_1000 2
  72. #define SPEED_STATUS_2500 3
  73. #define SPEED_STATUS_MASK SPEED_STATUS_2500
  74. #define PAUSE_RESOLUTION_TX_SIDE BIT(5)
  75. #define PAUSE_RESOLUTION_RX_SIDE BIT(6)
  76. #define LINK_STATUS_CHANGE BIT(7)
  77. #define EARLY_END_EXT_DET BIT(8)
  78. #define CARRIER_EXT_ERR_DET BIT(9)
  79. #define RX_ERR_DET BIT(10)
  80. #define TX_ERR_DET BIT(11)
  81. #define CRC_ERR_DET BIT(12)
  82. #define FALSE_CARRIER_ERR_DET BIT(13)
  83. #define RXFIFO_ERR_DET BIT(14)
  84. #define TXFIFO_ERR_DET BIT(15)
  85. /* Block offsets */
  86. #define SERDES_DIGITAL_BLK 0x8300
  87. #define SERDES_ID0 0x8310
  88. #define SERDES_MII_BLK 0xffe0
  89. #define SERDES_XGXSBLK0_BLOCKADDRESS 0xffd0
  90. struct phylink_link_state;
  91. static inline u8 b53_serdes_map_lane(struct b53_device *dev, int port)
  92. {
  93. if (!dev->ops->serdes_map_lane)
  94. return B53_INVALID_LANE;
  95. return dev->ops->serdes_map_lane(dev, port);
  96. }
  97. int b53_serdes_get_link(struct b53_device *dev, int port);
  98. int b53_serdes_link_state(struct b53_device *dev, int port,
  99. struct phylink_link_state *state);
  100. void b53_serdes_config(struct b53_device *dev, int port, unsigned int mode,
  101. const struct phylink_link_state *state);
  102. void b53_serdes_an_restart(struct b53_device *dev, int port);
  103. void b53_serdes_link_set(struct b53_device *dev, int port, unsigned int mode,
  104. phy_interface_t interface, bool link_up);
  105. void b53_serdes_phylink_validate(struct b53_device *dev, int port,
  106. unsigned long *supported,
  107. struct phylink_link_state *state);
  108. #if IS_ENABLED(CONFIG_B53_SERDES)
  109. int b53_serdes_init(struct b53_device *dev, int port);
  110. #else
  111. static inline int b53_serdes_init(struct b53_device *dev, int port)
  112. {
  113. return -ENODEV;
  114. }
  115. #endif