c_can.h 6.3 KB

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  1. /*
  2. * CAN bus driver for Bosch C_CAN controller
  3. *
  4. * Copyright (C) 2010 ST Microelectronics
  5. * Bhupesh Sharma <bhupesh.sharma@st.com>
  6. *
  7. * Borrowed heavily from the C_CAN driver originally written by:
  8. * Copyright (C) 2007
  9. * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de>
  10. * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch>
  11. *
  12. * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B.
  13. * Bosch C_CAN user manual can be obtained from:
  14. * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/
  15. * users_manual_c_can.pdf
  16. *
  17. * This file is licensed under the terms of the GNU General Public
  18. * License version 2. This program is licensed "as is" without any
  19. * warranty of any kind, whether express or implied.
  20. */
  21. #ifndef C_CAN_H
  22. #define C_CAN_H
  23. /* message object split */
  24. #define C_CAN_NO_OF_OBJECTS 32
  25. #define C_CAN_MSG_OBJ_RX_NUM 16
  26. #define C_CAN_MSG_OBJ_TX_NUM 16
  27. #define C_CAN_MSG_OBJ_RX_FIRST 1
  28. #define C_CAN_MSG_OBJ_RX_LAST (C_CAN_MSG_OBJ_RX_FIRST + \
  29. C_CAN_MSG_OBJ_RX_NUM - 1)
  30. #define C_CAN_MSG_OBJ_TX_FIRST (C_CAN_MSG_OBJ_RX_LAST + 1)
  31. #define C_CAN_MSG_OBJ_TX_LAST (C_CAN_MSG_OBJ_TX_FIRST + \
  32. C_CAN_MSG_OBJ_TX_NUM - 1)
  33. #define C_CAN_MSG_OBJ_RX_SPLIT 9
  34. #define C_CAN_MSG_RX_LOW_LAST (C_CAN_MSG_OBJ_RX_SPLIT - 1)
  35. #define RECEIVE_OBJECT_BITS 0x0000ffff
  36. enum reg {
  37. C_CAN_CTRL_REG = 0,
  38. C_CAN_CTRL_EX_REG,
  39. C_CAN_STS_REG,
  40. C_CAN_ERR_CNT_REG,
  41. C_CAN_BTR_REG,
  42. C_CAN_INT_REG,
  43. C_CAN_TEST_REG,
  44. C_CAN_BRPEXT_REG,
  45. C_CAN_IF1_COMREQ_REG,
  46. C_CAN_IF1_COMMSK_REG,
  47. C_CAN_IF1_MASK1_REG,
  48. C_CAN_IF1_MASK2_REG,
  49. C_CAN_IF1_ARB1_REG,
  50. C_CAN_IF1_ARB2_REG,
  51. C_CAN_IF1_MSGCTRL_REG,
  52. C_CAN_IF1_DATA1_REG,
  53. C_CAN_IF1_DATA2_REG,
  54. C_CAN_IF1_DATA3_REG,
  55. C_CAN_IF1_DATA4_REG,
  56. C_CAN_IF2_COMREQ_REG,
  57. C_CAN_IF2_COMMSK_REG,
  58. C_CAN_IF2_MASK1_REG,
  59. C_CAN_IF2_MASK2_REG,
  60. C_CAN_IF2_ARB1_REG,
  61. C_CAN_IF2_ARB2_REG,
  62. C_CAN_IF2_MSGCTRL_REG,
  63. C_CAN_IF2_DATA1_REG,
  64. C_CAN_IF2_DATA2_REG,
  65. C_CAN_IF2_DATA3_REG,
  66. C_CAN_IF2_DATA4_REG,
  67. C_CAN_TXRQST1_REG,
  68. C_CAN_TXRQST2_REG,
  69. C_CAN_NEWDAT1_REG,
  70. C_CAN_NEWDAT2_REG,
  71. C_CAN_INTPND1_REG,
  72. C_CAN_INTPND2_REG,
  73. C_CAN_MSGVAL1_REG,
  74. C_CAN_MSGVAL2_REG,
  75. C_CAN_FUNCTION_REG,
  76. };
  77. static const u16 reg_map_c_can[] = {
  78. [C_CAN_CTRL_REG] = 0x00,
  79. [C_CAN_STS_REG] = 0x02,
  80. [C_CAN_ERR_CNT_REG] = 0x04,
  81. [C_CAN_BTR_REG] = 0x06,
  82. [C_CAN_INT_REG] = 0x08,
  83. [C_CAN_TEST_REG] = 0x0A,
  84. [C_CAN_BRPEXT_REG] = 0x0C,
  85. [C_CAN_IF1_COMREQ_REG] = 0x10,
  86. [C_CAN_IF1_COMMSK_REG] = 0x12,
  87. [C_CAN_IF1_MASK1_REG] = 0x14,
  88. [C_CAN_IF1_MASK2_REG] = 0x16,
  89. [C_CAN_IF1_ARB1_REG] = 0x18,
  90. [C_CAN_IF1_ARB2_REG] = 0x1A,
  91. [C_CAN_IF1_MSGCTRL_REG] = 0x1C,
  92. [C_CAN_IF1_DATA1_REG] = 0x1E,
  93. [C_CAN_IF1_DATA2_REG] = 0x20,
  94. [C_CAN_IF1_DATA3_REG] = 0x22,
  95. [C_CAN_IF1_DATA4_REG] = 0x24,
  96. [C_CAN_IF2_COMREQ_REG] = 0x40,
  97. [C_CAN_IF2_COMMSK_REG] = 0x42,
  98. [C_CAN_IF2_MASK1_REG] = 0x44,
  99. [C_CAN_IF2_MASK2_REG] = 0x46,
  100. [C_CAN_IF2_ARB1_REG] = 0x48,
  101. [C_CAN_IF2_ARB2_REG] = 0x4A,
  102. [C_CAN_IF2_MSGCTRL_REG] = 0x4C,
  103. [C_CAN_IF2_DATA1_REG] = 0x4E,
  104. [C_CAN_IF2_DATA2_REG] = 0x50,
  105. [C_CAN_IF2_DATA3_REG] = 0x52,
  106. [C_CAN_IF2_DATA4_REG] = 0x54,
  107. [C_CAN_TXRQST1_REG] = 0x80,
  108. [C_CAN_TXRQST2_REG] = 0x82,
  109. [C_CAN_NEWDAT1_REG] = 0x90,
  110. [C_CAN_NEWDAT2_REG] = 0x92,
  111. [C_CAN_INTPND1_REG] = 0xA0,
  112. [C_CAN_INTPND2_REG] = 0xA2,
  113. [C_CAN_MSGVAL1_REG] = 0xB0,
  114. [C_CAN_MSGVAL2_REG] = 0xB2,
  115. };
  116. static const u16 reg_map_d_can[] = {
  117. [C_CAN_CTRL_REG] = 0x00,
  118. [C_CAN_CTRL_EX_REG] = 0x02,
  119. [C_CAN_STS_REG] = 0x04,
  120. [C_CAN_ERR_CNT_REG] = 0x08,
  121. [C_CAN_BTR_REG] = 0x0C,
  122. [C_CAN_BRPEXT_REG] = 0x0E,
  123. [C_CAN_INT_REG] = 0x10,
  124. [C_CAN_TEST_REG] = 0x14,
  125. [C_CAN_FUNCTION_REG] = 0x18,
  126. [C_CAN_TXRQST1_REG] = 0x88,
  127. [C_CAN_TXRQST2_REG] = 0x8A,
  128. [C_CAN_NEWDAT1_REG] = 0x9C,
  129. [C_CAN_NEWDAT2_REG] = 0x9E,
  130. [C_CAN_INTPND1_REG] = 0xB0,
  131. [C_CAN_INTPND2_REG] = 0xB2,
  132. [C_CAN_MSGVAL1_REG] = 0xC4,
  133. [C_CAN_MSGVAL2_REG] = 0xC6,
  134. [C_CAN_IF1_COMREQ_REG] = 0x100,
  135. [C_CAN_IF1_COMMSK_REG] = 0x102,
  136. [C_CAN_IF1_MASK1_REG] = 0x104,
  137. [C_CAN_IF1_MASK2_REG] = 0x106,
  138. [C_CAN_IF1_ARB1_REG] = 0x108,
  139. [C_CAN_IF1_ARB2_REG] = 0x10A,
  140. [C_CAN_IF1_MSGCTRL_REG] = 0x10C,
  141. [C_CAN_IF1_DATA1_REG] = 0x110,
  142. [C_CAN_IF1_DATA2_REG] = 0x112,
  143. [C_CAN_IF1_DATA3_REG] = 0x114,
  144. [C_CAN_IF1_DATA4_REG] = 0x116,
  145. [C_CAN_IF2_COMREQ_REG] = 0x120,
  146. [C_CAN_IF2_COMMSK_REG] = 0x122,
  147. [C_CAN_IF2_MASK1_REG] = 0x124,
  148. [C_CAN_IF2_MASK2_REG] = 0x126,
  149. [C_CAN_IF2_ARB1_REG] = 0x128,
  150. [C_CAN_IF2_ARB2_REG] = 0x12A,
  151. [C_CAN_IF2_MSGCTRL_REG] = 0x12C,
  152. [C_CAN_IF2_DATA1_REG] = 0x130,
  153. [C_CAN_IF2_DATA2_REG] = 0x132,
  154. [C_CAN_IF2_DATA3_REG] = 0x134,
  155. [C_CAN_IF2_DATA4_REG] = 0x136,
  156. };
  157. enum c_can_dev_id {
  158. BOSCH_C_CAN_PLATFORM,
  159. BOSCH_C_CAN,
  160. BOSCH_D_CAN,
  161. };
  162. struct raminit_bits {
  163. u8 start;
  164. u8 done;
  165. };
  166. struct c_can_driver_data {
  167. enum c_can_dev_id id;
  168. /* RAMINIT register description. Optional. */
  169. const struct raminit_bits *raminit_bits; /* Array of START/DONE bit positions */
  170. u8 raminit_num; /* Number of CAN instances on the SoC */
  171. bool raminit_pulse; /* If set, sets and clears START bit (pulse) */
  172. };
  173. /* Out of band RAMINIT register access via syscon regmap */
  174. struct c_can_raminit {
  175. struct regmap *syscon; /* for raminit ctrl. reg. access */
  176. unsigned int reg; /* register index within syscon */
  177. struct raminit_bits bits;
  178. bool needs_pulse;
  179. };
  180. /* c_can private data structure */
  181. struct c_can_priv {
  182. struct can_priv can; /* must be the first member */
  183. struct napi_struct napi;
  184. struct net_device *dev;
  185. struct device *device;
  186. atomic_t tx_active;
  187. atomic_t sie_pending;
  188. unsigned long tx_dir;
  189. int last_status;
  190. u16 (*read_reg) (const struct c_can_priv *priv, enum reg index);
  191. void (*write_reg) (const struct c_can_priv *priv, enum reg index, u16 val);
  192. u32 (*read_reg32) (const struct c_can_priv *priv, enum reg index);
  193. void (*write_reg32) (const struct c_can_priv *priv, enum reg index, u32 val);
  194. void __iomem *base;
  195. const u16 *regs;
  196. void *priv; /* for board-specific data */
  197. enum c_can_dev_id type;
  198. struct c_can_raminit raminit_sys; /* RAMINIT via syscon regmap */
  199. void (*raminit) (const struct c_can_priv *priv, bool enable);
  200. u32 comm_rcv_high;
  201. u32 rxmasked;
  202. u32 dlc[C_CAN_MSG_OBJ_TX_NUM];
  203. };
  204. struct net_device *alloc_c_can_dev(void);
  205. void free_c_can_dev(struct net_device *dev);
  206. int register_c_can_dev(struct net_device *dev);
  207. void unregister_c_can_dev(struct net_device *dev);
  208. #ifdef CONFIG_PM
  209. int c_can_power_up(struct net_device *dev);
  210. int c_can_power_down(struct net_device *dev);
  211. #endif
  212. #endif /* C_CAN_H */