stv090x.c 138 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. STV0900/0903 Multistandard Broadcast Frontend driver
  4. Copyright (C) Manu Abraham <abraham.manu@gmail.com>
  5. Copyright (C) ST Microelectronics
  6. */
  7. #include <linux/init.h>
  8. #include <linux/kernel.h>
  9. #include <linux/module.h>
  10. #include <linux/string.h>
  11. #include <linux/slab.h>
  12. #include <linux/mutex.h>
  13. #include <linux/dvb/frontend.h>
  14. #include <media/dvb_frontend.h>
  15. #include "stv6110x.h" /* for demodulator internal modes */
  16. #include "stv090x_reg.h"
  17. #include "stv090x.h"
  18. #include "stv090x_priv.h"
  19. /* Max transfer size done by I2C transfer functions */
  20. #define MAX_XFER_SIZE 64
  21. static unsigned int verbose;
  22. module_param(verbose, int, 0644);
  23. /* internal params node */
  24. struct stv090x_dev {
  25. /* pointer for internal params, one for each pair of demods */
  26. struct stv090x_internal *internal;
  27. struct stv090x_dev *next_dev;
  28. };
  29. /* first internal params */
  30. static struct stv090x_dev *stv090x_first_dev;
  31. /* find chip by i2c adapter and i2c address */
  32. static struct stv090x_dev *find_dev(struct i2c_adapter *i2c_adap,
  33. u8 i2c_addr)
  34. {
  35. struct stv090x_dev *temp_dev = stv090x_first_dev;
  36. /*
  37. Search of the last stv0900 chip or
  38. find it by i2c adapter and i2c address */
  39. while ((temp_dev != NULL) &&
  40. ((temp_dev->internal->i2c_adap != i2c_adap) ||
  41. (temp_dev->internal->i2c_addr != i2c_addr))) {
  42. temp_dev = temp_dev->next_dev;
  43. }
  44. return temp_dev;
  45. }
  46. /* deallocating chip */
  47. static void remove_dev(struct stv090x_internal *internal)
  48. {
  49. struct stv090x_dev *prev_dev = stv090x_first_dev;
  50. struct stv090x_dev *del_dev = find_dev(internal->i2c_adap,
  51. internal->i2c_addr);
  52. if (del_dev != NULL) {
  53. if (del_dev == stv090x_first_dev) {
  54. stv090x_first_dev = del_dev->next_dev;
  55. } else {
  56. while (prev_dev->next_dev != del_dev)
  57. prev_dev = prev_dev->next_dev;
  58. prev_dev->next_dev = del_dev->next_dev;
  59. }
  60. kfree(del_dev);
  61. }
  62. }
  63. /* allocating new chip */
  64. static struct stv090x_dev *append_internal(struct stv090x_internal *internal)
  65. {
  66. struct stv090x_dev *new_dev;
  67. struct stv090x_dev *temp_dev;
  68. new_dev = kmalloc(sizeof(struct stv090x_dev), GFP_KERNEL);
  69. if (new_dev != NULL) {
  70. new_dev->internal = internal;
  71. new_dev->next_dev = NULL;
  72. /* append to list */
  73. if (stv090x_first_dev == NULL) {
  74. stv090x_first_dev = new_dev;
  75. } else {
  76. temp_dev = stv090x_first_dev;
  77. while (temp_dev->next_dev != NULL)
  78. temp_dev = temp_dev->next_dev;
  79. temp_dev->next_dev = new_dev;
  80. }
  81. }
  82. return new_dev;
  83. }
  84. /* DVBS1 and DSS C/N Lookup table */
  85. static const struct stv090x_tab stv090x_s1cn_tab[] = {
  86. { 0, 8917 }, /* 0.0dB */
  87. { 5, 8801 }, /* 0.5dB */
  88. { 10, 8667 }, /* 1.0dB */
  89. { 15, 8522 }, /* 1.5dB */
  90. { 20, 8355 }, /* 2.0dB */
  91. { 25, 8175 }, /* 2.5dB */
  92. { 30, 7979 }, /* 3.0dB */
  93. { 35, 7763 }, /* 3.5dB */
  94. { 40, 7530 }, /* 4.0dB */
  95. { 45, 7282 }, /* 4.5dB */
  96. { 50, 7026 }, /* 5.0dB */
  97. { 55, 6781 }, /* 5.5dB */
  98. { 60, 6514 }, /* 6.0dB */
  99. { 65, 6241 }, /* 6.5dB */
  100. { 70, 5965 }, /* 7.0dB */
  101. { 75, 5690 }, /* 7.5dB */
  102. { 80, 5424 }, /* 8.0dB */
  103. { 85, 5161 }, /* 8.5dB */
  104. { 90, 4902 }, /* 9.0dB */
  105. { 95, 4654 }, /* 9.5dB */
  106. { 100, 4417 }, /* 10.0dB */
  107. { 105, 4186 }, /* 10.5dB */
  108. { 110, 3968 }, /* 11.0dB */
  109. { 115, 3757 }, /* 11.5dB */
  110. { 120, 3558 }, /* 12.0dB */
  111. { 125, 3366 }, /* 12.5dB */
  112. { 130, 3185 }, /* 13.0dB */
  113. { 135, 3012 }, /* 13.5dB */
  114. { 140, 2850 }, /* 14.0dB */
  115. { 145, 2698 }, /* 14.5dB */
  116. { 150, 2550 }, /* 15.0dB */
  117. { 160, 2283 }, /* 16.0dB */
  118. { 170, 2042 }, /* 17.0dB */
  119. { 180, 1827 }, /* 18.0dB */
  120. { 190, 1636 }, /* 19.0dB */
  121. { 200, 1466 }, /* 20.0dB */
  122. { 210, 1315 }, /* 21.0dB */
  123. { 220, 1181 }, /* 22.0dB */
  124. { 230, 1064 }, /* 23.0dB */
  125. { 240, 960 }, /* 24.0dB */
  126. { 250, 869 }, /* 25.0dB */
  127. { 260, 792 }, /* 26.0dB */
  128. { 270, 724 }, /* 27.0dB */
  129. { 280, 665 }, /* 28.0dB */
  130. { 290, 616 }, /* 29.0dB */
  131. { 300, 573 }, /* 30.0dB */
  132. { 310, 537 }, /* 31.0dB */
  133. { 320, 507 }, /* 32.0dB */
  134. { 330, 483 }, /* 33.0dB */
  135. { 400, 398 }, /* 40.0dB */
  136. { 450, 381 }, /* 45.0dB */
  137. { 500, 377 } /* 50.0dB */
  138. };
  139. /* DVBS2 C/N Lookup table */
  140. static const struct stv090x_tab stv090x_s2cn_tab[] = {
  141. { -30, 13348 }, /* -3.0dB */
  142. { -20, 12640 }, /* -2d.0B */
  143. { -10, 11883 }, /* -1.0dB */
  144. { 0, 11101 }, /* -0.0dB */
  145. { 5, 10718 }, /* 0.5dB */
  146. { 10, 10339 }, /* 1.0dB */
  147. { 15, 9947 }, /* 1.5dB */
  148. { 20, 9552 }, /* 2.0dB */
  149. { 25, 9183 }, /* 2.5dB */
  150. { 30, 8799 }, /* 3.0dB */
  151. { 35, 8422 }, /* 3.5dB */
  152. { 40, 8062 }, /* 4.0dB */
  153. { 45, 7707 }, /* 4.5dB */
  154. { 50, 7353 }, /* 5.0dB */
  155. { 55, 7025 }, /* 5.5dB */
  156. { 60, 6684 }, /* 6.0dB */
  157. { 65, 6331 }, /* 6.5dB */
  158. { 70, 6036 }, /* 7.0dB */
  159. { 75, 5727 }, /* 7.5dB */
  160. { 80, 5437 }, /* 8.0dB */
  161. { 85, 5164 }, /* 8.5dB */
  162. { 90, 4902 }, /* 9.0dB */
  163. { 95, 4653 }, /* 9.5dB */
  164. { 100, 4408 }, /* 10.0dB */
  165. { 105, 4187 }, /* 10.5dB */
  166. { 110, 3961 }, /* 11.0dB */
  167. { 115, 3751 }, /* 11.5dB */
  168. { 120, 3558 }, /* 12.0dB */
  169. { 125, 3368 }, /* 12.5dB */
  170. { 130, 3191 }, /* 13.0dB */
  171. { 135, 3017 }, /* 13.5dB */
  172. { 140, 2862 }, /* 14.0dB */
  173. { 145, 2710 }, /* 14.5dB */
  174. { 150, 2565 }, /* 15.0dB */
  175. { 160, 2300 }, /* 16.0dB */
  176. { 170, 2058 }, /* 17.0dB */
  177. { 180, 1849 }, /* 18.0dB */
  178. { 190, 1663 }, /* 19.0dB */
  179. { 200, 1495 }, /* 20.0dB */
  180. { 210, 1349 }, /* 21.0dB */
  181. { 220, 1222 }, /* 22.0dB */
  182. { 230, 1110 }, /* 23.0dB */
  183. { 240, 1011 }, /* 24.0dB */
  184. { 250, 925 }, /* 25.0dB */
  185. { 260, 853 }, /* 26.0dB */
  186. { 270, 789 }, /* 27.0dB */
  187. { 280, 734 }, /* 28.0dB */
  188. { 290, 690 }, /* 29.0dB */
  189. { 300, 650 }, /* 30.0dB */
  190. { 310, 619 }, /* 31.0dB */
  191. { 320, 593 }, /* 32.0dB */
  192. { 330, 571 }, /* 33.0dB */
  193. { 400, 498 }, /* 40.0dB */
  194. { 450, 484 }, /* 45.0dB */
  195. { 500, 481 } /* 50.0dB */
  196. };
  197. /* RF level C/N lookup table */
  198. static const struct stv090x_tab stv090x_rf_tab[] = {
  199. { -5, 0xcaa1 }, /* -5dBm */
  200. { -10, 0xc229 }, /* -10dBm */
  201. { -15, 0xbb08 }, /* -15dBm */
  202. { -20, 0xb4bc }, /* -20dBm */
  203. { -25, 0xad5a }, /* -25dBm */
  204. { -30, 0xa298 }, /* -30dBm */
  205. { -35, 0x98a8 }, /* -35dBm */
  206. { -40, 0x8389 }, /* -40dBm */
  207. { -45, 0x59be }, /* -45dBm */
  208. { -50, 0x3a14 }, /* -50dBm */
  209. { -55, 0x2d11 }, /* -55dBm */
  210. { -60, 0x210d }, /* -60dBm */
  211. { -65, 0xa14f }, /* -65dBm */
  212. { -70, 0x07aa } /* -70dBm */
  213. };
  214. static struct stv090x_reg stv0900_initval[] = {
  215. { STV090x_OUTCFG, 0x00 },
  216. { STV090x_MODECFG, 0xff },
  217. { STV090x_AGCRF1CFG, 0x11 },
  218. { STV090x_AGCRF2CFG, 0x13 },
  219. { STV090x_TSGENERAL1X, 0x14 },
  220. { STV090x_TSTTNR2, 0x21 },
  221. { STV090x_TSTTNR4, 0x21 },
  222. { STV090x_P2_DISTXCTL, 0x22 },
  223. { STV090x_P2_F22TX, 0xc0 },
  224. { STV090x_P2_F22RX, 0xc0 },
  225. { STV090x_P2_DISRXCTL, 0x00 },
  226. { STV090x_P2_DMDCFGMD, 0xF9 },
  227. { STV090x_P2_DEMOD, 0x08 },
  228. { STV090x_P2_DMDCFG3, 0xc4 },
  229. { STV090x_P2_CARFREQ, 0xed },
  230. { STV090x_P2_LDT, 0xd0 },
  231. { STV090x_P2_LDT2, 0xb8 },
  232. { STV090x_P2_TMGCFG, 0xd2 },
  233. { STV090x_P2_TMGTHRISE, 0x20 },
  234. { STV090x_P1_TMGCFG, 0xd2 },
  235. { STV090x_P2_TMGTHFALL, 0x00 },
  236. { STV090x_P2_FECSPY, 0x88 },
  237. { STV090x_P2_FSPYDATA, 0x3a },
  238. { STV090x_P2_FBERCPT4, 0x00 },
  239. { STV090x_P2_FSPYBER, 0x10 },
  240. { STV090x_P2_ERRCTRL1, 0x35 },
  241. { STV090x_P2_ERRCTRL2, 0xc1 },
  242. { STV090x_P2_CFRICFG, 0xf8 },
  243. { STV090x_P2_NOSCFG, 0x1c },
  244. { STV090x_P2_DMDTOM, 0x20 },
  245. { STV090x_P2_CORRELMANT, 0x70 },
  246. { STV090x_P2_CORRELABS, 0x88 },
  247. { STV090x_P2_AGC2O, 0x5b },
  248. { STV090x_P2_AGC2REF, 0x38 },
  249. { STV090x_P2_CARCFG, 0xe4 },
  250. { STV090x_P2_ACLC, 0x1A },
  251. { STV090x_P2_BCLC, 0x09 },
  252. { STV090x_P2_CARHDR, 0x08 },
  253. { STV090x_P2_KREFTMG, 0xc1 },
  254. { STV090x_P2_SFRUPRATIO, 0xf0 },
  255. { STV090x_P2_SFRLOWRATIO, 0x70 },
  256. { STV090x_P2_SFRSTEP, 0x58 },
  257. { STV090x_P2_TMGCFG2, 0x01 },
  258. { STV090x_P2_CAR2CFG, 0x26 },
  259. { STV090x_P2_BCLC2S2Q, 0x86 },
  260. { STV090x_P2_BCLC2S28, 0x86 },
  261. { STV090x_P2_SMAPCOEF7, 0x77 },
  262. { STV090x_P2_SMAPCOEF6, 0x85 },
  263. { STV090x_P2_SMAPCOEF5, 0x77 },
  264. { STV090x_P2_TSCFGL, 0x20 },
  265. { STV090x_P2_DMDCFG2, 0x3b },
  266. { STV090x_P2_MODCODLST0, 0xff },
  267. { STV090x_P2_MODCODLST1, 0xff },
  268. { STV090x_P2_MODCODLST2, 0xff },
  269. { STV090x_P2_MODCODLST3, 0xff },
  270. { STV090x_P2_MODCODLST4, 0xff },
  271. { STV090x_P2_MODCODLST5, 0xff },
  272. { STV090x_P2_MODCODLST6, 0xff },
  273. { STV090x_P2_MODCODLST7, 0xcc },
  274. { STV090x_P2_MODCODLST8, 0xcc },
  275. { STV090x_P2_MODCODLST9, 0xcc },
  276. { STV090x_P2_MODCODLSTA, 0xcc },
  277. { STV090x_P2_MODCODLSTB, 0xcc },
  278. { STV090x_P2_MODCODLSTC, 0xcc },
  279. { STV090x_P2_MODCODLSTD, 0xcc },
  280. { STV090x_P2_MODCODLSTE, 0xcc },
  281. { STV090x_P2_MODCODLSTF, 0xcf },
  282. { STV090x_P1_DISTXCTL, 0x22 },
  283. { STV090x_P1_F22TX, 0xc0 },
  284. { STV090x_P1_F22RX, 0xc0 },
  285. { STV090x_P1_DISRXCTL, 0x00 },
  286. { STV090x_P1_DMDCFGMD, 0xf9 },
  287. { STV090x_P1_DEMOD, 0x08 },
  288. { STV090x_P1_DMDCFG3, 0xc4 },
  289. { STV090x_P1_DMDTOM, 0x20 },
  290. { STV090x_P1_CARFREQ, 0xed },
  291. { STV090x_P1_LDT, 0xd0 },
  292. { STV090x_P1_LDT2, 0xb8 },
  293. { STV090x_P1_TMGCFG, 0xd2 },
  294. { STV090x_P1_TMGTHRISE, 0x20 },
  295. { STV090x_P1_TMGTHFALL, 0x00 },
  296. { STV090x_P1_SFRUPRATIO, 0xf0 },
  297. { STV090x_P1_SFRLOWRATIO, 0x70 },
  298. { STV090x_P1_TSCFGL, 0x20 },
  299. { STV090x_P1_FECSPY, 0x88 },
  300. { STV090x_P1_FSPYDATA, 0x3a },
  301. { STV090x_P1_FBERCPT4, 0x00 },
  302. { STV090x_P1_FSPYBER, 0x10 },
  303. { STV090x_P1_ERRCTRL1, 0x35 },
  304. { STV090x_P1_ERRCTRL2, 0xc1 },
  305. { STV090x_P1_CFRICFG, 0xf8 },
  306. { STV090x_P1_NOSCFG, 0x1c },
  307. { STV090x_P1_CORRELMANT, 0x70 },
  308. { STV090x_P1_CORRELABS, 0x88 },
  309. { STV090x_P1_AGC2O, 0x5b },
  310. { STV090x_P1_AGC2REF, 0x38 },
  311. { STV090x_P1_CARCFG, 0xe4 },
  312. { STV090x_P1_ACLC, 0x1A },
  313. { STV090x_P1_BCLC, 0x09 },
  314. { STV090x_P1_CARHDR, 0x08 },
  315. { STV090x_P1_KREFTMG, 0xc1 },
  316. { STV090x_P1_SFRSTEP, 0x58 },
  317. { STV090x_P1_TMGCFG2, 0x01 },
  318. { STV090x_P1_CAR2CFG, 0x26 },
  319. { STV090x_P1_BCLC2S2Q, 0x86 },
  320. { STV090x_P1_BCLC2S28, 0x86 },
  321. { STV090x_P1_SMAPCOEF7, 0x77 },
  322. { STV090x_P1_SMAPCOEF6, 0x85 },
  323. { STV090x_P1_SMAPCOEF5, 0x77 },
  324. { STV090x_P1_DMDCFG2, 0x3b },
  325. { STV090x_P1_MODCODLST0, 0xff },
  326. { STV090x_P1_MODCODLST1, 0xff },
  327. { STV090x_P1_MODCODLST2, 0xff },
  328. { STV090x_P1_MODCODLST3, 0xff },
  329. { STV090x_P1_MODCODLST4, 0xff },
  330. { STV090x_P1_MODCODLST5, 0xff },
  331. { STV090x_P1_MODCODLST6, 0xff },
  332. { STV090x_P1_MODCODLST7, 0xcc },
  333. { STV090x_P1_MODCODLST8, 0xcc },
  334. { STV090x_P1_MODCODLST9, 0xcc },
  335. { STV090x_P1_MODCODLSTA, 0xcc },
  336. { STV090x_P1_MODCODLSTB, 0xcc },
  337. { STV090x_P1_MODCODLSTC, 0xcc },
  338. { STV090x_P1_MODCODLSTD, 0xcc },
  339. { STV090x_P1_MODCODLSTE, 0xcc },
  340. { STV090x_P1_MODCODLSTF, 0xcf },
  341. { STV090x_GENCFG, 0x1d },
  342. { STV090x_NBITER_NF4, 0x37 },
  343. { STV090x_NBITER_NF5, 0x29 },
  344. { STV090x_NBITER_NF6, 0x37 },
  345. { STV090x_NBITER_NF7, 0x33 },
  346. { STV090x_NBITER_NF8, 0x31 },
  347. { STV090x_NBITER_NF9, 0x2f },
  348. { STV090x_NBITER_NF10, 0x39 },
  349. { STV090x_NBITER_NF11, 0x3a },
  350. { STV090x_NBITER_NF12, 0x29 },
  351. { STV090x_NBITER_NF13, 0x37 },
  352. { STV090x_NBITER_NF14, 0x33 },
  353. { STV090x_NBITER_NF15, 0x2f },
  354. { STV090x_NBITER_NF16, 0x39 },
  355. { STV090x_NBITER_NF17, 0x3a },
  356. { STV090x_NBITERNOERR, 0x04 },
  357. { STV090x_GAINLLR_NF4, 0x0C },
  358. { STV090x_GAINLLR_NF5, 0x0F },
  359. { STV090x_GAINLLR_NF6, 0x11 },
  360. { STV090x_GAINLLR_NF7, 0x14 },
  361. { STV090x_GAINLLR_NF8, 0x17 },
  362. { STV090x_GAINLLR_NF9, 0x19 },
  363. { STV090x_GAINLLR_NF10, 0x20 },
  364. { STV090x_GAINLLR_NF11, 0x21 },
  365. { STV090x_GAINLLR_NF12, 0x0D },
  366. { STV090x_GAINLLR_NF13, 0x0F },
  367. { STV090x_GAINLLR_NF14, 0x13 },
  368. { STV090x_GAINLLR_NF15, 0x1A },
  369. { STV090x_GAINLLR_NF16, 0x1F },
  370. { STV090x_GAINLLR_NF17, 0x21 },
  371. { STV090x_RCCFGH, 0x20 },
  372. { STV090x_P1_FECM, 0x01 }, /* disable DSS modes */
  373. { STV090x_P2_FECM, 0x01 }, /* disable DSS modes */
  374. { STV090x_P1_PRVIT, 0x2F }, /* disable PR 6/7 */
  375. { STV090x_P2_PRVIT, 0x2F }, /* disable PR 6/7 */
  376. };
  377. static struct stv090x_reg stv0903_initval[] = {
  378. { STV090x_OUTCFG, 0x00 },
  379. { STV090x_AGCRF1CFG, 0x11 },
  380. { STV090x_STOPCLK1, 0x48 },
  381. { STV090x_STOPCLK2, 0x14 },
  382. { STV090x_TSTTNR1, 0x27 },
  383. { STV090x_TSTTNR2, 0x21 },
  384. { STV090x_P1_DISTXCTL, 0x22 },
  385. { STV090x_P1_F22TX, 0xc0 },
  386. { STV090x_P1_F22RX, 0xc0 },
  387. { STV090x_P1_DISRXCTL, 0x00 },
  388. { STV090x_P1_DMDCFGMD, 0xF9 },
  389. { STV090x_P1_DEMOD, 0x08 },
  390. { STV090x_P1_DMDCFG3, 0xc4 },
  391. { STV090x_P1_CARFREQ, 0xed },
  392. { STV090x_P1_TNRCFG2, 0x82 },
  393. { STV090x_P1_LDT, 0xd0 },
  394. { STV090x_P1_LDT2, 0xb8 },
  395. { STV090x_P1_TMGCFG, 0xd2 },
  396. { STV090x_P1_TMGTHRISE, 0x20 },
  397. { STV090x_P1_TMGTHFALL, 0x00 },
  398. { STV090x_P1_SFRUPRATIO, 0xf0 },
  399. { STV090x_P1_SFRLOWRATIO, 0x70 },
  400. { STV090x_P1_TSCFGL, 0x20 },
  401. { STV090x_P1_FECSPY, 0x88 },
  402. { STV090x_P1_FSPYDATA, 0x3a },
  403. { STV090x_P1_FBERCPT4, 0x00 },
  404. { STV090x_P1_FSPYBER, 0x10 },
  405. { STV090x_P1_ERRCTRL1, 0x35 },
  406. { STV090x_P1_ERRCTRL2, 0xc1 },
  407. { STV090x_P1_CFRICFG, 0xf8 },
  408. { STV090x_P1_NOSCFG, 0x1c },
  409. { STV090x_P1_DMDTOM, 0x20 },
  410. { STV090x_P1_CORRELMANT, 0x70 },
  411. { STV090x_P1_CORRELABS, 0x88 },
  412. { STV090x_P1_AGC2O, 0x5b },
  413. { STV090x_P1_AGC2REF, 0x38 },
  414. { STV090x_P1_CARCFG, 0xe4 },
  415. { STV090x_P1_ACLC, 0x1A },
  416. { STV090x_P1_BCLC, 0x09 },
  417. { STV090x_P1_CARHDR, 0x08 },
  418. { STV090x_P1_KREFTMG, 0xc1 },
  419. { STV090x_P1_SFRSTEP, 0x58 },
  420. { STV090x_P1_TMGCFG2, 0x01 },
  421. { STV090x_P1_CAR2CFG, 0x26 },
  422. { STV090x_P1_BCLC2S2Q, 0x86 },
  423. { STV090x_P1_BCLC2S28, 0x86 },
  424. { STV090x_P1_SMAPCOEF7, 0x77 },
  425. { STV090x_P1_SMAPCOEF6, 0x85 },
  426. { STV090x_P1_SMAPCOEF5, 0x77 },
  427. { STV090x_P1_DMDCFG2, 0x3b },
  428. { STV090x_P1_MODCODLST0, 0xff },
  429. { STV090x_P1_MODCODLST1, 0xff },
  430. { STV090x_P1_MODCODLST2, 0xff },
  431. { STV090x_P1_MODCODLST3, 0xff },
  432. { STV090x_P1_MODCODLST4, 0xff },
  433. { STV090x_P1_MODCODLST5, 0xff },
  434. { STV090x_P1_MODCODLST6, 0xff },
  435. { STV090x_P1_MODCODLST7, 0xcc },
  436. { STV090x_P1_MODCODLST8, 0xcc },
  437. { STV090x_P1_MODCODLST9, 0xcc },
  438. { STV090x_P1_MODCODLSTA, 0xcc },
  439. { STV090x_P1_MODCODLSTB, 0xcc },
  440. { STV090x_P1_MODCODLSTC, 0xcc },
  441. { STV090x_P1_MODCODLSTD, 0xcc },
  442. { STV090x_P1_MODCODLSTE, 0xcc },
  443. { STV090x_P1_MODCODLSTF, 0xcf },
  444. { STV090x_GENCFG, 0x1c },
  445. { STV090x_NBITER_NF4, 0x37 },
  446. { STV090x_NBITER_NF5, 0x29 },
  447. { STV090x_NBITER_NF6, 0x37 },
  448. { STV090x_NBITER_NF7, 0x33 },
  449. { STV090x_NBITER_NF8, 0x31 },
  450. { STV090x_NBITER_NF9, 0x2f },
  451. { STV090x_NBITER_NF10, 0x39 },
  452. { STV090x_NBITER_NF11, 0x3a },
  453. { STV090x_NBITER_NF12, 0x29 },
  454. { STV090x_NBITER_NF13, 0x37 },
  455. { STV090x_NBITER_NF14, 0x33 },
  456. { STV090x_NBITER_NF15, 0x2f },
  457. { STV090x_NBITER_NF16, 0x39 },
  458. { STV090x_NBITER_NF17, 0x3a },
  459. { STV090x_NBITERNOERR, 0x04 },
  460. { STV090x_GAINLLR_NF4, 0x0C },
  461. { STV090x_GAINLLR_NF5, 0x0F },
  462. { STV090x_GAINLLR_NF6, 0x11 },
  463. { STV090x_GAINLLR_NF7, 0x14 },
  464. { STV090x_GAINLLR_NF8, 0x17 },
  465. { STV090x_GAINLLR_NF9, 0x19 },
  466. { STV090x_GAINLLR_NF10, 0x20 },
  467. { STV090x_GAINLLR_NF11, 0x21 },
  468. { STV090x_GAINLLR_NF12, 0x0D },
  469. { STV090x_GAINLLR_NF13, 0x0F },
  470. { STV090x_GAINLLR_NF14, 0x13 },
  471. { STV090x_GAINLLR_NF15, 0x1A },
  472. { STV090x_GAINLLR_NF16, 0x1F },
  473. { STV090x_GAINLLR_NF17, 0x21 },
  474. { STV090x_RCCFGH, 0x20 },
  475. { STV090x_P1_FECM, 0x01 }, /*disable the DSS mode */
  476. { STV090x_P1_PRVIT, 0x2f } /*disable puncture rate 6/7*/
  477. };
  478. static struct stv090x_reg stv0900_cut20_val[] = {
  479. { STV090x_P2_DMDCFG3, 0xe8 },
  480. { STV090x_P2_DMDCFG4, 0x10 },
  481. { STV090x_P2_CARFREQ, 0x38 },
  482. { STV090x_P2_CARHDR, 0x20 },
  483. { STV090x_P2_KREFTMG, 0x5a },
  484. { STV090x_P2_SMAPCOEF7, 0x06 },
  485. { STV090x_P2_SMAPCOEF6, 0x00 },
  486. { STV090x_P2_SMAPCOEF5, 0x04 },
  487. { STV090x_P2_NOSCFG, 0x0c },
  488. { STV090x_P1_DMDCFG3, 0xe8 },
  489. { STV090x_P1_DMDCFG4, 0x10 },
  490. { STV090x_P1_CARFREQ, 0x38 },
  491. { STV090x_P1_CARHDR, 0x20 },
  492. { STV090x_P1_KREFTMG, 0x5a },
  493. { STV090x_P1_SMAPCOEF7, 0x06 },
  494. { STV090x_P1_SMAPCOEF6, 0x00 },
  495. { STV090x_P1_SMAPCOEF5, 0x04 },
  496. { STV090x_P1_NOSCFG, 0x0c },
  497. { STV090x_GAINLLR_NF4, 0x21 },
  498. { STV090x_GAINLLR_NF5, 0x21 },
  499. { STV090x_GAINLLR_NF6, 0x20 },
  500. { STV090x_GAINLLR_NF7, 0x1F },
  501. { STV090x_GAINLLR_NF8, 0x1E },
  502. { STV090x_GAINLLR_NF9, 0x1E },
  503. { STV090x_GAINLLR_NF10, 0x1D },
  504. { STV090x_GAINLLR_NF11, 0x1B },
  505. { STV090x_GAINLLR_NF12, 0x20 },
  506. { STV090x_GAINLLR_NF13, 0x20 },
  507. { STV090x_GAINLLR_NF14, 0x20 },
  508. { STV090x_GAINLLR_NF15, 0x20 },
  509. { STV090x_GAINLLR_NF16, 0x20 },
  510. { STV090x_GAINLLR_NF17, 0x21 },
  511. };
  512. static struct stv090x_reg stv0903_cut20_val[] = {
  513. { STV090x_P1_DMDCFG3, 0xe8 },
  514. { STV090x_P1_DMDCFG4, 0x10 },
  515. { STV090x_P1_CARFREQ, 0x38 },
  516. { STV090x_P1_CARHDR, 0x20 },
  517. { STV090x_P1_KREFTMG, 0x5a },
  518. { STV090x_P1_SMAPCOEF7, 0x06 },
  519. { STV090x_P1_SMAPCOEF6, 0x00 },
  520. { STV090x_P1_SMAPCOEF5, 0x04 },
  521. { STV090x_P1_NOSCFG, 0x0c },
  522. { STV090x_GAINLLR_NF4, 0x21 },
  523. { STV090x_GAINLLR_NF5, 0x21 },
  524. { STV090x_GAINLLR_NF6, 0x20 },
  525. { STV090x_GAINLLR_NF7, 0x1F },
  526. { STV090x_GAINLLR_NF8, 0x1E },
  527. { STV090x_GAINLLR_NF9, 0x1E },
  528. { STV090x_GAINLLR_NF10, 0x1D },
  529. { STV090x_GAINLLR_NF11, 0x1B },
  530. { STV090x_GAINLLR_NF12, 0x20 },
  531. { STV090x_GAINLLR_NF13, 0x20 },
  532. { STV090x_GAINLLR_NF14, 0x20 },
  533. { STV090x_GAINLLR_NF15, 0x20 },
  534. { STV090x_GAINLLR_NF16, 0x20 },
  535. { STV090x_GAINLLR_NF17, 0x21 }
  536. };
  537. /* Cut 2.0 Long Frame Tracking CR loop */
  538. static struct stv090x_long_frame_crloop stv090x_s2_crl_cut20[] = {
  539. /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
  540. { STV090x_QPSK_12, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x1e },
  541. { STV090x_QPSK_35, 0x2f, 0x3f, 0x2e, 0x2f, 0x3d, 0x0f, 0x0e, 0x2e, 0x3d, 0x0e },
  542. { STV090x_QPSK_23, 0x2f, 0x3f, 0x2e, 0x2f, 0x0e, 0x0f, 0x0e, 0x1e, 0x3d, 0x3d },
  543. { STV090x_QPSK_34, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
  544. { STV090x_QPSK_45, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
  545. { STV090x_QPSK_56, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
  546. { STV090x_QPSK_89, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
  547. { STV090x_QPSK_910, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
  548. { STV090x_8PSK_35, 0x3c, 0x3e, 0x1c, 0x2e, 0x0c, 0x1e, 0x2b, 0x2d, 0x1b, 0x1d },
  549. { STV090x_8PSK_23, 0x1d, 0x3e, 0x3c, 0x2e, 0x2c, 0x1e, 0x0c, 0x2d, 0x2b, 0x1d },
  550. { STV090x_8PSK_34, 0x0e, 0x3e, 0x3d, 0x2e, 0x0d, 0x1e, 0x2c, 0x2d, 0x0c, 0x1d },
  551. { STV090x_8PSK_56, 0x2e, 0x3e, 0x1e, 0x2e, 0x2d, 0x1e, 0x3c, 0x2d, 0x2c, 0x1d },
  552. { STV090x_8PSK_89, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x0d, 0x2d, 0x3c, 0x1d },
  553. { STV090x_8PSK_910, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x1d, 0x2d, 0x0d, 0x1d }
  554. };
  555. /* Cut 3.0 Long Frame Tracking CR loop */
  556. static struct stv090x_long_frame_crloop stv090x_s2_crl_cut30[] = {
  557. /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
  558. { STV090x_QPSK_12, 0x3c, 0x2c, 0x0c, 0x2c, 0x1b, 0x2c, 0x1b, 0x1c, 0x0b, 0x3b },
  559. { STV090x_QPSK_35, 0x0d, 0x0d, 0x0c, 0x0d, 0x1b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b },
  560. { STV090x_QPSK_23, 0x1d, 0x0d, 0x0c, 0x1d, 0x2b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b },
  561. { STV090x_QPSK_34, 0x1d, 0x1d, 0x0c, 0x1d, 0x2b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b },
  562. { STV090x_QPSK_45, 0x2d, 0x1d, 0x1c, 0x1d, 0x2b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
  563. { STV090x_QPSK_56, 0x2d, 0x1d, 0x1c, 0x1d, 0x2b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
  564. { STV090x_QPSK_89, 0x3d, 0x2d, 0x1c, 0x1d, 0x3b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
  565. { STV090x_QPSK_910, 0x3d, 0x2d, 0x1c, 0x1d, 0x3b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
  566. { STV090x_8PSK_35, 0x39, 0x29, 0x39, 0x19, 0x19, 0x19, 0x19, 0x19, 0x09, 0x19 },
  567. { STV090x_8PSK_23, 0x2a, 0x39, 0x1a, 0x0a, 0x39, 0x0a, 0x29, 0x39, 0x29, 0x0a },
  568. { STV090x_8PSK_34, 0x2b, 0x3a, 0x1b, 0x1b, 0x3a, 0x1b, 0x1a, 0x0b, 0x1a, 0x3a },
  569. { STV090x_8PSK_56, 0x0c, 0x1b, 0x3b, 0x3b, 0x1b, 0x3b, 0x3a, 0x3b, 0x3a, 0x1b },
  570. { STV090x_8PSK_89, 0x0d, 0x3c, 0x2c, 0x2c, 0x2b, 0x0c, 0x0b, 0x3b, 0x0b, 0x1b },
  571. { STV090x_8PSK_910, 0x0d, 0x0d, 0x2c, 0x3c, 0x3b, 0x1c, 0x0b, 0x3b, 0x0b, 0x1b }
  572. };
  573. /* Cut 2.0 Long Frame Tracking CR Loop */
  574. static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut20[] = {
  575. /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
  576. { STV090x_16APSK_23, 0x0c, 0x0c, 0x0c, 0x0c, 0x1d, 0x0c, 0x3c, 0x0c, 0x2c, 0x0c },
  577. { STV090x_16APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0e, 0x0c, 0x2d, 0x0c, 0x1d, 0x0c },
  578. { STV090x_16APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c },
  579. { STV090x_16APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c },
  580. { STV090x_16APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c },
  581. { STV090x_16APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c },
  582. { STV090x_32APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
  583. { STV090x_32APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
  584. { STV090x_32APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
  585. { STV090x_32APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
  586. { STV090x_32APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }
  587. };
  588. /* Cut 3.0 Long Frame Tracking CR Loop */
  589. static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut30[] = {
  590. /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
  591. { STV090x_16APSK_23, 0x0a, 0x0a, 0x0a, 0x0a, 0x1a, 0x0a, 0x3a, 0x0a, 0x2a, 0x0a },
  592. { STV090x_16APSK_34, 0x0a, 0x0a, 0x0a, 0x0a, 0x0b, 0x0a, 0x3b, 0x0a, 0x1b, 0x0a },
  593. { STV090x_16APSK_45, 0x0a, 0x0a, 0x0a, 0x0a, 0x1b, 0x0a, 0x3b, 0x0a, 0x2b, 0x0a },
  594. { STV090x_16APSK_56, 0x0a, 0x0a, 0x0a, 0x0a, 0x1b, 0x0a, 0x3b, 0x0a, 0x2b, 0x0a },
  595. { STV090x_16APSK_89, 0x0a, 0x0a, 0x0a, 0x0a, 0x2b, 0x0a, 0x0c, 0x0a, 0x3b, 0x0a },
  596. { STV090x_16APSK_910, 0x0a, 0x0a, 0x0a, 0x0a, 0x2b, 0x0a, 0x0c, 0x0a, 0x3b, 0x0a },
  597. { STV090x_32APSK_34, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
  598. { STV090x_32APSK_45, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
  599. { STV090x_32APSK_56, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
  600. { STV090x_32APSK_89, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
  601. { STV090x_32APSK_910, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a }
  602. };
  603. static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut20[] = {
  604. /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
  605. { STV090x_QPSK_14, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x2d, 0x1f, 0x3d, 0x3e },
  606. { STV090x_QPSK_13, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x3d, 0x0f, 0x3d, 0x2e },
  607. { STV090x_QPSK_25, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x2e }
  608. };
  609. static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut30[] = {
  610. /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
  611. { STV090x_QPSK_14, 0x0c, 0x3c, 0x0b, 0x3c, 0x2a, 0x2c, 0x2a, 0x1c, 0x3a, 0x3b },
  612. { STV090x_QPSK_13, 0x0c, 0x3c, 0x0b, 0x3c, 0x2a, 0x2c, 0x3a, 0x0c, 0x3a, 0x2b },
  613. { STV090x_QPSK_25, 0x1c, 0x3c, 0x1b, 0x3c, 0x3a, 0x1c, 0x3a, 0x3b, 0x3a, 0x2b }
  614. };
  615. /* Cut 2.0 Short Frame Tracking CR Loop */
  616. static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut20[] = {
  617. /* MODCOD 2M 5M 10M 20M 30M */
  618. { STV090x_QPSK, 0x2f, 0x2e, 0x0e, 0x0e, 0x3d },
  619. { STV090x_8PSK, 0x3e, 0x0e, 0x2d, 0x0d, 0x3c },
  620. { STV090x_16APSK, 0x1e, 0x1e, 0x1e, 0x3d, 0x2d },
  621. { STV090x_32APSK, 0x1e, 0x1e, 0x1e, 0x3d, 0x2d }
  622. };
  623. /* Cut 3.0 Short Frame Tracking CR Loop */
  624. static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut30[] = {
  625. /* MODCOD 2M 5M 10M 20M 30M */
  626. { STV090x_QPSK, 0x2C, 0x2B, 0x0B, 0x0B, 0x3A },
  627. { STV090x_8PSK, 0x3B, 0x0B, 0x2A, 0x0A, 0x39 },
  628. { STV090x_16APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A },
  629. { STV090x_32APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A }
  630. };
  631. static inline s32 comp2(s32 __x, s32 __width)
  632. {
  633. if (__width == 32)
  634. return __x;
  635. else
  636. return (__x >= (1 << (__width - 1))) ? (__x - (1 << __width)) : __x;
  637. }
  638. static int stv090x_read_reg(struct stv090x_state *state, unsigned int reg)
  639. {
  640. const struct stv090x_config *config = state->config;
  641. int ret;
  642. u8 b0[] = { reg >> 8, reg & 0xff };
  643. u8 buf;
  644. struct i2c_msg msg[] = {
  645. { .addr = config->address, .flags = 0, .buf = b0, .len = 2 },
  646. { .addr = config->address, .flags = I2C_M_RD, .buf = &buf, .len = 1 }
  647. };
  648. ret = i2c_transfer(state->i2c, msg, 2);
  649. if (ret != 2) {
  650. if (ret != -ERESTARTSYS)
  651. dprintk(FE_ERROR, 1,
  652. "Read error, Reg=[0x%02x], Status=%d",
  653. reg, ret);
  654. return ret < 0 ? ret : -EREMOTEIO;
  655. }
  656. if (unlikely(*state->verbose >= FE_DEBUGREG))
  657. dprintk(FE_ERROR, 1, "Reg=[0x%02x], data=%02x",
  658. reg, buf);
  659. return (unsigned int) buf;
  660. }
  661. static int stv090x_write_regs(struct stv090x_state *state, unsigned int reg, u8 *data, u32 count)
  662. {
  663. const struct stv090x_config *config = state->config;
  664. int ret;
  665. u8 buf[MAX_XFER_SIZE];
  666. struct i2c_msg i2c_msg = { .addr = config->address, .flags = 0, .buf = buf, .len = 2 + count };
  667. if (2 + count > sizeof(buf)) {
  668. printk(KERN_WARNING
  669. "%s: i2c wr reg=%04x: len=%d is too big!\n",
  670. KBUILD_MODNAME, reg, count);
  671. return -EINVAL;
  672. }
  673. buf[0] = reg >> 8;
  674. buf[1] = reg & 0xff;
  675. memcpy(&buf[2], data, count);
  676. dprintk(FE_DEBUGREG, 1, "%s [0x%04x]: %*ph",
  677. __func__, reg, count, data);
  678. ret = i2c_transfer(state->i2c, &i2c_msg, 1);
  679. if (ret != 1) {
  680. if (ret != -ERESTARTSYS)
  681. dprintk(FE_ERROR, 1, "Reg=[0x%04x], Data=[0x%02x ...], Count=%u, Status=%d",
  682. reg, data[0], count, ret);
  683. return ret < 0 ? ret : -EREMOTEIO;
  684. }
  685. return 0;
  686. }
  687. static int stv090x_write_reg(struct stv090x_state *state, unsigned int reg, u8 data)
  688. {
  689. u8 tmp = data; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
  690. return stv090x_write_regs(state, reg, &tmp, 1);
  691. }
  692. static int stv090x_i2c_gate_ctrl(struct stv090x_state *state, int enable)
  693. {
  694. u32 reg;
  695. /*
  696. * NOTE! A lock is used as a FSM to control the state in which
  697. * access is serialized between two tuners on the same demod.
  698. * This has nothing to do with a lock to protect a critical section
  699. * which may in some other cases be confused with protecting I/O
  700. * access to the demodulator gate.
  701. * In case of any error, the lock is unlocked and exit within the
  702. * relevant operations themselves.
  703. */
  704. if (enable) {
  705. if (state->config->tuner_i2c_lock)
  706. state->config->tuner_i2c_lock(&state->frontend, 1);
  707. else
  708. mutex_lock(&state->internal->tuner_lock);
  709. }
  710. reg = STV090x_READ_DEMOD(state, I2CRPT);
  711. if (enable) {
  712. dprintk(FE_DEBUG, 1, "Enable Gate");
  713. STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 1);
  714. if (STV090x_WRITE_DEMOD(state, I2CRPT, reg) < 0)
  715. goto err;
  716. } else {
  717. dprintk(FE_DEBUG, 1, "Disable Gate");
  718. STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 0);
  719. if ((STV090x_WRITE_DEMOD(state, I2CRPT, reg)) < 0)
  720. goto err;
  721. }
  722. if (!enable) {
  723. if (state->config->tuner_i2c_lock)
  724. state->config->tuner_i2c_lock(&state->frontend, 0);
  725. else
  726. mutex_unlock(&state->internal->tuner_lock);
  727. }
  728. return 0;
  729. err:
  730. dprintk(FE_ERROR, 1, "I/O error");
  731. if (state->config->tuner_i2c_lock)
  732. state->config->tuner_i2c_lock(&state->frontend, 0);
  733. else
  734. mutex_unlock(&state->internal->tuner_lock);
  735. return -1;
  736. }
  737. static void stv090x_get_lock_tmg(struct stv090x_state *state)
  738. {
  739. switch (state->algo) {
  740. case STV090x_BLIND_SEARCH:
  741. dprintk(FE_DEBUG, 1, "Blind Search");
  742. if (state->srate <= 1500000) { /*10Msps< SR <=15Msps*/
  743. state->DemodTimeout = 1500;
  744. state->FecTimeout = 400;
  745. } else if (state->srate <= 5000000) { /*10Msps< SR <=15Msps*/
  746. state->DemodTimeout = 1000;
  747. state->FecTimeout = 300;
  748. } else { /*SR >20Msps*/
  749. state->DemodTimeout = 700;
  750. state->FecTimeout = 100;
  751. }
  752. break;
  753. case STV090x_COLD_SEARCH:
  754. case STV090x_WARM_SEARCH:
  755. default:
  756. dprintk(FE_DEBUG, 1, "Normal Search");
  757. if (state->srate <= 1000000) { /*SR <=1Msps*/
  758. state->DemodTimeout = 4500;
  759. state->FecTimeout = 1700;
  760. } else if (state->srate <= 2000000) { /*1Msps < SR <= 2Msps */
  761. state->DemodTimeout = 2500;
  762. state->FecTimeout = 1100;
  763. } else if (state->srate <= 5000000) { /*2Msps < SR <= 5Msps */
  764. state->DemodTimeout = 1000;
  765. state->FecTimeout = 550;
  766. } else if (state->srate <= 10000000) { /*5Msps < SR <= 10Msps */
  767. state->DemodTimeout = 700;
  768. state->FecTimeout = 250;
  769. } else if (state->srate <= 20000000) { /*10Msps < SR <= 20Msps */
  770. state->DemodTimeout = 400;
  771. state->FecTimeout = 130;
  772. } else { /*SR >20Msps*/
  773. state->DemodTimeout = 300;
  774. state->FecTimeout = 100;
  775. }
  776. break;
  777. }
  778. if (state->algo == STV090x_WARM_SEARCH)
  779. state->DemodTimeout /= 2;
  780. }
  781. static int stv090x_set_srate(struct stv090x_state *state, u32 srate)
  782. {
  783. u32 sym;
  784. if (srate > 60000000) {
  785. sym = (srate << 4); /* SR * 2^16 / master_clk */
  786. sym /= (state->internal->mclk >> 12);
  787. } else if (srate > 6000000) {
  788. sym = (srate << 6);
  789. sym /= (state->internal->mclk >> 10);
  790. } else {
  791. sym = (srate << 9);
  792. sym /= (state->internal->mclk >> 7);
  793. }
  794. if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0x7f) < 0) /* MSB */
  795. goto err;
  796. if (STV090x_WRITE_DEMOD(state, SFRINIT0, (sym & 0xff)) < 0) /* LSB */
  797. goto err;
  798. return 0;
  799. err:
  800. dprintk(FE_ERROR, 1, "I/O error");
  801. return -1;
  802. }
  803. static int stv090x_set_max_srate(struct stv090x_state *state, u32 clk, u32 srate)
  804. {
  805. u32 sym;
  806. srate = 105 * (srate / 100);
  807. if (srate > 60000000) {
  808. sym = (srate << 4); /* SR * 2^16 / master_clk */
  809. sym /= (state->internal->mclk >> 12);
  810. } else if (srate > 6000000) {
  811. sym = (srate << 6);
  812. sym /= (state->internal->mclk >> 10);
  813. } else {
  814. sym = (srate << 9);
  815. sym /= (state->internal->mclk >> 7);
  816. }
  817. if (sym < 0x7fff) {
  818. if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0) /* MSB */
  819. goto err;
  820. if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0) /* LSB */
  821. goto err;
  822. } else {
  823. if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x7f) < 0) /* MSB */
  824. goto err;
  825. if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xff) < 0) /* LSB */
  826. goto err;
  827. }
  828. return 0;
  829. err:
  830. dprintk(FE_ERROR, 1, "I/O error");
  831. return -1;
  832. }
  833. static int stv090x_set_min_srate(struct stv090x_state *state, u32 clk, u32 srate)
  834. {
  835. u32 sym;
  836. srate = 95 * (srate / 100);
  837. if (srate > 60000000) {
  838. sym = (srate << 4); /* SR * 2^16 / master_clk */
  839. sym /= (state->internal->mclk >> 12);
  840. } else if (srate > 6000000) {
  841. sym = (srate << 6);
  842. sym /= (state->internal->mclk >> 10);
  843. } else {
  844. sym = (srate << 9);
  845. sym /= (state->internal->mclk >> 7);
  846. }
  847. if (STV090x_WRITE_DEMOD(state, SFRLOW1, ((sym >> 8) & 0x7f)) < 0) /* MSB */
  848. goto err;
  849. if (STV090x_WRITE_DEMOD(state, SFRLOW0, (sym & 0xff)) < 0) /* LSB */
  850. goto err;
  851. return 0;
  852. err:
  853. dprintk(FE_ERROR, 1, "I/O error");
  854. return -1;
  855. }
  856. static u32 stv090x_car_width(u32 srate, enum stv090x_rolloff rolloff)
  857. {
  858. u32 ro;
  859. switch (rolloff) {
  860. case STV090x_RO_20:
  861. ro = 20;
  862. break;
  863. case STV090x_RO_25:
  864. ro = 25;
  865. break;
  866. case STV090x_RO_35:
  867. default:
  868. ro = 35;
  869. break;
  870. }
  871. return srate + (srate * ro) / 100;
  872. }
  873. static int stv090x_set_vit_thacq(struct stv090x_state *state)
  874. {
  875. if (STV090x_WRITE_DEMOD(state, VTH12, 0x96) < 0)
  876. goto err;
  877. if (STV090x_WRITE_DEMOD(state, VTH23, 0x64) < 0)
  878. goto err;
  879. if (STV090x_WRITE_DEMOD(state, VTH34, 0x36) < 0)
  880. goto err;
  881. if (STV090x_WRITE_DEMOD(state, VTH56, 0x23) < 0)
  882. goto err;
  883. if (STV090x_WRITE_DEMOD(state, VTH67, 0x1e) < 0)
  884. goto err;
  885. if (STV090x_WRITE_DEMOD(state, VTH78, 0x19) < 0)
  886. goto err;
  887. return 0;
  888. err:
  889. dprintk(FE_ERROR, 1, "I/O error");
  890. return -1;
  891. }
  892. static int stv090x_set_vit_thtracq(struct stv090x_state *state)
  893. {
  894. if (STV090x_WRITE_DEMOD(state, VTH12, 0xd0) < 0)
  895. goto err;
  896. if (STV090x_WRITE_DEMOD(state, VTH23, 0x7d) < 0)
  897. goto err;
  898. if (STV090x_WRITE_DEMOD(state, VTH34, 0x53) < 0)
  899. goto err;
  900. if (STV090x_WRITE_DEMOD(state, VTH56, 0x2f) < 0)
  901. goto err;
  902. if (STV090x_WRITE_DEMOD(state, VTH67, 0x24) < 0)
  903. goto err;
  904. if (STV090x_WRITE_DEMOD(state, VTH78, 0x1f) < 0)
  905. goto err;
  906. return 0;
  907. err:
  908. dprintk(FE_ERROR, 1, "I/O error");
  909. return -1;
  910. }
  911. static int stv090x_set_viterbi(struct stv090x_state *state)
  912. {
  913. switch (state->search_mode) {
  914. case STV090x_SEARCH_AUTO:
  915. if (STV090x_WRITE_DEMOD(state, FECM, 0x10) < 0) /* DVB-S and DVB-S2 */
  916. goto err;
  917. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x3f) < 0) /* all puncture rate */
  918. goto err;
  919. break;
  920. case STV090x_SEARCH_DVBS1:
  921. if (STV090x_WRITE_DEMOD(state, FECM, 0x00) < 0) /* disable DSS */
  922. goto err;
  923. switch (state->fec) {
  924. case STV090x_PR12:
  925. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
  926. goto err;
  927. break;
  928. case STV090x_PR23:
  929. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
  930. goto err;
  931. break;
  932. case STV090x_PR34:
  933. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x04) < 0)
  934. goto err;
  935. break;
  936. case STV090x_PR56:
  937. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x08) < 0)
  938. goto err;
  939. break;
  940. case STV090x_PR78:
  941. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x20) < 0)
  942. goto err;
  943. break;
  944. default:
  945. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x2f) < 0) /* all */
  946. goto err;
  947. break;
  948. }
  949. break;
  950. case STV090x_SEARCH_DSS:
  951. if (STV090x_WRITE_DEMOD(state, FECM, 0x80) < 0)
  952. goto err;
  953. switch (state->fec) {
  954. case STV090x_PR12:
  955. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
  956. goto err;
  957. break;
  958. case STV090x_PR23:
  959. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
  960. goto err;
  961. break;
  962. case STV090x_PR67:
  963. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x10) < 0)
  964. goto err;
  965. break;
  966. default:
  967. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x13) < 0) /* 1/2, 2/3, 6/7 */
  968. goto err;
  969. break;
  970. }
  971. break;
  972. default:
  973. break;
  974. }
  975. return 0;
  976. err:
  977. dprintk(FE_ERROR, 1, "I/O error");
  978. return -1;
  979. }
  980. static int stv090x_stop_modcod(struct stv090x_state *state)
  981. {
  982. if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
  983. goto err;
  984. if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0)
  985. goto err;
  986. if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0)
  987. goto err;
  988. if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0)
  989. goto err;
  990. if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0)
  991. goto err;
  992. if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0)
  993. goto err;
  994. if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0)
  995. goto err;
  996. if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xff) < 0)
  997. goto err;
  998. if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xff) < 0)
  999. goto err;
  1000. if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xff) < 0)
  1001. goto err;
  1002. if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xff) < 0)
  1003. goto err;
  1004. if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xff) < 0)
  1005. goto err;
  1006. if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xff) < 0)
  1007. goto err;
  1008. if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xff) < 0)
  1009. goto err;
  1010. if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0)
  1011. goto err;
  1012. if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xff) < 0)
  1013. goto err;
  1014. return 0;
  1015. err:
  1016. dprintk(FE_ERROR, 1, "I/O error");
  1017. return -1;
  1018. }
  1019. static int stv090x_activate_modcod(struct stv090x_state *state)
  1020. {
  1021. if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
  1022. goto err;
  1023. if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xfc) < 0)
  1024. goto err;
  1025. if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xcc) < 0)
  1026. goto err;
  1027. if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xcc) < 0)
  1028. goto err;
  1029. if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xcc) < 0)
  1030. goto err;
  1031. if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xcc) < 0)
  1032. goto err;
  1033. if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xcc) < 0)
  1034. goto err;
  1035. if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0)
  1036. goto err;
  1037. if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0)
  1038. goto err;
  1039. if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0)
  1040. goto err;
  1041. if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0)
  1042. goto err;
  1043. if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0)
  1044. goto err;
  1045. if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0)
  1046. goto err;
  1047. if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0)
  1048. goto err;
  1049. if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xcc) < 0)
  1050. goto err;
  1051. if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0)
  1052. goto err;
  1053. return 0;
  1054. err:
  1055. dprintk(FE_ERROR, 1, "I/O error");
  1056. return -1;
  1057. }
  1058. static int stv090x_activate_modcod_single(struct stv090x_state *state)
  1059. {
  1060. if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
  1061. goto err;
  1062. if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xf0) < 0)
  1063. goto err;
  1064. if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0x00) < 0)
  1065. goto err;
  1066. if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0x00) < 0)
  1067. goto err;
  1068. if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0x00) < 0)
  1069. goto err;
  1070. if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0x00) < 0)
  1071. goto err;
  1072. if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0x00) < 0)
  1073. goto err;
  1074. if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0x00) < 0)
  1075. goto err;
  1076. if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0x00) < 0)
  1077. goto err;
  1078. if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0x00) < 0)
  1079. goto err;
  1080. if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0x00) < 0)
  1081. goto err;
  1082. if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0x00) < 0)
  1083. goto err;
  1084. if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0x00) < 0)
  1085. goto err;
  1086. if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0x00) < 0)
  1087. goto err;
  1088. if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0x00) < 0)
  1089. goto err;
  1090. if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0x0f) < 0)
  1091. goto err;
  1092. return 0;
  1093. err:
  1094. dprintk(FE_ERROR, 1, "I/O error");
  1095. return -1;
  1096. }
  1097. static int stv090x_vitclk_ctl(struct stv090x_state *state, int enable)
  1098. {
  1099. u32 reg;
  1100. switch (state->demod) {
  1101. case STV090x_DEMODULATOR_0:
  1102. mutex_lock(&state->internal->demod_lock);
  1103. reg = stv090x_read_reg(state, STV090x_STOPCLK2);
  1104. STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, enable);
  1105. if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
  1106. goto err;
  1107. mutex_unlock(&state->internal->demod_lock);
  1108. break;
  1109. case STV090x_DEMODULATOR_1:
  1110. mutex_lock(&state->internal->demod_lock);
  1111. reg = stv090x_read_reg(state, STV090x_STOPCLK2);
  1112. STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, enable);
  1113. if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
  1114. goto err;
  1115. mutex_unlock(&state->internal->demod_lock);
  1116. break;
  1117. default:
  1118. dprintk(FE_ERROR, 1, "Wrong demodulator!");
  1119. break;
  1120. }
  1121. return 0;
  1122. err:
  1123. mutex_unlock(&state->internal->demod_lock);
  1124. dprintk(FE_ERROR, 1, "I/O error");
  1125. return -1;
  1126. }
  1127. static int stv090x_dvbs_track_crl(struct stv090x_state *state)
  1128. {
  1129. if (state->internal->dev_ver >= 0x30) {
  1130. /* Set ACLC BCLC optimised value vs SR */
  1131. if (state->srate >= 15000000) {
  1132. if (STV090x_WRITE_DEMOD(state, ACLC, 0x2b) < 0)
  1133. goto err;
  1134. if (STV090x_WRITE_DEMOD(state, BCLC, 0x1a) < 0)
  1135. goto err;
  1136. } else if ((state->srate >= 7000000) && (15000000 > state->srate)) {
  1137. if (STV090x_WRITE_DEMOD(state, ACLC, 0x0c) < 0)
  1138. goto err;
  1139. if (STV090x_WRITE_DEMOD(state, BCLC, 0x1b) < 0)
  1140. goto err;
  1141. } else if (state->srate < 7000000) {
  1142. if (STV090x_WRITE_DEMOD(state, ACLC, 0x2c) < 0)
  1143. goto err;
  1144. if (STV090x_WRITE_DEMOD(state, BCLC, 0x1c) < 0)
  1145. goto err;
  1146. }
  1147. } else {
  1148. /* Cut 2.0 */
  1149. if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0)
  1150. goto err;
  1151. if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
  1152. goto err;
  1153. }
  1154. return 0;
  1155. err:
  1156. dprintk(FE_ERROR, 1, "I/O error");
  1157. return -1;
  1158. }
  1159. static int stv090x_delivery_search(struct stv090x_state *state)
  1160. {
  1161. u32 reg;
  1162. switch (state->search_mode) {
  1163. case STV090x_SEARCH_DVBS1:
  1164. case STV090x_SEARCH_DSS:
  1165. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1166. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
  1167. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
  1168. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1169. goto err;
  1170. /* Activate Viterbi decoder in legacy search,
  1171. * do not use FRESVIT1, might impact VITERBI2
  1172. */
  1173. if (stv090x_vitclk_ctl(state, 0) < 0)
  1174. goto err;
  1175. if (stv090x_dvbs_track_crl(state) < 0)
  1176. goto err;
  1177. if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x22) < 0) /* disable DVB-S2 */
  1178. goto err;
  1179. if (stv090x_set_vit_thacq(state) < 0)
  1180. goto err;
  1181. if (stv090x_set_viterbi(state) < 0)
  1182. goto err;
  1183. break;
  1184. case STV090x_SEARCH_DVBS2:
  1185. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1186. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
  1187. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
  1188. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1189. goto err;
  1190. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
  1191. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
  1192. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1193. goto err;
  1194. if (stv090x_vitclk_ctl(state, 1) < 0)
  1195. goto err;
  1196. if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0) /* stop DVB-S CR loop */
  1197. goto err;
  1198. if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
  1199. goto err;
  1200. if (state->internal->dev_ver <= 0x20) {
  1201. /* enable S2 carrier loop */
  1202. if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
  1203. goto err;
  1204. } else {
  1205. /* > Cut 3: Stop carrier 3 */
  1206. if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0)
  1207. goto err;
  1208. }
  1209. if (state->demod_mode != STV090x_SINGLE) {
  1210. /* Cut 2: enable link during search */
  1211. if (stv090x_activate_modcod(state) < 0)
  1212. goto err;
  1213. } else {
  1214. /* Single demodulator
  1215. * Authorize SHORT and LONG frames,
  1216. * QPSK, 8PSK, 16APSK and 32APSK
  1217. */
  1218. if (stv090x_activate_modcod_single(state) < 0)
  1219. goto err;
  1220. }
  1221. if (stv090x_set_vit_thtracq(state) < 0)
  1222. goto err;
  1223. break;
  1224. case STV090x_SEARCH_AUTO:
  1225. default:
  1226. /* enable DVB-S2 and DVB-S2 in Auto MODE */
  1227. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1228. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
  1229. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
  1230. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1231. goto err;
  1232. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
  1233. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
  1234. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1235. goto err;
  1236. if (stv090x_vitclk_ctl(state, 0) < 0)
  1237. goto err;
  1238. if (stv090x_dvbs_track_crl(state) < 0)
  1239. goto err;
  1240. if (state->internal->dev_ver <= 0x20) {
  1241. /* enable S2 carrier loop */
  1242. if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
  1243. goto err;
  1244. } else {
  1245. /* > Cut 3: Stop carrier 3 */
  1246. if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0)
  1247. goto err;
  1248. }
  1249. if (state->demod_mode != STV090x_SINGLE) {
  1250. /* Cut 2: enable link during search */
  1251. if (stv090x_activate_modcod(state) < 0)
  1252. goto err;
  1253. } else {
  1254. /* Single demodulator
  1255. * Authorize SHORT and LONG frames,
  1256. * QPSK, 8PSK, 16APSK and 32APSK
  1257. */
  1258. if (stv090x_activate_modcod_single(state) < 0)
  1259. goto err;
  1260. }
  1261. if (stv090x_set_vit_thacq(state) < 0)
  1262. goto err;
  1263. if (stv090x_set_viterbi(state) < 0)
  1264. goto err;
  1265. break;
  1266. }
  1267. return 0;
  1268. err:
  1269. dprintk(FE_ERROR, 1, "I/O error");
  1270. return -1;
  1271. }
  1272. static int stv090x_start_search(struct stv090x_state *state)
  1273. {
  1274. u32 reg, freq_abs;
  1275. s16 freq;
  1276. /* Reset demodulator */
  1277. reg = STV090x_READ_DEMOD(state, DMDISTATE);
  1278. STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f);
  1279. if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
  1280. goto err;
  1281. if (state->internal->dev_ver <= 0x20) {
  1282. if (state->srate <= 5000000) {
  1283. if (STV090x_WRITE_DEMOD(state, CARCFG, 0x44) < 0)
  1284. goto err;
  1285. if (STV090x_WRITE_DEMOD(state, CFRUP1, 0x0f) < 0)
  1286. goto err;
  1287. if (STV090x_WRITE_DEMOD(state, CFRUP0, 0xff) < 0)
  1288. goto err;
  1289. if (STV090x_WRITE_DEMOD(state, CFRLOW1, 0xf0) < 0)
  1290. goto err;
  1291. if (STV090x_WRITE_DEMOD(state, CFRLOW0, 0x00) < 0)
  1292. goto err;
  1293. /*enlarge the timing bandwidth for Low SR*/
  1294. if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0)
  1295. goto err;
  1296. } else {
  1297. /* If the symbol rate is >5 Msps
  1298. Set The carrier search up and low to auto mode */
  1299. if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
  1300. goto err;
  1301. /*reduce the timing bandwidth for high SR*/
  1302. if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
  1303. goto err;
  1304. }
  1305. } else {
  1306. /* >= Cut 3 */
  1307. if (state->srate <= 5000000) {
  1308. /* enlarge the timing bandwidth for Low SR */
  1309. STV090x_WRITE_DEMOD(state, RTCS2, 0x68);
  1310. } else {
  1311. /* reduce timing bandwidth for high SR */
  1312. STV090x_WRITE_DEMOD(state, RTCS2, 0x44);
  1313. }
  1314. /* Set CFR min and max to manual mode */
  1315. STV090x_WRITE_DEMOD(state, CARCFG, 0x46);
  1316. if (state->algo == STV090x_WARM_SEARCH) {
  1317. /* WARM Start
  1318. * CFR min = -1MHz,
  1319. * CFR max = +1MHz
  1320. */
  1321. freq_abs = 1000 << 16;
  1322. freq_abs /= (state->internal->mclk / 1000);
  1323. freq = (s16) freq_abs;
  1324. } else {
  1325. /* COLD Start
  1326. * CFR min =- (SearchRange / 2 + 600KHz)
  1327. * CFR max = +(SearchRange / 2 + 600KHz)
  1328. * (600KHz for the tuner step size)
  1329. */
  1330. freq_abs = (state->search_range / 2000) + 600;
  1331. freq_abs = freq_abs << 16;
  1332. freq_abs /= (state->internal->mclk / 1000);
  1333. freq = (s16) freq_abs;
  1334. }
  1335. if (STV090x_WRITE_DEMOD(state, CFRUP1, MSB(freq)) < 0)
  1336. goto err;
  1337. if (STV090x_WRITE_DEMOD(state, CFRUP0, LSB(freq)) < 0)
  1338. goto err;
  1339. freq *= -1;
  1340. if (STV090x_WRITE_DEMOD(state, CFRLOW1, MSB(freq)) < 0)
  1341. goto err;
  1342. if (STV090x_WRITE_DEMOD(state, CFRLOW0, LSB(freq)) < 0)
  1343. goto err;
  1344. }
  1345. if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0) < 0)
  1346. goto err;
  1347. if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0) < 0)
  1348. goto err;
  1349. if (state->internal->dev_ver >= 0x20) {
  1350. if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
  1351. goto err;
  1352. if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
  1353. goto err;
  1354. if ((state->search_mode == STV090x_SEARCH_DVBS1) ||
  1355. (state->search_mode == STV090x_SEARCH_DSS) ||
  1356. (state->search_mode == STV090x_SEARCH_AUTO)) {
  1357. if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
  1358. goto err;
  1359. if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0)
  1360. goto err;
  1361. }
  1362. }
  1363. if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00) < 0)
  1364. goto err;
  1365. if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xe0) < 0)
  1366. goto err;
  1367. if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xc0) < 0)
  1368. goto err;
  1369. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1370. STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0);
  1371. STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
  1372. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1373. goto err;
  1374. reg = STV090x_READ_DEMOD(state, DMDCFG2);
  1375. STV090x_SETFIELD_Px(reg, S1S2_SEQUENTIAL_FIELD, 0x0);
  1376. if (STV090x_WRITE_DEMOD(state, DMDCFG2, reg) < 0)
  1377. goto err;
  1378. if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0)
  1379. goto err;
  1380. if (state->internal->dev_ver >= 0x20) {
  1381. /*Frequency offset detector setting*/
  1382. if (state->srate < 2000000) {
  1383. if (state->internal->dev_ver <= 0x20) {
  1384. /* Cut 2 */
  1385. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x39) < 0)
  1386. goto err;
  1387. } else {
  1388. /* Cut 3 */
  1389. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x89) < 0)
  1390. goto err;
  1391. }
  1392. if (STV090x_WRITE_DEMOD(state, CARHDR, 0x40) < 0)
  1393. goto err;
  1394. } else if (state->srate < 10000000) {
  1395. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4c) < 0)
  1396. goto err;
  1397. if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0)
  1398. goto err;
  1399. } else {
  1400. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4b) < 0)
  1401. goto err;
  1402. if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0)
  1403. goto err;
  1404. }
  1405. } else {
  1406. if (state->srate < 10000000) {
  1407. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xef) < 0)
  1408. goto err;
  1409. } else {
  1410. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0)
  1411. goto err;
  1412. }
  1413. }
  1414. switch (state->algo) {
  1415. case STV090x_WARM_SEARCH:
  1416. /* The symbol rate and the exact
  1417. * carrier Frequency are known
  1418. */
  1419. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
  1420. goto err;
  1421. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
  1422. goto err;
  1423. break;
  1424. case STV090x_COLD_SEARCH:
  1425. /* The symbol rate is known */
  1426. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
  1427. goto err;
  1428. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
  1429. goto err;
  1430. break;
  1431. default:
  1432. break;
  1433. }
  1434. return 0;
  1435. err:
  1436. dprintk(FE_ERROR, 1, "I/O error");
  1437. return -1;
  1438. }
  1439. static int stv090x_get_agc2_min_level(struct stv090x_state *state)
  1440. {
  1441. u32 agc2_min = 0xffff, agc2 = 0, freq_init, freq_step, reg;
  1442. s32 i, j, steps, dir;
  1443. if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
  1444. goto err;
  1445. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1446. STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0);
  1447. STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
  1448. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1449. goto err;
  1450. if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0) /* SR = 65 Msps Max */
  1451. goto err;
  1452. if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
  1453. goto err;
  1454. if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0) /* SR= 400 ksps Min */
  1455. goto err;
  1456. if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
  1457. goto err;
  1458. if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0) /* stop acq @ coarse carrier state */
  1459. goto err;
  1460. if (stv090x_set_srate(state, 1000000) < 0)
  1461. goto err;
  1462. steps = state->search_range / 1000000;
  1463. if (steps <= 0)
  1464. steps = 1;
  1465. dir = 1;
  1466. freq_step = (1000000 * 256) / (state->internal->mclk / 256);
  1467. freq_init = 0;
  1468. for (i = 0; i < steps; i++) {
  1469. if (dir > 0)
  1470. freq_init = freq_init + (freq_step * i);
  1471. else
  1472. freq_init = freq_init - (freq_step * i);
  1473. dir *= -1;
  1474. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod RESET */
  1475. goto err;
  1476. if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_init >> 8) & 0xff) < 0)
  1477. goto err;
  1478. if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_init & 0xff) < 0)
  1479. goto err;
  1480. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x58) < 0) /* Demod RESET */
  1481. goto err;
  1482. msleep(10);
  1483. agc2 = 0;
  1484. for (j = 0; j < 10; j++) {
  1485. agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
  1486. STV090x_READ_DEMOD(state, AGC2I0);
  1487. }
  1488. agc2 /= 10;
  1489. if (agc2 < agc2_min)
  1490. agc2_min = agc2;
  1491. }
  1492. return agc2_min;
  1493. err:
  1494. dprintk(FE_ERROR, 1, "I/O error");
  1495. return -1;
  1496. }
  1497. static u32 stv090x_get_srate(struct stv090x_state *state, u32 clk)
  1498. {
  1499. u8 r3, r2, r1, r0;
  1500. s32 srate, int_1, int_2, tmp_1, tmp_2;
  1501. r3 = STV090x_READ_DEMOD(state, SFR3);
  1502. r2 = STV090x_READ_DEMOD(state, SFR2);
  1503. r1 = STV090x_READ_DEMOD(state, SFR1);
  1504. r0 = STV090x_READ_DEMOD(state, SFR0);
  1505. srate = ((r3 << 24) | (r2 << 16) | (r1 << 8) | r0);
  1506. int_1 = clk >> 16;
  1507. int_2 = srate >> 16;
  1508. tmp_1 = clk % 0x10000;
  1509. tmp_2 = srate % 0x10000;
  1510. srate = (int_1 * int_2) +
  1511. ((int_1 * tmp_2) >> 16) +
  1512. ((int_2 * tmp_1) >> 16);
  1513. return srate;
  1514. }
  1515. static u32 stv090x_srate_srch_coarse(struct stv090x_state *state)
  1516. {
  1517. struct dvb_frontend *fe = &state->frontend;
  1518. int tmg_lock = 0, i;
  1519. s32 tmg_cpt = 0, dir = 1, steps, cur_step = 0, freq;
  1520. u32 srate_coarse = 0, agc2 = 0, car_step = 1200, reg;
  1521. u32 agc2th;
  1522. if (state->internal->dev_ver >= 0x30)
  1523. agc2th = 0x2e00;
  1524. else
  1525. agc2th = 0x1f00;
  1526. reg = STV090x_READ_DEMOD(state, DMDISTATE);
  1527. STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f); /* Demod RESET */
  1528. if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
  1529. goto err;
  1530. if (STV090x_WRITE_DEMOD(state, TMGCFG, 0x12) < 0)
  1531. goto err;
  1532. if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0)
  1533. goto err;
  1534. if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xf0) < 0)
  1535. goto err;
  1536. if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xe0) < 0)
  1537. goto err;
  1538. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1539. STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 1);
  1540. STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
  1541. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1542. goto err;
  1543. if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0)
  1544. goto err;
  1545. if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
  1546. goto err;
  1547. if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0)
  1548. goto err;
  1549. if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
  1550. goto err;
  1551. if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0)
  1552. goto err;
  1553. if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x50) < 0)
  1554. goto err;
  1555. if (state->internal->dev_ver >= 0x30) {
  1556. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x99) < 0)
  1557. goto err;
  1558. if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x98) < 0)
  1559. goto err;
  1560. } else if (state->internal->dev_ver >= 0x20) {
  1561. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x6a) < 0)
  1562. goto err;
  1563. if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x95) < 0)
  1564. goto err;
  1565. }
  1566. if (state->srate <= 2000000)
  1567. car_step = 1000;
  1568. else if (state->srate <= 5000000)
  1569. car_step = 2000;
  1570. else if (state->srate <= 12000000)
  1571. car_step = 3000;
  1572. else
  1573. car_step = 5000;
  1574. steps = -1 + ((state->search_range / 1000) / car_step);
  1575. steps /= 2;
  1576. steps = (2 * steps) + 1;
  1577. if (steps < 0)
  1578. steps = 1;
  1579. else if (steps > 10) {
  1580. steps = 11;
  1581. car_step = (state->search_range / 1000) / 10;
  1582. }
  1583. cur_step = 0;
  1584. dir = 1;
  1585. freq = state->frequency;
  1586. while ((!tmg_lock) && (cur_step < steps)) {
  1587. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5f) < 0) /* Demod RESET */
  1588. goto err;
  1589. if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0)
  1590. goto err;
  1591. if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
  1592. goto err;
  1593. if (STV090x_WRITE_DEMOD(state, SFRINIT1, 0x00) < 0)
  1594. goto err;
  1595. if (STV090x_WRITE_DEMOD(state, SFRINIT0, 0x00) < 0)
  1596. goto err;
  1597. /* trigger acquisition */
  1598. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x40) < 0)
  1599. goto err;
  1600. msleep(50);
  1601. for (i = 0; i < 10; i++) {
  1602. reg = STV090x_READ_DEMOD(state, DSTATUS);
  1603. if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
  1604. tmg_cpt++;
  1605. agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
  1606. STV090x_READ_DEMOD(state, AGC2I0);
  1607. }
  1608. agc2 /= 10;
  1609. srate_coarse = stv090x_get_srate(state, state->internal->mclk);
  1610. cur_step++;
  1611. dir *= -1;
  1612. if ((tmg_cpt >= 5) && (agc2 < agc2th) &&
  1613. (srate_coarse < 50000000) && (srate_coarse > 850000))
  1614. tmg_lock = 1;
  1615. else if (cur_step < steps) {
  1616. if (dir > 0)
  1617. freq += cur_step * car_step;
  1618. else
  1619. freq -= cur_step * car_step;
  1620. /* Setup tuner */
  1621. if (stv090x_i2c_gate_ctrl(state, 1) < 0)
  1622. goto err;
  1623. if (state->config->tuner_set_frequency) {
  1624. if (state->config->tuner_set_frequency(fe, freq) < 0)
  1625. goto err_gateoff;
  1626. }
  1627. if (state->config->tuner_set_bandwidth) {
  1628. if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
  1629. goto err_gateoff;
  1630. }
  1631. if (stv090x_i2c_gate_ctrl(state, 0) < 0)
  1632. goto err;
  1633. msleep(50);
  1634. if (stv090x_i2c_gate_ctrl(state, 1) < 0)
  1635. goto err;
  1636. if (state->config->tuner_get_status) {
  1637. if (state->config->tuner_get_status(fe, &reg) < 0)
  1638. goto err_gateoff;
  1639. }
  1640. if (reg)
  1641. dprintk(FE_DEBUG, 1, "Tuner phase locked");
  1642. else
  1643. dprintk(FE_DEBUG, 1, "Tuner unlocked");
  1644. if (stv090x_i2c_gate_ctrl(state, 0) < 0)
  1645. goto err;
  1646. }
  1647. }
  1648. if (!tmg_lock)
  1649. srate_coarse = 0;
  1650. else
  1651. srate_coarse = stv090x_get_srate(state, state->internal->mclk);
  1652. return srate_coarse;
  1653. err_gateoff:
  1654. stv090x_i2c_gate_ctrl(state, 0);
  1655. err:
  1656. dprintk(FE_ERROR, 1, "I/O error");
  1657. return -1;
  1658. }
  1659. static u32 stv090x_srate_srch_fine(struct stv090x_state *state)
  1660. {
  1661. u32 srate_coarse, freq_coarse, sym, reg;
  1662. srate_coarse = stv090x_get_srate(state, state->internal->mclk);
  1663. freq_coarse = STV090x_READ_DEMOD(state, CFR2) << 8;
  1664. freq_coarse |= STV090x_READ_DEMOD(state, CFR1);
  1665. sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
  1666. if (sym < state->srate)
  1667. srate_coarse = 0;
  1668. else {
  1669. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) /* Demod RESET */
  1670. goto err;
  1671. if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0)
  1672. goto err;
  1673. if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
  1674. goto err;
  1675. if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
  1676. goto err;
  1677. if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
  1678. goto err;
  1679. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1680. STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
  1681. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1682. goto err;
  1683. if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
  1684. goto err;
  1685. if (state->internal->dev_ver >= 0x30) {
  1686. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x79) < 0)
  1687. goto err;
  1688. } else if (state->internal->dev_ver >= 0x20) {
  1689. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
  1690. goto err;
  1691. }
  1692. if (srate_coarse > 3000000) {
  1693. sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
  1694. sym = (sym / 1000) * 65536;
  1695. sym /= (state->internal->mclk / 1000);
  1696. if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
  1697. goto err;
  1698. if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
  1699. goto err;
  1700. sym = 10 * (srate_coarse / 13); /* SFRLOW = SFR - 30% */
  1701. sym = (sym / 1000) * 65536;
  1702. sym /= (state->internal->mclk / 1000);
  1703. if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
  1704. goto err;
  1705. if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
  1706. goto err;
  1707. sym = (srate_coarse / 1000) * 65536;
  1708. sym /= (state->internal->mclk / 1000);
  1709. if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
  1710. goto err;
  1711. if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
  1712. goto err;
  1713. } else {
  1714. sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
  1715. sym = (sym / 100) * 65536;
  1716. sym /= (state->internal->mclk / 100);
  1717. if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
  1718. goto err;
  1719. if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
  1720. goto err;
  1721. sym = 10 * (srate_coarse / 14); /* SFRLOW = SFR - 30% */
  1722. sym = (sym / 100) * 65536;
  1723. sym /= (state->internal->mclk / 100);
  1724. if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
  1725. goto err;
  1726. if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
  1727. goto err;
  1728. sym = (srate_coarse / 100) * 65536;
  1729. sym /= (state->internal->mclk / 100);
  1730. if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
  1731. goto err;
  1732. if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
  1733. goto err;
  1734. }
  1735. if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
  1736. goto err;
  1737. if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_coarse >> 8) & 0xff) < 0)
  1738. goto err;
  1739. if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_coarse & 0xff) < 0)
  1740. goto err;
  1741. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) /* trigger acquisition */
  1742. goto err;
  1743. }
  1744. return srate_coarse;
  1745. err:
  1746. dprintk(FE_ERROR, 1, "I/O error");
  1747. return -1;
  1748. }
  1749. static int stv090x_get_dmdlock(struct stv090x_state *state, s32 timeout)
  1750. {
  1751. s32 timer = 0, lock = 0;
  1752. u32 reg;
  1753. u8 stat;
  1754. while ((timer < timeout) && (!lock)) {
  1755. reg = STV090x_READ_DEMOD(state, DMDSTATE);
  1756. stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
  1757. switch (stat) {
  1758. case 0: /* searching */
  1759. case 1: /* first PLH detected */
  1760. default:
  1761. dprintk(FE_DEBUG, 1, "Demodulator searching ..");
  1762. lock = 0;
  1763. break;
  1764. case 2: /* DVB-S2 mode */
  1765. case 3: /* DVB-S1/legacy mode */
  1766. reg = STV090x_READ_DEMOD(state, DSTATUS);
  1767. lock = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
  1768. break;
  1769. }
  1770. if (!lock)
  1771. msleep(10);
  1772. else
  1773. dprintk(FE_DEBUG, 1, "Demodulator acquired LOCK");
  1774. timer += 10;
  1775. }
  1776. return lock;
  1777. }
  1778. static int stv090x_blind_search(struct stv090x_state *state)
  1779. {
  1780. u32 agc2, reg, srate_coarse;
  1781. s32 cpt_fail, agc2_ovflw, i;
  1782. u8 k_ref, k_max, k_min;
  1783. int coarse_fail = 0;
  1784. int lock;
  1785. k_max = 110;
  1786. k_min = 10;
  1787. agc2 = stv090x_get_agc2_min_level(state);
  1788. if (agc2 > STV090x_SEARCH_AGC2_TH(state->internal->dev_ver)) {
  1789. lock = 0;
  1790. } else {
  1791. if (state->internal->dev_ver <= 0x20) {
  1792. if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
  1793. goto err;
  1794. } else {
  1795. /* > Cut 3 */
  1796. if (STV090x_WRITE_DEMOD(state, CARCFG, 0x06) < 0)
  1797. goto err;
  1798. }
  1799. if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
  1800. goto err;
  1801. if (state->internal->dev_ver >= 0x20) {
  1802. if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
  1803. goto err;
  1804. if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
  1805. goto err;
  1806. if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
  1807. goto err;
  1808. if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0) /* set viterbi hysteresis */
  1809. goto err;
  1810. }
  1811. k_ref = k_max;
  1812. do {
  1813. if (STV090x_WRITE_DEMOD(state, KREFTMG, k_ref) < 0)
  1814. goto err;
  1815. if (stv090x_srate_srch_coarse(state) != 0) {
  1816. srate_coarse = stv090x_srate_srch_fine(state);
  1817. if (srate_coarse != 0) {
  1818. stv090x_get_lock_tmg(state);
  1819. lock = stv090x_get_dmdlock(state,
  1820. state->DemodTimeout);
  1821. } else {
  1822. lock = 0;
  1823. }
  1824. } else {
  1825. cpt_fail = 0;
  1826. agc2_ovflw = 0;
  1827. for (i = 0; i < 10; i++) {
  1828. agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
  1829. STV090x_READ_DEMOD(state, AGC2I0);
  1830. if (agc2 >= 0xff00)
  1831. agc2_ovflw++;
  1832. reg = STV090x_READ_DEMOD(state, DSTATUS2);
  1833. if ((STV090x_GETFIELD_Px(reg, CFR_OVERFLOW_FIELD) == 0x01) &&
  1834. (STV090x_GETFIELD_Px(reg, DEMOD_DELOCK_FIELD) == 0x01))
  1835. cpt_fail++;
  1836. }
  1837. if ((cpt_fail > 7) || (agc2_ovflw > 7))
  1838. coarse_fail = 1;
  1839. lock = 0;
  1840. }
  1841. k_ref -= 20;
  1842. } while ((k_ref >= k_min) && (!lock) && (!coarse_fail));
  1843. }
  1844. return lock;
  1845. err:
  1846. dprintk(FE_ERROR, 1, "I/O error");
  1847. return -1;
  1848. }
  1849. static int stv090x_chk_tmg(struct stv090x_state *state)
  1850. {
  1851. u32 reg;
  1852. s32 tmg_cpt = 0, i;
  1853. u8 freq, tmg_thh, tmg_thl;
  1854. int tmg_lock = 0;
  1855. freq = STV090x_READ_DEMOD(state, CARFREQ);
  1856. tmg_thh = STV090x_READ_DEMOD(state, TMGTHRISE);
  1857. tmg_thl = STV090x_READ_DEMOD(state, TMGTHFALL);
  1858. if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
  1859. goto err;
  1860. if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
  1861. goto err;
  1862. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1863. STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00); /* stop carrier offset search */
  1864. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1865. goto err;
  1866. if (STV090x_WRITE_DEMOD(state, RTC, 0x80) < 0)
  1867. goto err;
  1868. if (STV090x_WRITE_DEMOD(state, RTCS2, 0x40) < 0)
  1869. goto err;
  1870. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x00) < 0)
  1871. goto err;
  1872. if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) /* set car ofset to 0 */
  1873. goto err;
  1874. if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
  1875. goto err;
  1876. if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x65) < 0)
  1877. goto err;
  1878. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) /* trigger acquisition */
  1879. goto err;
  1880. msleep(10);
  1881. for (i = 0; i < 10; i++) {
  1882. reg = STV090x_READ_DEMOD(state, DSTATUS);
  1883. if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
  1884. tmg_cpt++;
  1885. msleep(1);
  1886. }
  1887. if (tmg_cpt >= 3)
  1888. tmg_lock = 1;
  1889. if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
  1890. goto err;
  1891. if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0) /* DVB-S1 timing */
  1892. goto err;
  1893. if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0) /* DVB-S2 timing */
  1894. goto err;
  1895. if (STV090x_WRITE_DEMOD(state, CARFREQ, freq) < 0)
  1896. goto err;
  1897. if (STV090x_WRITE_DEMOD(state, TMGTHRISE, tmg_thh) < 0)
  1898. goto err;
  1899. if (STV090x_WRITE_DEMOD(state, TMGTHFALL, tmg_thl) < 0)
  1900. goto err;
  1901. return tmg_lock;
  1902. err:
  1903. dprintk(FE_ERROR, 1, "I/O error");
  1904. return -1;
  1905. }
  1906. static int stv090x_get_coldlock(struct stv090x_state *state, s32 timeout_dmd)
  1907. {
  1908. struct dvb_frontend *fe = &state->frontend;
  1909. u32 reg;
  1910. s32 car_step, steps, cur_step, dir, freq, timeout_lock;
  1911. int lock;
  1912. if (state->srate >= 10000000)
  1913. timeout_lock = timeout_dmd / 3;
  1914. else
  1915. timeout_lock = timeout_dmd / 2;
  1916. lock = stv090x_get_dmdlock(state, timeout_lock); /* cold start wait */
  1917. if (lock)
  1918. return lock;
  1919. if (state->srate >= 10000000) {
  1920. if (stv090x_chk_tmg(state)) {
  1921. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
  1922. goto err;
  1923. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
  1924. goto err;
  1925. return stv090x_get_dmdlock(state, timeout_dmd);
  1926. }
  1927. return 0;
  1928. }
  1929. if (state->srate <= 4000000)
  1930. car_step = 1000;
  1931. else if (state->srate <= 7000000)
  1932. car_step = 2000;
  1933. else if (state->srate <= 10000000)
  1934. car_step = 3000;
  1935. else
  1936. car_step = 5000;
  1937. steps = (state->search_range / 1000) / car_step;
  1938. steps /= 2;
  1939. steps = 2 * (steps + 1);
  1940. if (steps < 0)
  1941. steps = 2;
  1942. else if (steps > 12)
  1943. steps = 12;
  1944. cur_step = 1;
  1945. dir = 1;
  1946. freq = state->frequency;
  1947. state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + state->srate;
  1948. while ((cur_step <= steps) && (!lock)) {
  1949. if (dir > 0)
  1950. freq += cur_step * car_step;
  1951. else
  1952. freq -= cur_step * car_step;
  1953. /* Setup tuner */
  1954. if (stv090x_i2c_gate_ctrl(state, 1) < 0)
  1955. goto err;
  1956. if (state->config->tuner_set_frequency) {
  1957. if (state->config->tuner_set_frequency(fe, freq) < 0)
  1958. goto err_gateoff;
  1959. }
  1960. if (state->config->tuner_set_bandwidth) {
  1961. if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
  1962. goto err_gateoff;
  1963. }
  1964. if (stv090x_i2c_gate_ctrl(state, 0) < 0)
  1965. goto err;
  1966. msleep(50);
  1967. if (stv090x_i2c_gate_ctrl(state, 1) < 0)
  1968. goto err;
  1969. if (state->config->tuner_get_status) {
  1970. if (state->config->tuner_get_status(fe, &reg) < 0)
  1971. goto err_gateoff;
  1972. if (reg)
  1973. dprintk(FE_DEBUG, 1, "Tuner phase locked");
  1974. else
  1975. dprintk(FE_DEBUG, 1, "Tuner unlocked");
  1976. }
  1977. if (stv090x_i2c_gate_ctrl(state, 0) < 0)
  1978. goto err;
  1979. STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c);
  1980. if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0)
  1981. goto err;
  1982. if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
  1983. goto err;
  1984. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
  1985. goto err;
  1986. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
  1987. goto err;
  1988. lock = stv090x_get_dmdlock(state, (timeout_dmd / 3));
  1989. dir *= -1;
  1990. cur_step++;
  1991. }
  1992. return lock;
  1993. err_gateoff:
  1994. stv090x_i2c_gate_ctrl(state, 0);
  1995. err:
  1996. dprintk(FE_ERROR, 1, "I/O error");
  1997. return -1;
  1998. }
  1999. static int stv090x_get_loop_params(struct stv090x_state *state, s32 *freq_inc, s32 *timeout_sw, s32 *steps)
  2000. {
  2001. s32 timeout, inc, steps_max, srate, car_max;
  2002. srate = state->srate;
  2003. car_max = state->search_range / 1000;
  2004. car_max += car_max / 10;
  2005. car_max = 65536 * (car_max / 2);
  2006. car_max /= (state->internal->mclk / 1000);
  2007. if (car_max > 0x4000)
  2008. car_max = 0x4000 ; /* maxcarrier should be<= +-1/4 Mclk */
  2009. inc = srate;
  2010. inc /= state->internal->mclk / 1000;
  2011. inc *= 256;
  2012. inc *= 256;
  2013. inc /= 1000;
  2014. switch (state->search_mode) {
  2015. case STV090x_SEARCH_DVBS1:
  2016. case STV090x_SEARCH_DSS:
  2017. inc *= 3; /* freq step = 3% of srate */
  2018. timeout = 20;
  2019. break;
  2020. case STV090x_SEARCH_DVBS2:
  2021. inc *= 4;
  2022. timeout = 25;
  2023. break;
  2024. case STV090x_SEARCH_AUTO:
  2025. default:
  2026. inc *= 3;
  2027. timeout = 25;
  2028. break;
  2029. }
  2030. inc /= 100;
  2031. if ((inc > car_max) || (inc < 0))
  2032. inc = car_max / 2; /* increment <= 1/8 Mclk */
  2033. timeout *= 27500; /* 27.5 Msps reference */
  2034. if (srate > 0)
  2035. timeout /= (srate / 1000);
  2036. if ((timeout > 100) || (timeout < 0))
  2037. timeout = 100;
  2038. steps_max = (car_max / inc) + 1; /* min steps = 3 */
  2039. if ((steps_max > 100) || (steps_max < 0)) {
  2040. steps_max = 100; /* max steps <= 100 */
  2041. inc = car_max / steps_max;
  2042. }
  2043. *freq_inc = inc;
  2044. *timeout_sw = timeout;
  2045. *steps = steps_max;
  2046. return 0;
  2047. }
  2048. static int stv090x_chk_signal(struct stv090x_state *state)
  2049. {
  2050. s32 offst_car, agc2, car_max;
  2051. int no_signal;
  2052. offst_car = STV090x_READ_DEMOD(state, CFR2) << 8;
  2053. offst_car |= STV090x_READ_DEMOD(state, CFR1);
  2054. offst_car = comp2(offst_car, 16);
  2055. agc2 = STV090x_READ_DEMOD(state, AGC2I1) << 8;
  2056. agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
  2057. car_max = state->search_range / 1000;
  2058. car_max += (car_max / 10); /* 10% margin */
  2059. car_max = (65536 * car_max / 2);
  2060. car_max /= state->internal->mclk / 1000;
  2061. if (car_max > 0x4000)
  2062. car_max = 0x4000;
  2063. if ((agc2 > 0x2000) || (offst_car > 2 * car_max) || (offst_car < -2 * car_max)) {
  2064. no_signal = 1;
  2065. dprintk(FE_DEBUG, 1, "No Signal");
  2066. } else {
  2067. no_signal = 0;
  2068. dprintk(FE_DEBUG, 1, "Found Signal");
  2069. }
  2070. return no_signal;
  2071. }
  2072. static int stv090x_search_car_loop(struct stv090x_state *state, s32 inc, s32 timeout, int zigzag, s32 steps_max)
  2073. {
  2074. int no_signal, lock = 0;
  2075. s32 cpt_step = 0, offst_freq, car_max;
  2076. u32 reg;
  2077. car_max = state->search_range / 1000;
  2078. car_max += (car_max / 10);
  2079. car_max = (65536 * car_max / 2);
  2080. car_max /= (state->internal->mclk / 1000);
  2081. if (car_max > 0x4000)
  2082. car_max = 0x4000;
  2083. if (zigzag)
  2084. offst_freq = 0;
  2085. else
  2086. offst_freq = -car_max + inc;
  2087. do {
  2088. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c) < 0)
  2089. goto err;
  2090. if (STV090x_WRITE_DEMOD(state, CFRINIT1, ((offst_freq / 256) & 0xff)) < 0)
  2091. goto err;
  2092. if (STV090x_WRITE_DEMOD(state, CFRINIT0, offst_freq & 0xff) < 0)
  2093. goto err;
  2094. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
  2095. goto err;
  2096. reg = STV090x_READ_DEMOD(state, PDELCTRL1);
  2097. STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x1); /* stop DVB-S2 packet delin */
  2098. if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
  2099. goto err;
  2100. if (zigzag) {
  2101. if (offst_freq >= 0)
  2102. offst_freq = -offst_freq - 2 * inc;
  2103. else
  2104. offst_freq = -offst_freq;
  2105. } else {
  2106. offst_freq += 2 * inc;
  2107. }
  2108. cpt_step++;
  2109. lock = stv090x_get_dmdlock(state, timeout);
  2110. no_signal = stv090x_chk_signal(state);
  2111. } while ((!lock) &&
  2112. (!no_signal) &&
  2113. ((offst_freq - inc) < car_max) &&
  2114. ((offst_freq + inc) > -car_max) &&
  2115. (cpt_step < steps_max));
  2116. reg = STV090x_READ_DEMOD(state, PDELCTRL1);
  2117. STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0);
  2118. if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
  2119. goto err;
  2120. return lock;
  2121. err:
  2122. dprintk(FE_ERROR, 1, "I/O error");
  2123. return -1;
  2124. }
  2125. static int stv090x_sw_algo(struct stv090x_state *state)
  2126. {
  2127. int no_signal, zigzag, lock = 0;
  2128. u32 reg;
  2129. s32 dvbs2_fly_wheel;
  2130. s32 inc, timeout_step, trials, steps_max;
  2131. /* get params */
  2132. stv090x_get_loop_params(state, &inc, &timeout_step, &steps_max);
  2133. switch (state->search_mode) {
  2134. case STV090x_SEARCH_DVBS1:
  2135. case STV090x_SEARCH_DSS:
  2136. /* accelerate the frequency detector */
  2137. if (state->internal->dev_ver >= 0x20) {
  2138. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3B) < 0)
  2139. goto err;
  2140. }
  2141. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x49) < 0)
  2142. goto err;
  2143. zigzag = 0;
  2144. break;
  2145. case STV090x_SEARCH_DVBS2:
  2146. if (state->internal->dev_ver >= 0x20) {
  2147. if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
  2148. goto err;
  2149. }
  2150. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
  2151. goto err;
  2152. zigzag = 1;
  2153. break;
  2154. case STV090x_SEARCH_AUTO:
  2155. default:
  2156. /* accelerate the frequency detector */
  2157. if (state->internal->dev_ver >= 0x20) {
  2158. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3b) < 0)
  2159. goto err;
  2160. if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
  2161. goto err;
  2162. }
  2163. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0xc9) < 0)
  2164. goto err;
  2165. zigzag = 0;
  2166. break;
  2167. }
  2168. trials = 0;
  2169. do {
  2170. lock = stv090x_search_car_loop(state, inc, timeout_step, zigzag, steps_max);
  2171. no_signal = stv090x_chk_signal(state);
  2172. trials++;
  2173. /*run the SW search 2 times maximum*/
  2174. if (lock || no_signal || (trials == 2)) {
  2175. /*Check if the demod is not losing lock in DVBS2*/
  2176. if (state->internal->dev_ver >= 0x20) {
  2177. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
  2178. goto err;
  2179. if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0)
  2180. goto err;
  2181. }
  2182. reg = STV090x_READ_DEMOD(state, DMDSTATE);
  2183. if ((lock) && (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == STV090x_DVBS2)) {
  2184. /*Check if the demod is not losing lock in DVBS2*/
  2185. msleep(timeout_step);
  2186. reg = STV090x_READ_DEMOD(state, DMDFLYW);
  2187. dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
  2188. if (dvbs2_fly_wheel < 0xd) { /*if correct frames is decrementing */
  2189. msleep(timeout_step);
  2190. reg = STV090x_READ_DEMOD(state, DMDFLYW);
  2191. dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
  2192. }
  2193. if (dvbs2_fly_wheel < 0xd) {
  2194. /*FALSE lock, The demod is losing lock */
  2195. lock = 0;
  2196. if (trials < 2) {
  2197. if (state->internal->dev_ver >= 0x20) {
  2198. if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
  2199. goto err;
  2200. }
  2201. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
  2202. goto err;
  2203. }
  2204. }
  2205. }
  2206. }
  2207. } while ((!lock) && (trials < 2) && (!no_signal));
  2208. return lock;
  2209. err:
  2210. dprintk(FE_ERROR, 1, "I/O error");
  2211. return -1;
  2212. }
  2213. static enum stv090x_delsys stv090x_get_std(struct stv090x_state *state)
  2214. {
  2215. u32 reg;
  2216. enum stv090x_delsys delsys;
  2217. reg = STV090x_READ_DEMOD(state, DMDSTATE);
  2218. if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 2)
  2219. delsys = STV090x_DVBS2;
  2220. else if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 3) {
  2221. reg = STV090x_READ_DEMOD(state, FECM);
  2222. if (STV090x_GETFIELD_Px(reg, DSS_DVB_FIELD) == 1)
  2223. delsys = STV090x_DSS;
  2224. else
  2225. delsys = STV090x_DVBS1;
  2226. } else {
  2227. delsys = STV090x_ERROR;
  2228. }
  2229. return delsys;
  2230. }
  2231. /* in Hz */
  2232. static s32 stv090x_get_car_freq(struct stv090x_state *state, u32 mclk)
  2233. {
  2234. s32 derot, int_1, int_2, tmp_1, tmp_2;
  2235. derot = STV090x_READ_DEMOD(state, CFR2) << 16;
  2236. derot |= STV090x_READ_DEMOD(state, CFR1) << 8;
  2237. derot |= STV090x_READ_DEMOD(state, CFR0);
  2238. derot = comp2(derot, 24);
  2239. int_1 = mclk >> 12;
  2240. int_2 = derot >> 12;
  2241. /* carrier_frequency = MasterClock * Reg / 2^24 */
  2242. tmp_1 = mclk % 0x1000;
  2243. tmp_2 = derot % 0x1000;
  2244. derot = (int_1 * int_2) +
  2245. ((int_1 * tmp_2) >> 12) +
  2246. ((int_2 * tmp_1) >> 12);
  2247. return derot;
  2248. }
  2249. static int stv090x_get_viterbi(struct stv090x_state *state)
  2250. {
  2251. u32 reg, rate;
  2252. reg = STV090x_READ_DEMOD(state, VITCURPUN);
  2253. rate = STV090x_GETFIELD_Px(reg, VIT_CURPUN_FIELD);
  2254. switch (rate) {
  2255. case 13:
  2256. state->fec = STV090x_PR12;
  2257. break;
  2258. case 18:
  2259. state->fec = STV090x_PR23;
  2260. break;
  2261. case 21:
  2262. state->fec = STV090x_PR34;
  2263. break;
  2264. case 24:
  2265. state->fec = STV090x_PR56;
  2266. break;
  2267. case 25:
  2268. state->fec = STV090x_PR67;
  2269. break;
  2270. case 26:
  2271. state->fec = STV090x_PR78;
  2272. break;
  2273. default:
  2274. state->fec = STV090x_PRERR;
  2275. break;
  2276. }
  2277. return 0;
  2278. }
  2279. static enum stv090x_signal_state stv090x_get_sig_params(struct stv090x_state *state)
  2280. {
  2281. struct dvb_frontend *fe = &state->frontend;
  2282. u8 tmg;
  2283. u32 reg;
  2284. s32 i = 0, offst_freq;
  2285. msleep(5);
  2286. if (state->algo == STV090x_BLIND_SEARCH) {
  2287. tmg = STV090x_READ_DEMOD(state, TMGREG2);
  2288. STV090x_WRITE_DEMOD(state, SFRSTEP, 0x5c);
  2289. while ((i <= 50) && (tmg != 0) && (tmg != 0xff)) {
  2290. tmg = STV090x_READ_DEMOD(state, TMGREG2);
  2291. msleep(5);
  2292. i += 5;
  2293. }
  2294. }
  2295. state->delsys = stv090x_get_std(state);
  2296. if (stv090x_i2c_gate_ctrl(state, 1) < 0)
  2297. goto err;
  2298. if (state->config->tuner_get_frequency) {
  2299. if (state->config->tuner_get_frequency(fe, &state->frequency) < 0)
  2300. goto err_gateoff;
  2301. }
  2302. if (stv090x_i2c_gate_ctrl(state, 0) < 0)
  2303. goto err;
  2304. offst_freq = stv090x_get_car_freq(state, state->internal->mclk) / 1000;
  2305. state->frequency += offst_freq;
  2306. if (stv090x_get_viterbi(state) < 0)
  2307. goto err;
  2308. reg = STV090x_READ_DEMOD(state, DMDMODCOD);
  2309. state->modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
  2310. state->pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
  2311. state->frame_len = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) >> 1;
  2312. reg = STV090x_READ_DEMOD(state, TMGOBS);
  2313. state->rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD);
  2314. reg = STV090x_READ_DEMOD(state, FECM);
  2315. state->inversion = STV090x_GETFIELD_Px(reg, IQINV_FIELD);
  2316. if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000)) {
  2317. if (stv090x_i2c_gate_ctrl(state, 1) < 0)
  2318. goto err;
  2319. if (state->config->tuner_get_frequency) {
  2320. if (state->config->tuner_get_frequency(fe, &state->frequency) < 0)
  2321. goto err_gateoff;
  2322. }
  2323. if (stv090x_i2c_gate_ctrl(state, 0) < 0)
  2324. goto err;
  2325. if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
  2326. return STV090x_RANGEOK;
  2327. else if (abs(offst_freq) <= (stv090x_car_width(state->srate, state->rolloff) / 2000))
  2328. return STV090x_RANGEOK;
  2329. } else {
  2330. if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
  2331. return STV090x_RANGEOK;
  2332. }
  2333. return STV090x_OUTOFRANGE;
  2334. err_gateoff:
  2335. stv090x_i2c_gate_ctrl(state, 0);
  2336. err:
  2337. dprintk(FE_ERROR, 1, "I/O error");
  2338. return -1;
  2339. }
  2340. static u32 stv090x_get_tmgoffst(struct stv090x_state *state, u32 srate)
  2341. {
  2342. s32 offst_tmg;
  2343. offst_tmg = STV090x_READ_DEMOD(state, TMGREG2) << 16;
  2344. offst_tmg |= STV090x_READ_DEMOD(state, TMGREG1) << 8;
  2345. offst_tmg |= STV090x_READ_DEMOD(state, TMGREG0);
  2346. offst_tmg = comp2(offst_tmg, 24); /* 2's complement */
  2347. if (!offst_tmg)
  2348. offst_tmg = 1;
  2349. offst_tmg = ((s32) srate * 10) / ((s32) 0x1000000 / offst_tmg);
  2350. offst_tmg /= 320;
  2351. return offst_tmg;
  2352. }
  2353. static u8 stv090x_optimize_carloop(struct stv090x_state *state, enum stv090x_modcod modcod, s32 pilots)
  2354. {
  2355. u8 aclc = 0x29;
  2356. s32 i;
  2357. struct stv090x_long_frame_crloop *car_loop, *car_loop_qpsk_low, *car_loop_apsk_low;
  2358. if (state->internal->dev_ver == 0x20) {
  2359. car_loop = stv090x_s2_crl_cut20;
  2360. car_loop_qpsk_low = stv090x_s2_lowqpsk_crl_cut20;
  2361. car_loop_apsk_low = stv090x_s2_apsk_crl_cut20;
  2362. } else {
  2363. /* >= Cut 3 */
  2364. car_loop = stv090x_s2_crl_cut30;
  2365. car_loop_qpsk_low = stv090x_s2_lowqpsk_crl_cut30;
  2366. car_loop_apsk_low = stv090x_s2_apsk_crl_cut30;
  2367. }
  2368. if (modcod < STV090x_QPSK_12) {
  2369. i = 0;
  2370. while ((i < 3) && (modcod != car_loop_qpsk_low[i].modcod))
  2371. i++;
  2372. if (i >= 3)
  2373. i = 2;
  2374. } else {
  2375. i = 0;
  2376. while ((i < 14) && (modcod != car_loop[i].modcod))
  2377. i++;
  2378. if (i >= 14) {
  2379. i = 0;
  2380. while ((i < 11) && (modcod != car_loop_apsk_low[i].modcod))
  2381. i++;
  2382. if (i >= 11)
  2383. i = 10;
  2384. }
  2385. }
  2386. if (modcod <= STV090x_QPSK_25) {
  2387. if (pilots) {
  2388. if (state->srate <= 3000000)
  2389. aclc = car_loop_qpsk_low[i].crl_pilots_on_2;
  2390. else if (state->srate <= 7000000)
  2391. aclc = car_loop_qpsk_low[i].crl_pilots_on_5;
  2392. else if (state->srate <= 15000000)
  2393. aclc = car_loop_qpsk_low[i].crl_pilots_on_10;
  2394. else if (state->srate <= 25000000)
  2395. aclc = car_loop_qpsk_low[i].crl_pilots_on_20;
  2396. else
  2397. aclc = car_loop_qpsk_low[i].crl_pilots_on_30;
  2398. } else {
  2399. if (state->srate <= 3000000)
  2400. aclc = car_loop_qpsk_low[i].crl_pilots_off_2;
  2401. else if (state->srate <= 7000000)
  2402. aclc = car_loop_qpsk_low[i].crl_pilots_off_5;
  2403. else if (state->srate <= 15000000)
  2404. aclc = car_loop_qpsk_low[i].crl_pilots_off_10;
  2405. else if (state->srate <= 25000000)
  2406. aclc = car_loop_qpsk_low[i].crl_pilots_off_20;
  2407. else
  2408. aclc = car_loop_qpsk_low[i].crl_pilots_off_30;
  2409. }
  2410. } else if (modcod <= STV090x_8PSK_910) {
  2411. if (pilots) {
  2412. if (state->srate <= 3000000)
  2413. aclc = car_loop[i].crl_pilots_on_2;
  2414. else if (state->srate <= 7000000)
  2415. aclc = car_loop[i].crl_pilots_on_5;
  2416. else if (state->srate <= 15000000)
  2417. aclc = car_loop[i].crl_pilots_on_10;
  2418. else if (state->srate <= 25000000)
  2419. aclc = car_loop[i].crl_pilots_on_20;
  2420. else
  2421. aclc = car_loop[i].crl_pilots_on_30;
  2422. } else {
  2423. if (state->srate <= 3000000)
  2424. aclc = car_loop[i].crl_pilots_off_2;
  2425. else if (state->srate <= 7000000)
  2426. aclc = car_loop[i].crl_pilots_off_5;
  2427. else if (state->srate <= 15000000)
  2428. aclc = car_loop[i].crl_pilots_off_10;
  2429. else if (state->srate <= 25000000)
  2430. aclc = car_loop[i].crl_pilots_off_20;
  2431. else
  2432. aclc = car_loop[i].crl_pilots_off_30;
  2433. }
  2434. } else { /* 16APSK and 32APSK */
  2435. /*
  2436. * This should never happen in practice, except if
  2437. * something is really wrong at the car_loop table.
  2438. */
  2439. if (i >= 11)
  2440. i = 10;
  2441. if (state->srate <= 3000000)
  2442. aclc = car_loop_apsk_low[i].crl_pilots_on_2;
  2443. else if (state->srate <= 7000000)
  2444. aclc = car_loop_apsk_low[i].crl_pilots_on_5;
  2445. else if (state->srate <= 15000000)
  2446. aclc = car_loop_apsk_low[i].crl_pilots_on_10;
  2447. else if (state->srate <= 25000000)
  2448. aclc = car_loop_apsk_low[i].crl_pilots_on_20;
  2449. else
  2450. aclc = car_loop_apsk_low[i].crl_pilots_on_30;
  2451. }
  2452. return aclc;
  2453. }
  2454. static u8 stv090x_optimize_carloop_short(struct stv090x_state *state)
  2455. {
  2456. struct stv090x_short_frame_crloop *short_crl = NULL;
  2457. s32 index = 0;
  2458. u8 aclc = 0x0b;
  2459. switch (state->modulation) {
  2460. case STV090x_QPSK:
  2461. default:
  2462. index = 0;
  2463. break;
  2464. case STV090x_8PSK:
  2465. index = 1;
  2466. break;
  2467. case STV090x_16APSK:
  2468. index = 2;
  2469. break;
  2470. case STV090x_32APSK:
  2471. index = 3;
  2472. break;
  2473. }
  2474. if (state->internal->dev_ver >= 0x30) {
  2475. /* Cut 3.0 and up */
  2476. short_crl = stv090x_s2_short_crl_cut30;
  2477. } else {
  2478. /* Cut 2.0 and up: we don't support cuts older than 2.0 */
  2479. short_crl = stv090x_s2_short_crl_cut20;
  2480. }
  2481. if (state->srate <= 3000000)
  2482. aclc = short_crl[index].crl_2;
  2483. else if (state->srate <= 7000000)
  2484. aclc = short_crl[index].crl_5;
  2485. else if (state->srate <= 15000000)
  2486. aclc = short_crl[index].crl_10;
  2487. else if (state->srate <= 25000000)
  2488. aclc = short_crl[index].crl_20;
  2489. else
  2490. aclc = short_crl[index].crl_30;
  2491. return aclc;
  2492. }
  2493. static int stv090x_optimize_track(struct stv090x_state *state)
  2494. {
  2495. struct dvb_frontend *fe = &state->frontend;
  2496. enum stv090x_modcod modcod;
  2497. s32 srate, pilots, aclc, f_1, f_0, i = 0, blind_tune = 0;
  2498. u32 reg;
  2499. srate = stv090x_get_srate(state, state->internal->mclk);
  2500. srate += stv090x_get_tmgoffst(state, srate);
  2501. switch (state->delsys) {
  2502. case STV090x_DVBS1:
  2503. case STV090x_DSS:
  2504. if (state->search_mode == STV090x_SEARCH_AUTO) {
  2505. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  2506. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
  2507. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
  2508. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  2509. goto err;
  2510. }
  2511. reg = STV090x_READ_DEMOD(state, DEMOD);
  2512. STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
  2513. STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x01);
  2514. if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
  2515. goto err;
  2516. if (state->internal->dev_ver >= 0x30) {
  2517. if (stv090x_get_viterbi(state) < 0)
  2518. goto err;
  2519. if (state->fec == STV090x_PR12) {
  2520. if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x98) < 0)
  2521. goto err;
  2522. if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0)
  2523. goto err;
  2524. } else {
  2525. if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x18) < 0)
  2526. goto err;
  2527. if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0)
  2528. goto err;
  2529. }
  2530. }
  2531. if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
  2532. goto err;
  2533. break;
  2534. case STV090x_DVBS2:
  2535. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  2536. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
  2537. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
  2538. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  2539. goto err;
  2540. if (state->internal->dev_ver >= 0x30) {
  2541. if (STV090x_WRITE_DEMOD(state, ACLC, 0) < 0)
  2542. goto err;
  2543. if (STV090x_WRITE_DEMOD(state, BCLC, 0) < 0)
  2544. goto err;
  2545. }
  2546. if (state->frame_len == STV090x_LONG_FRAME) {
  2547. reg = STV090x_READ_DEMOD(state, DMDMODCOD);
  2548. modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
  2549. pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
  2550. aclc = stv090x_optimize_carloop(state, modcod, pilots);
  2551. if (modcod <= STV090x_QPSK_910) {
  2552. STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc);
  2553. } else if (modcod <= STV090x_8PSK_910) {
  2554. if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
  2555. goto err;
  2556. if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
  2557. goto err;
  2558. }
  2559. if ((state->demod_mode == STV090x_SINGLE) && (modcod > STV090x_8PSK_910)) {
  2560. if (modcod <= STV090x_16APSK_910) {
  2561. if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
  2562. goto err;
  2563. if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
  2564. goto err;
  2565. } else {
  2566. if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
  2567. goto err;
  2568. if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
  2569. goto err;
  2570. }
  2571. }
  2572. } else {
  2573. /*Carrier loop setting for short frame*/
  2574. aclc = stv090x_optimize_carloop_short(state);
  2575. if (state->modulation == STV090x_QPSK) {
  2576. if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc) < 0)
  2577. goto err;
  2578. } else if (state->modulation == STV090x_8PSK) {
  2579. if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
  2580. goto err;
  2581. if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
  2582. goto err;
  2583. } else if (state->modulation == STV090x_16APSK) {
  2584. if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
  2585. goto err;
  2586. if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
  2587. goto err;
  2588. } else if (state->modulation == STV090x_32APSK) {
  2589. if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
  2590. goto err;
  2591. if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
  2592. goto err;
  2593. }
  2594. }
  2595. STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67); /* PER */
  2596. break;
  2597. case STV090x_ERROR:
  2598. default:
  2599. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  2600. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
  2601. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
  2602. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  2603. goto err;
  2604. break;
  2605. }
  2606. f_1 = STV090x_READ_DEMOD(state, CFR2);
  2607. f_0 = STV090x_READ_DEMOD(state, CFR1);
  2608. reg = STV090x_READ_DEMOD(state, TMGOBS);
  2609. if (state->algo == STV090x_BLIND_SEARCH) {
  2610. STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00);
  2611. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  2612. STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0x00);
  2613. STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
  2614. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  2615. goto err;
  2616. if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0)
  2617. goto err;
  2618. if (stv090x_set_srate(state, srate) < 0)
  2619. goto err;
  2620. blind_tune = 1;
  2621. if (stv090x_dvbs_track_crl(state) < 0)
  2622. goto err;
  2623. }
  2624. if (state->internal->dev_ver >= 0x20) {
  2625. if ((state->search_mode == STV090x_SEARCH_DVBS1) ||
  2626. (state->search_mode == STV090x_SEARCH_DSS) ||
  2627. (state->search_mode == STV090x_SEARCH_AUTO)) {
  2628. if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x0a) < 0)
  2629. goto err;
  2630. if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x00) < 0)
  2631. goto err;
  2632. }
  2633. }
  2634. if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
  2635. goto err;
  2636. /* AUTO tracking MODE */
  2637. if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x80) < 0)
  2638. goto err;
  2639. /* AUTO tracking MODE */
  2640. if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x80) < 0)
  2641. goto err;
  2642. if ((state->internal->dev_ver >= 0x20) || (blind_tune == 1) ||
  2643. (state->srate < 10000000)) {
  2644. /* update initial carrier freq with the found freq offset */
  2645. if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
  2646. goto err;
  2647. if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
  2648. goto err;
  2649. state->tuner_bw = stv090x_car_width(srate, state->rolloff) + 10000000;
  2650. if ((state->internal->dev_ver >= 0x20) || (blind_tune == 1)) {
  2651. if (state->algo != STV090x_WARM_SEARCH) {
  2652. if (stv090x_i2c_gate_ctrl(state, 1) < 0)
  2653. goto err;
  2654. if (state->config->tuner_set_bandwidth) {
  2655. if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
  2656. goto err_gateoff;
  2657. }
  2658. if (stv090x_i2c_gate_ctrl(state, 0) < 0)
  2659. goto err;
  2660. }
  2661. }
  2662. if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000))
  2663. msleep(50); /* blind search: wait 50ms for SR stabilization */
  2664. else
  2665. msleep(5);
  2666. stv090x_get_lock_tmg(state);
  2667. if (!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) {
  2668. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
  2669. goto err;
  2670. if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
  2671. goto err;
  2672. if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
  2673. goto err;
  2674. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
  2675. goto err;
  2676. i = 0;
  2677. while ((!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) && (i <= 2)) {
  2678. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
  2679. goto err;
  2680. if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
  2681. goto err;
  2682. if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
  2683. goto err;
  2684. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
  2685. goto err;
  2686. i++;
  2687. }
  2688. }
  2689. }
  2690. if (state->internal->dev_ver >= 0x20) {
  2691. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
  2692. goto err;
  2693. }
  2694. if ((state->delsys == STV090x_DVBS1) || (state->delsys == STV090x_DSS))
  2695. stv090x_set_vit_thtracq(state);
  2696. return 0;
  2697. err_gateoff:
  2698. stv090x_i2c_gate_ctrl(state, 0);
  2699. err:
  2700. dprintk(FE_ERROR, 1, "I/O error");
  2701. return -1;
  2702. }
  2703. static int stv090x_get_feclock(struct stv090x_state *state, s32 timeout)
  2704. {
  2705. s32 timer = 0, lock = 0, stat;
  2706. u32 reg;
  2707. while ((timer < timeout) && (!lock)) {
  2708. reg = STV090x_READ_DEMOD(state, DMDSTATE);
  2709. stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
  2710. switch (stat) {
  2711. case 0: /* searching */
  2712. case 1: /* first PLH detected */
  2713. default:
  2714. lock = 0;
  2715. break;
  2716. case 2: /* DVB-S2 mode */
  2717. reg = STV090x_READ_DEMOD(state, PDELSTATUS1);
  2718. lock = STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD);
  2719. break;
  2720. case 3: /* DVB-S1/legacy mode */
  2721. reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
  2722. lock = STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD);
  2723. break;
  2724. }
  2725. if (!lock) {
  2726. msleep(10);
  2727. timer += 10;
  2728. }
  2729. }
  2730. return lock;
  2731. }
  2732. static int stv090x_get_lock(struct stv090x_state *state, s32 timeout_dmd, s32 timeout_fec)
  2733. {
  2734. u32 reg;
  2735. s32 timer = 0;
  2736. int lock;
  2737. lock = stv090x_get_dmdlock(state, timeout_dmd);
  2738. if (lock)
  2739. lock = stv090x_get_feclock(state, timeout_fec);
  2740. if (lock) {
  2741. lock = 0;
  2742. while ((timer < timeout_fec) && (!lock)) {
  2743. reg = STV090x_READ_DEMOD(state, TSSTATUS);
  2744. lock = STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD);
  2745. msleep(1);
  2746. timer++;
  2747. }
  2748. }
  2749. return lock;
  2750. }
  2751. static int stv090x_set_s2rolloff(struct stv090x_state *state)
  2752. {
  2753. u32 reg;
  2754. if (state->internal->dev_ver <= 0x20) {
  2755. /* rolloff to auto mode if DVBS2 */
  2756. reg = STV090x_READ_DEMOD(state, DEMOD);
  2757. STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x00);
  2758. if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
  2759. goto err;
  2760. } else {
  2761. /* DVB-S2 rolloff to auto mode if DVBS2 */
  2762. reg = STV090x_READ_DEMOD(state, DEMOD);
  2763. STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 0x00);
  2764. if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
  2765. goto err;
  2766. }
  2767. return 0;
  2768. err:
  2769. dprintk(FE_ERROR, 1, "I/O error");
  2770. return -1;
  2771. }
  2772. static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state)
  2773. {
  2774. struct dvb_frontend *fe = &state->frontend;
  2775. enum stv090x_signal_state signal_state = STV090x_NOCARRIER;
  2776. u32 reg;
  2777. s32 agc1_power, power_iq = 0, i;
  2778. int lock = 0, low_sr = 0;
  2779. reg = STV090x_READ_DEMOD(state, TSCFGH);
  2780. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* Stop path 1 stream merger */
  2781. if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
  2782. goto err;
  2783. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod stop */
  2784. goto err;
  2785. if (state->internal->dev_ver >= 0x20) {
  2786. if (state->srate > 5000000) {
  2787. if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0)
  2788. goto err;
  2789. } else {
  2790. if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x82) < 0)
  2791. goto err;
  2792. }
  2793. }
  2794. stv090x_get_lock_tmg(state);
  2795. if (state->algo == STV090x_BLIND_SEARCH) {
  2796. state->tuner_bw = 2 * 36000000; /* wide bw for unknown srate */
  2797. if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0) /* wider srate scan */
  2798. goto err;
  2799. if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0)
  2800. goto err;
  2801. if (stv090x_set_srate(state, 1000000) < 0) /* initial srate = 1Msps */
  2802. goto err;
  2803. } else {
  2804. /* known srate */
  2805. if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
  2806. goto err;
  2807. if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
  2808. goto err;
  2809. if (state->srate < 2000000) {
  2810. /* SR < 2MSPS */
  2811. if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x63) < 0)
  2812. goto err;
  2813. } else {
  2814. /* SR >= 2Msps */
  2815. if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0)
  2816. goto err;
  2817. }
  2818. if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
  2819. goto err;
  2820. if (state->internal->dev_ver >= 0x20) {
  2821. if (STV090x_WRITE_DEMOD(state, KREFTMG, 0x5a) < 0)
  2822. goto err;
  2823. if (state->algo == STV090x_COLD_SEARCH)
  2824. state->tuner_bw = (15 * (stv090x_car_width(state->srate, state->rolloff) + 10000000)) / 10;
  2825. else if (state->algo == STV090x_WARM_SEARCH)
  2826. state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + 10000000;
  2827. }
  2828. /* if cold start or warm (Symbolrate is known)
  2829. * use a Narrow symbol rate scan range
  2830. */
  2831. if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0) /* narrow srate scan */
  2832. goto err;
  2833. if (stv090x_set_srate(state, state->srate) < 0)
  2834. goto err;
  2835. if (stv090x_set_max_srate(state, state->internal->mclk,
  2836. state->srate) < 0)
  2837. goto err;
  2838. if (stv090x_set_min_srate(state, state->internal->mclk,
  2839. state->srate) < 0)
  2840. goto err;
  2841. if (state->srate >= 10000000)
  2842. low_sr = 0;
  2843. else
  2844. low_sr = 1;
  2845. }
  2846. /* Setup tuner */
  2847. if (stv090x_i2c_gate_ctrl(state, 1) < 0)
  2848. goto err;
  2849. if (state->config->tuner_set_bbgain) {
  2850. reg = state->config->tuner_bbgain;
  2851. if (reg == 0)
  2852. reg = 10; /* default: 10dB */
  2853. if (state->config->tuner_set_bbgain(fe, reg) < 0)
  2854. goto err_gateoff;
  2855. }
  2856. if (state->config->tuner_set_frequency) {
  2857. if (state->config->tuner_set_frequency(fe, state->frequency) < 0)
  2858. goto err_gateoff;
  2859. }
  2860. if (state->config->tuner_set_bandwidth) {
  2861. if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
  2862. goto err_gateoff;
  2863. }
  2864. if (stv090x_i2c_gate_ctrl(state, 0) < 0)
  2865. goto err;
  2866. msleep(50);
  2867. if (state->config->tuner_get_status) {
  2868. if (stv090x_i2c_gate_ctrl(state, 1) < 0)
  2869. goto err;
  2870. if (state->config->tuner_get_status(fe, &reg) < 0)
  2871. goto err_gateoff;
  2872. if (stv090x_i2c_gate_ctrl(state, 0) < 0)
  2873. goto err;
  2874. if (reg)
  2875. dprintk(FE_DEBUG, 1, "Tuner phase locked");
  2876. else {
  2877. dprintk(FE_DEBUG, 1, "Tuner unlocked");
  2878. return STV090x_NOCARRIER;
  2879. }
  2880. }
  2881. msleep(10);
  2882. agc1_power = MAKEWORD16(STV090x_READ_DEMOD(state, AGCIQIN1),
  2883. STV090x_READ_DEMOD(state, AGCIQIN0));
  2884. if (agc1_power == 0) {
  2885. /* If AGC1 integrator value is 0
  2886. * then read POWERI, POWERQ
  2887. */
  2888. for (i = 0; i < 5; i++) {
  2889. power_iq += (STV090x_READ_DEMOD(state, POWERI) +
  2890. STV090x_READ_DEMOD(state, POWERQ)) >> 1;
  2891. }
  2892. power_iq /= 5;
  2893. }
  2894. if ((agc1_power == 0) && (power_iq < STV090x_IQPOWER_THRESHOLD)) {
  2895. dprintk(FE_ERROR, 1, "No Signal: POWER_IQ=0x%02x", power_iq);
  2896. lock = 0;
  2897. signal_state = STV090x_NOAGC1;
  2898. } else {
  2899. reg = STV090x_READ_DEMOD(state, DEMOD);
  2900. STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, state->inversion);
  2901. if (state->internal->dev_ver <= 0x20) {
  2902. /* rolloff to auto mode if DVBS2 */
  2903. STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 1);
  2904. } else {
  2905. /* DVB-S2 rolloff to auto mode if DVBS2 */
  2906. STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 1);
  2907. }
  2908. if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
  2909. goto err;
  2910. if (stv090x_delivery_search(state) < 0)
  2911. goto err;
  2912. if (state->algo != STV090x_BLIND_SEARCH) {
  2913. if (stv090x_start_search(state) < 0)
  2914. goto err;
  2915. }
  2916. }
  2917. if (signal_state == STV090x_NOAGC1)
  2918. return signal_state;
  2919. if (state->algo == STV090x_BLIND_SEARCH)
  2920. lock = stv090x_blind_search(state);
  2921. else if (state->algo == STV090x_COLD_SEARCH)
  2922. lock = stv090x_get_coldlock(state, state->DemodTimeout);
  2923. else if (state->algo == STV090x_WARM_SEARCH)
  2924. lock = stv090x_get_dmdlock(state, state->DemodTimeout);
  2925. if ((!lock) && (state->algo == STV090x_COLD_SEARCH)) {
  2926. if (!low_sr) {
  2927. if (stv090x_chk_tmg(state))
  2928. lock = stv090x_sw_algo(state);
  2929. }
  2930. }
  2931. if (lock)
  2932. signal_state = stv090x_get_sig_params(state);
  2933. if ((lock) && (signal_state == STV090x_RANGEOK)) { /* signal within Range */
  2934. stv090x_optimize_track(state);
  2935. if (state->internal->dev_ver >= 0x20) {
  2936. /* >= Cut 2.0 :release TS reset after
  2937. * demod lock and optimized Tracking
  2938. */
  2939. reg = STV090x_READ_DEMOD(state, TSCFGH);
  2940. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
  2941. if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
  2942. goto err;
  2943. msleep(3);
  2944. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* merger reset */
  2945. if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
  2946. goto err;
  2947. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
  2948. if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
  2949. goto err;
  2950. }
  2951. lock = stv090x_get_lock(state, state->FecTimeout,
  2952. state->FecTimeout);
  2953. if (lock) {
  2954. if (state->delsys == STV090x_DVBS2) {
  2955. stv090x_set_s2rolloff(state);
  2956. reg = STV090x_READ_DEMOD(state, PDELCTRL2);
  2957. STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 1);
  2958. if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0)
  2959. goto err;
  2960. /* Reset DVBS2 packet delinator error counter */
  2961. reg = STV090x_READ_DEMOD(state, PDELCTRL2);
  2962. STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 0);
  2963. if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0)
  2964. goto err;
  2965. if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67) < 0) /* PER */
  2966. goto err;
  2967. } else {
  2968. if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
  2969. goto err;
  2970. }
  2971. /* Reset the Total packet counter */
  2972. if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0x00) < 0)
  2973. goto err;
  2974. /* Reset the packet Error counter2 */
  2975. if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
  2976. goto err;
  2977. } else {
  2978. signal_state = STV090x_NODATA;
  2979. stv090x_chk_signal(state);
  2980. }
  2981. }
  2982. return signal_state;
  2983. err_gateoff:
  2984. stv090x_i2c_gate_ctrl(state, 0);
  2985. err:
  2986. dprintk(FE_ERROR, 1, "I/O error");
  2987. return -1;
  2988. }
  2989. static int stv090x_set_pls(struct stv090x_state *state, u32 pls_code)
  2990. {
  2991. dprintk(FE_DEBUG, 1, "Set Gold PLS code %d", pls_code);
  2992. if (STV090x_WRITE_DEMOD(state, PLROOT0, pls_code & 0xff) < 0)
  2993. goto err;
  2994. if (STV090x_WRITE_DEMOD(state, PLROOT1, (pls_code >> 8) & 0xff) < 0)
  2995. goto err;
  2996. if (STV090x_WRITE_DEMOD(state, PLROOT2, 0x04 | (pls_code >> 16)) < 0)
  2997. goto err;
  2998. return 0;
  2999. err:
  3000. dprintk(FE_ERROR, 1, "I/O error");
  3001. return -1;
  3002. }
  3003. static int stv090x_set_mis(struct stv090x_state *state, int mis)
  3004. {
  3005. u32 reg;
  3006. if (mis < 0 || mis > 255) {
  3007. dprintk(FE_DEBUG, 1, "Disable MIS filtering");
  3008. reg = STV090x_READ_DEMOD(state, PDELCTRL1);
  3009. STV090x_SETFIELD_Px(reg, FILTER_EN_FIELD, 0x00);
  3010. if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
  3011. goto err;
  3012. } else {
  3013. dprintk(FE_DEBUG, 1, "Enable MIS filtering - %d", mis);
  3014. reg = STV090x_READ_DEMOD(state, PDELCTRL1);
  3015. STV090x_SETFIELD_Px(reg, FILTER_EN_FIELD, 0x01);
  3016. if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
  3017. goto err;
  3018. if (STV090x_WRITE_DEMOD(state, ISIENTRY, mis) < 0)
  3019. goto err;
  3020. if (STV090x_WRITE_DEMOD(state, ISIBITENA, 0xff) < 0)
  3021. goto err;
  3022. }
  3023. return 0;
  3024. err:
  3025. dprintk(FE_ERROR, 1, "I/O error");
  3026. return -1;
  3027. }
  3028. static enum dvbfe_search stv090x_search(struct dvb_frontend *fe)
  3029. {
  3030. struct stv090x_state *state = fe->demodulator_priv;
  3031. struct dtv_frontend_properties *props = &fe->dtv_property_cache;
  3032. if (props->frequency == 0)
  3033. return DVBFE_ALGO_SEARCH_INVALID;
  3034. switch (props->delivery_system) {
  3035. case SYS_DSS:
  3036. state->delsys = STV090x_DSS;
  3037. break;
  3038. case SYS_DVBS:
  3039. state->delsys = STV090x_DVBS1;
  3040. break;
  3041. case SYS_DVBS2:
  3042. state->delsys = STV090x_DVBS2;
  3043. break;
  3044. default:
  3045. return DVBFE_ALGO_SEARCH_INVALID;
  3046. }
  3047. state->frequency = props->frequency;
  3048. state->srate = props->symbol_rate;
  3049. state->search_mode = STV090x_SEARCH_AUTO;
  3050. state->algo = STV090x_COLD_SEARCH;
  3051. state->fec = STV090x_PRERR;
  3052. if (state->srate > 10000000) {
  3053. dprintk(FE_DEBUG, 1, "Search range: 10 MHz");
  3054. state->search_range = 10000000;
  3055. } else {
  3056. dprintk(FE_DEBUG, 1, "Search range: 5 MHz");
  3057. state->search_range = 5000000;
  3058. }
  3059. stv090x_set_pls(state, props->scrambling_sequence_index);
  3060. stv090x_set_mis(state, props->stream_id);
  3061. if (stv090x_algo(state) == STV090x_RANGEOK) {
  3062. dprintk(FE_DEBUG, 1, "Search success!");
  3063. return DVBFE_ALGO_SEARCH_SUCCESS;
  3064. } else {
  3065. dprintk(FE_DEBUG, 1, "Search failed!");
  3066. return DVBFE_ALGO_SEARCH_FAILED;
  3067. }
  3068. return DVBFE_ALGO_SEARCH_ERROR;
  3069. }
  3070. static int stv090x_read_status(struct dvb_frontend *fe, enum fe_status *status)
  3071. {
  3072. struct stv090x_state *state = fe->demodulator_priv;
  3073. u32 reg, dstatus;
  3074. u8 search_state;
  3075. *status = 0;
  3076. dstatus = STV090x_READ_DEMOD(state, DSTATUS);
  3077. if (STV090x_GETFIELD_Px(dstatus, CAR_LOCK_FIELD))
  3078. *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER;
  3079. reg = STV090x_READ_DEMOD(state, DMDSTATE);
  3080. search_state = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
  3081. switch (search_state) {
  3082. case 0: /* searching */
  3083. case 1: /* first PLH detected */
  3084. default:
  3085. dprintk(FE_DEBUG, 1, "Status: Unlocked (Searching ..)");
  3086. break;
  3087. case 2: /* DVB-S2 mode */
  3088. dprintk(FE_DEBUG, 1, "Delivery system: DVB-S2");
  3089. if (STV090x_GETFIELD_Px(dstatus, LOCK_DEFINITIF_FIELD)) {
  3090. reg = STV090x_READ_DEMOD(state, PDELSTATUS1);
  3091. if (STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD)) {
  3092. *status |= FE_HAS_VITERBI;
  3093. reg = STV090x_READ_DEMOD(state, TSSTATUS);
  3094. if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD))
  3095. *status |= FE_HAS_SYNC | FE_HAS_LOCK;
  3096. }
  3097. }
  3098. break;
  3099. case 3: /* DVB-S1/legacy mode */
  3100. dprintk(FE_DEBUG, 1, "Delivery system: DVB-S");
  3101. if (STV090x_GETFIELD_Px(dstatus, LOCK_DEFINITIF_FIELD)) {
  3102. reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
  3103. if (STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD)) {
  3104. *status |= FE_HAS_VITERBI;
  3105. reg = STV090x_READ_DEMOD(state, TSSTATUS);
  3106. if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD))
  3107. *status |= FE_HAS_SYNC | FE_HAS_LOCK;
  3108. }
  3109. }
  3110. break;
  3111. }
  3112. return 0;
  3113. }
  3114. static int stv090x_read_per(struct dvb_frontend *fe, u32 *per)
  3115. {
  3116. struct stv090x_state *state = fe->demodulator_priv;
  3117. s32 count_4, count_3, count_2, count_1, count_0, count;
  3118. u32 reg, h, m, l;
  3119. enum fe_status status;
  3120. stv090x_read_status(fe, &status);
  3121. if (!(status & FE_HAS_LOCK)) {
  3122. *per = 1 << 23; /* Max PER */
  3123. } else {
  3124. /* Counter 2 */
  3125. reg = STV090x_READ_DEMOD(state, ERRCNT22);
  3126. h = STV090x_GETFIELD_Px(reg, ERR_CNT2_FIELD);
  3127. reg = STV090x_READ_DEMOD(state, ERRCNT21);
  3128. m = STV090x_GETFIELD_Px(reg, ERR_CNT21_FIELD);
  3129. reg = STV090x_READ_DEMOD(state, ERRCNT20);
  3130. l = STV090x_GETFIELD_Px(reg, ERR_CNT20_FIELD);
  3131. *per = ((h << 16) | (m << 8) | l);
  3132. count_4 = STV090x_READ_DEMOD(state, FBERCPT4);
  3133. count_3 = STV090x_READ_DEMOD(state, FBERCPT3);
  3134. count_2 = STV090x_READ_DEMOD(state, FBERCPT2);
  3135. count_1 = STV090x_READ_DEMOD(state, FBERCPT1);
  3136. count_0 = STV090x_READ_DEMOD(state, FBERCPT0);
  3137. if ((!count_4) && (!count_3)) {
  3138. count = (count_2 & 0xff) << 16;
  3139. count |= (count_1 & 0xff) << 8;
  3140. count |= count_0 & 0xff;
  3141. } else {
  3142. count = 1 << 24;
  3143. }
  3144. if (count == 0)
  3145. *per = 1;
  3146. }
  3147. if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0) < 0)
  3148. goto err;
  3149. if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
  3150. goto err;
  3151. return 0;
  3152. err:
  3153. dprintk(FE_ERROR, 1, "I/O error");
  3154. return -1;
  3155. }
  3156. static int stv090x_table_lookup(const struct stv090x_tab *tab, int max, int val)
  3157. {
  3158. int res = 0;
  3159. int min = 0, med;
  3160. if ((val >= tab[min].read && val < tab[max].read) ||
  3161. (val >= tab[max].read && val < tab[min].read)) {
  3162. while ((max - min) > 1) {
  3163. med = (max + min) / 2;
  3164. if ((val >= tab[min].read && val < tab[med].read) ||
  3165. (val >= tab[med].read && val < tab[min].read))
  3166. max = med;
  3167. else
  3168. min = med;
  3169. }
  3170. res = ((val - tab[min].read) *
  3171. (tab[max].real - tab[min].real) /
  3172. (tab[max].read - tab[min].read)) +
  3173. tab[min].real;
  3174. } else {
  3175. if (tab[min].read < tab[max].read) {
  3176. if (val < tab[min].read)
  3177. res = tab[min].real;
  3178. else if (val >= tab[max].read)
  3179. res = tab[max].real;
  3180. } else {
  3181. if (val >= tab[min].read)
  3182. res = tab[min].real;
  3183. else if (val < tab[max].read)
  3184. res = tab[max].real;
  3185. }
  3186. }
  3187. return res;
  3188. }
  3189. static int stv090x_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
  3190. {
  3191. struct stv090x_state *state = fe->demodulator_priv;
  3192. u32 reg;
  3193. s32 agc_0, agc_1, agc;
  3194. s32 str;
  3195. reg = STV090x_READ_DEMOD(state, AGCIQIN1);
  3196. agc_1 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD);
  3197. reg = STV090x_READ_DEMOD(state, AGCIQIN0);
  3198. agc_0 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD);
  3199. agc = MAKEWORD16(agc_1, agc_0);
  3200. str = stv090x_table_lookup(stv090x_rf_tab,
  3201. ARRAY_SIZE(stv090x_rf_tab) - 1, agc);
  3202. if (agc > stv090x_rf_tab[0].read)
  3203. str = 0;
  3204. else if (agc < stv090x_rf_tab[ARRAY_SIZE(stv090x_rf_tab) - 1].read)
  3205. str = -100;
  3206. *strength = (str + 100) * 0xFFFF / 100;
  3207. return 0;
  3208. }
  3209. static int stv090x_read_cnr(struct dvb_frontend *fe, u16 *cnr)
  3210. {
  3211. struct stv090x_state *state = fe->demodulator_priv;
  3212. u32 reg_0, reg_1, reg, i;
  3213. s32 val_0, val_1, val = 0;
  3214. u8 lock_f;
  3215. s32 div;
  3216. u32 last;
  3217. switch (state->delsys) {
  3218. case STV090x_DVBS2:
  3219. reg = STV090x_READ_DEMOD(state, DSTATUS);
  3220. lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
  3221. if (lock_f) {
  3222. msleep(5);
  3223. for (i = 0; i < 16; i++) {
  3224. reg_1 = STV090x_READ_DEMOD(state, NNOSPLHT1);
  3225. val_1 = STV090x_GETFIELD_Px(reg_1, NOSPLHT_NORMED_FIELD);
  3226. reg_0 = STV090x_READ_DEMOD(state, NNOSPLHT0);
  3227. val_0 = STV090x_GETFIELD_Px(reg_0, NOSPLHT_NORMED_FIELD);
  3228. val += MAKEWORD16(val_1, val_0);
  3229. msleep(1);
  3230. }
  3231. val /= 16;
  3232. last = ARRAY_SIZE(stv090x_s2cn_tab) - 1;
  3233. div = stv090x_s2cn_tab[last].real -
  3234. stv090x_s2cn_tab[3].real;
  3235. val = stv090x_table_lookup(stv090x_s2cn_tab, last, val);
  3236. if (val < 0)
  3237. val = 0;
  3238. *cnr = val * 0xFFFF / div;
  3239. }
  3240. break;
  3241. case STV090x_DVBS1:
  3242. case STV090x_DSS:
  3243. reg = STV090x_READ_DEMOD(state, DSTATUS);
  3244. lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
  3245. if (lock_f) {
  3246. msleep(5);
  3247. for (i = 0; i < 16; i++) {
  3248. reg_1 = STV090x_READ_DEMOD(state, NOSDATAT1);
  3249. val_1 = STV090x_GETFIELD_Px(reg_1, NOSDATAT_UNNORMED_FIELD);
  3250. reg_0 = STV090x_READ_DEMOD(state, NOSDATAT0);
  3251. val_0 = STV090x_GETFIELD_Px(reg_0, NOSDATAT_UNNORMED_FIELD);
  3252. val += MAKEWORD16(val_1, val_0);
  3253. msleep(1);
  3254. }
  3255. val /= 16;
  3256. last = ARRAY_SIZE(stv090x_s1cn_tab) - 1;
  3257. div = stv090x_s1cn_tab[last].real -
  3258. stv090x_s1cn_tab[0].real;
  3259. val = stv090x_table_lookup(stv090x_s1cn_tab, last, val);
  3260. *cnr = val * 0xFFFF / div;
  3261. }
  3262. break;
  3263. default:
  3264. break;
  3265. }
  3266. return 0;
  3267. }
  3268. static int stv090x_set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone)
  3269. {
  3270. struct stv090x_state *state = fe->demodulator_priv;
  3271. u32 reg;
  3272. reg = STV090x_READ_DEMOD(state, DISTXCTL);
  3273. switch (tone) {
  3274. case SEC_TONE_ON:
  3275. STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
  3276. STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
  3277. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3278. goto err;
  3279. STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
  3280. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3281. goto err;
  3282. break;
  3283. case SEC_TONE_OFF:
  3284. STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
  3285. STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
  3286. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3287. goto err;
  3288. break;
  3289. default:
  3290. return -EINVAL;
  3291. }
  3292. return 0;
  3293. err:
  3294. dprintk(FE_ERROR, 1, "I/O error");
  3295. return -1;
  3296. }
  3297. static enum dvbfe_algo stv090x_frontend_algo(struct dvb_frontend *fe)
  3298. {
  3299. return DVBFE_ALGO_CUSTOM;
  3300. }
  3301. static int stv090x_send_diseqc_msg(struct dvb_frontend *fe, struct dvb_diseqc_master_cmd *cmd)
  3302. {
  3303. struct stv090x_state *state = fe->demodulator_priv;
  3304. u32 reg, idle = 0, fifo_full = 1;
  3305. int i;
  3306. reg = STV090x_READ_DEMOD(state, DISTXCTL);
  3307. STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD,
  3308. (state->config->diseqc_envelope_mode) ? 4 : 2);
  3309. STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
  3310. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3311. goto err;
  3312. STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
  3313. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3314. goto err;
  3315. STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1);
  3316. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3317. goto err;
  3318. for (i = 0; i < cmd->msg_len; i++) {
  3319. while (fifo_full) {
  3320. reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
  3321. fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD);
  3322. }
  3323. if (STV090x_WRITE_DEMOD(state, DISTXDATA, cmd->msg[i]) < 0)
  3324. goto err;
  3325. }
  3326. reg = STV090x_READ_DEMOD(state, DISTXCTL);
  3327. STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0);
  3328. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3329. goto err;
  3330. i = 0;
  3331. while ((!idle) && (i < 10)) {
  3332. reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
  3333. idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD);
  3334. msleep(10);
  3335. i++;
  3336. }
  3337. return 0;
  3338. err:
  3339. dprintk(FE_ERROR, 1, "I/O error");
  3340. return -1;
  3341. }
  3342. static int stv090x_send_diseqc_burst(struct dvb_frontend *fe,
  3343. enum fe_sec_mini_cmd burst)
  3344. {
  3345. struct stv090x_state *state = fe->demodulator_priv;
  3346. u32 reg, idle = 0, fifo_full = 1;
  3347. u8 mode, value;
  3348. int i;
  3349. reg = STV090x_READ_DEMOD(state, DISTXCTL);
  3350. if (burst == SEC_MINI_A) {
  3351. mode = (state->config->diseqc_envelope_mode) ? 5 : 3;
  3352. value = 0x00;
  3353. } else {
  3354. mode = (state->config->diseqc_envelope_mode) ? 4 : 2;
  3355. value = 0xFF;
  3356. }
  3357. STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, mode);
  3358. STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
  3359. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3360. goto err;
  3361. STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
  3362. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3363. goto err;
  3364. STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1);
  3365. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3366. goto err;
  3367. while (fifo_full) {
  3368. reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
  3369. fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD);
  3370. }
  3371. if (STV090x_WRITE_DEMOD(state, DISTXDATA, value) < 0)
  3372. goto err;
  3373. reg = STV090x_READ_DEMOD(state, DISTXCTL);
  3374. STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0);
  3375. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3376. goto err;
  3377. i = 0;
  3378. while ((!idle) && (i < 10)) {
  3379. reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
  3380. idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD);
  3381. msleep(10);
  3382. i++;
  3383. }
  3384. return 0;
  3385. err:
  3386. dprintk(FE_ERROR, 1, "I/O error");
  3387. return -1;
  3388. }
  3389. static int stv090x_recv_slave_reply(struct dvb_frontend *fe, struct dvb_diseqc_slave_reply *reply)
  3390. {
  3391. struct stv090x_state *state = fe->demodulator_priv;
  3392. u32 reg = 0, i = 0, rx_end = 0;
  3393. while ((rx_end != 1) && (i < 10)) {
  3394. msleep(10);
  3395. i++;
  3396. reg = STV090x_READ_DEMOD(state, DISRX_ST0);
  3397. rx_end = STV090x_GETFIELD_Px(reg, RX_END_FIELD);
  3398. }
  3399. if (rx_end) {
  3400. reply->msg_len = STV090x_GETFIELD_Px(reg, FIFO_BYTENBR_FIELD);
  3401. for (i = 0; i < reply->msg_len; i++)
  3402. reply->msg[i] = STV090x_READ_DEMOD(state, DISRXDATA);
  3403. }
  3404. return 0;
  3405. }
  3406. static int stv090x_sleep(struct dvb_frontend *fe)
  3407. {
  3408. struct stv090x_state *state = fe->demodulator_priv;
  3409. u32 reg;
  3410. u8 full_standby = 0;
  3411. if (stv090x_i2c_gate_ctrl(state, 1) < 0)
  3412. goto err;
  3413. if (state->config->tuner_sleep) {
  3414. if (state->config->tuner_sleep(fe) < 0)
  3415. goto err_gateoff;
  3416. }
  3417. if (stv090x_i2c_gate_ctrl(state, 0) < 0)
  3418. goto err;
  3419. dprintk(FE_DEBUG, 1, "Set %s(%d) to sleep",
  3420. state->device == STV0900 ? "STV0900" : "STV0903",
  3421. state->demod);
  3422. mutex_lock(&state->internal->demod_lock);
  3423. switch (state->demod) {
  3424. case STV090x_DEMODULATOR_0:
  3425. /* power off ADC 1 */
  3426. reg = stv090x_read_reg(state, STV090x_TSTTNR1);
  3427. STV090x_SETFIELD(reg, ADC1_PON_FIELD, 0);
  3428. if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
  3429. goto err_unlock;
  3430. /* power off DiSEqC 1 */
  3431. reg = stv090x_read_reg(state, STV090x_TSTTNR2);
  3432. STV090x_SETFIELD(reg, DISEQC1_PON_FIELD, 0);
  3433. if (stv090x_write_reg(state, STV090x_TSTTNR2, reg) < 0)
  3434. goto err_unlock;
  3435. /* check whether path 2 is already sleeping, that is when
  3436. ADC2 is off */
  3437. reg = stv090x_read_reg(state, STV090x_TSTTNR3);
  3438. if (STV090x_GETFIELD(reg, ADC2_PON_FIELD) == 0)
  3439. full_standby = 1;
  3440. /* stop clocks */
  3441. reg = stv090x_read_reg(state, STV090x_STOPCLK1);
  3442. /* packet delineator 1 clock */
  3443. STV090x_SETFIELD(reg, STOP_CLKPKDT1_FIELD, 1);
  3444. /* ADC 1 clock */
  3445. STV090x_SETFIELD(reg, STOP_CLKADCI1_FIELD, 1);
  3446. /* FEC clock is shared between the two paths, only stop it
  3447. when full standby is possible */
  3448. if (full_standby)
  3449. STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 1);
  3450. if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0)
  3451. goto err_unlock;
  3452. reg = stv090x_read_reg(state, STV090x_STOPCLK2);
  3453. /* sampling 1 clock */
  3454. STV090x_SETFIELD(reg, STOP_CLKSAMP1_FIELD, 1);
  3455. /* viterbi 1 clock */
  3456. STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, 1);
  3457. /* TS clock is shared between the two paths, only stop it
  3458. when full standby is possible */
  3459. if (full_standby)
  3460. STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 1);
  3461. if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
  3462. goto err_unlock;
  3463. break;
  3464. case STV090x_DEMODULATOR_1:
  3465. /* power off ADC 2 */
  3466. reg = stv090x_read_reg(state, STV090x_TSTTNR3);
  3467. STV090x_SETFIELD(reg, ADC2_PON_FIELD, 0);
  3468. if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0)
  3469. goto err_unlock;
  3470. /* power off DiSEqC 2 */
  3471. reg = stv090x_read_reg(state, STV090x_TSTTNR4);
  3472. STV090x_SETFIELD(reg, DISEQC2_PON_FIELD, 0);
  3473. if (stv090x_write_reg(state, STV090x_TSTTNR4, reg) < 0)
  3474. goto err_unlock;
  3475. /* check whether path 1 is already sleeping, that is when
  3476. ADC1 is off */
  3477. reg = stv090x_read_reg(state, STV090x_TSTTNR1);
  3478. if (STV090x_GETFIELD(reg, ADC1_PON_FIELD) == 0)
  3479. full_standby = 1;
  3480. /* stop clocks */
  3481. reg = stv090x_read_reg(state, STV090x_STOPCLK1);
  3482. /* packet delineator 2 clock */
  3483. STV090x_SETFIELD(reg, STOP_CLKPKDT2_FIELD, 1);
  3484. /* ADC 2 clock */
  3485. STV090x_SETFIELD(reg, STOP_CLKADCI2_FIELD, 1);
  3486. /* FEC clock is shared between the two paths, only stop it
  3487. when full standby is possible */
  3488. if (full_standby)
  3489. STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 1);
  3490. if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0)
  3491. goto err_unlock;
  3492. reg = stv090x_read_reg(state, STV090x_STOPCLK2);
  3493. /* sampling 2 clock */
  3494. STV090x_SETFIELD(reg, STOP_CLKSAMP2_FIELD, 1);
  3495. /* viterbi 2 clock */
  3496. STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, 1);
  3497. /* TS clock is shared between the two paths, only stop it
  3498. when full standby is possible */
  3499. if (full_standby)
  3500. STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 1);
  3501. if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
  3502. goto err_unlock;
  3503. break;
  3504. default:
  3505. dprintk(FE_ERROR, 1, "Wrong demodulator!");
  3506. break;
  3507. }
  3508. if (full_standby) {
  3509. /* general power off */
  3510. reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
  3511. STV090x_SETFIELD(reg, STANDBY_FIELD, 0x01);
  3512. if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
  3513. goto err_unlock;
  3514. }
  3515. mutex_unlock(&state->internal->demod_lock);
  3516. return 0;
  3517. err_gateoff:
  3518. stv090x_i2c_gate_ctrl(state, 0);
  3519. goto err;
  3520. err_unlock:
  3521. mutex_unlock(&state->internal->demod_lock);
  3522. err:
  3523. dprintk(FE_ERROR, 1, "I/O error");
  3524. return -1;
  3525. }
  3526. static int stv090x_wakeup(struct dvb_frontend *fe)
  3527. {
  3528. struct stv090x_state *state = fe->demodulator_priv;
  3529. u32 reg;
  3530. dprintk(FE_DEBUG, 1, "Wake %s(%d) from standby",
  3531. state->device == STV0900 ? "STV0900" : "STV0903",
  3532. state->demod);
  3533. mutex_lock(&state->internal->demod_lock);
  3534. /* general power on */
  3535. reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
  3536. STV090x_SETFIELD(reg, STANDBY_FIELD, 0x00);
  3537. if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
  3538. goto err;
  3539. switch (state->demod) {
  3540. case STV090x_DEMODULATOR_0:
  3541. /* power on ADC 1 */
  3542. reg = stv090x_read_reg(state, STV090x_TSTTNR1);
  3543. STV090x_SETFIELD(reg, ADC1_PON_FIELD, 1);
  3544. if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
  3545. goto err;
  3546. /* power on DiSEqC 1 */
  3547. reg = stv090x_read_reg(state, STV090x_TSTTNR2);
  3548. STV090x_SETFIELD(reg, DISEQC1_PON_FIELD, 1);
  3549. if (stv090x_write_reg(state, STV090x_TSTTNR2, reg) < 0)
  3550. goto err;
  3551. /* activate clocks */
  3552. reg = stv090x_read_reg(state, STV090x_STOPCLK1);
  3553. /* packet delineator 1 clock */
  3554. STV090x_SETFIELD(reg, STOP_CLKPKDT1_FIELD, 0);
  3555. /* ADC 1 clock */
  3556. STV090x_SETFIELD(reg, STOP_CLKADCI1_FIELD, 0);
  3557. /* FEC clock */
  3558. STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 0);
  3559. if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0)
  3560. goto err;
  3561. reg = stv090x_read_reg(state, STV090x_STOPCLK2);
  3562. /* sampling 1 clock */
  3563. STV090x_SETFIELD(reg, STOP_CLKSAMP1_FIELD, 0);
  3564. /* viterbi 1 clock */
  3565. STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, 0);
  3566. /* TS clock */
  3567. STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 0);
  3568. if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
  3569. goto err;
  3570. break;
  3571. case STV090x_DEMODULATOR_1:
  3572. /* power on ADC 2 */
  3573. reg = stv090x_read_reg(state, STV090x_TSTTNR3);
  3574. STV090x_SETFIELD(reg, ADC2_PON_FIELD, 1);
  3575. if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0)
  3576. goto err;
  3577. /* power on DiSEqC 2 */
  3578. reg = stv090x_read_reg(state, STV090x_TSTTNR4);
  3579. STV090x_SETFIELD(reg, DISEQC2_PON_FIELD, 1);
  3580. if (stv090x_write_reg(state, STV090x_TSTTNR4, reg) < 0)
  3581. goto err;
  3582. /* activate clocks */
  3583. reg = stv090x_read_reg(state, STV090x_STOPCLK1);
  3584. /* packet delineator 2 clock */
  3585. STV090x_SETFIELD(reg, STOP_CLKPKDT2_FIELD, 0);
  3586. /* ADC 2 clock */
  3587. STV090x_SETFIELD(reg, STOP_CLKADCI2_FIELD, 0);
  3588. /* FEC clock */
  3589. STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 0);
  3590. if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0)
  3591. goto err;
  3592. reg = stv090x_read_reg(state, STV090x_STOPCLK2);
  3593. /* sampling 2 clock */
  3594. STV090x_SETFIELD(reg, STOP_CLKSAMP2_FIELD, 0);
  3595. /* viterbi 2 clock */
  3596. STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, 0);
  3597. /* TS clock */
  3598. STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 0);
  3599. if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
  3600. goto err;
  3601. break;
  3602. default:
  3603. dprintk(FE_ERROR, 1, "Wrong demodulator!");
  3604. break;
  3605. }
  3606. mutex_unlock(&state->internal->demod_lock);
  3607. return 0;
  3608. err:
  3609. mutex_unlock(&state->internal->demod_lock);
  3610. dprintk(FE_ERROR, 1, "I/O error");
  3611. return -1;
  3612. }
  3613. static void stv090x_release(struct dvb_frontend *fe)
  3614. {
  3615. struct stv090x_state *state = fe->demodulator_priv;
  3616. state->internal->num_used--;
  3617. if (state->internal->num_used <= 0) {
  3618. dprintk(FE_ERROR, 1, "Actually removing");
  3619. remove_dev(state->internal);
  3620. kfree(state->internal);
  3621. }
  3622. kfree(state);
  3623. }
  3624. static int stv090x_ldpc_mode(struct stv090x_state *state, enum stv090x_mode ldpc_mode)
  3625. {
  3626. u32 reg = 0;
  3627. reg = stv090x_read_reg(state, STV090x_GENCFG);
  3628. switch (ldpc_mode) {
  3629. case STV090x_DUAL:
  3630. default:
  3631. if ((state->demod_mode != STV090x_DUAL) || (STV090x_GETFIELD(reg, DDEMOD_FIELD) != 1)) {
  3632. /* set LDPC to dual mode */
  3633. if (stv090x_write_reg(state, STV090x_GENCFG, 0x1d) < 0)
  3634. goto err;
  3635. state->demod_mode = STV090x_DUAL;
  3636. reg = stv090x_read_reg(state, STV090x_TSTRES0);
  3637. STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
  3638. if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
  3639. goto err;
  3640. STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
  3641. if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
  3642. goto err;
  3643. if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
  3644. goto err;
  3645. if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0)
  3646. goto err;
  3647. if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0)
  3648. goto err;
  3649. if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0)
  3650. goto err;
  3651. if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0)
  3652. goto err;
  3653. if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0)
  3654. goto err;
  3655. if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0)
  3656. goto err;
  3657. if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0)
  3658. goto err;
  3659. if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0)
  3660. goto err;
  3661. if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0)
  3662. goto err;
  3663. if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0)
  3664. goto err;
  3665. if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0)
  3666. goto err;
  3667. if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0)
  3668. goto err;
  3669. if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0)
  3670. goto err;
  3671. if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0)
  3672. goto err;
  3673. if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0)
  3674. goto err;
  3675. }
  3676. break;
  3677. case STV090x_SINGLE:
  3678. if (stv090x_stop_modcod(state) < 0)
  3679. goto err;
  3680. if (stv090x_activate_modcod_single(state) < 0)
  3681. goto err;
  3682. if (state->demod == STV090x_DEMODULATOR_1) {
  3683. if (stv090x_write_reg(state, STV090x_GENCFG, 0x06) < 0) /* path 2 */
  3684. goto err;
  3685. } else {
  3686. if (stv090x_write_reg(state, STV090x_GENCFG, 0x04) < 0) /* path 1 */
  3687. goto err;
  3688. }
  3689. reg = stv090x_read_reg(state, STV090x_TSTRES0);
  3690. STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
  3691. if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
  3692. goto err;
  3693. STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
  3694. if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
  3695. goto err;
  3696. reg = STV090x_READ_DEMOD(state, PDELCTRL1);
  3697. STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x01);
  3698. if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
  3699. goto err;
  3700. STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x00);
  3701. if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
  3702. goto err;
  3703. break;
  3704. }
  3705. return 0;
  3706. err:
  3707. dprintk(FE_ERROR, 1, "I/O error");
  3708. return -1;
  3709. }
  3710. /* return (Hz), clk in Hz*/
  3711. static u32 stv090x_get_mclk(struct stv090x_state *state)
  3712. {
  3713. const struct stv090x_config *config = state->config;
  3714. u32 div, reg;
  3715. u8 ratio;
  3716. div = stv090x_read_reg(state, STV090x_NCOARSE);
  3717. reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
  3718. ratio = STV090x_GETFIELD(reg, SELX1RATIO_FIELD) ? 4 : 6;
  3719. return (div + 1) * config->xtal / ratio; /* kHz */
  3720. }
  3721. static int stv090x_set_mclk(struct stv090x_state *state, u32 mclk, u32 clk)
  3722. {
  3723. const struct stv090x_config *config = state->config;
  3724. u32 reg, div, clk_sel;
  3725. reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
  3726. clk_sel = ((STV090x_GETFIELD(reg, SELX1RATIO_FIELD) == 1) ? 4 : 6);
  3727. div = ((clk_sel * mclk) / config->xtal) - 1;
  3728. reg = stv090x_read_reg(state, STV090x_NCOARSE);
  3729. STV090x_SETFIELD(reg, M_DIV_FIELD, div);
  3730. if (stv090x_write_reg(state, STV090x_NCOARSE, reg) < 0)
  3731. goto err;
  3732. state->internal->mclk = stv090x_get_mclk(state);
  3733. /*Set the DiseqC frequency to 22KHz */
  3734. div = state->internal->mclk / 704000;
  3735. if (STV090x_WRITE_DEMOD(state, F22TX, div) < 0)
  3736. goto err;
  3737. if (STV090x_WRITE_DEMOD(state, F22RX, div) < 0)
  3738. goto err;
  3739. return 0;
  3740. err:
  3741. dprintk(FE_ERROR, 1, "I/O error");
  3742. return -1;
  3743. }
  3744. static int stv0900_set_tspath(struct stv090x_state *state)
  3745. {
  3746. u32 reg;
  3747. if (state->internal->dev_ver >= 0x20) {
  3748. switch (state->config->ts1_mode) {
  3749. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3750. case STV090x_TSMODE_DVBCI:
  3751. switch (state->config->ts2_mode) {
  3752. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3753. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3754. default:
  3755. stv090x_write_reg(state, STV090x_TSGENERAL, 0x00);
  3756. break;
  3757. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3758. case STV090x_TSMODE_DVBCI:
  3759. if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x06) < 0) /* Mux'd stream mode */
  3760. goto err;
  3761. reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
  3762. STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
  3763. if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
  3764. goto err;
  3765. reg = stv090x_read_reg(state, STV090x_P2_TSCFGM);
  3766. STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
  3767. if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0)
  3768. goto err;
  3769. if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
  3770. goto err;
  3771. if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
  3772. goto err;
  3773. break;
  3774. }
  3775. break;
  3776. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3777. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3778. default:
  3779. switch (state->config->ts2_mode) {
  3780. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3781. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3782. default:
  3783. if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
  3784. goto err;
  3785. break;
  3786. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3787. case STV090x_TSMODE_DVBCI:
  3788. if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0a) < 0)
  3789. goto err;
  3790. break;
  3791. }
  3792. break;
  3793. }
  3794. } else {
  3795. switch (state->config->ts1_mode) {
  3796. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3797. case STV090x_TSMODE_DVBCI:
  3798. switch (state->config->ts2_mode) {
  3799. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3800. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3801. default:
  3802. stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x10);
  3803. break;
  3804. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3805. case STV090x_TSMODE_DVBCI:
  3806. stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x16);
  3807. reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
  3808. STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
  3809. if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
  3810. goto err;
  3811. reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
  3812. STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 0);
  3813. if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
  3814. goto err;
  3815. if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
  3816. goto err;
  3817. if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
  3818. goto err;
  3819. break;
  3820. }
  3821. break;
  3822. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3823. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3824. default:
  3825. switch (state->config->ts2_mode) {
  3826. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3827. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3828. default:
  3829. stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x14);
  3830. break;
  3831. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3832. case STV090x_TSMODE_DVBCI:
  3833. stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x12);
  3834. break;
  3835. }
  3836. break;
  3837. }
  3838. }
  3839. switch (state->config->ts1_mode) {
  3840. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3841. reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
  3842. STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei);
  3843. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
  3844. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
  3845. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  3846. goto err;
  3847. break;
  3848. case STV090x_TSMODE_DVBCI:
  3849. reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
  3850. STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei);
  3851. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
  3852. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
  3853. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  3854. goto err;
  3855. break;
  3856. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3857. reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
  3858. STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei);
  3859. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
  3860. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
  3861. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  3862. goto err;
  3863. break;
  3864. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3865. reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
  3866. STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei);
  3867. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
  3868. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
  3869. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  3870. goto err;
  3871. break;
  3872. default:
  3873. break;
  3874. }
  3875. switch (state->config->ts2_mode) {
  3876. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3877. reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
  3878. STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei);
  3879. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
  3880. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
  3881. if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
  3882. goto err;
  3883. break;
  3884. case STV090x_TSMODE_DVBCI:
  3885. reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
  3886. STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei);
  3887. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
  3888. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
  3889. if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
  3890. goto err;
  3891. break;
  3892. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3893. reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
  3894. STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei);
  3895. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
  3896. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
  3897. if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
  3898. goto err;
  3899. break;
  3900. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3901. reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
  3902. STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei);
  3903. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
  3904. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
  3905. if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
  3906. goto err;
  3907. break;
  3908. default:
  3909. break;
  3910. }
  3911. if (state->config->ts1_clk > 0) {
  3912. u32 speed;
  3913. switch (state->config->ts1_mode) {
  3914. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3915. case STV090x_TSMODE_DVBCI:
  3916. default:
  3917. speed = state->internal->mclk /
  3918. (state->config->ts1_clk / 4);
  3919. if (speed < 0x08)
  3920. speed = 0x08;
  3921. if (speed > 0xFF)
  3922. speed = 0xFF;
  3923. break;
  3924. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3925. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3926. speed = state->internal->mclk /
  3927. (state->config->ts1_clk / 32);
  3928. if (speed < 0x20)
  3929. speed = 0x20;
  3930. if (speed > 0xFF)
  3931. speed = 0xFF;
  3932. break;
  3933. }
  3934. reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
  3935. STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
  3936. if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
  3937. goto err;
  3938. if (stv090x_write_reg(state, STV090x_P1_TSSPEED, speed) < 0)
  3939. goto err;
  3940. }
  3941. if (state->config->ts2_clk > 0) {
  3942. u32 speed;
  3943. switch (state->config->ts2_mode) {
  3944. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3945. case STV090x_TSMODE_DVBCI:
  3946. default:
  3947. speed = state->internal->mclk /
  3948. (state->config->ts2_clk / 4);
  3949. if (speed < 0x08)
  3950. speed = 0x08;
  3951. if (speed > 0xFF)
  3952. speed = 0xFF;
  3953. break;
  3954. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3955. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3956. speed = state->internal->mclk /
  3957. (state->config->ts2_clk / 32);
  3958. if (speed < 0x20)
  3959. speed = 0x20;
  3960. if (speed > 0xFF)
  3961. speed = 0xFF;
  3962. break;
  3963. }
  3964. reg = stv090x_read_reg(state, STV090x_P2_TSCFGM);
  3965. STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
  3966. if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0)
  3967. goto err;
  3968. if (stv090x_write_reg(state, STV090x_P2_TSSPEED, speed) < 0)
  3969. goto err;
  3970. }
  3971. reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
  3972. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
  3973. if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
  3974. goto err;
  3975. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
  3976. if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
  3977. goto err;
  3978. reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
  3979. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
  3980. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  3981. goto err;
  3982. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
  3983. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  3984. goto err;
  3985. return 0;
  3986. err:
  3987. dprintk(FE_ERROR, 1, "I/O error");
  3988. return -1;
  3989. }
  3990. static int stv0903_set_tspath(struct stv090x_state *state)
  3991. {
  3992. u32 reg;
  3993. if (state->internal->dev_ver >= 0x20) {
  3994. switch (state->config->ts1_mode) {
  3995. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3996. case STV090x_TSMODE_DVBCI:
  3997. stv090x_write_reg(state, STV090x_TSGENERAL, 0x00);
  3998. break;
  3999. case STV090x_TSMODE_SERIAL_PUNCTURED:
  4000. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  4001. default:
  4002. stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c);
  4003. break;
  4004. }
  4005. } else {
  4006. switch (state->config->ts1_mode) {
  4007. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  4008. case STV090x_TSMODE_DVBCI:
  4009. stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x10);
  4010. break;
  4011. case STV090x_TSMODE_SERIAL_PUNCTURED:
  4012. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  4013. default:
  4014. stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x14);
  4015. break;
  4016. }
  4017. }
  4018. switch (state->config->ts1_mode) {
  4019. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  4020. reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
  4021. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
  4022. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
  4023. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  4024. goto err;
  4025. break;
  4026. case STV090x_TSMODE_DVBCI:
  4027. reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
  4028. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
  4029. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
  4030. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  4031. goto err;
  4032. break;
  4033. case STV090x_TSMODE_SERIAL_PUNCTURED:
  4034. reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
  4035. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
  4036. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
  4037. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  4038. goto err;
  4039. break;
  4040. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  4041. reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
  4042. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
  4043. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
  4044. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  4045. goto err;
  4046. break;
  4047. default:
  4048. break;
  4049. }
  4050. if (state->config->ts1_clk > 0) {
  4051. u32 speed;
  4052. switch (state->config->ts1_mode) {
  4053. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  4054. case STV090x_TSMODE_DVBCI:
  4055. default:
  4056. speed = state->internal->mclk /
  4057. (state->config->ts1_clk / 4);
  4058. if (speed < 0x08)
  4059. speed = 0x08;
  4060. if (speed > 0xFF)
  4061. speed = 0xFF;
  4062. break;
  4063. case STV090x_TSMODE_SERIAL_PUNCTURED:
  4064. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  4065. speed = state->internal->mclk /
  4066. (state->config->ts1_clk / 32);
  4067. if (speed < 0x20)
  4068. speed = 0x20;
  4069. if (speed > 0xFF)
  4070. speed = 0xFF;
  4071. break;
  4072. }
  4073. reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
  4074. STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
  4075. if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
  4076. goto err;
  4077. if (stv090x_write_reg(state, STV090x_P1_TSSPEED, speed) < 0)
  4078. goto err;
  4079. }
  4080. reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
  4081. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
  4082. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  4083. goto err;
  4084. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
  4085. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  4086. goto err;
  4087. return 0;
  4088. err:
  4089. dprintk(FE_ERROR, 1, "I/O error");
  4090. return -1;
  4091. }
  4092. static int stv090x_init(struct dvb_frontend *fe)
  4093. {
  4094. struct stv090x_state *state = fe->demodulator_priv;
  4095. const struct stv090x_config *config = state->config;
  4096. u32 reg;
  4097. if (state->internal->mclk == 0) {
  4098. /* call tuner init to configure the tuner's clock output
  4099. divider directly before setting up the master clock of
  4100. the stv090x. */
  4101. if (stv090x_i2c_gate_ctrl(state, 1) < 0)
  4102. goto err;
  4103. if (config->tuner_init) {
  4104. if (config->tuner_init(fe) < 0)
  4105. goto err_gateoff;
  4106. }
  4107. if (stv090x_i2c_gate_ctrl(state, 0) < 0)
  4108. goto err;
  4109. stv090x_set_mclk(state, 135000000, config->xtal); /* 135 Mhz */
  4110. msleep(5);
  4111. if (stv090x_write_reg(state, STV090x_SYNTCTRL,
  4112. 0x20 | config->clk_mode) < 0)
  4113. goto err;
  4114. stv090x_get_mclk(state);
  4115. }
  4116. if (stv090x_wakeup(fe) < 0) {
  4117. dprintk(FE_ERROR, 1, "Error waking device");
  4118. goto err;
  4119. }
  4120. if (stv090x_ldpc_mode(state, state->demod_mode) < 0)
  4121. goto err;
  4122. reg = STV090x_READ_DEMOD(state, TNRCFG2);
  4123. STV090x_SETFIELD_Px(reg, TUN_IQSWAP_FIELD, state->inversion);
  4124. if (STV090x_WRITE_DEMOD(state, TNRCFG2, reg) < 0)
  4125. goto err;
  4126. reg = STV090x_READ_DEMOD(state, DEMOD);
  4127. STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
  4128. if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
  4129. goto err;
  4130. if (stv090x_i2c_gate_ctrl(state, 1) < 0)
  4131. goto err;
  4132. if (config->tuner_set_mode) {
  4133. if (config->tuner_set_mode(fe, TUNER_WAKE) < 0)
  4134. goto err_gateoff;
  4135. }
  4136. if (config->tuner_init) {
  4137. if (config->tuner_init(fe) < 0)
  4138. goto err_gateoff;
  4139. }
  4140. if (stv090x_i2c_gate_ctrl(state, 0) < 0)
  4141. goto err;
  4142. if (state->device == STV0900) {
  4143. if (stv0900_set_tspath(state) < 0)
  4144. goto err;
  4145. } else {
  4146. if (stv0903_set_tspath(state) < 0)
  4147. goto err;
  4148. }
  4149. return 0;
  4150. err_gateoff:
  4151. stv090x_i2c_gate_ctrl(state, 0);
  4152. err:
  4153. dprintk(FE_ERROR, 1, "I/O error");
  4154. return -1;
  4155. }
  4156. static int stv090x_setup(struct dvb_frontend *fe)
  4157. {
  4158. struct stv090x_state *state = fe->demodulator_priv;
  4159. const struct stv090x_config *config = state->config;
  4160. const struct stv090x_reg *stv090x_initval = NULL;
  4161. const struct stv090x_reg *stv090x_cut20_val = NULL;
  4162. unsigned long t1_size = 0, t2_size = 0;
  4163. u32 reg = 0;
  4164. int i;
  4165. if (state->device == STV0900) {
  4166. dprintk(FE_DEBUG, 1, "Initializing STV0900");
  4167. stv090x_initval = stv0900_initval;
  4168. t1_size = ARRAY_SIZE(stv0900_initval);
  4169. stv090x_cut20_val = stv0900_cut20_val;
  4170. t2_size = ARRAY_SIZE(stv0900_cut20_val);
  4171. } else if (state->device == STV0903) {
  4172. dprintk(FE_DEBUG, 1, "Initializing STV0903");
  4173. stv090x_initval = stv0903_initval;
  4174. t1_size = ARRAY_SIZE(stv0903_initval);
  4175. stv090x_cut20_val = stv0903_cut20_val;
  4176. t2_size = ARRAY_SIZE(stv0903_cut20_val);
  4177. }
  4178. /* STV090x init */
  4179. /* Stop Demod */
  4180. if (stv090x_write_reg(state, STV090x_P1_DMDISTATE, 0x5c) < 0)
  4181. goto err;
  4182. if (state->device == STV0900)
  4183. if (stv090x_write_reg(state, STV090x_P2_DMDISTATE, 0x5c) < 0)
  4184. goto err;
  4185. msleep(5);
  4186. /* Set No Tuner Mode */
  4187. if (stv090x_write_reg(state, STV090x_P1_TNRCFG, 0x6c) < 0)
  4188. goto err;
  4189. if (state->device == STV0900)
  4190. if (stv090x_write_reg(state, STV090x_P2_TNRCFG, 0x6c) < 0)
  4191. goto err;
  4192. /* I2C repeater OFF */
  4193. STV090x_SETFIELD_Px(reg, ENARPT_LEVEL_FIELD, config->repeater_level);
  4194. if (stv090x_write_reg(state, STV090x_P1_I2CRPT, reg) < 0)
  4195. goto err;
  4196. if (state->device == STV0900)
  4197. if (stv090x_write_reg(state, STV090x_P2_I2CRPT, reg) < 0)
  4198. goto err;
  4199. if (stv090x_write_reg(state, STV090x_NCOARSE, 0x13) < 0) /* set PLL divider */
  4200. goto err;
  4201. msleep(5);
  4202. if (stv090x_write_reg(state, STV090x_I2CCFG, 0x08) < 0) /* 1/41 oversampling */
  4203. goto err;
  4204. if (stv090x_write_reg(state, STV090x_SYNTCTRL, 0x20 | config->clk_mode) < 0) /* enable PLL */
  4205. goto err;
  4206. msleep(5);
  4207. /* write initval */
  4208. dprintk(FE_DEBUG, 1, "Setting up initial values");
  4209. for (i = 0; i < t1_size; i++) {
  4210. if (stv090x_write_reg(state, stv090x_initval[i].addr, stv090x_initval[i].data) < 0)
  4211. goto err;
  4212. }
  4213. state->internal->dev_ver = stv090x_read_reg(state, STV090x_MID);
  4214. if (state->internal->dev_ver >= 0x20) {
  4215. if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
  4216. goto err;
  4217. /* write cut20_val*/
  4218. dprintk(FE_DEBUG, 1, "Setting up Cut 2.0 initial values");
  4219. for (i = 0; i < t2_size; i++) {
  4220. if (stv090x_write_reg(state, stv090x_cut20_val[i].addr, stv090x_cut20_val[i].data) < 0)
  4221. goto err;
  4222. }
  4223. } else if (state->internal->dev_ver < 0x20) {
  4224. dprintk(FE_ERROR, 1, "ERROR: Unsupported Cut: 0x%02x!",
  4225. state->internal->dev_ver);
  4226. goto err;
  4227. } else if (state->internal->dev_ver > 0x30) {
  4228. /* we shouldn't bail out from here */
  4229. dprintk(FE_ERROR, 1, "INFO: Cut: 0x%02x probably incomplete support!",
  4230. state->internal->dev_ver);
  4231. }
  4232. /* ADC1 range */
  4233. reg = stv090x_read_reg(state, STV090x_TSTTNR1);
  4234. STV090x_SETFIELD(reg, ADC1_INMODE_FIELD,
  4235. (config->adc1_range == STV090x_ADC_1Vpp) ? 0 : 1);
  4236. if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
  4237. goto err;
  4238. /* ADC2 range */
  4239. reg = stv090x_read_reg(state, STV090x_TSTTNR3);
  4240. STV090x_SETFIELD(reg, ADC2_INMODE_FIELD,
  4241. (config->adc2_range == STV090x_ADC_1Vpp) ? 0 : 1);
  4242. if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0)
  4243. goto err;
  4244. if (stv090x_write_reg(state, STV090x_TSTRES0, 0x80) < 0)
  4245. goto err;
  4246. if (stv090x_write_reg(state, STV090x_TSTRES0, 0x00) < 0)
  4247. goto err;
  4248. return 0;
  4249. err:
  4250. dprintk(FE_ERROR, 1, "I/O error");
  4251. return -1;
  4252. }
  4253. static int stv090x_set_gpio(struct dvb_frontend *fe, u8 gpio, u8 dir,
  4254. u8 value, u8 xor_value)
  4255. {
  4256. struct stv090x_state *state = fe->demodulator_priv;
  4257. u8 reg = 0;
  4258. STV090x_SETFIELD(reg, GPIOx_OPD_FIELD, dir);
  4259. STV090x_SETFIELD(reg, GPIOx_CONFIG_FIELD, value);
  4260. STV090x_SETFIELD(reg, GPIOx_XOR_FIELD, xor_value);
  4261. return stv090x_write_reg(state, STV090x_GPIOxCFG(gpio), reg);
  4262. }
  4263. static int stv090x_setup_compound(struct stv090x_state *state)
  4264. {
  4265. struct stv090x_dev *temp_int;
  4266. temp_int = find_dev(state->i2c,
  4267. state->config->address);
  4268. if (temp_int && state->demod_mode == STV090x_DUAL) {
  4269. state->internal = temp_int->internal;
  4270. state->internal->num_used++;
  4271. dprintk(FE_INFO, 1, "Found Internal Structure!");
  4272. } else {
  4273. state->internal = kmalloc(sizeof(*state->internal), GFP_KERNEL);
  4274. if (!state->internal)
  4275. goto error;
  4276. temp_int = append_internal(state->internal);
  4277. if (!temp_int) {
  4278. kfree(state->internal);
  4279. goto error;
  4280. }
  4281. state->internal->num_used = 1;
  4282. state->internal->mclk = 0;
  4283. state->internal->dev_ver = 0;
  4284. state->internal->i2c_adap = state->i2c;
  4285. state->internal->i2c_addr = state->config->address;
  4286. dprintk(FE_INFO, 1, "Create New Internal Structure!");
  4287. mutex_init(&state->internal->demod_lock);
  4288. mutex_init(&state->internal->tuner_lock);
  4289. if (stv090x_setup(&state->frontend) < 0) {
  4290. dprintk(FE_ERROR, 1, "Error setting up device");
  4291. goto err_remove;
  4292. }
  4293. }
  4294. if (state->internal->dev_ver >= 0x30)
  4295. state->frontend.ops.info.caps |= FE_CAN_MULTISTREAM;
  4296. /* workaround for stuck DiSEqC output */
  4297. if (state->config->diseqc_envelope_mode)
  4298. stv090x_send_diseqc_burst(&state->frontend, SEC_MINI_A);
  4299. state->config->set_gpio = stv090x_set_gpio;
  4300. dprintk(FE_ERROR, 1, "Probing %s demodulator(%d) Cut=0x%02x",
  4301. state->device == STV0900 ? "STV0900" : "STV0903",
  4302. state->config->demod,
  4303. state->internal->dev_ver);
  4304. return 0;
  4305. error:
  4306. return -ENOMEM;
  4307. err_remove:
  4308. remove_dev(state->internal);
  4309. kfree(state->internal);
  4310. return -ENODEV;
  4311. }
  4312. static const struct dvb_frontend_ops stv090x_ops = {
  4313. .delsys = { SYS_DVBS, SYS_DVBS2, SYS_DSS },
  4314. .info = {
  4315. .name = "STV090x Multistandard",
  4316. .frequency_min_hz = 950 * MHz,
  4317. .frequency_max_hz = 2150 * MHz,
  4318. .symbol_rate_min = 1000000,
  4319. .symbol_rate_max = 45000000,
  4320. .caps = FE_CAN_INVERSION_AUTO |
  4321. FE_CAN_FEC_AUTO |
  4322. FE_CAN_QPSK |
  4323. FE_CAN_2G_MODULATION
  4324. },
  4325. .release = stv090x_release,
  4326. .init = stv090x_init,
  4327. .sleep = stv090x_sleep,
  4328. .get_frontend_algo = stv090x_frontend_algo,
  4329. .diseqc_send_master_cmd = stv090x_send_diseqc_msg,
  4330. .diseqc_send_burst = stv090x_send_diseqc_burst,
  4331. .diseqc_recv_slave_reply = stv090x_recv_slave_reply,
  4332. .set_tone = stv090x_set_tone,
  4333. .search = stv090x_search,
  4334. .read_status = stv090x_read_status,
  4335. .read_ber = stv090x_read_per,
  4336. .read_signal_strength = stv090x_read_signal_strength,
  4337. .read_snr = stv090x_read_cnr,
  4338. };
  4339. static struct dvb_frontend *stv090x_get_dvb_frontend(struct i2c_client *client)
  4340. {
  4341. struct stv090x_state *state = i2c_get_clientdata(client);
  4342. dev_dbg(&client->dev, "\n");
  4343. return &state->frontend;
  4344. }
  4345. static int stv090x_probe(struct i2c_client *client,
  4346. const struct i2c_device_id *id)
  4347. {
  4348. int ret = 0;
  4349. struct stv090x_config *config = client->dev.platform_data;
  4350. struct stv090x_state *state = NULL;
  4351. state = kzalloc(sizeof(*state), GFP_KERNEL);
  4352. if (!state) {
  4353. ret = -ENOMEM;
  4354. goto error;
  4355. }
  4356. state->verbose = &verbose;
  4357. state->config = config;
  4358. state->i2c = client->adapter;
  4359. state->frontend.ops = stv090x_ops;
  4360. state->frontend.demodulator_priv = state;
  4361. state->demod = config->demod;
  4362. /* Single or Dual mode */
  4363. state->demod_mode = config->demod_mode;
  4364. state->device = config->device;
  4365. /* default */
  4366. state->rolloff = STV090x_RO_35;
  4367. ret = stv090x_setup_compound(state);
  4368. if (ret)
  4369. goto error;
  4370. i2c_set_clientdata(client, state);
  4371. /* setup callbacks */
  4372. config->get_dvb_frontend = stv090x_get_dvb_frontend;
  4373. return 0;
  4374. error:
  4375. kfree(state);
  4376. return ret;
  4377. }
  4378. static int stv090x_remove(struct i2c_client *client)
  4379. {
  4380. struct stv090x_state *state = i2c_get_clientdata(client);
  4381. stv090x_release(&state->frontend);
  4382. return 0;
  4383. }
  4384. struct dvb_frontend *stv090x_attach(struct stv090x_config *config,
  4385. struct i2c_adapter *i2c,
  4386. enum stv090x_demodulator demod)
  4387. {
  4388. int ret = 0;
  4389. struct stv090x_state *state = NULL;
  4390. state = kzalloc(sizeof(*state), GFP_KERNEL);
  4391. if (!state)
  4392. goto error;
  4393. state->verbose = &verbose;
  4394. state->config = config;
  4395. state->i2c = i2c;
  4396. state->frontend.ops = stv090x_ops;
  4397. state->frontend.demodulator_priv = state;
  4398. state->demod = demod;
  4399. /* Single or Dual mode */
  4400. state->demod_mode = config->demod_mode;
  4401. state->device = config->device;
  4402. /* default */
  4403. state->rolloff = STV090x_RO_35;
  4404. ret = stv090x_setup_compound(state);
  4405. if (ret)
  4406. goto error;
  4407. return &state->frontend;
  4408. error:
  4409. kfree(state);
  4410. return NULL;
  4411. }
  4412. EXPORT_SYMBOL(stv090x_attach);
  4413. static const struct i2c_device_id stv090x_id_table[] = {
  4414. {"stv090x", 0},
  4415. {}
  4416. };
  4417. MODULE_DEVICE_TABLE(i2c, stv090x_id_table);
  4418. static struct i2c_driver stv090x_driver = {
  4419. .driver = {
  4420. .name = "stv090x",
  4421. .suppress_bind_attrs = true,
  4422. },
  4423. .probe = stv090x_probe,
  4424. .remove = stv090x_remove,
  4425. .id_table = stv090x_id_table,
  4426. };
  4427. module_i2c_driver(stv090x_driver);
  4428. MODULE_PARM_DESC(verbose, "Set Verbosity level");
  4429. MODULE_AUTHOR("Manu Abraham");
  4430. MODULE_DESCRIPTION("STV090x Multi-Std Broadcast frontend");
  4431. MODULE_LICENSE("GPL");