stv0367_regs.h 96 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * stv0367_regs.h
  4. *
  5. * Driver for ST STV0367 DVB-T & DVB-C demodulator IC.
  6. *
  7. * Copyright (C) ST Microelectronics.
  8. * Copyright (C) 2010,2011 NetUP Inc.
  9. * Copyright (C) 2010,2011 Igor M. Liplianin <liplianin@netup.ru>
  10. */
  11. #ifndef STV0367_REGS_H
  12. #define STV0367_REGS_H
  13. /* ID */
  14. #define R367TER_ID 0xf000
  15. #define F367TER_IDENTIFICATIONREG 0xf00000ff
  16. /* I2CRPT */
  17. #define R367TER_I2CRPT 0xf001
  18. #define F367TER_I2CT_ON 0xf0010080
  19. #define F367TER_ENARPT_LEVEL 0xf0010070
  20. #define F367TER_SCLT_DELAY 0xf0010008
  21. #define F367TER_SCLT_NOD 0xf0010004
  22. #define F367TER_STOP_ENABLE 0xf0010002
  23. #define F367TER_SDAT_NOD 0xf0010001
  24. /* TOPCTRL */
  25. #define R367TER_TOPCTRL 0xf002
  26. #define F367TER_STDBY 0xf0020080
  27. #define F367TER_STDBY_FEC 0xf0020040
  28. #define F367TER_STDBY_CORE 0xf0020020
  29. #define F367TER_QAM_COFDM 0xf0020010
  30. #define F367TER_TS_DIS 0xf0020008
  31. #define F367TER_DIR_CLK_216 0xf0020004
  32. #define F367TER_TUNER_BB 0xf0020002
  33. #define F367TER_DVBT_H 0xf0020001
  34. /* IOCFG0 */
  35. #define R367TER_IOCFG0 0xf003
  36. #define F367TER_OP0_SD 0xf0030080
  37. #define F367TER_OP0_VAL 0xf0030040
  38. #define F367TER_OP0_OD 0xf0030020
  39. #define F367TER_OP0_INV 0xf0030010
  40. #define F367TER_OP0_DACVALUE_HI 0xf003000f
  41. /* DAc0R */
  42. #define R367TER_DAC0R 0xf004
  43. #define F367TER_OP0_DACVALUE_LO 0xf00400ff
  44. /* IOCFG1 */
  45. #define R367TER_IOCFG1 0xf005
  46. #define F367TER_IP0 0xf0050040
  47. #define F367TER_OP1_OD 0xf0050020
  48. #define F367TER_OP1_INV 0xf0050010
  49. #define F367TER_OP1_DACVALUE_HI 0xf005000f
  50. /* DAC1R */
  51. #define R367TER_DAC1R 0xf006
  52. #define F367TER_OP1_DACVALUE_LO 0xf00600ff
  53. /* IOCFG2 */
  54. #define R367TER_IOCFG2 0xf007
  55. #define F367TER_OP2_LOCK_CONF 0xf00700e0
  56. #define F367TER_OP2_OD 0xf0070010
  57. #define F367TER_OP2_VAL 0xf0070008
  58. #define F367TER_OP1_LOCK_CONF 0xf0070007
  59. /* SDFR */
  60. #define R367TER_SDFR 0xf008
  61. #define F367TER_OP0_FREQ 0xf00800f0
  62. #define F367TER_OP1_FREQ 0xf008000f
  63. /* STATUS */
  64. #define R367TER_STATUS 0xf009
  65. #define F367TER_TPS_LOCK 0xf0090080
  66. #define F367TER_SYR_LOCK 0xf0090040
  67. #define F367TER_AGC_LOCK 0xf0090020
  68. #define F367TER_PRF 0xf0090010
  69. #define F367TER_LK 0xf0090008
  70. #define F367TER_PR 0xf0090007
  71. /* AUX_CLK */
  72. #define R367TER_AUX_CLK 0xf00a
  73. #define F367TER_AUXFEC_CTL 0xf00a00c0
  74. #define F367TER_DIS_CKX4 0xf00a0020
  75. #define F367TER_CKSEL 0xf00a0018
  76. #define F367TER_CKDIV_PROG 0xf00a0006
  77. #define F367TER_AUXCLK_ENA 0xf00a0001
  78. /* FREESYS1 */
  79. #define R367TER_FREESYS1 0xf00b
  80. #define F367TER_FREE_SYS1 0xf00b00ff
  81. /* FREESYS2 */
  82. #define R367TER_FREESYS2 0xf00c
  83. #define F367TER_FREE_SYS2 0xf00c00ff
  84. /* FREESYS3 */
  85. #define R367TER_FREESYS3 0xf00d
  86. #define F367TER_FREE_SYS3 0xf00d00ff
  87. /* GPIO_CFG */
  88. #define R367TER_GPIO_CFG 0xf00e
  89. #define F367TER_GPIO7_NOD 0xf00e0080
  90. #define F367TER_GPIO7_CFG 0xf00e0040
  91. #define F367TER_GPIO6_NOD 0xf00e0020
  92. #define F367TER_GPIO6_CFG 0xf00e0010
  93. #define F367TER_GPIO5_NOD 0xf00e0008
  94. #define F367TER_GPIO5_CFG 0xf00e0004
  95. #define F367TER_GPIO4_NOD 0xf00e0002
  96. #define F367TER_GPIO4_CFG 0xf00e0001
  97. /* GPIO_CMD */
  98. #define R367TER_GPIO_CMD 0xf00f
  99. #define F367TER_GPIO7_VAL 0xf00f0008
  100. #define F367TER_GPIO6_VAL 0xf00f0004
  101. #define F367TER_GPIO5_VAL 0xf00f0002
  102. #define F367TER_GPIO4_VAL 0xf00f0001
  103. /* AGC2MAX */
  104. #define R367TER_AGC2MAX 0xf010
  105. #define F367TER_AGC2_MAX 0xf01000ff
  106. /* AGC2MIN */
  107. #define R367TER_AGC2MIN 0xf011
  108. #define F367TER_AGC2_MIN 0xf01100ff
  109. /* AGC1MAX */
  110. #define R367TER_AGC1MAX 0xf012
  111. #define F367TER_AGC1_MAX 0xf01200ff
  112. /* AGC1MIN */
  113. #define R367TER_AGC1MIN 0xf013
  114. #define F367TER_AGC1_MIN 0xf01300ff
  115. /* AGCR */
  116. #define R367TER_AGCR 0xf014
  117. #define F367TER_RATIO_A 0xf01400e0
  118. #define F367TER_RATIO_B 0xf0140018
  119. #define F367TER_RATIO_C 0xf0140007
  120. /* AGC2TH */
  121. #define R367TER_AGC2TH 0xf015
  122. #define F367TER_AGC2_THRES 0xf01500ff
  123. /* AGC12c */
  124. #define R367TER_AGC12C 0xf016
  125. #define F367TER_AGC1_IV 0xf0160080
  126. #define F367TER_AGC1_OD 0xf0160040
  127. #define F367TER_AGC1_LOAD 0xf0160020
  128. #define F367TER_AGC2_IV 0xf0160010
  129. #define F367TER_AGC2_OD 0xf0160008
  130. #define F367TER_AGC2_LOAD 0xf0160004
  131. #define F367TER_AGC12_MODE 0xf0160003
  132. /* AGCCTRL1 */
  133. #define R367TER_AGCCTRL1 0xf017
  134. #define F367TER_DAGC_ON 0xf0170080
  135. #define F367TER_INVERT_AGC12 0xf0170040
  136. #define F367TER_AGC1_MODE 0xf0170008
  137. #define F367TER_AGC2_MODE 0xf0170007
  138. /* AGCCTRL2 */
  139. #define R367TER_AGCCTRL2 0xf018
  140. #define F367TER_FRZ2_CTRL 0xf0180060
  141. #define F367TER_FRZ1_CTRL 0xf0180018
  142. #define F367TER_TIME_CST 0xf0180007
  143. /* AGC1VAL1 */
  144. #define R367TER_AGC1VAL1 0xf019
  145. #define F367TER_AGC1_VAL_LO 0xf01900ff
  146. /* AGC1VAL2 */
  147. #define R367TER_AGC1VAL2 0xf01a
  148. #define F367TER_AGC1_VAL_HI 0xf01a000f
  149. /* AGC2VAL1 */
  150. #define R367TER_AGC2VAL1 0xf01b
  151. #define F367TER_AGC2_VAL_LO 0xf01b00ff
  152. /* AGC2VAL2 */
  153. #define R367TER_AGC2VAL2 0xf01c
  154. #define F367TER_AGC2_VAL_HI 0xf01c000f
  155. /* AGC2PGA */
  156. #define R367TER_AGC2PGA 0xf01d
  157. #define F367TER_AGC2_PGA 0xf01d00ff
  158. /* OVF_RATE1 */
  159. #define R367TER_OVF_RATE1 0xf01e
  160. #define F367TER_OVF_RATE_HI 0xf01e000f
  161. /* OVF_RATE2 */
  162. #define R367TER_OVF_RATE2 0xf01f
  163. #define F367TER_OVF_RATE_LO 0xf01f00ff
  164. /* GAIN_SRC1 */
  165. #define R367TER_GAIN_SRC1 0xf020
  166. #define F367TER_INV_SPECTR 0xf0200080
  167. #define F367TER_IQ_INVERT 0xf0200040
  168. #define F367TER_INR_BYPASS 0xf0200020
  169. #define F367TER_STATUS_INV_SPECRUM 0xf0200010
  170. #define F367TER_GAIN_SRC_HI 0xf020000f
  171. /* GAIN_SRC2 */
  172. #define R367TER_GAIN_SRC2 0xf021
  173. #define F367TER_GAIN_SRC_LO 0xf02100ff
  174. /* INC_DEROT1 */
  175. #define R367TER_INC_DEROT1 0xf022
  176. #define F367TER_INC_DEROT_HI 0xf02200ff
  177. /* INC_DEROT2 */
  178. #define R367TER_INC_DEROT2 0xf023
  179. #define F367TER_INC_DEROT_LO 0xf02300ff
  180. /* PPM_CPAMP_DIR */
  181. #define R367TER_PPM_CPAMP_DIR 0xf024
  182. #define F367TER_PPM_CPAMP_DIRECT 0xf02400ff
  183. /* PPM_CPAMP_INV */
  184. #define R367TER_PPM_CPAMP_INV 0xf025
  185. #define F367TER_PPM_CPAMP_INVER 0xf02500ff
  186. /* FREESTFE_1 */
  187. #define R367TER_FREESTFE_1 0xf026
  188. #define F367TER_SYMBOL_NUMBER_INC 0xf02600c0
  189. #define F367TER_SEL_LSB 0xf0260004
  190. #define F367TER_AVERAGE_ON 0xf0260002
  191. #define F367TER_DC_ADJ 0xf0260001
  192. /* FREESTFE_2 */
  193. #define R367TER_FREESTFE_2 0xf027
  194. #define F367TER_SEL_SRCOUT 0xf02700c0
  195. #define F367TER_SEL_SYRTHR 0xf027001f
  196. /* DCOFFSET */
  197. #define R367TER_DCOFFSET 0xf028
  198. #define F367TER_SELECT_I_Q 0xf0280080
  199. #define F367TER_DC_OFFSET 0xf028007f
  200. /* EN_PROCESS */
  201. #define R367TER_EN_PROCESS 0xf029
  202. #define F367TER_FREE 0xf02900f0
  203. #define F367TER_ENAB_MANUAL 0xf0290001
  204. /* SDI_SMOOTHER */
  205. #define R367TER_SDI_SMOOTHER 0xf02a
  206. #define F367TER_DIS_SMOOTH 0xf02a0080
  207. #define F367TER_SDI_INC_SMOOTHER 0xf02a007f
  208. /* FE_LOOP_OPEN */
  209. #define R367TER_FE_LOOP_OPEN 0xf02b
  210. #define F367TER_TRL_LOOP_OP 0xf02b0002
  211. #define F367TER_CRL_LOOP_OP 0xf02b0001
  212. /* FREQOFF1 */
  213. #define R367TER_FREQOFF1 0xf02c
  214. #define F367TER_FREQ_OFFSET_LOOP_OPEN_VHI 0xf02c00ff
  215. /* FREQOFF2 */
  216. #define R367TER_FREQOFF2 0xf02d
  217. #define F367TER_FREQ_OFFSET_LOOP_OPEN_HI 0xf02d00ff
  218. /* FREQOFF3 */
  219. #define R367TER_FREQOFF3 0xf02e
  220. #define F367TER_FREQ_OFFSET_LOOP_OPEN_LO 0xf02e00ff
  221. /* TIMOFF1 */
  222. #define R367TER_TIMOFF1 0xf02f
  223. #define F367TER_TIM_OFFSET_LOOP_OPEN_HI 0xf02f00ff
  224. /* TIMOFF2 */
  225. #define R367TER_TIMOFF2 0xf030
  226. #define F367TER_TIM_OFFSET_LOOP_OPEN_LO 0xf03000ff
  227. /* EPQ */
  228. #define R367TER_EPQ 0xf031
  229. #define F367TER_EPQ1 0xf03100ff
  230. /* EPQAUTO */
  231. #define R367TER_EPQAUTO 0xf032
  232. #define F367TER_EPQ2 0xf03200ff
  233. /* SYR_UPDATE */
  234. #define R367TER_SYR_UPDATE 0xf033
  235. #define F367TER_SYR_PROTV 0xf0330080
  236. #define F367TER_SYR_PROTV_GAIN 0xf0330060
  237. #define F367TER_SYR_FILTER 0xf0330010
  238. #define F367TER_SYR_TRACK_THRES 0xf033000c
  239. /* CHPFREE */
  240. #define R367TER_CHPFREE 0xf034
  241. #define F367TER_CHP_FREE 0xf03400ff
  242. /* PPM_STATE_MAC */
  243. #define R367TER_PPM_STATE_MAC 0xf035
  244. #define F367TER_PPM_STATE_MACHINE_DECODER 0xf035003f
  245. /* INR_THRESHOLD */
  246. #define R367TER_INR_THRESHOLD 0xf036
  247. #define F367TER_INR_THRESH 0xf03600ff
  248. /* EPQ_TPS_ID_CELL */
  249. #define R367TER_EPQ_TPS_ID_CELL 0xf037
  250. #define F367TER_ENABLE_LGTH_TO_CF 0xf0370080
  251. #define F367TER_DIS_TPS_RSVD 0xf0370040
  252. #define F367TER_DIS_BCH 0xf0370020
  253. #define F367TER_DIS_ID_CEL 0xf0370010
  254. #define F367TER_TPS_ADJUST_SYM 0xf037000f
  255. /* EPQ_CFG */
  256. #define R367TER_EPQ_CFG 0xf038
  257. #define F367TER_EPQ_RANGE 0xf0380002
  258. #define F367TER_EPQ_SOFT 0xf0380001
  259. /* EPQ_STATUS */
  260. #define R367TER_EPQ_STATUS 0xf039
  261. #define F367TER_SLOPE_INC 0xf03900fc
  262. #define F367TER_TPS_FIELD 0xf0390003
  263. /* AUTORELOCK */
  264. #define R367TER_AUTORELOCK 0xf03a
  265. #define F367TER_BYPASS_BER_TEMPO 0xf03a0080
  266. #define F367TER_BER_TEMPO 0xf03a0070
  267. #define F367TER_BYPASS_COFDM_TEMPO 0xf03a0008
  268. #define F367TER_COFDM_TEMPO 0xf03a0007
  269. /* BER_THR_VMSB */
  270. #define R367TER_BER_THR_VMSB 0xf03b
  271. #define F367TER_BER_THRESHOLD_HI 0xf03b00ff
  272. /* BER_THR_MSB */
  273. #define R367TER_BER_THR_MSB 0xf03c
  274. #define F367TER_BER_THRESHOLD_MID 0xf03c00ff
  275. /* BER_THR_LSB */
  276. #define R367TER_BER_THR_LSB 0xf03d
  277. #define F367TER_BER_THRESHOLD_LO 0xf03d00ff
  278. /* CCD */
  279. #define R367TER_CCD 0xf03e
  280. #define F367TER_CCD_DETECTED 0xf03e0080
  281. #define F367TER_CCD_RESET 0xf03e0040
  282. #define F367TER_CCD_THRESHOLD 0xf03e000f
  283. /* SPECTR_CFG */
  284. #define R367TER_SPECTR_CFG 0xf03f
  285. #define F367TER_SPECT_CFG 0xf03f0003
  286. /* CONSTMU_MSB */
  287. #define R367TER_CONSTMU_MSB 0xf040
  288. #define F367TER_CONSTMU_FREEZE 0xf0400080
  289. #define F367TER_CONSTNU_FORCE_EN 0xf0400040
  290. #define F367TER_CONST_MU_MSB 0xf040003f
  291. /* CONSTMU_LSB */
  292. #define R367TER_CONSTMU_LSB 0xf041
  293. #define F367TER_CONST_MU_LSB 0xf04100ff
  294. /* CONSTMU_MAX_MSB */
  295. #define R367TER_CONSTMU_MAX_MSB 0xf042
  296. #define F367TER_CONST_MU_MAX_MSB 0xf042003f
  297. /* CONSTMU_MAX_LSB */
  298. #define R367TER_CONSTMU_MAX_LSB 0xf043
  299. #define F367TER_CONST_MU_MAX_LSB 0xf04300ff
  300. /* ALPHANOISE */
  301. #define R367TER_ALPHANOISE 0xf044
  302. #define F367TER_USE_ALLFILTER 0xf0440080
  303. #define F367TER_INTER_ON 0xf0440040
  304. #define F367TER_ALPHA_NOISE 0xf044001f
  305. /* MAXGP_MSB */
  306. #define R367TER_MAXGP_MSB 0xf045
  307. #define F367TER_MUFILTER_LENGTH 0xf04500f0
  308. #define F367TER_MAX_GP_MSB 0xf045000f
  309. /* MAXGP_LSB */
  310. #define R367TER_MAXGP_LSB 0xf046
  311. #define F367TER_MAX_GP_LSB 0xf04600ff
  312. /* ALPHAMSB */
  313. #define R367TER_ALPHAMSB 0xf047
  314. #define F367TER_CHC_DATARATE 0xf04700c0
  315. #define F367TER_ALPHA_MSB 0xf047003f
  316. /* ALPHALSB */
  317. #define R367TER_ALPHALSB 0xf048
  318. #define F367TER_ALPHA_LSB 0xf04800ff
  319. /* PILOT_ACCU */
  320. #define R367TER_PILOT_ACCU 0xf049
  321. #define F367TER_USE_SCAT4ADDAPT 0xf0490080
  322. #define F367TER_PILOT_ACC 0xf049001f
  323. /* PILOTMU_ACCU */
  324. #define R367TER_PILOTMU_ACCU 0xf04a
  325. #define F367TER_DISCARD_BAD_SP 0xf04a0080
  326. #define F367TER_DISCARD_BAD_CP 0xf04a0040
  327. #define F367TER_PILOT_MU_ACCU 0xf04a001f
  328. /* FILT_CHANNEL_EST */
  329. #define R367TER_FILT_CHANNEL_EST 0xf04b
  330. #define F367TER_USE_FILT_PILOT 0xf04b0080
  331. #define F367TER_FILT_CHANNEL 0xf04b007f
  332. /* ALPHA_NOPISE_FREQ */
  333. #define R367TER_ALPHA_NOPISE_FREQ 0xf04c
  334. #define F367TER_NOISE_FREQ_FILT 0xf04c0040
  335. #define F367TER_ALPHA_NOISE_FREQ 0xf04c003f
  336. /* RATIO_PILOT */
  337. #define R367TER_RATIO_PILOT 0xf04d
  338. #define F367TER_RATIO_MEAN_SP 0xf04d00f0
  339. #define F367TER_RATIO_MEAN_CP 0xf04d000f
  340. /* CHC_CTL */
  341. #define R367TER_CHC_CTL 0xf04e
  342. #define F367TER_TRACK_EN 0xf04e0080
  343. #define F367TER_NOISE_NORM_EN 0xf04e0040
  344. #define F367TER_FORCE_CHC_RESET 0xf04e0020
  345. #define F367TER_SHORT_TIME 0xf04e0010
  346. #define F367TER_FORCE_STATE_EN 0xf04e0008
  347. #define F367TER_FORCE_STATE 0xf04e0007
  348. /* EPQ_ADJUST */
  349. #define R367TER_EPQ_ADJUST 0xf04f
  350. #define F367TER_ADJUST_SCAT_IND 0xf04f00c0
  351. #define F367TER_ONE_SYMBOL 0xf04f0010
  352. #define F367TER_EPQ_DECAY 0xf04f000e
  353. #define F367TER_HOLD_SLOPE 0xf04f0001
  354. /* EPQ_THRES */
  355. #define R367TER_EPQ_THRES 0xf050
  356. #define F367TER_EPQ_THR 0xf05000ff
  357. /* OMEGA_CTL */
  358. #define R367TER_OMEGA_CTL 0xf051
  359. #define F367TER_OMEGA_RST 0xf0510080
  360. #define F367TER_FREEZE_OMEGA 0xf0510040
  361. #define F367TER_OMEGA_SEL 0xf051003f
  362. /* GP_CTL */
  363. #define R367TER_GP_CTL 0xf052
  364. #define F367TER_CHC_STATE 0xf05200e0
  365. #define F367TER_FREEZE_GP 0xf0520010
  366. #define F367TER_GP_SEL 0xf052000f
  367. /* MUMSB */
  368. #define R367TER_MUMSB 0xf053
  369. #define F367TER_MU_MSB 0xf053007f
  370. /* MULSB */
  371. #define R367TER_MULSB 0xf054
  372. #define F367TER_MU_LSB 0xf05400ff
  373. /* GPMSB */
  374. #define R367TER_GPMSB 0xf055
  375. #define F367TER_CSI_THRESHOLD 0xf05500e0
  376. #define F367TER_GP_MSB 0xf055000f
  377. /* GPLSB */
  378. #define R367TER_GPLSB 0xf056
  379. #define F367TER_GP_LSB 0xf05600ff
  380. /* OMEGAMSB */
  381. #define R367TER_OMEGAMSB 0xf057
  382. #define F367TER_OMEGA_MSB 0xf057007f
  383. /* OMEGALSB */
  384. #define R367TER_OMEGALSB 0xf058
  385. #define F367TER_OMEGA_LSB 0xf05800ff
  386. /* SCAT_NB */
  387. #define R367TER_SCAT_NB 0xf059
  388. #define F367TER_CHC_TEST 0xf05900f8
  389. #define F367TER_SCAT_NUMB 0xf0590003
  390. /* CHC_DUMMY */
  391. #define R367TER_CHC_DUMMY 0xf05a
  392. #define F367TER_CHC_DUM 0xf05a00ff
  393. /* INC_CTL */
  394. #define R367TER_INC_CTL 0xf05b
  395. #define F367TER_INC_BYPASS 0xf05b0080
  396. #define F367TER_INC_NDEPTH 0xf05b000c
  397. #define F367TER_INC_MADEPTH 0xf05b0003
  398. /* INCTHRES_COR1 */
  399. #define R367TER_INCTHRES_COR1 0xf05c
  400. #define F367TER_INC_THRES_COR1 0xf05c00ff
  401. /* INCTHRES_COR2 */
  402. #define R367TER_INCTHRES_COR2 0xf05d
  403. #define F367TER_INC_THRES_COR2 0xf05d00ff
  404. /* INCTHRES_DET1 */
  405. #define R367TER_INCTHRES_DET1 0xf05e
  406. #define F367TER_INC_THRES_DET1 0xf05e003f
  407. /* INCTHRES_DET2 */
  408. #define R367TER_INCTHRES_DET2 0xf05f
  409. #define F367TER_INC_THRES_DET2 0xf05f003f
  410. /* IIR_CELLNB */
  411. #define R367TER_IIR_CELLNB 0xf060
  412. #define F367TER_NRST_IIR 0xf0600080
  413. #define F367TER_IIR_CELL_NB 0xf0600007
  414. /* IIRCX_COEFF1_MSB */
  415. #define R367TER_IIRCX_COEFF1_MSB 0xf061
  416. #define F367TER_IIR_CX_COEFF1_MSB 0xf06100ff
  417. /* IIRCX_COEFF1_LSB */
  418. #define R367TER_IIRCX_COEFF1_LSB 0xf062
  419. #define F367TER_IIR_CX_COEFF1_LSB 0xf06200ff
  420. /* IIRCX_COEFF2_MSB */
  421. #define R367TER_IIRCX_COEFF2_MSB 0xf063
  422. #define F367TER_IIR_CX_COEFF2_MSB 0xf06300ff
  423. /* IIRCX_COEFF2_LSB */
  424. #define R367TER_IIRCX_COEFF2_LSB 0xf064
  425. #define F367TER_IIR_CX_COEFF2_LSB 0xf06400ff
  426. /* IIRCX_COEFF3_MSB */
  427. #define R367TER_IIRCX_COEFF3_MSB 0xf065
  428. #define F367TER_IIR_CX_COEFF3_MSB 0xf06500ff
  429. /* IIRCX_COEFF3_LSB */
  430. #define R367TER_IIRCX_COEFF3_LSB 0xf066
  431. #define F367TER_IIR_CX_COEFF3_LSB 0xf06600ff
  432. /* IIRCX_COEFF4_MSB */
  433. #define R367TER_IIRCX_COEFF4_MSB 0xf067
  434. #define F367TER_IIR_CX_COEFF4_MSB 0xf06700ff
  435. /* IIRCX_COEFF4_LSB */
  436. #define R367TER_IIRCX_COEFF4_LSB 0xf068
  437. #define F367TER_IIR_CX_COEFF4_LSB 0xf06800ff
  438. /* IIRCX_COEFF5_MSB */
  439. #define R367TER_IIRCX_COEFF5_MSB 0xf069
  440. #define F367TER_IIR_CX_COEFF5_MSB 0xf06900ff
  441. /* IIRCX_COEFF5_LSB */
  442. #define R367TER_IIRCX_COEFF5_LSB 0xf06a
  443. #define F367TER_IIR_CX_COEFF5_LSB 0xf06a00ff
  444. /* FEPATH_CFG */
  445. #define R367TER_FEPATH_CFG 0xf06b
  446. #define F367TER_DEMUX_SWAP 0xf06b0004
  447. #define F367TER_DIGAGC_SWAP 0xf06b0002
  448. #define F367TER_LONGPATH_IF 0xf06b0001
  449. /* PMC1_FUNC */
  450. #define R367TER_PMC1_FUNC 0xf06c
  451. #define F367TER_SOFT_RSTN 0xf06c0080
  452. #define F367TER_PMC1_AVERAGE_TIME 0xf06c0078
  453. #define F367TER_PMC1_WAIT_TIME 0xf06c0006
  454. #define F367TER_PMC1_2N_SEL 0xf06c0001
  455. /* PMC1_FOR */
  456. #define R367TER_PMC1_FOR 0xf06d
  457. #define F367TER_PMC1_FORCE 0xf06d0080
  458. #define F367TER_PMC1_FORCE_VALUE 0xf06d007c
  459. /* PMC2_FUNC */
  460. #define R367TER_PMC2_FUNC 0xf06e
  461. #define F367TER_PMC2_SOFT_STN 0xf06e0080
  462. #define F367TER_PMC2_ACCU_TIME 0xf06e0070
  463. #define F367TER_PMC2_CMDP_MN 0xf06e0008
  464. #define F367TER_PMC2_SWAP 0xf06e0004
  465. /* STATUS_ERR_DA */
  466. #define R367TER_STATUS_ERR_DA 0xf06f
  467. #define F367TER_COM_USEGAINTRK 0xf06f0080
  468. #define F367TER_COM_AGCLOCK 0xf06f0040
  469. #define F367TER_AUT_AGCLOCK 0xf06f0020
  470. #define F367TER_MIN_ERR_X_LSB 0xf06f000f
  471. /* DIG_AGC_R */
  472. #define R367TER_DIG_AGC_R 0xf070
  473. #define F367TER_COM_SOFT_RSTN 0xf0700080
  474. #define F367TER_COM_AGC_ON 0xf0700040
  475. #define F367TER_COM_EARLY 0xf0700020
  476. #define F367TER_AUT_SOFT_RESETN 0xf0700010
  477. #define F367TER_AUT_AGC_ON 0xf0700008
  478. #define F367TER_AUT_EARLY 0xf0700004
  479. #define F367TER_AUT_ROT_EN 0xf0700002
  480. #define F367TER_LOCK_SOFT_RESETN 0xf0700001
  481. /* COMAGC_TARMSB */
  482. #define R367TER_COMAGC_TARMSB 0xf071
  483. #define F367TER_COM_AGC_TARGET_MSB 0xf07100ff
  484. /* COM_AGC_TAR_ENMODE */
  485. #define R367TER_COM_AGC_TAR_ENMODE 0xf072
  486. #define F367TER_COM_AGC_TARGET_LSB 0xf07200f0
  487. #define F367TER_COM_ENMODE 0xf072000f
  488. /* COM_AGC_CFG */
  489. #define R367TER_COM_AGC_CFG 0xf073
  490. #define F367TER_COM_N 0xf07300f8
  491. #define F367TER_COM_STABMODE 0xf0730006
  492. #define F367TER_ERR_SEL 0xf0730001
  493. /* COM_AGC_GAIN1 */
  494. #define R367TER_COM_AGC_GAIN1 0xf074
  495. #define F367TER_COM_GAIN1aCK 0xf07400f0
  496. #define F367TER_COM_GAIN1TRK 0xf074000f
  497. /* AUT_AGC_TARGETMSB */
  498. #define R367TER_AUT_AGC_TARGETMSB 0xf075
  499. #define F367TER_AUT_AGC_TARGET_MSB 0xf07500ff
  500. /* LOCK_DET_MSB */
  501. #define R367TER_LOCK_DET_MSB 0xf076
  502. #define F367TER_LOCK_DETECT_MSB 0xf07600ff
  503. /* AGCTAR_LOCK_LSBS */
  504. #define R367TER_AGCTAR_LOCK_LSBS 0xf077
  505. #define F367TER_AUT_AGC_TARGET_LSB 0xf07700f0
  506. #define F367TER_LOCK_DETECT_LSB 0xf077000f
  507. /* AUT_GAIN_EN */
  508. #define R367TER_AUT_GAIN_EN 0xf078
  509. #define F367TER_AUT_ENMODE 0xf07800f0
  510. #define F367TER_AUT_GAIN2 0xf078000f
  511. /* AUT_CFG */
  512. #define R367TER_AUT_CFG 0xf079
  513. #define F367TER_AUT_N 0xf07900f8
  514. #define F367TER_INT_CHOICE 0xf0790006
  515. #define F367TER_INT_LOAD 0xf0790001
  516. /* LOCKN */
  517. #define R367TER_LOCKN 0xf07a
  518. #define F367TER_LOCK_N 0xf07a00f8
  519. #define F367TER_SEL_IQNTAR 0xf07a0004
  520. #define F367TER_LOCK_DETECT_CHOICE 0xf07a0003
  521. /* INT_X_3 */
  522. #define R367TER_INT_X_3 0xf07b
  523. #define F367TER_INT_X3 0xf07b00ff
  524. /* INT_X_2 */
  525. #define R367TER_INT_X_2 0xf07c
  526. #define F367TER_INT_X2 0xf07c00ff
  527. /* INT_X_1 */
  528. #define R367TER_INT_X_1 0xf07d
  529. #define F367TER_INT_X1 0xf07d00ff
  530. /* INT_X_0 */
  531. #define R367TER_INT_X_0 0xf07e
  532. #define F367TER_INT_X0 0xf07e00ff
  533. /* MIN_ERRX_MSB */
  534. #define R367TER_MIN_ERRX_MSB 0xf07f
  535. #define F367TER_MIN_ERR_X_MSB 0xf07f00ff
  536. /* COR_CTL */
  537. #define R367TER_COR_CTL 0xf080
  538. #define F367TER_CORE_ACTIVE 0xf0800020
  539. #define F367TER_HOLD 0xf0800010
  540. #define F367TER_CORE_STATE_CTL 0xf080000f
  541. /* COR_STAT */
  542. #define R367TER_COR_STAT 0xf081
  543. #define F367TER_SCATT_LOCKED 0xf0810080
  544. #define F367TER_TPS_LOCKED 0xf0810040
  545. #define F367TER_SYR_LOCKED_COR 0xf0810020
  546. #define F367TER_AGC_LOCKED_STAT 0xf0810010
  547. #define F367TER_CORE_STATE_STAT 0xf081000f
  548. /* COR_INTEN */
  549. #define R367TER_COR_INTEN 0xf082
  550. #define F367TER_INTEN 0xf0820080
  551. #define F367TER_INTEN_SYR 0xf0820020
  552. #define F367TER_INTEN_FFT 0xf0820010
  553. #define F367TER_INTEN_AGC 0xf0820008
  554. #define F367TER_INTEN_TPS1 0xf0820004
  555. #define F367TER_INTEN_TPS2 0xf0820002
  556. #define F367TER_INTEN_TPS3 0xf0820001
  557. /* COR_INTSTAT */
  558. #define R367TER_COR_INTSTAT 0xf083
  559. #define F367TER_INTSTAT_SYR 0xf0830020
  560. #define F367TER_INTSTAT_FFT 0xf0830010
  561. #define F367TER_INTSAT_AGC 0xf0830008
  562. #define F367TER_INTSTAT_TPS1 0xf0830004
  563. #define F367TER_INTSTAT_TPS2 0xf0830002
  564. #define F367TER_INTSTAT_TPS3 0xf0830001
  565. /* COR_MODEGUARD */
  566. #define R367TER_COR_MODEGUARD 0xf084
  567. #define F367TER_FORCE 0xf0840010
  568. #define F367TER_MODE 0xf084000c
  569. #define F367TER_GUARD 0xf0840003
  570. /* AGC_CTL */
  571. #define R367TER_AGC_CTL 0xf085
  572. #define F367TER_AGC_TIMING_FACTOR 0xf08500e0
  573. #define F367TER_AGC_LAST 0xf0850010
  574. #define F367TER_AGC_GAIN 0xf085000c
  575. #define F367TER_AGC_NEG 0xf0850002
  576. #define F367TER_AGC_SET 0xf0850001
  577. /* AGC_MANUAL1 */
  578. #define R367TER_AGC_MANUAL1 0xf086
  579. #define F367TER_AGC_VAL_LO 0xf08600ff
  580. /* AGC_MANUAL2 */
  581. #define R367TER_AGC_MANUAL2 0xf087
  582. #define F367TER_AGC_VAL_HI 0xf087000f
  583. /* AGC_TARG */
  584. #define R367TER_AGC_TARG 0xf088
  585. #define F367TER_AGC_TARGET 0xf08800ff
  586. /* AGC_GAIN1 */
  587. #define R367TER_AGC_GAIN1 0xf089
  588. #define F367TER_AGC_GAIN_LO 0xf08900ff
  589. /* AGC_GAIN2 */
  590. #define R367TER_AGC_GAIN2 0xf08a
  591. #define F367TER_AGC_LOCKED_GAIN2 0xf08a0010
  592. #define F367TER_AGC_GAIN_HI 0xf08a000f
  593. /* RESERVED_1 */
  594. #define R367TER_RESERVED_1 0xf08b
  595. #define F367TER_RESERVED1 0xf08b00ff
  596. /* RESERVED_2 */
  597. #define R367TER_RESERVED_2 0xf08c
  598. #define F367TER_RESERVED2 0xf08c00ff
  599. /* RESERVED_3 */
  600. #define R367TER_RESERVED_3 0xf08d
  601. #define F367TER_RESERVED3 0xf08d00ff
  602. /* CAS_CTL */
  603. #define R367TER_CAS_CTL 0xf08e
  604. #define F367TER_CCS_ENABLE 0xf08e0080
  605. #define F367TER_ACS_DISABLE 0xf08e0040
  606. #define F367TER_DAGC_DIS 0xf08e0020
  607. #define F367TER_DAGC_GAIN 0xf08e0018
  608. #define F367TER_CCSMU 0xf08e0007
  609. /* CAS_FREQ */
  610. #define R367TER_CAS_FREQ 0xf08f
  611. #define F367TER_CCS_FREQ 0xf08f00ff
  612. /* CAS_DAGCGAIN */
  613. #define R367TER_CAS_DAGCGAIN 0xf090
  614. #define F367TER_CAS_DAGC_GAIN 0xf09000ff
  615. /* SYR_CTL */
  616. #define R367TER_SYR_CTL 0xf091
  617. #define F367TER_SICTH_ENABLE 0xf0910080
  618. #define F367TER_LONG_ECHO 0xf0910078
  619. #define F367TER_AUTO_LE_EN 0xf0910004
  620. #define F367TER_SYR_BYPASS 0xf0910002
  621. #define F367TER_SYR_TR_DIS 0xf0910001
  622. /* SYR_STAT */
  623. #define R367TER_SYR_STAT 0xf092
  624. #define F367TER_SYR_LOCKED_STAT 0xf0920010
  625. #define F367TER_SYR_MODE 0xf092000c
  626. #define F367TER_SYR_GUARD 0xf0920003
  627. /* SYR_NCO1 */
  628. #define R367TER_SYR_NCO1 0xf093
  629. #define F367TER_SYR_NCO_LO 0xf09300ff
  630. /* SYR_NCO2 */
  631. #define R367TER_SYR_NCO2 0xf094
  632. #define F367TER_SYR_NCO_HI 0xf094003f
  633. /* SYR_OFFSET1 */
  634. #define R367TER_SYR_OFFSET1 0xf095
  635. #define F367TER_SYR_OFFSET_LO 0xf09500ff
  636. /* SYR_OFFSET2 */
  637. #define R367TER_SYR_OFFSET2 0xf096
  638. #define F367TER_SYR_OFFSET_HI 0xf096003f
  639. /* FFT_CTL */
  640. #define R367TER_FFT_CTL 0xf097
  641. #define F367TER_SHIFT_FFT_TRIG 0xf0970018
  642. #define F367TER_FFT_TRIGGER 0xf0970004
  643. #define F367TER_FFT_MANUAL 0xf0970002
  644. #define F367TER_IFFT_MODE 0xf0970001
  645. /* SCR_CTL */
  646. #define R367TER_SCR_CTL 0xf098
  647. #define F367TER_SYRADJDECAY 0xf0980070
  648. #define F367TER_SCR_CPEDIS 0xf0980002
  649. #define F367TER_SCR_DIS 0xf0980001
  650. /* PPM_CTL1 */
  651. #define R367TER_PPM_CTL1 0xf099
  652. #define F367TER_PPM_MAXFREQ 0xf0990030
  653. #define F367TER_PPM_MAXTIM 0xf0990008
  654. #define F367TER_PPM_INVSEL 0xf0990004
  655. #define F367TER_PPM_SCATDIS 0xf0990002
  656. #define F367TER_PPM_BYP 0xf0990001
  657. /* TRL_CTL */
  658. #define R367TER_TRL_CTL 0xf09a
  659. #define F367TER_TRL_NOMRATE_LSB 0xf09a0080
  660. #define F367TER_TRL_GAIN_FACTOR 0xf09a0078
  661. #define F367TER_TRL_LOOPGAIN 0xf09a0007
  662. /* TRL_NOMRATE1 */
  663. #define R367TER_TRL_NOMRATE1 0xf09b
  664. #define F367TER_TRL_NOMRATE_LO 0xf09b00ff
  665. /* TRL_NOMRATE2 */
  666. #define R367TER_TRL_NOMRATE2 0xf09c
  667. #define F367TER_TRL_NOMRATE_HI 0xf09c00ff
  668. /* TRL_TIME1 */
  669. #define R367TER_TRL_TIME1 0xf09d
  670. #define F367TER_TRL_TOFFSET_LO 0xf09d00ff
  671. /* TRL_TIME2 */
  672. #define R367TER_TRL_TIME2 0xf09e
  673. #define F367TER_TRL_TOFFSET_HI 0xf09e00ff
  674. /* CRL_CTL */
  675. #define R367TER_CRL_CTL 0xf09f
  676. #define F367TER_CRL_DIS 0xf09f0080
  677. #define F367TER_CRL_GAIN_FACTOR 0xf09f0078
  678. #define F367TER_CRL_LOOPGAIN 0xf09f0007
  679. /* CRL_FREQ1 */
  680. #define R367TER_CRL_FREQ1 0xf0a0
  681. #define F367TER_CRL_FOFFSET_LO 0xf0a000ff
  682. /* CRL_FREQ2 */
  683. #define R367TER_CRL_FREQ2 0xf0a1
  684. #define F367TER_CRL_FOFFSET_HI 0xf0a100ff
  685. /* CRL_FREQ3 */
  686. #define R367TER_CRL_FREQ3 0xf0a2
  687. #define F367TER_CRL_FOFFSET_VHI 0xf0a200ff
  688. /* TPS_SFRAME_CTL */
  689. #define R367TER_TPS_SFRAME_CTL 0xf0a3
  690. #define F367TER_TPS_SFRAME_SYNC 0xf0a30001
  691. /* CHC_SNR */
  692. #define R367TER_CHC_SNR 0xf0a4
  693. #define F367TER_CHCSNR 0xf0a400ff
  694. /* BDI_CTL */
  695. #define R367TER_BDI_CTL 0xf0a5
  696. #define F367TER_BDI_LPSEL 0xf0a50002
  697. #define F367TER_BDI_SERIAL 0xf0a50001
  698. /* DMP_CTL */
  699. #define R367TER_DMP_CTL 0xf0a6
  700. #define F367TER_DMP_SCALING_FACTOR 0xf0a6001e
  701. #define F367TER_DMP_SDDIS 0xf0a60001
  702. /* TPS_RCVD1 */
  703. #define R367TER_TPS_RCVD1 0xf0a7
  704. #define F367TER_TPS_CHANGE 0xf0a70040
  705. #define F367TER_BCH_OK 0xf0a70020
  706. #define F367TER_TPS_SYNC 0xf0a70010
  707. #define F367TER_TPS_FRAME 0xf0a70003
  708. /* TPS_RCVD2 */
  709. #define R367TER_TPS_RCVD2 0xf0a8
  710. #define F367TER_TPS_HIERMODE 0xf0a80070
  711. #define F367TER_TPS_CONST 0xf0a80003
  712. /* TPS_RCVD3 */
  713. #define R367TER_TPS_RCVD3 0xf0a9
  714. #define F367TER_TPS_LPCODE 0xf0a90070
  715. #define F367TER_TPS_HPCODE 0xf0a90007
  716. /* TPS_RCVD4 */
  717. #define R367TER_TPS_RCVD4 0xf0aa
  718. #define F367TER_TPS_GUARD 0xf0aa0030
  719. #define F367TER_TPS_MODE 0xf0aa0003
  720. /* TPS_ID_CELL1 */
  721. #define R367TER_TPS_ID_CELL1 0xf0ab
  722. #define F367TER_TPS_ID_CELL_LO 0xf0ab00ff
  723. /* TPS_ID_CELL2 */
  724. #define R367TER_TPS_ID_CELL2 0xf0ac
  725. #define F367TER_TPS_ID_CELL_HI 0xf0ac00ff
  726. /* TPS_RCVD5_SET1 */
  727. #define R367TER_TPS_RCVD5_SET1 0xf0ad
  728. #define F367TER_TPS_NA 0xf0ad00fC
  729. #define F367TER_TPS_SETFRAME 0xf0ad0003
  730. /* TPS_SET2 */
  731. #define R367TER_TPS_SET2 0xf0ae
  732. #define F367TER_TPS_SETHIERMODE 0xf0ae0070
  733. #define F367TER_TPS_SETCONST 0xf0ae0003
  734. /* TPS_SET3 */
  735. #define R367TER_TPS_SET3 0xf0af
  736. #define F367TER_TPS_SETLPCODE 0xf0af0070
  737. #define F367TER_TPS_SETHPCODE 0xf0af0007
  738. /* TPS_CTL */
  739. #define R367TER_TPS_CTL 0xf0b0
  740. #define F367TER_TPS_IMM 0xf0b00004
  741. #define F367TER_TPS_BCHDIS 0xf0b00002
  742. #define F367TER_TPS_UPDDIS 0xf0b00001
  743. /* CTL_FFTOSNUM */
  744. #define R367TER_CTL_FFTOSNUM 0xf0b1
  745. #define F367TER_SYMBOL_NUMBER 0xf0b1007f
  746. /* TESTSELECT */
  747. #define R367TER_TESTSELECT 0xf0b2
  748. #define F367TER_TEST_SELECT 0xf0b2001f
  749. /* MSC_REV */
  750. #define R367TER_MSC_REV 0xf0b3
  751. #define F367TER_REV_NUMBER 0xf0b300ff
  752. /* PIR_CTL */
  753. #define R367TER_PIR_CTL 0xf0b4
  754. #define F367TER_FREEZE 0xf0b40001
  755. /* SNR_CARRIER1 */
  756. #define R367TER_SNR_CARRIER1 0xf0b5
  757. #define F367TER_SNR_CARRIER_LO 0xf0b500ff
  758. /* SNR_CARRIER2 */
  759. #define R367TER_SNR_CARRIER2 0xf0b6
  760. #define F367TER_MEAN 0xf0b600c0
  761. #define F367TER_SNR_CARRIER_HI 0xf0b6001f
  762. /* PPM_CPAMP */
  763. #define R367TER_PPM_CPAMP 0xf0b7
  764. #define F367TER_PPM_CPC 0xf0b700ff
  765. /* TSM_AP0 */
  766. #define R367TER_TSM_AP0 0xf0b8
  767. #define F367TER_ADDRESS_BYTE_0 0xf0b800ff
  768. /* TSM_AP1 */
  769. #define R367TER_TSM_AP1 0xf0b9
  770. #define F367TER_ADDRESS_BYTE_1 0xf0b900ff
  771. /* TSM_AP2 */
  772. #define R367TER_TSM_AP2 0xf0bA
  773. #define F367TER_DATA_BYTE_0 0xf0ba00ff
  774. /* TSM_AP3 */
  775. #define R367TER_TSM_AP3 0xf0bB
  776. #define F367TER_DATA_BYTE_1 0xf0bb00ff
  777. /* TSM_AP4 */
  778. #define R367TER_TSM_AP4 0xf0bC
  779. #define F367TER_DATA_BYTE_2 0xf0bc00ff
  780. /* TSM_AP5 */
  781. #define R367TER_TSM_AP5 0xf0bD
  782. #define F367TER_DATA_BYTE_3 0xf0bd00ff
  783. /* TSM_AP6 */
  784. #define R367TER_TSM_AP6 0xf0bE
  785. #define F367TER_TSM_AP_6 0xf0be00ff
  786. /* TSM_AP7 */
  787. #define R367TER_TSM_AP7 0xf0bF
  788. #define F367TER_MEM_SELECT_BYTE 0xf0bf00ff
  789. /* TSTRES */
  790. #define R367TER_TSTRES 0xf0c0
  791. #define F367TER_FRES_DISPLAY 0xf0c00080
  792. #define F367TER_FRES_FIFO_AD 0xf0c00020
  793. #define F367TER_FRESRS 0xf0c00010
  794. #define F367TER_FRESACS 0xf0c00008
  795. #define F367TER_FRESFEC 0xf0c00004
  796. #define F367TER_FRES_PRIF 0xf0c00002
  797. #define F367TER_FRESCORE 0xf0c00001
  798. /* ANACTRL */
  799. #define R367TER_ANACTRL 0xf0c1
  800. #define F367TER_BYPASS_XTAL 0xf0c10040
  801. #define F367TER_BYPASS_PLLXN 0xf0c1000c
  802. #define F367TER_DIS_PAD_OSC 0xf0c10002
  803. #define F367TER_STDBY_PLLXN 0xf0c10001
  804. /* TSTBUS */
  805. #define R367TER_TSTBUS 0xf0c2
  806. #define F367TER_TS_BYTE_CLK_INV 0xf0c20080
  807. #define F367TER_CFG_IP 0xf0c20070
  808. #define F367TER_CFG_TST 0xf0c2000f
  809. /* TSTRATE */
  810. #define R367TER_TSTRATE 0xf0c6
  811. #define F367TER_FORCEPHA 0xf0c60080
  812. #define F367TER_FNEWPHA 0xf0c60010
  813. #define F367TER_FROT90 0xf0c60008
  814. #define F367TER_FR 0xf0c60007
  815. /* CONSTMODE */
  816. #define R367TER_CONSTMODE 0xf0cb
  817. #define F367TER_TST_PRIF 0xf0cb00e0
  818. #define F367TER_CAR_TYPE 0xf0cb0018
  819. #define F367TER_CONST_MODE 0xf0cb0003
  820. /* CONSTCARR1 */
  821. #define R367TER_CONSTCARR1 0xf0cc
  822. #define F367TER_CONST_CARR_LO 0xf0cc00ff
  823. /* CONSTCARR2 */
  824. #define R367TER_CONSTCARR2 0xf0cd
  825. #define F367TER_CONST_CARR_HI 0xf0cd001f
  826. /* ICONSTEL */
  827. #define R367TER_ICONSTEL 0xf0ce
  828. #define F367TER_PICONSTEL 0xf0ce00ff
  829. /* QCONSTEL */
  830. #define R367TER_QCONSTEL 0xf0cf
  831. #define F367TER_PQCONSTEL 0xf0cf00ff
  832. /* TSTBISTRES0 */
  833. #define R367TER_TSTBISTRES0 0xf0d0
  834. #define F367TER_BEND_PPM 0xf0d00080
  835. #define F367TER_BBAD_PPM 0xf0d00040
  836. #define F367TER_BEND_FFTW 0xf0d00020
  837. #define F367TER_BBAD_FFTW 0xf0d00010
  838. #define F367TER_BEND_FFT_BUF 0xf0d00008
  839. #define F367TER_BBAD_FFT_BUF 0xf0d00004
  840. #define F367TER_BEND_SYR 0xf0d00002
  841. #define F367TER_BBAD_SYR 0xf0d00001
  842. /* TSTBISTRES1 */
  843. #define R367TER_TSTBISTRES1 0xf0d1
  844. #define F367TER_BEND_CHC_CP 0xf0d10080
  845. #define F367TER_BBAD_CHC_CP 0xf0d10040
  846. #define F367TER_BEND_CHCI 0xf0d10020
  847. #define F367TER_BBAD_CHCI 0xf0d10010
  848. #define F367TER_BEND_BDI 0xf0d10008
  849. #define F367TER_BBAD_BDI 0xf0d10004
  850. #define F367TER_BEND_SDI 0xf0d10002
  851. #define F367TER_BBAD_SDI 0xf0d10001
  852. /* TSTBISTRES2 */
  853. #define R367TER_TSTBISTRES2 0xf0d2
  854. #define F367TER_BEND_CHC_INC 0xf0d20080
  855. #define F367TER_BBAD_CHC_INC 0xf0d20040
  856. #define F367TER_BEND_CHC_SPP 0xf0d20020
  857. #define F367TER_BBAD_CHC_SPP 0xf0d20010
  858. #define F367TER_BEND_CHC_CPP 0xf0d20008
  859. #define F367TER_BBAD_CHC_CPP 0xf0d20004
  860. #define F367TER_BEND_CHC_SP 0xf0d20002
  861. #define F367TER_BBAD_CHC_SP 0xf0d20001
  862. /* TSTBISTRES3 */
  863. #define R367TER_TSTBISTRES3 0xf0d3
  864. #define F367TER_BEND_QAM 0xf0d30080
  865. #define F367TER_BBAD_QAM 0xf0d30040
  866. #define F367TER_BEND_SFEC_VIT 0xf0d30020
  867. #define F367TER_BBAD_SFEC_VIT 0xf0d30010
  868. #define F367TER_BEND_SFEC_DLINE 0xf0d30008
  869. #define F367TER_BBAD_SFEC_DLINE 0xf0d30004
  870. #define F367TER_BEND_SFEC_HW 0xf0d30002
  871. #define F367TER_BBAD_SFEC_HW 0xf0d30001
  872. /* RF_AGC1 */
  873. #define R367TER_RF_AGC1 0xf0d4
  874. #define F367TER_RF_AGC1_LEVEL_HI 0xf0d400ff
  875. /* RF_AGC2 */
  876. #define R367TER_RF_AGC2 0xf0d5
  877. #define F367TER_REF_ADGP 0xf0d50080
  878. #define F367TER_STDBY_ADCGP 0xf0d50020
  879. #define F367TER_CHANNEL_SEL 0xf0d5001c
  880. #define F367TER_RF_AGC1_LEVEL_LO 0xf0d50003
  881. /* ANADIGCTRL */
  882. #define R367TER_ANADIGCTRL 0xf0d7
  883. #define F367TER_SEL_CLKDEM 0xf0d70020
  884. #define F367TER_EN_BUFFER_Q 0xf0d70010
  885. #define F367TER_EN_BUFFER_I 0xf0d70008
  886. #define F367TER_ADC_RIS_EGDE 0xf0d70004
  887. #define F367TER_SGN_ADC 0xf0d70002
  888. #define F367TER_SEL_AD12_SYNC 0xf0d70001
  889. /* PLLMDIV */
  890. #define R367TER_PLLMDIV 0xf0d8
  891. #define F367TER_PLL_MDIV 0xf0d800ff
  892. /* PLLNDIV */
  893. #define R367TER_PLLNDIV 0xf0d9
  894. #define F367TER_PLL_NDIV 0xf0d900ff
  895. /* PLLSETUP */
  896. #define R367TER_PLLSETUP 0xf0dA
  897. #define F367TER_PLL_PDIV 0xf0da0070
  898. #define F367TER_PLL_KDIV 0xf0da000f
  899. /* DUAL_AD12 */
  900. #define R367TER_DUAL_AD12 0xf0dB
  901. #define F367TER_FS20M 0xf0db0020
  902. #define F367TER_FS50M 0xf0db0010
  903. #define F367TER_INMODe0 0xf0db0008
  904. #define F367TER_POFFQ 0xf0db0004
  905. #define F367TER_POFFI 0xf0db0002
  906. #define F367TER_INMODE1 0xf0db0001
  907. /* TSTBIST */
  908. #define R367TER_TSTBIST 0xf0dC
  909. #define F367TER_TST_BYP_CLK 0xf0dc0080
  910. #define F367TER_TST_GCLKENA_STD 0xf0dc0040
  911. #define F367TER_TST_GCLKENA 0xf0dc0020
  912. #define F367TER_TST_MEMBIST 0xf0dc001f
  913. /* PAD_COMP_CTRL */
  914. #define R367TER_PAD_COMP_CTRL 0xf0dD
  915. #define F367TER_COMPTQ 0xf0dd0010
  916. #define F367TER_COMPEN 0xf0dd0008
  917. #define F367TER_FREEZE2 0xf0dd0004
  918. #define F367TER_SLEEP_INHBT 0xf0dd0002
  919. #define F367TER_CHIP_SLEEP 0xf0dd0001
  920. /* PAD_COMP_WR */
  921. #define R367TER_PAD_COMP_WR 0xf0de
  922. #define F367TER_WR_ASRC 0xf0de007f
  923. /* PAD_COMP_RD */
  924. #define R367TER_PAD_COMP_RD 0xf0df
  925. #define F367TER_COMPOK 0xf0df0080
  926. #define F367TER_RD_ASRC 0xf0df007f
  927. /* SYR_TARGET_FFTADJT_MSB */
  928. #define R367TER_SYR_TARGET_FFTADJT_MSB 0xf100
  929. #define F367TER_SYR_START 0xf1000080
  930. #define F367TER_SYR_TARGET_FFTADJ_HI 0xf100000f
  931. /* SYR_TARGET_FFTADJT_LSB */
  932. #define R367TER_SYR_TARGET_FFTADJT_LSB 0xf101
  933. #define F367TER_SYR_TARGET_FFTADJ_LO 0xf10100ff
  934. /* SYR_TARGET_CHCADJT_MSB */
  935. #define R367TER_SYR_TARGET_CHCADJT_MSB 0xf102
  936. #define F367TER_SYR_TARGET_CHCADJ_HI 0xf102000f
  937. /* SYR_TARGET_CHCADJT_LSB */
  938. #define R367TER_SYR_TARGET_CHCADJT_LSB 0xf103
  939. #define F367TER_SYR_TARGET_CHCADJ_LO 0xf10300ff
  940. /* SYR_FLAG */
  941. #define R367TER_SYR_FLAG 0xf104
  942. #define F367TER_TRIG_FLG1 0xf1040080
  943. #define F367TER_TRIG_FLG0 0xf1040040
  944. #define F367TER_FFT_FLG1 0xf1040008
  945. #define F367TER_FFT_FLG0 0xf1040004
  946. #define F367TER_CHC_FLG1 0xf1040002
  947. #define F367TER_CHC_FLG0 0xf1040001
  948. /* CRL_TARGET1 */
  949. #define R367TER_CRL_TARGET1 0xf105
  950. #define F367TER_CRL_START 0xf1050080
  951. #define F367TER_CRL_TARGET_VHI 0xf105000f
  952. /* CRL_TARGET2 */
  953. #define R367TER_CRL_TARGET2 0xf106
  954. #define F367TER_CRL_TARGET_HI 0xf10600ff
  955. /* CRL_TARGET3 */
  956. #define R367TER_CRL_TARGET3 0xf107
  957. #define F367TER_CRL_TARGET_LO 0xf10700ff
  958. /* CRL_TARGET4 */
  959. #define R367TER_CRL_TARGET4 0xf108
  960. #define F367TER_CRL_TARGET_VLO 0xf10800ff
  961. /* CRL_FLAG */
  962. #define R367TER_CRL_FLAG 0xf109
  963. #define F367TER_CRL_FLAG1 0xf1090002
  964. #define F367TER_CRL_FLAG0 0xf1090001
  965. /* TRL_TARGET1 */
  966. #define R367TER_TRL_TARGET1 0xf10a
  967. #define F367TER_TRL_TARGET_HI 0xf10a00ff
  968. /* TRL_TARGET2 */
  969. #define R367TER_TRL_TARGET2 0xf10b
  970. #define F367TER_TRL_TARGET_LO 0xf10b00ff
  971. /* TRL_CHC */
  972. #define R367TER_TRL_CHC 0xf10c
  973. #define F367TER_TRL_START 0xf10c0080
  974. #define F367TER_CHC_START 0xf10c0040
  975. #define F367TER_TRL_FLAG1 0xf10c0002
  976. #define F367TER_TRL_FLAG0 0xf10c0001
  977. /* CHC_SNR_TARG */
  978. #define R367TER_CHC_SNR_TARG 0xf10d
  979. #define F367TER_CHC_SNR_TARGET 0xf10d00ff
  980. /* TOP_TRACK */
  981. #define R367TER_TOP_TRACK 0xf10e
  982. #define F367TER_TOP_START 0xf10e0080
  983. #define F367TER_FIRST_FLAG 0xf10e0070
  984. #define F367TER_TOP_FLAG1 0xf10e0008
  985. #define F367TER_TOP_FLAG0 0xf10e0004
  986. #define F367TER_CHC_FLAG1 0xf10e0002
  987. #define F367TER_CHC_FLAG0 0xf10e0001
  988. /* TRACKER_FREE1 */
  989. #define R367TER_TRACKER_FREE1 0xf10f
  990. #define F367TER_TRACKER_FREE_1 0xf10f00ff
  991. /* ERROR_CRL1 */
  992. #define R367TER_ERROR_CRL1 0xf110
  993. #define F367TER_ERROR_CRL_VHI 0xf11000ff
  994. /* ERROR_CRL2 */
  995. #define R367TER_ERROR_CRL2 0xf111
  996. #define F367TER_ERROR_CRL_HI 0xf11100ff
  997. /* ERROR_CRL3 */
  998. #define R367TER_ERROR_CRL3 0xf112
  999. #define F367TER_ERROR_CRL_LOI 0xf11200ff
  1000. /* ERROR_CRL4 */
  1001. #define R367TER_ERROR_CRL4 0xf113
  1002. #define F367TER_ERROR_CRL_VLO 0xf11300ff
  1003. /* DEC_NCO1 */
  1004. #define R367TER_DEC_NCO1 0xf114
  1005. #define F367TER_DEC_NCO_VHI 0xf11400ff
  1006. /* DEC_NCO2 */
  1007. #define R367TER_DEC_NCO2 0xf115
  1008. #define F367TER_DEC_NCO_HI 0xf11500ff
  1009. /* DEC_NCO3 */
  1010. #define R367TER_DEC_NCO3 0xf116
  1011. #define F367TER_DEC_NCO_LO 0xf11600ff
  1012. /* SNR */
  1013. #define R367TER_SNR 0xf117
  1014. #define F367TER_SNRATIO 0xf11700ff
  1015. /* SYR_FFTADJ1 */
  1016. #define R367TER_SYR_FFTADJ1 0xf118
  1017. #define F367TER_SYR_FFTADJ_HI 0xf11800ff
  1018. /* SYR_FFTADJ2 */
  1019. #define R367TER_SYR_FFTADJ2 0xf119
  1020. #define F367TER_SYR_FFTADJ_LO 0xf11900ff
  1021. /* SYR_CHCADJ1 */
  1022. #define R367TER_SYR_CHCADJ1 0xf11a
  1023. #define F367TER_SYR_CHCADJ_HI 0xf11a00ff
  1024. /* SYR_CHCADJ2 */
  1025. #define R367TER_SYR_CHCADJ2 0xf11b
  1026. #define F367TER_SYR_CHCADJ_LO 0xf11b00ff
  1027. /* SYR_OFF */
  1028. #define R367TER_SYR_OFF 0xf11c
  1029. #define F367TER_SYR_OFFSET 0xf11c00ff
  1030. /* PPM_OFFSET1 */
  1031. #define R367TER_PPM_OFFSET1 0xf11d
  1032. #define F367TER_PPM_OFFSET_HI 0xf11d00ff
  1033. /* PPM_OFFSET2 */
  1034. #define R367TER_PPM_OFFSET2 0xf11e
  1035. #define F367TER_PPM_OFFSET_LO 0xf11e00ff
  1036. /* TRACKER_FREE2 */
  1037. #define R367TER_TRACKER_FREE2 0xf11f
  1038. #define F367TER_TRACKER_FREE_2 0xf11f00ff
  1039. /* DEBG_LT10 */
  1040. #define R367TER_DEBG_LT10 0xf120
  1041. #define F367TER_DEBUG_LT10 0xf12000ff
  1042. /* DEBG_LT11 */
  1043. #define R367TER_DEBG_LT11 0xf121
  1044. #define F367TER_DEBUG_LT11 0xf12100ff
  1045. /* DEBG_LT12 */
  1046. #define R367TER_DEBG_LT12 0xf122
  1047. #define F367TER_DEBUG_LT12 0xf12200ff
  1048. /* DEBG_LT13 */
  1049. #define R367TER_DEBG_LT13 0xf123
  1050. #define F367TER_DEBUG_LT13 0xf12300ff
  1051. /* DEBG_LT14 */
  1052. #define R367TER_DEBG_LT14 0xf124
  1053. #define F367TER_DEBUG_LT14 0xf12400ff
  1054. /* DEBG_LT15 */
  1055. #define R367TER_DEBG_LT15 0xf125
  1056. #define F367TER_DEBUG_LT15 0xf12500ff
  1057. /* DEBG_LT16 */
  1058. #define R367TER_DEBG_LT16 0xf126
  1059. #define F367TER_DEBUG_LT16 0xf12600ff
  1060. /* DEBG_LT17 */
  1061. #define R367TER_DEBG_LT17 0xf127
  1062. #define F367TER_DEBUG_LT17 0xf12700ff
  1063. /* DEBG_LT18 */
  1064. #define R367TER_DEBG_LT18 0xf128
  1065. #define F367TER_DEBUG_LT18 0xf12800ff
  1066. /* DEBG_LT19 */
  1067. #define R367TER_DEBG_LT19 0xf129
  1068. #define F367TER_DEBUG_LT19 0xf12900ff
  1069. /* DEBG_LT1a */
  1070. #define R367TER_DEBG_LT1A 0xf12a
  1071. #define F367TER_DEBUG_LT1A 0xf12a00ff
  1072. /* DEBG_LT1b */
  1073. #define R367TER_DEBG_LT1B 0xf12b
  1074. #define F367TER_DEBUG_LT1B 0xf12b00ff
  1075. /* DEBG_LT1c */
  1076. #define R367TER_DEBG_LT1C 0xf12c
  1077. #define F367TER_DEBUG_LT1C 0xf12c00ff
  1078. /* DEBG_LT1D */
  1079. #define R367TER_DEBG_LT1D 0xf12d
  1080. #define F367TER_DEBUG_LT1D 0xf12d00ff
  1081. /* DEBG_LT1E */
  1082. #define R367TER_DEBG_LT1E 0xf12e
  1083. #define F367TER_DEBUG_LT1E 0xf12e00ff
  1084. /* DEBG_LT1F */
  1085. #define R367TER_DEBG_LT1F 0xf12f
  1086. #define F367TER_DEBUG_LT1F 0xf12f00ff
  1087. /* RCCFGH */
  1088. #define R367TER_RCCFGH 0xf200
  1089. #define F367TER_TSRCFIFO_DVBCI 0xf2000080
  1090. #define F367TER_TSRCFIFO_SERIAL 0xf2000040
  1091. #define F367TER_TSRCFIFO_DISABLE 0xf2000020
  1092. #define F367TER_TSFIFO_2TORC 0xf2000010
  1093. #define F367TER_TSRCFIFO_HSGNLOUT 0xf2000008
  1094. #define F367TER_TSRCFIFO_ERRMODE 0xf2000006
  1095. #define F367TER_RCCFGH_0 0xf2000001
  1096. /* RCCFGM */
  1097. #define R367TER_RCCFGM 0xf201
  1098. #define F367TER_TSRCFIFO_MANSPEED 0xf20100c0
  1099. #define F367TER_TSRCFIFO_PERMDATA 0xf2010020
  1100. #define F367TER_TSRCFIFO_NONEWSGNL 0xf2010010
  1101. #define F367TER_RCBYTE_OVERSAMPLING 0xf201000e
  1102. #define F367TER_TSRCFIFO_INVDATA 0xf2010001
  1103. /* RCCFGL */
  1104. #define R367TER_RCCFGL 0xf202
  1105. #define F367TER_TSRCFIFO_BCLKDEL1cK 0xf20200c0
  1106. #define F367TER_RCCFGL_5 0xf2020020
  1107. #define F367TER_TSRCFIFO_DUTY50 0xf2020010
  1108. #define F367TER_TSRCFIFO_NSGNL2dATA 0xf2020008
  1109. #define F367TER_TSRCFIFO_DISSERMUX 0xf2020004
  1110. #define F367TER_RCCFGL_1 0xf2020002
  1111. #define F367TER_TSRCFIFO_STOPCKDIS 0xf2020001
  1112. /* RCINSDELH */
  1113. #define R367TER_RCINSDELH 0xf203
  1114. #define F367TER_TSRCDEL_SYNCBYTE 0xf2030080
  1115. #define F367TER_TSRCDEL_XXHEADER 0xf2030040
  1116. #define F367TER_TSRCDEL_BBHEADER 0xf2030020
  1117. #define F367TER_TSRCDEL_DATAFIELD 0xf2030010
  1118. #define F367TER_TSRCINSDEL_ISCR 0xf2030008
  1119. #define F367TER_TSRCINSDEL_NPD 0xf2030004
  1120. #define F367TER_TSRCINSDEL_RSPARITY 0xf2030002
  1121. #define F367TER_TSRCINSDEL_CRC8 0xf2030001
  1122. /* RCINSDELM */
  1123. #define R367TER_RCINSDELM 0xf204
  1124. #define F367TER_TSRCINS_BBPADDING 0xf2040080
  1125. #define F367TER_TSRCINS_BCHFEC 0xf2040040
  1126. #define F367TER_TSRCINS_LDPCFEC 0xf2040020
  1127. #define F367TER_TSRCINS_EMODCOD 0xf2040010
  1128. #define F367TER_TSRCINS_TOKEN 0xf2040008
  1129. #define F367TER_TSRCINS_XXXERR 0xf2040004
  1130. #define F367TER_TSRCINS_MATYPE 0xf2040002
  1131. #define F367TER_TSRCINS_UPL 0xf2040001
  1132. /* RCINSDELL */
  1133. #define R367TER_RCINSDELL 0xf205
  1134. #define F367TER_TSRCINS_DFL 0xf2050080
  1135. #define F367TER_TSRCINS_SYNCD 0xf2050040
  1136. #define F367TER_TSRCINS_BLOCLEN 0xf2050020
  1137. #define F367TER_TSRCINS_SIGPCOUNT 0xf2050010
  1138. #define F367TER_TSRCINS_FIFO 0xf2050008
  1139. #define F367TER_TSRCINS_REALPACK 0xf2050004
  1140. #define F367TER_TSRCINS_TSCONFIG 0xf2050002
  1141. #define F367TER_TSRCINS_LATENCY 0xf2050001
  1142. /* RCSTATUS */
  1143. #define R367TER_RCSTATUS 0xf206
  1144. #define F367TER_TSRCFIFO_LINEOK 0xf2060080
  1145. #define F367TER_TSRCFIFO_ERROR 0xf2060040
  1146. #define F367TER_TSRCFIFO_DATA7 0xf2060020
  1147. #define F367TER_RCSTATUS_4 0xf2060010
  1148. #define F367TER_TSRCFIFO_DEMODSEL 0xf2060008
  1149. #define F367TER_TSRC1FIFOSPEED_STORE 0xf2060004
  1150. #define F367TER_RCSTATUS_1 0xf2060002
  1151. #define F367TER_TSRCSERIAL_IMPOSSIBLE 0xf2060001
  1152. /* RCSPEED */
  1153. #define R367TER_RCSPEED 0xf207
  1154. #define F367TER_TSRCFIFO_OUTSPEED 0xf20700ff
  1155. /* RCDEBUGM */
  1156. #define R367TER_RCDEBUGM 0xf208
  1157. #define F367TER_SD_UNSYNC 0xf2080080
  1158. #define F367TER_ULFLOCK_DETECTM 0xf2080040
  1159. #define F367TER_SUL_SELECTOS 0xf2080020
  1160. #define F367TER_DILUL_NOSCRBLE 0xf2080010
  1161. #define F367TER_NUL_SCRB 0xf2080008
  1162. #define F367TER_UL_SCRB 0xf2080004
  1163. #define F367TER_SCRAULBAD 0xf2080002
  1164. #define F367TER_SCRAUL_UNSYNC 0xf2080001
  1165. /* RCDEBUGL */
  1166. #define R367TER_RCDEBUGL 0xf209
  1167. #define F367TER_RS_ERR 0xf2090080
  1168. #define F367TER_LLFLOCK_DETECTM 0xf2090040
  1169. #define F367TER_NOT_SUL_SELECTOS 0xf2090020
  1170. #define F367TER_DILLL_NOSCRBLE 0xf2090010
  1171. #define F367TER_NLL_SCRB 0xf2090008
  1172. #define F367TER_LL_SCRB 0xf2090004
  1173. #define F367TER_SCRALLBAD 0xf2090002
  1174. #define F367TER_SCRALL_UNSYNC 0xf2090001
  1175. /* RCOBSCFG */
  1176. #define R367TER_RCOBSCFG 0xf20a
  1177. #define F367TER_TSRCFIFO_OBSCFG 0xf20a00ff
  1178. /* RCOBSM */
  1179. #define R367TER_RCOBSM 0xf20b
  1180. #define F367TER_TSRCFIFO_OBSDATA_HI 0xf20b00ff
  1181. /* RCOBSL */
  1182. #define R367TER_RCOBSL 0xf20c
  1183. #define F367TER_TSRCFIFO_OBSDATA_LO 0xf20c00ff
  1184. /* RCFECSPY */
  1185. #define R367TER_RCFECSPY 0xf210
  1186. #define F367TER_SPYRC_ENABLE 0xf2100080
  1187. #define F367TER_RCNO_SYNCBYTE 0xf2100040
  1188. #define F367TER_RCSERIAL_MODE 0xf2100020
  1189. #define F367TER_RCUNUSUAL_PACKET 0xf2100010
  1190. #define F367TER_BERRCMETER_DATAMODE 0xf210000c
  1191. #define F367TER_BERRCMETER_LMODE 0xf2100002
  1192. #define F367TER_BERRCMETER_RESET 0xf2100001
  1193. /* RCFSPYCFG */
  1194. #define R367TER_RCFSPYCFG 0xf211
  1195. #define F367TER_FECSPYRC_INPUT 0xf21100c0
  1196. #define F367TER_RCRST_ON_ERROR 0xf2110020
  1197. #define F367TER_RCONE_SHOT 0xf2110010
  1198. #define F367TER_RCI2C_MODE 0xf211000c
  1199. #define F367TER_SPYRC_HSTERESIS 0xf2110003
  1200. /* RCFSPYDATA */
  1201. #define R367TER_RCFSPYDATA 0xf212
  1202. #define F367TER_SPYRC_STUFFING 0xf2120080
  1203. #define F367TER_RCNOERR_PKTJITTER 0xf2120040
  1204. #define F367TER_SPYRC_CNULLPKT 0xf2120020
  1205. #define F367TER_SPYRC_OUTDATA_MODE 0xf212001f
  1206. /* RCFSPYOUT */
  1207. #define R367TER_RCFSPYOUT 0xf213
  1208. #define F367TER_FSPYRC_DIRECT 0xf2130080
  1209. #define F367TER_RCFSPYOUT_6 0xf2130040
  1210. #define F367TER_SPYRC_OUTDATA_BUS 0xf2130038
  1211. #define F367TER_RCSTUFF_MODE 0xf2130007
  1212. /* RCFSTATUS */
  1213. #define R367TER_RCFSTATUS 0xf214
  1214. #define F367TER_SPYRC_ENDSIM 0xf2140080
  1215. #define F367TER_RCVALID_SIM 0xf2140040
  1216. #define F367TER_RCFOUND_SIGNAL 0xf2140020
  1217. #define F367TER_RCDSS_SYNCBYTE 0xf2140010
  1218. #define F367TER_RCRESULT_STATE 0xf214000f
  1219. /* RCFGOODPACK */
  1220. #define R367TER_RCFGOODPACK 0xf215
  1221. #define F367TER_RCGOOD_PACKET 0xf21500ff
  1222. /* RCFPACKCNT */
  1223. #define R367TER_RCFPACKCNT 0xf216
  1224. #define F367TER_RCPACKET_COUNTER 0xf21600ff
  1225. /* RCFSPYMISC */
  1226. #define R367TER_RCFSPYMISC 0xf217
  1227. #define F367TER_RCLABEL_COUNTER 0xf21700ff
  1228. /* RCFBERCPT4 */
  1229. #define R367TER_RCFBERCPT4 0xf218
  1230. #define F367TER_FBERRCMETER_CPT_MMMMSB 0xf21800ff
  1231. /* RCFBERCPT3 */
  1232. #define R367TER_RCFBERCPT3 0xf219
  1233. #define F367TER_FBERRCMETER_CPT_MMMSB 0xf21900ff
  1234. /* RCFBERCPT2 */
  1235. #define R367TER_RCFBERCPT2 0xf21a
  1236. #define F367TER_FBERRCMETER_CPT_MMSB 0xf21a00ff
  1237. /* RCFBERCPT1 */
  1238. #define R367TER_RCFBERCPT1 0xf21b
  1239. #define F367TER_FBERRCMETER_CPT_MSB 0xf21b00ff
  1240. /* RCFBERCPT0 */
  1241. #define R367TER_RCFBERCPT0 0xf21c
  1242. #define F367TER_FBERRCMETER_CPT_LSB 0xf21c00ff
  1243. /* RCFBERERR2 */
  1244. #define R367TER_RCFBERERR2 0xf21d
  1245. #define F367TER_FBERRCMETER_ERR_HI 0xf21d00ff
  1246. /* RCFBERERR1 */
  1247. #define R367TER_RCFBERERR1 0xf21e
  1248. #define F367TER_FBERRCMETER_ERR 0xf21e00ff
  1249. /* RCFBERERR0 */
  1250. #define R367TER_RCFBERERR0 0xf21f
  1251. #define F367TER_FBERRCMETER_ERR_LO 0xf21f00ff
  1252. /* RCFSTATESM */
  1253. #define R367TER_RCFSTATESM 0xf220
  1254. #define F367TER_RCRSTATE_F 0xf2200080
  1255. #define F367TER_RCRSTATE_E 0xf2200040
  1256. #define F367TER_RCRSTATE_D 0xf2200020
  1257. #define F367TER_RCRSTATE_C 0xf2200010
  1258. #define F367TER_RCRSTATE_B 0xf2200008
  1259. #define F367TER_RCRSTATE_A 0xf2200004
  1260. #define F367TER_RCRSTATE_9 0xf2200002
  1261. #define F367TER_RCRSTATE_8 0xf2200001
  1262. /* RCFSTATESL */
  1263. #define R367TER_RCFSTATESL 0xf221
  1264. #define F367TER_RCRSTATE_7 0xf2210080
  1265. #define F367TER_RCRSTATE_6 0xf2210040
  1266. #define F367TER_RCRSTATE_5 0xf2210020
  1267. #define F367TER_RCRSTATE_4 0xf2210010
  1268. #define F367TER_RCRSTATE_3 0xf2210008
  1269. #define F367TER_RCRSTATE_2 0xf2210004
  1270. #define F367TER_RCRSTATE_1 0xf2210002
  1271. #define F367TER_RCRSTATE_0 0xf2210001
  1272. /* RCFSPYBER */
  1273. #define R367TER_RCFSPYBER 0xf222
  1274. #define F367TER_RCFSPYBER_7 0xf2220080
  1275. #define F367TER_SPYRCOBS_XORREAD 0xf2220040
  1276. #define F367TER_FSPYRCBER_OBSMODE 0xf2220020
  1277. #define F367TER_FSPYRCBER_SYNCBYT 0xf2220010
  1278. #define F367TER_FSPYRCBER_UNSYNC 0xf2220008
  1279. #define F367TER_FSPYRCBER_CTIME 0xf2220007
  1280. /* RCFSPYDISTM */
  1281. #define R367TER_RCFSPYDISTM 0xf223
  1282. #define F367TER_RCPKTTIME_DISTANCE_HI 0xf22300ff
  1283. /* RCFSPYDISTL */
  1284. #define R367TER_RCFSPYDISTL 0xf224
  1285. #define F367TER_RCPKTTIME_DISTANCE_LO 0xf22400ff
  1286. /* RCFSPYOBS7 */
  1287. #define R367TER_RCFSPYOBS7 0xf228
  1288. #define F367TER_RCSPYOBS_SPYFAIL 0xf2280080
  1289. #define F367TER_RCSPYOBS_SPYFAIL1 0xf2280040
  1290. #define F367TER_RCSPYOBS_ERROR 0xf2280020
  1291. #define F367TER_RCSPYOBS_STROUT 0xf2280010
  1292. #define F367TER_RCSPYOBS_RESULTSTATE1 0xf228000f
  1293. /* RCFSPYOBS6 */
  1294. #define R367TER_RCFSPYOBS6 0xf229
  1295. #define F367TER_RCSPYOBS_RESULTSTATe0 0xf22900f0
  1296. #define F367TER_RCSPYOBS_RESULTSTATEM1 0xf229000f
  1297. /* RCFSPYOBS5 */
  1298. #define R367TER_RCFSPYOBS5 0xf22a
  1299. #define F367TER_RCSPYOBS_BYTEOFPACKET1 0xf22a00ff
  1300. /* RCFSPYOBS4 */
  1301. #define R367TER_RCFSPYOBS4 0xf22b
  1302. #define F367TER_RCSPYOBS_BYTEVALUE1 0xf22b00ff
  1303. /* RCFSPYOBS3 */
  1304. #define R367TER_RCFSPYOBS3 0xf22c
  1305. #define F367TER_RCSPYOBS_DATA1 0xf22c00ff
  1306. /* RCFSPYOBS2 */
  1307. #define R367TER_RCFSPYOBS2 0xf22d
  1308. #define F367TER_RCSPYOBS_DATa0 0xf22d00ff
  1309. /* RCFSPYOBS1 */
  1310. #define R367TER_RCFSPYOBS1 0xf22e
  1311. #define F367TER_RCSPYOBS_DATAM1 0xf22e00ff
  1312. /* RCFSPYOBS0 */
  1313. #define R367TER_RCFSPYOBS0 0xf22f
  1314. #define F367TER_RCSPYOBS_DATAM2 0xf22f00ff
  1315. /* TSGENERAL */
  1316. #define R367TER_TSGENERAL 0xf230
  1317. #define F367TER_TSGENERAL_7 0xf2300080
  1318. #define F367TER_TSGENERAL_6 0xf2300040
  1319. #define F367TER_TSFIFO_BCLK1aLL 0xf2300020
  1320. #define F367TER_TSGENERAL_4 0xf2300010
  1321. #define F367TER_MUXSTREAM_OUTMODE 0xf2300008
  1322. #define F367TER_TSFIFO_PERMPARAL 0xf2300006
  1323. #define F367TER_RST_REEDSOLO 0xf2300001
  1324. /* RC1SPEED */
  1325. #define R367TER_RC1SPEED 0xf231
  1326. #define F367TER_TSRCFIFO1_OUTSPEED 0xf23100ff
  1327. /* TSGSTATUS */
  1328. #define R367TER_TSGSTATUS 0xf232
  1329. #define F367TER_TSGSTATUS_7 0xf2320080
  1330. #define F367TER_TSGSTATUS_6 0xf2320040
  1331. #define F367TER_RSMEM_FULL 0xf2320020
  1332. #define F367TER_RS_MULTCALC 0xf2320010
  1333. #define F367TER_RSIN_OVERTIME 0xf2320008
  1334. #define F367TER_TSFIFO3_DEMODSEL 0xf2320004
  1335. #define F367TER_TSFIFO2_DEMODSEL 0xf2320002
  1336. #define F367TER_TSFIFO1_DEMODSEL 0xf2320001
  1337. /* FECM */
  1338. #define R367TER_FECM 0xf233
  1339. #define F367TER_DSS_DVB 0xf2330080
  1340. #define F367TER_DEMOD_BYPASS 0xf2330040
  1341. #define F367TER_CMP_SLOWMODE 0xf2330020
  1342. #define F367TER_DSS_SRCH 0xf2330010
  1343. #define F367TER_FECM_3 0xf2330008
  1344. #define F367TER_DIFF_MODEVIT 0xf2330004
  1345. #define F367TER_SYNCVIT 0xf2330002
  1346. #define F367TER_I2CSYM 0xf2330001
  1347. /* VTH12 */
  1348. #define R367TER_VTH12 0xf234
  1349. #define F367TER_VTH_12 0xf23400ff
  1350. /* VTH23 */
  1351. #define R367TER_VTH23 0xf235
  1352. #define F367TER_VTH_23 0xf23500ff
  1353. /* VTH34 */
  1354. #define R367TER_VTH34 0xf236
  1355. #define F367TER_VTH_34 0xf23600ff
  1356. /* VTH56 */
  1357. #define R367TER_VTH56 0xf237
  1358. #define F367TER_VTH_56 0xf23700ff
  1359. /* VTH67 */
  1360. #define R367TER_VTH67 0xf238
  1361. #define F367TER_VTH_67 0xf23800ff
  1362. /* VTH78 */
  1363. #define R367TER_VTH78 0xf239
  1364. #define F367TER_VTH_78 0xf23900ff
  1365. /* VITCURPUN */
  1366. #define R367TER_VITCURPUN 0xf23a
  1367. #define F367TER_VIT_MAPPING 0xf23a00e0
  1368. #define F367TER_VIT_CURPUN 0xf23a001f
  1369. /* VERROR */
  1370. #define R367TER_VERROR 0xf23b
  1371. #define F367TER_REGERR_VIT 0xf23b00ff
  1372. /* PRVIT */
  1373. #define R367TER_PRVIT 0xf23c
  1374. #define F367TER_PRVIT_7 0xf23c0080
  1375. #define F367TER_DIS_VTHLOCK 0xf23c0040
  1376. #define F367TER_E7_8VIT 0xf23c0020
  1377. #define F367TER_E6_7VIT 0xf23c0010
  1378. #define F367TER_E5_6VIT 0xf23c0008
  1379. #define F367TER_E3_4VIT 0xf23c0004
  1380. #define F367TER_E2_3VIT 0xf23c0002
  1381. #define F367TER_E1_2VIT 0xf23c0001
  1382. /* VAVSRVIT */
  1383. #define R367TER_VAVSRVIT 0xf23d
  1384. #define F367TER_AMVIT 0xf23d0080
  1385. #define F367TER_FROZENVIT 0xf23d0040
  1386. #define F367TER_SNVIT 0xf23d0030
  1387. #define F367TER_TOVVIT 0xf23d000c
  1388. #define F367TER_HYPVIT 0xf23d0003
  1389. /* VSTATUSVIT */
  1390. #define R367TER_VSTATUSVIT 0xf23e
  1391. #define F367TER_VITERBI_ON 0xf23e0080
  1392. #define F367TER_END_LOOPVIT 0xf23e0040
  1393. #define F367TER_VITERBI_DEPRF 0xf23e0020
  1394. #define F367TER_PRFVIT 0xf23e0010
  1395. #define F367TER_LOCKEDVIT 0xf23e0008
  1396. #define F367TER_VITERBI_DELOCK 0xf23e0004
  1397. #define F367TER_VIT_DEMODSEL 0xf23e0002
  1398. #define F367TER_VITERBI_COMPOUT 0xf23e0001
  1399. /* VTHINUSE */
  1400. #define R367TER_VTHINUSE 0xf23f
  1401. #define F367TER_VIT_INUSE 0xf23f00ff
  1402. /* KDIV12 */
  1403. #define R367TER_KDIV12 0xf240
  1404. #define F367TER_KDIV12_MANUAL 0xf2400080
  1405. #define F367TER_K_DIVIDER_12 0xf240007f
  1406. /* KDIV23 */
  1407. #define R367TER_KDIV23 0xf241
  1408. #define F367TER_KDIV23_MANUAL 0xf2410080
  1409. #define F367TER_K_DIVIDER_23 0xf241007f
  1410. /* KDIV34 */
  1411. #define R367TER_KDIV34 0xf242
  1412. #define F367TER_KDIV34_MANUAL 0xf2420080
  1413. #define F367TER_K_DIVIDER_34 0xf242007f
  1414. /* KDIV56 */
  1415. #define R367TER_KDIV56 0xf243
  1416. #define F367TER_KDIV56_MANUAL 0xf2430080
  1417. #define F367TER_K_DIVIDER_56 0xf243007f
  1418. /* KDIV67 */
  1419. #define R367TER_KDIV67 0xf244
  1420. #define F367TER_KDIV67_MANUAL 0xf2440080
  1421. #define F367TER_K_DIVIDER_67 0xf244007f
  1422. /* KDIV78 */
  1423. #define R367TER_KDIV78 0xf245
  1424. #define F367TER_KDIV78_MANUAL 0xf2450080
  1425. #define F367TER_K_DIVIDER_78 0xf245007f
  1426. /* SIGPOWER */
  1427. #define R367TER_SIGPOWER 0xf246
  1428. #define F367TER_SIGPOWER_MANUAL 0xf2460080
  1429. #define F367TER_SIG_POWER 0xf246007f
  1430. /* DEMAPVIT */
  1431. #define R367TER_DEMAPVIT 0xf247
  1432. #define F367TER_DEMAPVIT_7 0xf2470080
  1433. #define F367TER_K_DIVIDER_VIT 0xf247007f
  1434. /* VITSCALE */
  1435. #define R367TER_VITSCALE 0xf248
  1436. #define F367TER_NVTH_NOSRANGE 0xf2480080
  1437. #define F367TER_VERROR_MAXMODE 0xf2480040
  1438. #define F367TER_KDIV_MODE 0xf2480030
  1439. #define F367TER_NSLOWSN_LOCKED 0xf2480008
  1440. #define F367TER_DELOCK_PRFLOSS 0xf2480004
  1441. #define F367TER_DIS_RSFLOCK 0xf2480002
  1442. #define F367TER_VITSCALE_0 0xf2480001
  1443. /* FFEC1PRG */
  1444. #define R367TER_FFEC1PRG 0xf249
  1445. #define F367TER_FDSS_DVB 0xf2490080
  1446. #define F367TER_FDSS_SRCH 0xf2490040
  1447. #define F367TER_FFECPROG_5 0xf2490020
  1448. #define F367TER_FFECPROG_4 0xf2490010
  1449. #define F367TER_FFECPROG_3 0xf2490008
  1450. #define F367TER_FFECPROG_2 0xf2490004
  1451. #define F367TER_FTS1_DISABLE 0xf2490002
  1452. #define F367TER_FTS2_DISABLE 0xf2490001
  1453. /* FVITCURPUN */
  1454. #define R367TER_FVITCURPUN 0xf24a
  1455. #define F367TER_FVIT_MAPPING 0xf24a00e0
  1456. #define F367TER_FVIT_CURPUN 0xf24a001f
  1457. /* FVERROR */
  1458. #define R367TER_FVERROR 0xf24b
  1459. #define F367TER_FREGERR_VIT 0xf24b00ff
  1460. /* FVSTATUSVIT */
  1461. #define R367TER_FVSTATUSVIT 0xf24c
  1462. #define F367TER_FVITERBI_ON 0xf24c0080
  1463. #define F367TER_F1END_LOOPVIT 0xf24c0040
  1464. #define F367TER_FVITERBI_DEPRF 0xf24c0020
  1465. #define F367TER_FPRFVIT 0xf24c0010
  1466. #define F367TER_FLOCKEDVIT 0xf24c0008
  1467. #define F367TER_FVITERBI_DELOCK 0xf24c0004
  1468. #define F367TER_FVIT_DEMODSEL 0xf24c0002
  1469. #define F367TER_FVITERBI_COMPOUT 0xf24c0001
  1470. /* DEBUG_LT1 */
  1471. #define R367TER_DEBUG_LT1 0xf24d
  1472. #define F367TER_DBG_LT1 0xf24d00ff
  1473. /* DEBUG_LT2 */
  1474. #define R367TER_DEBUG_LT2 0xf24e
  1475. #define F367TER_DBG_LT2 0xf24e00ff
  1476. /* DEBUG_LT3 */
  1477. #define R367TER_DEBUG_LT3 0xf24f
  1478. #define F367TER_DBG_LT3 0xf24f00ff
  1479. /* TSTSFMET */
  1480. #define R367TER_TSTSFMET 0xf250
  1481. #define F367TER_TSTSFEC_METRIQUES 0xf25000ff
  1482. /* SELOUT */
  1483. #define R367TER_SELOUT 0xf252
  1484. #define F367TER_EN_SYNC 0xf2520080
  1485. #define F367TER_EN_TBUSDEMAP 0xf2520040
  1486. #define F367TER_SELOUT_5 0xf2520020
  1487. #define F367TER_SELOUT_4 0xf2520010
  1488. #define F367TER_TSTSYNCHRO_MODE 0xf2520002
  1489. /* TSYNC */
  1490. #define R367TER_TSYNC 0xf253
  1491. #define F367TER_CURPUN_INCMODE 0xf2530080
  1492. #define F367TER_CERR_TSTMODE 0xf2530040
  1493. #define F367TER_SHIFTSOF_MODE 0xf2530030
  1494. #define F367TER_SLOWPHA_MODE 0xf2530008
  1495. #define F367TER_PXX_BYPALL 0xf2530004
  1496. #define F367TER_FROTA45_FIRST 0xf2530002
  1497. #define F367TER_TST_BCHERROR 0xf2530001
  1498. /* TSTERR */
  1499. #define R367TER_TSTERR 0xf254
  1500. #define F367TER_TST_LONGPKT 0xf2540080
  1501. #define F367TER_TST_ISSYION 0xf2540040
  1502. #define F367TER_TST_NPDON 0xf2540020
  1503. #define F367TER_TSTERR_4 0xf2540010
  1504. #define F367TER_TRACEBACK_MODE 0xf2540008
  1505. #define F367TER_TST_RSPARITY 0xf2540004
  1506. #define F367TER_METRIQUE_MODE 0xf2540003
  1507. /* TSFSYNC */
  1508. #define R367TER_TSFSYNC 0xf255
  1509. #define F367TER_EN_SFECSYNC 0xf2550080
  1510. #define F367TER_EN_SFECDEMAP 0xf2550040
  1511. #define F367TER_SFCERR_TSTMODE 0xf2550020
  1512. #define F367TER_SFECPXX_BYPALL 0xf2550010
  1513. #define F367TER_SFECTSTSYNCHRO_MODE 0xf255000f
  1514. /* TSTSFERR */
  1515. #define R367TER_TSTSFERR 0xf256
  1516. #define F367TER_TSTSTERR_7 0xf2560080
  1517. #define F367TER_TSTSTERR_6 0xf2560040
  1518. #define F367TER_TSTSTERR_5 0xf2560020
  1519. #define F367TER_TSTSTERR_4 0xf2560010
  1520. #define F367TER_SFECTRACEBACK_MODE 0xf2560008
  1521. #define F367TER_SFEC_NCONVPROG 0xf2560004
  1522. #define F367TER_SFECMETRIQUE_MODE 0xf2560003
  1523. /* TSTTSSF1 */
  1524. #define R367TER_TSTTSSF1 0xf258
  1525. #define F367TER_TSTERSSF 0xf2580080
  1526. #define F367TER_TSTTSSFEN 0xf2580040
  1527. #define F367TER_SFEC_OUTMODE 0xf2580030
  1528. #define F367TER_XLSF_NOFTHRESHOLD 0xf2580008
  1529. #define F367TER_TSTTSSF_STACKSEL 0xf2580007
  1530. /* TSTTSSF2 */
  1531. #define R367TER_TSTTSSF2 0xf259
  1532. #define F367TER_DILSF_DBBHEADER 0xf2590080
  1533. #define F367TER_TSTTSSF_DISBUG 0xf2590040
  1534. #define F367TER_TSTTSSF_NOBADSTART 0xf2590020
  1535. #define F367TER_TSTTSSF_SELECT 0xf259001f
  1536. /* TSTTSSF3 */
  1537. #define R367TER_TSTTSSF3 0xf25a
  1538. #define F367TER_TSTTSSF3_7 0xf25a0080
  1539. #define F367TER_TSTTSSF3_6 0xf25a0040
  1540. #define F367TER_TSTTSSF3_5 0xf25a0020
  1541. #define F367TER_TSTTSSF3_4 0xf25a0010
  1542. #define F367TER_TSTTSSF3_3 0xf25a0008
  1543. #define F367TER_TSTTSSF3_2 0xf25a0004
  1544. #define F367TER_TSTTSSF3_1 0xf25a0002
  1545. #define F367TER_DISSF_CLKENABLE 0xf25a0001
  1546. /* TSTTS1 */
  1547. #define R367TER_TSTTS1 0xf25c
  1548. #define F367TER_TSTERS 0xf25c0080
  1549. #define F367TER_TSFIFO_DSSSYNCB 0xf25c0040
  1550. #define F367TER_TSTTS_FSPYBEFRS 0xf25c0020
  1551. #define F367TER_NFORCE_SYNCBYTE 0xf25c0010
  1552. #define F367TER_XL_NOFTHRESHOLD 0xf25c0008
  1553. #define F367TER_TSTTS_FRFORCEPKT 0xf25c0004
  1554. #define F367TER_DESCR_NOTAUTO 0xf25c0002
  1555. #define F367TER_TSTTSEN 0xf25c0001
  1556. /* TSTTS2 */
  1557. #define R367TER_TSTTS2 0xf25d
  1558. #define F367TER_DIL_DBBHEADER 0xf25d0080
  1559. #define F367TER_TSTTS_NOBADXXX 0xf25d0040
  1560. #define F367TER_TSFIFO_DELSPEEDUP 0xf25d0020
  1561. #define F367TER_TSTTS_SELECT 0xf25d001f
  1562. /* TSTTS3 */
  1563. #define R367TER_TSTTS3 0xf25e
  1564. #define F367TER_TSTTS_NOPKTGAIN 0xf25e0080
  1565. #define F367TER_TSTTS_NOPKTENE 0xf25e0040
  1566. #define F367TER_TSTTS_ISOLATION 0xf25e0020
  1567. #define F367TER_TSTTS_DISBUG 0xf25e0010
  1568. #define F367TER_TSTTS_NOBADSTART 0xf25e0008
  1569. #define F367TER_TSTTS_STACKSEL 0xf25e0007
  1570. /* TSTTS4 */
  1571. #define R367TER_TSTTS4 0xf25f
  1572. #define F367TER_TSTTS4_7 0xf25f0080
  1573. #define F367TER_TSTTS4_6 0xf25f0040
  1574. #define F367TER_TSTTS4_5 0xf25f0020
  1575. #define F367TER_TSTTS_DISDSTATE 0xf25f0010
  1576. #define F367TER_TSTTS_FASTNOSYNC 0xf25f0008
  1577. #define F367TER_EXT_FECSPYIN 0xf25f0004
  1578. #define F367TER_TSTTS_NODPZERO 0xf25f0002
  1579. #define F367TER_TSTTS_NODIV3 0xf25f0001
  1580. /* TSTTSRC */
  1581. #define R367TER_TSTTSRC 0xf26c
  1582. #define F367TER_TSTTSRC_7 0xf26c0080
  1583. #define F367TER_TSRCFIFO_DSSSYNCB 0xf26c0040
  1584. #define F367TER_TSRCFIFO_DPUNACTIVE 0xf26c0020
  1585. #define F367TER_TSRCFIFO_DELSPEEDUP 0xf26c0010
  1586. #define F367TER_TSTTSRC_NODIV3 0xf26c0008
  1587. #define F367TER_TSTTSRC_FRFORCEPKT 0xf26c0004
  1588. #define F367TER_SAT25_SDDORIGINE 0xf26c0002
  1589. #define F367TER_TSTTSRC_INACTIVE 0xf26c0001
  1590. /* TSTTSRS */
  1591. #define R367TER_TSTTSRS 0xf26d
  1592. #define F367TER_TSTTSRS_7 0xf26d0080
  1593. #define F367TER_TSTTSRS_6 0xf26d0040
  1594. #define F367TER_TSTTSRS_5 0xf26d0020
  1595. #define F367TER_TSTTSRS_4 0xf26d0010
  1596. #define F367TER_TSTTSRS_3 0xf26d0008
  1597. #define F367TER_TSTTSRS_2 0xf26d0004
  1598. #define F367TER_TSTRS_DISRS2 0xf26d0002
  1599. #define F367TER_TSTRS_DISRS1 0xf26d0001
  1600. /* TSSTATEM */
  1601. #define R367TER_TSSTATEM 0xf270
  1602. #define F367TER_TSDIL_ON 0xf2700080
  1603. #define F367TER_TSSKIPRS_ON 0xf2700040
  1604. #define F367TER_TSRS_ON 0xf2700020
  1605. #define F367TER_TSDESCRAMB_ON 0xf2700010
  1606. #define F367TER_TSFRAME_MODE 0xf2700008
  1607. #define F367TER_TS_DISABLE 0xf2700004
  1608. #define F367TER_TSACM_MODE 0xf2700002
  1609. #define F367TER_TSOUT_NOSYNC 0xf2700001
  1610. /* TSSTATEL */
  1611. #define R367TER_TSSTATEL 0xf271
  1612. #define F367TER_TSNOSYNCBYTE 0xf2710080
  1613. #define F367TER_TSPARITY_ON 0xf2710040
  1614. #define F367TER_TSSYNCOUTRS_ON 0xf2710020
  1615. #define F367TER_TSDVBS2_MODE 0xf2710010
  1616. #define F367TER_TSISSYI_ON 0xf2710008
  1617. #define F367TER_TSNPD_ON 0xf2710004
  1618. #define F367TER_TSCRC8_ON 0xf2710002
  1619. #define F367TER_TSDSS_PACKET 0xf2710001
  1620. /* TSCFGH */
  1621. #define R367TER_TSCFGH 0xf272
  1622. #define F367TER_TSFIFO_DVBCI 0xf2720080
  1623. #define F367TER_TSFIFO_SERIAL 0xf2720040
  1624. #define F367TER_TSFIFO_TEIUPDATE 0xf2720020
  1625. #define F367TER_TSFIFO_DUTY50 0xf2720010
  1626. #define F367TER_TSFIFO_HSGNLOUT 0xf2720008
  1627. #define F367TER_TSFIFO_ERRMODE 0xf2720006
  1628. #define F367TER_RST_HWARE 0xf2720001
  1629. /* TSCFGM */
  1630. #define R367TER_TSCFGM 0xf273
  1631. #define F367TER_TSFIFO_MANSPEED 0xf27300c0
  1632. #define F367TER_TSFIFO_PERMDATA 0xf2730020
  1633. #define F367TER_TSFIFO_NONEWSGNL 0xf2730010
  1634. #define F367TER_TSFIFO_BITSPEED 0xf2730008
  1635. #define F367TER_NPD_SPECDVBS2 0xf2730004
  1636. #define F367TER_TSFIFO_STOPCKDIS 0xf2730002
  1637. #define F367TER_TSFIFO_INVDATA 0xf2730001
  1638. /* TSCFGL */
  1639. #define R367TER_TSCFGL 0xf274
  1640. #define F367TER_TSFIFO_BCLKDEL1cK 0xf27400c0
  1641. #define F367TER_BCHERROR_MODE 0xf2740030
  1642. #define F367TER_TSFIFO_NSGNL2dATA 0xf2740008
  1643. #define F367TER_TSFIFO_EMBINDVB 0xf2740004
  1644. #define F367TER_TSFIFO_DPUNACT 0xf2740002
  1645. #define F367TER_TSFIFO_NPDOFF 0xf2740001
  1646. /* TSSYNC */
  1647. #define R367TER_TSSYNC 0xf275
  1648. #define F367TER_TSFIFO_PERMUTE 0xf2750080
  1649. #define F367TER_TSFIFO_FISCR3B 0xf2750060
  1650. #define F367TER_TSFIFO_SYNCMODE 0xf2750018
  1651. #define F367TER_TSFIFO_SYNCSEL 0xf2750007
  1652. /* TSINSDELH */
  1653. #define R367TER_TSINSDELH 0xf276
  1654. #define F367TER_TSDEL_SYNCBYTE 0xf2760080
  1655. #define F367TER_TSDEL_XXHEADER 0xf2760040
  1656. #define F367TER_TSDEL_BBHEADER 0xf2760020
  1657. #define F367TER_TSDEL_DATAFIELD 0xf2760010
  1658. #define F367TER_TSINSDEL_ISCR 0xf2760008
  1659. #define F367TER_TSINSDEL_NPD 0xf2760004
  1660. #define F367TER_TSINSDEL_RSPARITY 0xf2760002
  1661. #define F367TER_TSINSDEL_CRC8 0xf2760001
  1662. /* TSINSDELM */
  1663. #define R367TER_TSINSDELM 0xf277
  1664. #define F367TER_TSINS_BBPADDING 0xf2770080
  1665. #define F367TER_TSINS_BCHFEC 0xf2770040
  1666. #define F367TER_TSINS_LDPCFEC 0xf2770020
  1667. #define F367TER_TSINS_EMODCOD 0xf2770010
  1668. #define F367TER_TSINS_TOKEN 0xf2770008
  1669. #define F367TER_TSINS_XXXERR 0xf2770004
  1670. #define F367TER_TSINS_MATYPE 0xf2770002
  1671. #define F367TER_TSINS_UPL 0xf2770001
  1672. /* TSINSDELL */
  1673. #define R367TER_TSINSDELL 0xf278
  1674. #define F367TER_TSINS_DFL 0xf2780080
  1675. #define F367TER_TSINS_SYNCD 0xf2780040
  1676. #define F367TER_TSINS_BLOCLEN 0xf2780020
  1677. #define F367TER_TSINS_SIGPCOUNT 0xf2780010
  1678. #define F367TER_TSINS_FIFO 0xf2780008
  1679. #define F367TER_TSINS_REALPACK 0xf2780004
  1680. #define F367TER_TSINS_TSCONFIG 0xf2780002
  1681. #define F367TER_TSINS_LATENCY 0xf2780001
  1682. /* TSDIVN */
  1683. #define R367TER_TSDIVN 0xf279
  1684. #define F367TER_TSFIFO_LOWSPEED 0xf2790080
  1685. #define F367TER_BYTE_OVERSAMPLING 0xf2790070
  1686. #define F367TER_TSMANUAL_PACKETNBR 0xf279000f
  1687. /* TSDIVPM */
  1688. #define R367TER_TSDIVPM 0xf27a
  1689. #define F367TER_TSMANUAL_P_HI 0xf27a00ff
  1690. /* TSDIVPL */
  1691. #define R367TER_TSDIVPL 0xf27b
  1692. #define F367TER_TSMANUAL_P_LO 0xf27b00ff
  1693. /* TSDIVQM */
  1694. #define R367TER_TSDIVQM 0xf27c
  1695. #define F367TER_TSMANUAL_Q_HI 0xf27c00ff
  1696. /* TSDIVQL */
  1697. #define R367TER_TSDIVQL 0xf27d
  1698. #define F367TER_TSMANUAL_Q_LO 0xf27d00ff
  1699. /* TSDILSTKM */
  1700. #define R367TER_TSDILSTKM 0xf27e
  1701. #define F367TER_TSFIFO_DILSTK_HI 0xf27e00ff
  1702. /* TSDILSTKL */
  1703. #define R367TER_TSDILSTKL 0xf27f
  1704. #define F367TER_TSFIFO_DILSTK_LO 0xf27f00ff
  1705. /* TSSPEED */
  1706. #define R367TER_TSSPEED 0xf280
  1707. #define F367TER_TSFIFO_OUTSPEED 0xf28000ff
  1708. /* TSSTATUS */
  1709. #define R367TER_TSSTATUS 0xf281
  1710. #define F367TER_TSFIFO_LINEOK 0xf2810080
  1711. #define F367TER_TSFIFO_ERROR 0xf2810040
  1712. #define F367TER_TSFIFO_DATA7 0xf2810020
  1713. #define F367TER_TSFIFO_NOSYNC 0xf2810010
  1714. #define F367TER_ISCR_INITIALIZED 0xf2810008
  1715. #define F367TER_ISCR_UPDATED 0xf2810004
  1716. #define F367TER_SOFFIFO_UNREGUL 0xf2810002
  1717. #define F367TER_DIL_READY 0xf2810001
  1718. /* TSSTATUS2 */
  1719. #define R367TER_TSSTATUS2 0xf282
  1720. #define F367TER_TSFIFO_DEMODSEL 0xf2820080
  1721. #define F367TER_TSFIFOSPEED_STORE 0xf2820040
  1722. #define F367TER_DILXX_RESET 0xf2820020
  1723. #define F367TER_TSSERIAL_IMPOSSIBLE 0xf2820010
  1724. #define F367TER_TSFIFO_UNDERSPEED 0xf2820008
  1725. #define F367TER_BITSPEED_EVENT 0xf2820004
  1726. #define F367TER_UL_SCRAMBDETECT 0xf2820002
  1727. #define F367TER_ULDTV67_FALSELOCK 0xf2820001
  1728. /* TSBITRATEM */
  1729. #define R367TER_TSBITRATEM 0xf283
  1730. #define F367TER_TSFIFO_BITRATE_HI 0xf28300ff
  1731. /* TSBITRATEL */
  1732. #define R367TER_TSBITRATEL 0xf284
  1733. #define F367TER_TSFIFO_BITRATE_LO 0xf28400ff
  1734. /* TSPACKLENM */
  1735. #define R367TER_TSPACKLENM 0xf285
  1736. #define F367TER_TSFIFO_PACKCPT 0xf28500e0
  1737. #define F367TER_DIL_RPLEN_HI 0xf285001f
  1738. /* TSPACKLENL */
  1739. #define R367TER_TSPACKLENL 0xf286
  1740. #define F367TER_DIL_RPLEN_LO 0xf28600ff
  1741. /* TSBLOCLENM */
  1742. #define R367TER_TSBLOCLENM 0xf287
  1743. #define F367TER_TSFIFO_PFLEN_HI 0xf28700ff
  1744. /* TSBLOCLENL */
  1745. #define R367TER_TSBLOCLENL 0xf288
  1746. #define F367TER_TSFIFO_PFLEN_LO 0xf28800ff
  1747. /* TSDLYH */
  1748. #define R367TER_TSDLYH 0xf289
  1749. #define F367TER_SOFFIFO_TSTIMEVALID 0xf2890080
  1750. #define F367TER_SOFFIFO_SPEEDUP 0xf2890040
  1751. #define F367TER_SOFFIFO_STOP 0xf2890020
  1752. #define F367TER_SOFFIFO_REGULATED 0xf2890010
  1753. #define F367TER_SOFFIFO_REALSBOFF_HI 0xf289000f
  1754. /* TSDLYM */
  1755. #define R367TER_TSDLYM 0xf28a
  1756. #define F367TER_SOFFIFO_REALSBOFF_MED 0xf28a00ff
  1757. /* TSDLYL */
  1758. #define R367TER_TSDLYL 0xf28b
  1759. #define F367TER_SOFFIFO_REALSBOFF_LO 0xf28b00ff
  1760. /* TSNPDAV */
  1761. #define R367TER_TSNPDAV 0xf28c
  1762. #define F367TER_TSNPD_AVERAGE 0xf28c00ff
  1763. /* TSBUFSTATH */
  1764. #define R367TER_TSBUFSTATH 0xf28d
  1765. #define F367TER_TSISCR_3BYTES 0xf28d0080
  1766. #define F367TER_TSISCR_NEWDATA 0xf28d0040
  1767. #define F367TER_TSISCR_BUFSTAT_HI 0xf28d003f
  1768. /* TSBUFSTATM */
  1769. #define R367TER_TSBUFSTATM 0xf28e
  1770. #define F367TER_TSISCR_BUFSTAT_MED 0xf28e00ff
  1771. /* TSBUFSTATL */
  1772. #define R367TER_TSBUFSTATL 0xf28f
  1773. #define F367TER_TSISCR_BUFSTAT_LO 0xf28f00ff
  1774. /* TSDEBUGM */
  1775. #define R367TER_TSDEBUGM 0xf290
  1776. #define F367TER_TSFIFO_ILLPACKET 0xf2900080
  1777. #define F367TER_DIL_NOSYNC 0xf2900040
  1778. #define F367TER_DIL_ISCR 0xf2900020
  1779. #define F367TER_DILOUT_BSYNCB 0xf2900010
  1780. #define F367TER_TSFIFO_EMPTYPKT 0xf2900008
  1781. #define F367TER_TSFIFO_EMPTYRD 0xf2900004
  1782. #define F367TER_SOFFIFO_STOPM 0xf2900002
  1783. #define F367TER_SOFFIFO_SPEEDUPM 0xf2900001
  1784. /* TSDEBUGL */
  1785. #define R367TER_TSDEBUGL 0xf291
  1786. #define F367TER_TSFIFO_PACKLENFAIL 0xf2910080
  1787. #define F367TER_TSFIFO_SYNCBFAIL 0xf2910040
  1788. #define F367TER_TSFIFO_VITLIBRE 0xf2910020
  1789. #define F367TER_TSFIFO_BOOSTSPEEDM 0xf2910010
  1790. #define F367TER_TSFIFO_UNDERSPEEDM 0xf2910008
  1791. #define F367TER_TSFIFO_ERROR_EVNT 0xf2910004
  1792. #define F367TER_TSFIFO_FULL 0xf2910002
  1793. #define F367TER_TSFIFO_OVERFLOWM 0xf2910001
  1794. /* TSDLYSETH */
  1795. #define R367TER_TSDLYSETH 0xf292
  1796. #define F367TER_SOFFIFO_OFFSET 0xf29200e0
  1797. #define F367TER_SOFFIFO_SYMBOFFSET_HI 0xf292001f
  1798. /* TSDLYSETM */
  1799. #define R367TER_TSDLYSETM 0xf293
  1800. #define F367TER_SOFFIFO_SYMBOFFSET_MED 0xf29300ff
  1801. /* TSDLYSETL */
  1802. #define R367TER_TSDLYSETL 0xf294
  1803. #define F367TER_SOFFIFO_SYMBOFFSET_LO 0xf29400ff
  1804. /* TSOBSCFG */
  1805. #define R367TER_TSOBSCFG 0xf295
  1806. #define F367TER_TSFIFO_OBSCFG 0xf29500ff
  1807. /* TSOBSM */
  1808. #define R367TER_TSOBSM 0xf296
  1809. #define F367TER_TSFIFO_OBSDATA_HI 0xf29600ff
  1810. /* TSOBSL */
  1811. #define R367TER_TSOBSL 0xf297
  1812. #define F367TER_TSFIFO_OBSDATA_LO 0xf29700ff
  1813. /* ERRCTRL1 */
  1814. #define R367TER_ERRCTRL1 0xf298
  1815. #define F367TER_ERR_SRC1 0xf29800f0
  1816. #define F367TER_ERRCTRL1_3 0xf2980008
  1817. #define F367TER_NUM_EVT1 0xf2980007
  1818. /* ERRCNT1H */
  1819. #define R367TER_ERRCNT1H 0xf299
  1820. #define F367TER_ERRCNT1_OLDVALUE 0xf2990080
  1821. #define F367TER_ERR_CNT1 0xf299007f
  1822. /* ERRCNT1M */
  1823. #define R367TER_ERRCNT1M 0xf29a
  1824. #define F367TER_ERR_CNT1_HI 0xf29a00ff
  1825. /* ERRCNT1L */
  1826. #define R367TER_ERRCNT1L 0xf29b
  1827. #define F367TER_ERR_CNT1_LO 0xf29b00ff
  1828. /* ERRCTRL2 */
  1829. #define R367TER_ERRCTRL2 0xf29c
  1830. #define F367TER_ERR_SRC2 0xf29c00f0
  1831. #define F367TER_ERRCTRL2_3 0xf29c0008
  1832. #define F367TER_NUM_EVT2 0xf29c0007
  1833. /* ERRCNT2H */
  1834. #define R367TER_ERRCNT2H 0xf29d
  1835. #define F367TER_ERRCNT2_OLDVALUE 0xf29d0080
  1836. #define F367TER_ERR_CNT2_HI 0xf29d007f
  1837. /* ERRCNT2M */
  1838. #define R367TER_ERRCNT2M 0xf29e
  1839. #define F367TER_ERR_CNT2_MED 0xf29e00ff
  1840. /* ERRCNT2L */
  1841. #define R367TER_ERRCNT2L 0xf29f
  1842. #define F367TER_ERR_CNT2_LO 0xf29f00ff
  1843. /* FECSPY */
  1844. #define R367TER_FECSPY 0xf2a0
  1845. #define F367TER_SPY_ENABLE 0xf2a00080
  1846. #define F367TER_NO_SYNCBYTE 0xf2a00040
  1847. #define F367TER_SERIAL_MODE 0xf2a00020
  1848. #define F367TER_UNUSUAL_PACKET 0xf2a00010
  1849. #define F367TER_BERMETER_DATAMODE 0xf2a0000c
  1850. #define F367TER_BERMETER_LMODE 0xf2a00002
  1851. #define F367TER_BERMETER_RESET 0xf2a00001
  1852. /* FSPYCFG */
  1853. #define R367TER_FSPYCFG 0xf2a1
  1854. #define F367TER_FECSPY_INPUT 0xf2a100c0
  1855. #define F367TER_RST_ON_ERROR 0xf2a10020
  1856. #define F367TER_ONE_SHOT 0xf2a10010
  1857. #define F367TER_I2C_MOD 0xf2a1000c
  1858. #define F367TER_SPY_HYSTERESIS 0xf2a10003
  1859. /* FSPYDATA */
  1860. #define R367TER_FSPYDATA 0xf2a2
  1861. #define F367TER_SPY_STUFFING 0xf2a20080
  1862. #define F367TER_NOERROR_PKTJITTER 0xf2a20040
  1863. #define F367TER_SPY_CNULLPKT 0xf2a20020
  1864. #define F367TER_SPY_OUTDATA_MODE 0xf2a2001f
  1865. /* FSPYOUT */
  1866. #define R367TER_FSPYOUT 0xf2a3
  1867. #define F367TER_FSPY_DIRECT 0xf2a30080
  1868. #define F367TER_FSPYOUT_6 0xf2a30040
  1869. #define F367TER_SPY_OUTDATA_BUS 0xf2a30038
  1870. #define F367TER_STUFF_MODE 0xf2a30007
  1871. /* FSTATUS */
  1872. #define R367TER_FSTATUS 0xf2a4
  1873. #define F367TER_SPY_ENDSIM 0xf2a40080
  1874. #define F367TER_VALID_SIM 0xf2a40040
  1875. #define F367TER_FOUND_SIGNAL 0xf2a40020
  1876. #define F367TER_DSS_SYNCBYTE 0xf2a40010
  1877. #define F367TER_RESULT_STATE 0xf2a4000f
  1878. /* FGOODPACK */
  1879. #define R367TER_FGOODPACK 0xf2a5
  1880. #define F367TER_FGOOD_PACKET 0xf2a500ff
  1881. /* FPACKCNT */
  1882. #define R367TER_FPACKCNT 0xf2a6
  1883. #define F367TER_FPACKET_COUNTER 0xf2a600ff
  1884. /* FSPYMISC */
  1885. #define R367TER_FSPYMISC 0xf2a7
  1886. #define F367TER_FLABEL_COUNTER 0xf2a700ff
  1887. /* FBERCPT4 */
  1888. #define R367TER_FBERCPT4 0xf2a8
  1889. #define F367TER_FBERMETER_CPT5 0xf2a800ff
  1890. /* FBERCPT3 */
  1891. #define R367TER_FBERCPT3 0xf2a9
  1892. #define F367TER_FBERMETER_CPT4 0xf2a900ff
  1893. /* FBERCPT2 */
  1894. #define R367TER_FBERCPT2 0xf2aa
  1895. #define F367TER_FBERMETER_CPT3 0xf2aa00ff
  1896. /* FBERCPT1 */
  1897. #define R367TER_FBERCPT1 0xf2ab
  1898. #define F367TER_FBERMETER_CPT2 0xf2ab00ff
  1899. /* FBERCPT0 */
  1900. #define R367TER_FBERCPT0 0xf2ac
  1901. #define F367TER_FBERMETER_CPT1 0xf2ac00ff
  1902. /* FBERERR2 */
  1903. #define R367TER_FBERERR2 0xf2ad
  1904. #define F367TER_FBERMETER_ERR_HI 0xf2ad00ff
  1905. /* FBERERR1 */
  1906. #define R367TER_FBERERR1 0xf2ae
  1907. #define F367TER_FBERMETER_ERR_MED 0xf2ae00ff
  1908. /* FBERERR0 */
  1909. #define R367TER_FBERERR0 0xf2af
  1910. #define F367TER_FBERMETER_ERR_LO 0xf2af00ff
  1911. /* FSTATESM */
  1912. #define R367TER_FSTATESM 0xf2b0
  1913. #define F367TER_RSTATE_F 0xf2b00080
  1914. #define F367TER_RSTATE_E 0xf2b00040
  1915. #define F367TER_RSTATE_D 0xf2b00020
  1916. #define F367TER_RSTATE_C 0xf2b00010
  1917. #define F367TER_RSTATE_B 0xf2b00008
  1918. #define F367TER_RSTATE_A 0xf2b00004
  1919. #define F367TER_RSTATE_9 0xf2b00002
  1920. #define F367TER_RSTATE_8 0xf2b00001
  1921. /* FSTATESL */
  1922. #define R367TER_FSTATESL 0xf2b1
  1923. #define F367TER_RSTATE_7 0xf2b10080
  1924. #define F367TER_RSTATE_6 0xf2b10040
  1925. #define F367TER_RSTATE_5 0xf2b10020
  1926. #define F367TER_RSTATE_4 0xf2b10010
  1927. #define F367TER_RSTATE_3 0xf2b10008
  1928. #define F367TER_RSTATE_2 0xf2b10004
  1929. #define F367TER_RSTATE_1 0xf2b10002
  1930. #define F367TER_RSTATE_0 0xf2b10001
  1931. /* FSPYBER */
  1932. #define R367TER_FSPYBER 0xf2b2
  1933. #define F367TER_FSPYBER_7 0xf2b20080
  1934. #define F367TER_FSPYOBS_XORREAD 0xf2b20040
  1935. #define F367TER_FSPYBER_OBSMODE 0xf2b20020
  1936. #define F367TER_FSPYBER_SYNCBYTE 0xf2b20010
  1937. #define F367TER_FSPYBER_UNSYNC 0xf2b20008
  1938. #define F367TER_FSPYBER_CTIME 0xf2b20007
  1939. /* FSPYDISTM */
  1940. #define R367TER_FSPYDISTM 0xf2b3
  1941. #define F367TER_PKTTIME_DISTANCE_HI 0xf2b300ff
  1942. /* FSPYDISTL */
  1943. #define R367TER_FSPYDISTL 0xf2b4
  1944. #define F367TER_PKTTIME_DISTANCE_LO 0xf2b400ff
  1945. /* FSPYOBS7 */
  1946. #define R367TER_FSPYOBS7 0xf2b8
  1947. #define F367TER_FSPYOBS_SPYFAIL 0xf2b80080
  1948. #define F367TER_FSPYOBS_SPYFAIL1 0xf2b80040
  1949. #define F367TER_FSPYOBS_ERROR 0xf2b80020
  1950. #define F367TER_FSPYOBS_STROUT 0xf2b80010
  1951. #define F367TER_FSPYOBS_RESULTSTATE1 0xf2b8000f
  1952. /* FSPYOBS6 */
  1953. #define R367TER_FSPYOBS6 0xf2b9
  1954. #define F367TER_FSPYOBS_RESULTSTATe0 0xf2b900f0
  1955. #define F367TER_FSPYOBS_RESULTSTATEM1 0xf2b9000f
  1956. /* FSPYOBS5 */
  1957. #define R367TER_FSPYOBS5 0xf2ba
  1958. #define F367TER_FSPYOBS_BYTEOFPACKET1 0xf2ba00ff
  1959. /* FSPYOBS4 */
  1960. #define R367TER_FSPYOBS4 0xf2bb
  1961. #define F367TER_FSPYOBS_BYTEVALUE1 0xf2bb00ff
  1962. /* FSPYOBS3 */
  1963. #define R367TER_FSPYOBS3 0xf2bc
  1964. #define F367TER_FSPYOBS_DATA1 0xf2bc00ff
  1965. /* FSPYOBS2 */
  1966. #define R367TER_FSPYOBS2 0xf2bd
  1967. #define F367TER_FSPYOBS_DATa0 0xf2bd00ff
  1968. /* FSPYOBS1 */
  1969. #define R367TER_FSPYOBS1 0xf2be
  1970. #define F367TER_FSPYOBS_DATAM1 0xf2be00ff
  1971. /* FSPYOBS0 */
  1972. #define R367TER_FSPYOBS0 0xf2bf
  1973. #define F367TER_FSPYOBS_DATAM2 0xf2bf00ff
  1974. /* SFDEMAP */
  1975. #define R367TER_SFDEMAP 0xf2c0
  1976. #define F367TER_SFDEMAP_7 0xf2c00080
  1977. #define F367TER_SFEC_K_DIVIDER_VIT 0xf2c0007f
  1978. /* SFERROR */
  1979. #define R367TER_SFERROR 0xf2c1
  1980. #define F367TER_SFEC_REGERR_VIT 0xf2c100ff
  1981. /* SFAVSR */
  1982. #define R367TER_SFAVSR 0xf2c2
  1983. #define F367TER_SFEC_SUMERRORS 0xf2c20080
  1984. #define F367TER_SERROR_MAXMODE 0xf2c20040
  1985. #define F367TER_SN_SFEC 0xf2c20030
  1986. #define F367TER_KDIV_MODE_SFEC 0xf2c2000c
  1987. #define F367TER_SFAVSR_1 0xf2c20002
  1988. #define F367TER_SFAVSR_0 0xf2c20001
  1989. /* SFECSTATUS */
  1990. #define R367TER_SFECSTATUS 0xf2c3
  1991. #define F367TER_SFEC_ON 0xf2c30080
  1992. #define F367TER_SFSTATUS_6 0xf2c30040
  1993. #define F367TER_SFSTATUS_5 0xf2c30020
  1994. #define F367TER_SFSTATUS_4 0xf2c30010
  1995. #define F367TER_LOCKEDSFEC 0xf2c30008
  1996. #define F367TER_SFEC_DELOCK 0xf2c30004
  1997. #define F367TER_SFEC_DEMODSEL1 0xf2c30002
  1998. #define F367TER_SFEC_OVFON 0xf2c30001
  1999. /* SFKDIV12 */
  2000. #define R367TER_SFKDIV12 0xf2c4
  2001. #define F367TER_SFECKDIV12_MAN 0xf2c40080
  2002. #define F367TER_SFEC_K_DIVIDER_12 0xf2c4007f
  2003. /* SFKDIV23 */
  2004. #define R367TER_SFKDIV23 0xf2c5
  2005. #define F367TER_SFECKDIV23_MAN 0xf2c50080
  2006. #define F367TER_SFEC_K_DIVIDER_23 0xf2c5007f
  2007. /* SFKDIV34 */
  2008. #define R367TER_SFKDIV34 0xf2c6
  2009. #define F367TER_SFECKDIV34_MAN 0xf2c60080
  2010. #define F367TER_SFEC_K_DIVIDER_34 0xf2c6007f
  2011. /* SFKDIV56 */
  2012. #define R367TER_SFKDIV56 0xf2c7
  2013. #define F367TER_SFECKDIV56_MAN 0xf2c70080
  2014. #define F367TER_SFEC_K_DIVIDER_56 0xf2c7007f
  2015. /* SFKDIV67 */
  2016. #define R367TER_SFKDIV67 0xf2c8
  2017. #define F367TER_SFECKDIV67_MAN 0xf2c80080
  2018. #define F367TER_SFEC_K_DIVIDER_67 0xf2c8007f
  2019. /* SFKDIV78 */
  2020. #define R367TER_SFKDIV78 0xf2c9
  2021. #define F367TER_SFECKDIV78_MAN 0xf2c90080
  2022. #define F367TER_SFEC_K_DIVIDER_78 0xf2c9007f
  2023. /* SFDILSTKM */
  2024. #define R367TER_SFDILSTKM 0xf2ca
  2025. #define F367TER_SFEC_PACKCPT 0xf2ca00e0
  2026. #define F367TER_SFEC_DILSTK_HI 0xf2ca001f
  2027. /* SFDILSTKL */
  2028. #define R367TER_SFDILSTKL 0xf2cb
  2029. #define F367TER_SFEC_DILSTK_LO 0xf2cb00ff
  2030. /* SFSTATUS */
  2031. #define R367TER_SFSTATUS 0xf2cc
  2032. #define F367TER_SFEC_LINEOK 0xf2cc0080
  2033. #define F367TER_SFEC_ERROR 0xf2cc0040
  2034. #define F367TER_SFEC_DATA7 0xf2cc0020
  2035. #define F367TER_SFEC_OVERFLOW 0xf2cc0010
  2036. #define F367TER_SFEC_DEMODSEL2 0xf2cc0008
  2037. #define F367TER_SFEC_NOSYNC 0xf2cc0004
  2038. #define F367TER_SFEC_UNREGULA 0xf2cc0002
  2039. #define F367TER_SFEC_READY 0xf2cc0001
  2040. /* SFDLYH */
  2041. #define R367TER_SFDLYH 0xf2cd
  2042. #define F367TER_SFEC_TSTIMEVALID 0xf2cd0080
  2043. #define F367TER_SFEC_SPEEDUP 0xf2cd0040
  2044. #define F367TER_SFEC_STOP 0xf2cd0020
  2045. #define F367TER_SFEC_REGULATED 0xf2cd0010
  2046. #define F367TER_SFEC_REALSYMBOFFSET 0xf2cd000f
  2047. /* SFDLYM */
  2048. #define R367TER_SFDLYM 0xf2ce
  2049. #define F367TER_SFEC_REALSYMBOFFSET_HI 0xf2ce00ff
  2050. /* SFDLYL */
  2051. #define R367TER_SFDLYL 0xf2cf
  2052. #define F367TER_SFEC_REALSYMBOFFSET_LO 0xf2cf00ff
  2053. /* SFDLYSETH */
  2054. #define R367TER_SFDLYSETH 0xf2d0
  2055. #define F367TER_SFEC_OFFSET 0xf2d000e0
  2056. #define F367TER_SFECDLYSETH_4 0xf2d00010
  2057. #define F367TER_RST_SFEC 0xf2d00008
  2058. #define F367TER_SFECDLYSETH_2 0xf2d00004
  2059. #define F367TER_SFEC_DISABLE 0xf2d00002
  2060. #define F367TER_SFEC_UNREGUL 0xf2d00001
  2061. /* SFDLYSETM */
  2062. #define R367TER_SFDLYSETM 0xf2d1
  2063. #define F367TER_SFECDLYSETM_7 0xf2d10080
  2064. #define F367TER_SFEC_SYMBOFFSET_HI 0xf2d1007f
  2065. /* SFDLYSETL */
  2066. #define R367TER_SFDLYSETL 0xf2d2
  2067. #define F367TER_SFEC_SYMBOFFSET_LO 0xf2d200ff
  2068. /* SFOBSCFG */
  2069. #define R367TER_SFOBSCFG 0xf2d3
  2070. #define F367TER_SFEC_OBSCFG 0xf2d300ff
  2071. /* SFOBSM */
  2072. #define R367TER_SFOBSM 0xf2d4
  2073. #define F367TER_SFEC_OBSDATA_HI 0xf2d400ff
  2074. /* SFOBSL */
  2075. #define R367TER_SFOBSL 0xf2d5
  2076. #define F367TER_SFEC_OBSDATA_LO 0xf2d500ff
  2077. /* SFECINFO */
  2078. #define R367TER_SFECINFO 0xf2d6
  2079. #define F367TER_SFECINFO_7 0xf2d60080
  2080. #define F367TER_SFEC_SYNCDLSB 0xf2d60070
  2081. #define F367TER_SFCE_S1cPHASE 0xf2d6000f
  2082. /* SFERRCTRL */
  2083. #define R367TER_SFERRCTRL 0xf2d8
  2084. #define F367TER_SFEC_ERR_SOURCE 0xf2d800f0
  2085. #define F367TER_SFERRCTRL_3 0xf2d80008
  2086. #define F367TER_SFEC_NUM_EVENT 0xf2d80007
  2087. /* SFERRCNTH */
  2088. #define R367TER_SFERRCNTH 0xf2d9
  2089. #define F367TER_SFERRC_OLDVALUE 0xf2d90080
  2090. #define F367TER_SFEC_ERR_CNT 0xf2d9007f
  2091. /* SFERRCNTM */
  2092. #define R367TER_SFERRCNTM 0xf2da
  2093. #define F367TER_SFEC_ERR_CNT_HI 0xf2da00ff
  2094. /* SFERRCNTL */
  2095. #define R367TER_SFERRCNTL 0xf2db
  2096. #define F367TER_SFEC_ERR_CNT_LO 0xf2db00ff
  2097. /* SYMBRATEM */
  2098. #define R367TER_SYMBRATEM 0xf2e0
  2099. #define F367TER_DEFGEN_SYMBRATE_HI 0xf2e000ff
  2100. /* SYMBRATEL */
  2101. #define R367TER_SYMBRATEL 0xf2e1
  2102. #define F367TER_DEFGEN_SYMBRATE_LO 0xf2e100ff
  2103. /* SYMBSTATUS */
  2104. #define R367TER_SYMBSTATUS 0xf2e2
  2105. #define F367TER_SYMBDLINE2_OFF 0xf2e20080
  2106. #define F367TER_SDDL_REINIT1 0xf2e20040
  2107. #define F367TER_SDD_REINIT1 0xf2e20020
  2108. #define F367TER_TOKENID_ERROR 0xf2e20010
  2109. #define F367TER_SYMBRATE_OVERFLOW 0xf2e20008
  2110. #define F367TER_SYMBRATE_UNDERFLOW 0xf2e20004
  2111. #define F367TER_TOKENID_RSTEVENT 0xf2e20002
  2112. #define F367TER_TOKENID_RESET1 0xf2e20001
  2113. /* SYMBCFG */
  2114. #define R367TER_SYMBCFG 0xf2e3
  2115. #define F367TER_SYMBCFG_7 0xf2e30080
  2116. #define F367TER_SYMBCFG_6 0xf2e30040
  2117. #define F367TER_SYMBCFG_5 0xf2e30020
  2118. #define F367TER_SYMBCFG_4 0xf2e30010
  2119. #define F367TER_SYMRATE_FSPEED 0xf2e3000c
  2120. #define F367TER_SYMRATE_SSPEED 0xf2e30003
  2121. /* SYMBFIFOM */
  2122. #define R367TER_SYMBFIFOM 0xf2e4
  2123. #define F367TER_SYMBFIFOM_7 0xf2e40080
  2124. #define F367TER_SYMBFIFOM_6 0xf2e40040
  2125. #define F367TER_DEFGEN_SYMFIFO_HI 0xf2e4003f
  2126. /* SYMBFIFOL */
  2127. #define R367TER_SYMBFIFOL 0xf2e5
  2128. #define F367TER_DEFGEN_SYMFIFO_LO 0xf2e500ff
  2129. /* SYMBOFFSM */
  2130. #define R367TER_SYMBOFFSM 0xf2e6
  2131. #define F367TER_TOKENID_RESET2 0xf2e60080
  2132. #define F367TER_SDDL_REINIT2 0xf2e60040
  2133. #define F367TER_SDD_REINIT2 0xf2e60020
  2134. #define F367TER_SYMBOFFSM_4 0xf2e60010
  2135. #define F367TER_SYMBOFFSM_3 0xf2e60008
  2136. #define F367TER_DEFGEN_SYMBOFFSET_HI 0xf2e60007
  2137. /* SYMBOFFSL */
  2138. #define R367TER_SYMBOFFSL 0xf2e7
  2139. #define F367TER_DEFGEN_SYMBOFFSET_LO 0xf2e700ff
  2140. /* DEBUG_LT4 */
  2141. #define R367TER_DEBUG_LT4 0xf400
  2142. #define F367TER_F_DEBUG_LT4 0xf40000ff
  2143. /* DEBUG_LT5 */
  2144. #define R367TER_DEBUG_LT5 0xf401
  2145. #define F367TER_F_DEBUG_LT5 0xf40100ff
  2146. /* DEBUG_LT6 */
  2147. #define R367TER_DEBUG_LT6 0xf402
  2148. #define F367TER_F_DEBUG_LT6 0xf40200ff
  2149. /* DEBUG_LT7 */
  2150. #define R367TER_DEBUG_LT7 0xf403
  2151. #define F367TER_F_DEBUG_LT7 0xf40300ff
  2152. /* DEBUG_LT8 */
  2153. #define R367TER_DEBUG_LT8 0xf404
  2154. #define F367TER_F_DEBUG_LT8 0xf40400ff
  2155. /* DEBUG_LT9 */
  2156. #define R367TER_DEBUG_LT9 0xf405
  2157. #define F367TER_F_DEBUG_LT9 0xf40500ff
  2158. /* ID */
  2159. #define R367CAB_ID 0xf000
  2160. #define F367CAB_IDENTIFICATIONREGISTER 0xf00000ff
  2161. /* I2CRPT */
  2162. #define R367CAB_I2CRPT 0xf001
  2163. #define F367CAB_I2CT_ON 0xf0010080
  2164. #define F367CAB_ENARPT_LEVEL 0xf0010070
  2165. #define F367CAB_SCLT_DELAY 0xf0010008
  2166. #define F367CAB_SCLT_NOD 0xf0010004
  2167. #define F367CAB_STOP_ENABLE 0xf0010002
  2168. #define F367CAB_SDAT_NOD 0xf0010001
  2169. /* TOPCTRL */
  2170. #define R367CAB_TOPCTRL 0xf002
  2171. #define F367CAB_STDBY 0xf0020080
  2172. #define F367CAB_STDBY_CORE 0xf0020020
  2173. #define F367CAB_QAM_COFDM 0xf0020010
  2174. #define F367CAB_TS_DIS 0xf0020008
  2175. #define F367CAB_DIR_CLK_216 0xf0020004
  2176. /* IOCFG0 */
  2177. #define R367CAB_IOCFG0 0xf003
  2178. #define F367CAB_OP0_SD 0xf0030080
  2179. #define F367CAB_OP0_VAL 0xf0030040
  2180. #define F367CAB_OP0_OD 0xf0030020
  2181. #define F367CAB_OP0_INV 0xf0030010
  2182. #define F367CAB_OP0_DACVALUE_HI 0xf003000f
  2183. /* DAc0R */
  2184. #define R367CAB_DAC0R 0xf004
  2185. #define F367CAB_OP0_DACVALUE_LO 0xf00400ff
  2186. /* IOCFG1 */
  2187. #define R367CAB_IOCFG1 0xf005
  2188. #define F367CAB_IP0 0xf0050040
  2189. #define F367CAB_OP1_OD 0xf0050020
  2190. #define F367CAB_OP1_INV 0xf0050010
  2191. #define F367CAB_OP1_DACVALUE_HI 0xf005000f
  2192. /* DAC1R */
  2193. #define R367CAB_DAC1R 0xf006
  2194. #define F367CAB_OP1_DACVALUE_LO 0xf00600ff
  2195. /* IOCFG2 */
  2196. #define R367CAB_IOCFG2 0xf007
  2197. #define F367CAB_OP2_LOCK_CONF 0xf00700e0
  2198. #define F367CAB_OP2_OD 0xf0070010
  2199. #define F367CAB_OP2_VAL 0xf0070008
  2200. #define F367CAB_OP1_LOCK_CONF 0xf0070007
  2201. /* SDFR */
  2202. #define R367CAB_SDFR 0xf008
  2203. #define F367CAB_OP0_FREQ 0xf00800f0
  2204. #define F367CAB_OP1_FREQ 0xf008000f
  2205. /* AUX_CLK */
  2206. #define R367CAB_AUX_CLK 0xf00a
  2207. #define F367CAB_AUXFEC_CTL 0xf00a00c0
  2208. #define F367CAB_DIS_CKX4 0xf00a0020
  2209. #define F367CAB_CKSEL 0xf00a0018
  2210. #define F367CAB_CKDIV_PROG 0xf00a0006
  2211. #define F367CAB_AUXCLK_ENA 0xf00a0001
  2212. /* FREESYS1 */
  2213. #define R367CAB_FREESYS1 0xf00b
  2214. #define F367CAB_FREESYS_1 0xf00b00ff
  2215. /* FREESYS2 */
  2216. #define R367CAB_FREESYS2 0xf00c
  2217. #define F367CAB_FREESYS_2 0xf00c00ff
  2218. /* FREESYS3 */
  2219. #define R367CAB_FREESYS3 0xf00d
  2220. #define F367CAB_FREESYS_3 0xf00d00ff
  2221. /* GPIO_CFG */
  2222. #define R367CAB_GPIO_CFG 0xf00e
  2223. #define F367CAB_GPIO7_OD 0xf00e0080
  2224. #define F367CAB_GPIO7_CFG 0xf00e0040
  2225. #define F367CAB_GPIO6_OD 0xf00e0020
  2226. #define F367CAB_GPIO6_CFG 0xf00e0010
  2227. #define F367CAB_GPIO5_OD 0xf00e0008
  2228. #define F367CAB_GPIO5_CFG 0xf00e0004
  2229. #define F367CAB_GPIO4_OD 0xf00e0002
  2230. #define F367CAB_GPIO4_CFG 0xf00e0001
  2231. /* GPIO_CMD */
  2232. #define R367CAB_GPIO_CMD 0xf00f
  2233. #define F367CAB_GPIO7_VAL 0xf00f0008
  2234. #define F367CAB_GPIO6_VAL 0xf00f0004
  2235. #define F367CAB_GPIO5_VAL 0xf00f0002
  2236. #define F367CAB_GPIO4_VAL 0xf00f0001
  2237. /* TSTRES */
  2238. #define R367CAB_TSTRES 0xf0c0
  2239. #define F367CAB_FRES_DISPLAY 0xf0c00080
  2240. #define F367CAB_FRES_FIFO_AD 0xf0c00020
  2241. #define F367CAB_FRESRS 0xf0c00010
  2242. #define F367CAB_FRESACS 0xf0c00008
  2243. #define F367CAB_FRESFEC 0xf0c00004
  2244. #define F367CAB_FRES_PRIF 0xf0c00002
  2245. #define F367CAB_FRESCORE 0xf0c00001
  2246. /* ANACTRL */
  2247. #define R367CAB_ANACTRL 0xf0c1
  2248. #define F367CAB_BYPASS_XTAL 0xf0c10040
  2249. #define F367CAB_BYPASS_PLLXN 0xf0c1000c
  2250. #define F367CAB_DIS_PAD_OSC 0xf0c10002
  2251. #define F367CAB_STDBY_PLLXN 0xf0c10001
  2252. /* TSTBUS */
  2253. #define R367CAB_TSTBUS 0xf0c2
  2254. #define F367CAB_TS_BYTE_CLK_INV 0xf0c20080
  2255. #define F367CAB_CFG_IP 0xf0c20070
  2256. #define F367CAB_CFG_TST 0xf0c2000f
  2257. /* RF_AGC1 */
  2258. #define R367CAB_RF_AGC1 0xf0d4
  2259. #define F367CAB_RF_AGC1_LEVEL_HI 0xf0d400ff
  2260. /* RF_AGC2 */
  2261. #define R367CAB_RF_AGC2 0xf0d5
  2262. #define F367CAB_REF_ADGP 0xf0d50080
  2263. #define F367CAB_STDBY_ADCGP 0xf0d50020
  2264. #define F367CAB_RF_AGC1_LEVEL_LO 0xf0d50003
  2265. /* ANADIGCTRL */
  2266. #define R367CAB_ANADIGCTRL 0xf0d7
  2267. #define F367CAB_SEL_CLKDEM 0xf0d70020
  2268. #define F367CAB_EN_BUFFER_Q 0xf0d70010
  2269. #define F367CAB_EN_BUFFER_I 0xf0d70008
  2270. #define F367CAB_ADC_RIS_EGDE 0xf0d70004
  2271. #define F367CAB_SGN_ADC 0xf0d70002
  2272. #define F367CAB_SEL_AD12_SYNC 0xf0d70001
  2273. /* PLLMDIV */
  2274. #define R367CAB_PLLMDIV 0xf0d8
  2275. #define F367CAB_PLL_MDIV 0xf0d800ff
  2276. /* PLLNDIV */
  2277. #define R367CAB_PLLNDIV 0xf0d9
  2278. #define F367CAB_PLL_NDIV 0xf0d900ff
  2279. /* PLLSETUP */
  2280. #define R367CAB_PLLSETUP 0xf0da
  2281. #define F367CAB_PLL_PDIV 0xf0da0070
  2282. #define F367CAB_PLL_KDIV 0xf0da000f
  2283. /* DUAL_AD12 */
  2284. #define R367CAB_DUAL_AD12 0xf0db
  2285. #define F367CAB_FS20M 0xf0db0020
  2286. #define F367CAB_FS50M 0xf0db0010
  2287. #define F367CAB_INMODe0 0xf0db0008
  2288. #define F367CAB_POFFQ 0xf0db0004
  2289. #define F367CAB_POFFI 0xf0db0002
  2290. #define F367CAB_INMODE1 0xf0db0001
  2291. /* TSTBIST */
  2292. #define R367CAB_TSTBIST 0xf0dc
  2293. #define F367CAB_TST_BYP_CLK 0xf0dc0080
  2294. #define F367CAB_TST_GCLKENA_STD 0xf0dc0040
  2295. #define F367CAB_TST_GCLKENA 0xf0dc0020
  2296. #define F367CAB_TST_MEMBIST 0xf0dc001f
  2297. /* CTRL_1 */
  2298. #define R367CAB_CTRL_1 0xf402
  2299. #define F367CAB_SOFT_RST 0xf4020080
  2300. #define F367CAB_EQU_RST 0xf4020008
  2301. #define F367CAB_CRL_RST 0xf4020004
  2302. #define F367CAB_TRL_RST 0xf4020002
  2303. #define F367CAB_AGC_RST 0xf4020001
  2304. /* CTRL_2 */
  2305. #define R367CAB_CTRL_2 0xf403
  2306. #define F367CAB_DEINT_RST 0xf4030008
  2307. #define F367CAB_RS_RST 0xf4030004
  2308. /* IT_STATUS1 */
  2309. #define R367CAB_IT_STATUS1 0xf408
  2310. #define F367CAB_SWEEP_OUT 0xf4080080
  2311. #define F367CAB_FSM_CRL 0xf4080040
  2312. #define F367CAB_CRL_LOCK 0xf4080020
  2313. #define F367CAB_MFSM 0xf4080010
  2314. #define F367CAB_TRL_LOCK 0xf4080008
  2315. #define F367CAB_TRL_AGC_LIMIT 0xf4080004
  2316. #define F367CAB_ADJ_AGC_LOCK 0xf4080002
  2317. #define F367CAB_AGC_QAM_LOCK 0xf4080001
  2318. /* IT_STATUS2 */
  2319. #define R367CAB_IT_STATUS2 0xf409
  2320. #define F367CAB_TSMF_CNT 0xf4090080
  2321. #define F367CAB_TSMF_EOF 0xf4090040
  2322. #define F367CAB_TSMF_RDY 0xf4090020
  2323. #define F367CAB_FEC_NOCORR 0xf4090010
  2324. #define F367CAB_SYNCSTATE 0xf4090008
  2325. #define F367CAB_DEINT_LOCK 0xf4090004
  2326. #define F367CAB_FADDING_FRZ 0xf4090002
  2327. #define F367CAB_TAPMON_ALARM 0xf4090001
  2328. /* IT_EN1 */
  2329. #define R367CAB_IT_EN1 0xf40a
  2330. #define F367CAB_SWEEP_OUTE 0xf40a0080
  2331. #define F367CAB_FSM_CRLE 0xf40a0040
  2332. #define F367CAB_CRL_LOCKE 0xf40a0020
  2333. #define F367CAB_MFSME 0xf40a0010
  2334. #define F367CAB_TRL_LOCKE 0xf40a0008
  2335. #define F367CAB_TRL_AGC_LIMITE 0xf40a0004
  2336. #define F367CAB_ADJ_AGC_LOCKE 0xf40a0002
  2337. #define F367CAB_AGC_LOCKE 0xf40a0001
  2338. /* IT_EN2 */
  2339. #define R367CAB_IT_EN2 0xf40b
  2340. #define F367CAB_TSMF_CNTE 0xf40b0080
  2341. #define F367CAB_TSMF_EOFE 0xf40b0040
  2342. #define F367CAB_TSMF_RDYE 0xf40b0020
  2343. #define F367CAB_FEC_NOCORRE 0xf40b0010
  2344. #define F367CAB_SYNCSTATEE 0xf40b0008
  2345. #define F367CAB_DEINT_LOCKE 0xf40b0004
  2346. #define F367CAB_FADDING_FRZE 0xf40b0002
  2347. #define F367CAB_TAPMON_ALARME 0xf40b0001
  2348. /* CTRL_STATUS */
  2349. #define R367CAB_CTRL_STATUS 0xf40c
  2350. #define F367CAB_QAMFEC_LOCK 0xf40c0004
  2351. #define F367CAB_TSMF_LOCK 0xf40c0002
  2352. #define F367CAB_TSMF_ERROR 0xf40c0001
  2353. /* TEST_CTL */
  2354. #define R367CAB_TEST_CTL 0xf40f
  2355. #define F367CAB_TST_BLK_SEL 0xf40f0060
  2356. #define F367CAB_TST_BUS_SEL 0xf40f001f
  2357. /* AGC_CTL */
  2358. #define R367CAB_AGC_CTL 0xf410
  2359. #define F367CAB_AGC_LCK_TH 0xf41000f0
  2360. #define F367CAB_AGC_ACCUMRSTSEL 0xf4100007
  2361. /* AGC_IF_CFG */
  2362. #define R367CAB_AGC_IF_CFG 0xf411
  2363. #define F367CAB_AGC_IF_BWSEL 0xf41100f0
  2364. #define F367CAB_AGC_IF_FREEZE 0xf4110002
  2365. /* AGC_RF_CFG */
  2366. #define R367CAB_AGC_RF_CFG 0xf412
  2367. #define F367CAB_AGC_RF_BWSEL 0xf4120070
  2368. #define F367CAB_AGC_RF_FREEZE 0xf4120002
  2369. /* AGC_PWM_CFG */
  2370. #define R367CAB_AGC_PWM_CFG 0xf413
  2371. #define F367CAB_AGC_RF_PWM_TST 0xf4130080
  2372. #define F367CAB_AGC_RF_PWM_INV 0xf4130040
  2373. #define F367CAB_AGC_IF_PWM_TST 0xf4130008
  2374. #define F367CAB_AGC_IF_PWM_INV 0xf4130004
  2375. #define F367CAB_AGC_PWM_CLKDIV 0xf4130003
  2376. /* AGC_PWR_REF_L */
  2377. #define R367CAB_AGC_PWR_REF_L 0xf414
  2378. #define F367CAB_AGC_PWRREF_LO 0xf41400ff
  2379. /* AGC_PWR_REF_H */
  2380. #define R367CAB_AGC_PWR_REF_H 0xf415
  2381. #define F367CAB_AGC_PWRREF_HI 0xf4150003
  2382. /* AGC_RF_TH_L */
  2383. #define R367CAB_AGC_RF_TH_L 0xf416
  2384. #define F367CAB_AGC_RF_TH_LO 0xf41600ff
  2385. /* AGC_RF_TH_H */
  2386. #define R367CAB_AGC_RF_TH_H 0xf417
  2387. #define F367CAB_AGC_RF_TH_HI 0xf417000f
  2388. /* AGC_IF_LTH_L */
  2389. #define R367CAB_AGC_IF_LTH_L 0xf418
  2390. #define F367CAB_AGC_IF_THLO_LO 0xf41800ff
  2391. /* AGC_IF_LTH_H */
  2392. #define R367CAB_AGC_IF_LTH_H 0xf419
  2393. #define F367CAB_AGC_IF_THLO_HI 0xf419000f
  2394. /* AGC_IF_HTH_L */
  2395. #define R367CAB_AGC_IF_HTH_L 0xf41a
  2396. #define F367CAB_AGC_IF_THHI_LO 0xf41a00ff
  2397. /* AGC_IF_HTH_H */
  2398. #define R367CAB_AGC_IF_HTH_H 0xf41b
  2399. #define F367CAB_AGC_IF_THHI_HI 0xf41b000f
  2400. /* AGC_PWR_RD_L */
  2401. #define R367CAB_AGC_PWR_RD_L 0xf41c
  2402. #define F367CAB_AGC_PWR_WORD_LO 0xf41c00ff
  2403. /* AGC_PWR_RD_M */
  2404. #define R367CAB_AGC_PWR_RD_M 0xf41d
  2405. #define F367CAB_AGC_PWR_WORD_ME 0xf41d00ff
  2406. /* AGC_PWR_RD_H */
  2407. #define R367CAB_AGC_PWR_RD_H 0xf41e
  2408. #define F367CAB_AGC_PWR_WORD_HI 0xf41e0003
  2409. /* AGC_PWM_IFCMD_L */
  2410. #define R367CAB_AGC_PWM_IFCMD_L 0xf420
  2411. #define F367CAB_AGC_IF_PWMCMD_LO 0xf42000ff
  2412. /* AGC_PWM_IFCMD_H */
  2413. #define R367CAB_AGC_PWM_IFCMD_H 0xf421
  2414. #define F367CAB_AGC_IF_PWMCMD_HI 0xf421000f
  2415. /* AGC_PWM_RFCMD_L */
  2416. #define R367CAB_AGC_PWM_RFCMD_L 0xf422
  2417. #define F367CAB_AGC_RF_PWMCMD_LO 0xf42200ff
  2418. /* AGC_PWM_RFCMD_H */
  2419. #define R367CAB_AGC_PWM_RFCMD_H 0xf423
  2420. #define F367CAB_AGC_RF_PWMCMD_HI 0xf423000f
  2421. /* IQDEM_CFG */
  2422. #define R367CAB_IQDEM_CFG 0xf424
  2423. #define F367CAB_IQDEM_CLK_SEL 0xf4240004
  2424. #define F367CAB_IQDEM_INVIQ 0xf4240002
  2425. #define F367CAB_IQDEM_A2dTYPE 0xf4240001
  2426. /* MIX_NCO_LL */
  2427. #define R367CAB_MIX_NCO_LL 0xf425
  2428. #define F367CAB_MIX_NCO_INC_LL 0xf42500ff
  2429. /* MIX_NCO_HL */
  2430. #define R367CAB_MIX_NCO_HL 0xf426
  2431. #define F367CAB_MIX_NCO_INC_HL 0xf42600ff
  2432. /* MIX_NCO_HH */
  2433. #define R367CAB_MIX_NCO_HH 0xf427
  2434. #define F367CAB_MIX_NCO_INVCNST 0xf4270080
  2435. #define F367CAB_MIX_NCO_INC_HH 0xf427007f
  2436. /* SRC_NCO_LL */
  2437. #define R367CAB_SRC_NCO_LL 0xf428
  2438. #define F367CAB_SRC_NCO_INC_LL 0xf42800ff
  2439. /* SRC_NCO_LH */
  2440. #define R367CAB_SRC_NCO_LH 0xf429
  2441. #define F367CAB_SRC_NCO_INC_LH 0xf42900ff
  2442. /* SRC_NCO_HL */
  2443. #define R367CAB_SRC_NCO_HL 0xf42a
  2444. #define F367CAB_SRC_NCO_INC_HL 0xf42a00ff
  2445. /* SRC_NCO_HH */
  2446. #define R367CAB_SRC_NCO_HH 0xf42b
  2447. #define F367CAB_SRC_NCO_INC_HH 0xf42b007f
  2448. /* IQDEM_GAIN_SRC_L */
  2449. #define R367CAB_IQDEM_GAIN_SRC_L 0xf42c
  2450. #define F367CAB_GAIN_SRC_LO 0xf42c00ff
  2451. /* IQDEM_GAIN_SRC_H */
  2452. #define R367CAB_IQDEM_GAIN_SRC_H 0xf42d
  2453. #define F367CAB_GAIN_SRC_HI 0xf42d0003
  2454. /* IQDEM_DCRM_CFG_LL */
  2455. #define R367CAB_IQDEM_DCRM_CFG_LL 0xf430
  2456. #define F367CAB_DCRM0_DCIN_L 0xf43000ff
  2457. /* IQDEM_DCRM_CFG_LH */
  2458. #define R367CAB_IQDEM_DCRM_CFG_LH 0xf431
  2459. #define F367CAB_DCRM1_I_DCIN_L 0xf43100fc
  2460. #define F367CAB_DCRM0_DCIN_H 0xf4310003
  2461. /* IQDEM_DCRM_CFG_HL */
  2462. #define R367CAB_IQDEM_DCRM_CFG_HL 0xf432
  2463. #define F367CAB_DCRM1_Q_DCIN_L 0xf43200f0
  2464. #define F367CAB_DCRM1_I_DCIN_H 0xf432000f
  2465. /* IQDEM_DCRM_CFG_HH */
  2466. #define R367CAB_IQDEM_DCRM_CFG_HH 0xf433
  2467. #define F367CAB_DCRM1_FRZ 0xf4330080
  2468. #define F367CAB_DCRM0_FRZ 0xf4330040
  2469. #define F367CAB_DCRM1_Q_DCIN_H 0xf433003f
  2470. /* IQDEM_ADJ_COEFf0 */
  2471. #define R367CAB_IQDEM_ADJ_COEFF0 0xf434
  2472. #define F367CAB_ADJIIR_COEFF10_L 0xf43400ff
  2473. /* IQDEM_ADJ_COEFF1 */
  2474. #define R367CAB_IQDEM_ADJ_COEFF1 0xf435
  2475. #define F367CAB_ADJIIR_COEFF11_L 0xf43500fc
  2476. #define F367CAB_ADJIIR_COEFF10_H 0xf4350003
  2477. /* IQDEM_ADJ_COEFF2 */
  2478. #define R367CAB_IQDEM_ADJ_COEFF2 0xf436
  2479. #define F367CAB_ADJIIR_COEFF12_L 0xf43600f0
  2480. #define F367CAB_ADJIIR_COEFF11_H 0xf436000f
  2481. /* IQDEM_ADJ_COEFF3 */
  2482. #define R367CAB_IQDEM_ADJ_COEFF3 0xf437
  2483. #define F367CAB_ADJIIR_COEFF20_L 0xf43700c0
  2484. #define F367CAB_ADJIIR_COEFF12_H 0xf437003f
  2485. /* IQDEM_ADJ_COEFF4 */
  2486. #define R367CAB_IQDEM_ADJ_COEFF4 0xf438
  2487. #define F367CAB_ADJIIR_COEFF20_H 0xf43800ff
  2488. /* IQDEM_ADJ_COEFF5 */
  2489. #define R367CAB_IQDEM_ADJ_COEFF5 0xf439
  2490. #define F367CAB_ADJIIR_COEFF21_L 0xf43900ff
  2491. /* IQDEM_ADJ_COEFF6 */
  2492. #define R367CAB_IQDEM_ADJ_COEFF6 0xf43a
  2493. #define F367CAB_ADJIIR_COEFF22_L 0xf43a00fc
  2494. #define F367CAB_ADJIIR_COEFF21_H 0xf43a0003
  2495. /* IQDEM_ADJ_COEFF7 */
  2496. #define R367CAB_IQDEM_ADJ_COEFF7 0xf43b
  2497. #define F367CAB_ADJIIR_COEFF22_H 0xf43b000f
  2498. /* IQDEM_ADJ_EN */
  2499. #define R367CAB_IQDEM_ADJ_EN 0xf43c
  2500. #define F367CAB_ALLPASSFILT_EN 0xf43c0008
  2501. #define F367CAB_ADJ_AGC_EN 0xf43c0004
  2502. #define F367CAB_ADJ_COEFF_FRZ 0xf43c0002
  2503. #define F367CAB_ADJ_EN 0xf43c0001
  2504. /* IQDEM_ADJ_AGC_REF */
  2505. #define R367CAB_IQDEM_ADJ_AGC_REF 0xf43d
  2506. #define F367CAB_ADJ_AGC_REF 0xf43d00ff
  2507. /* ALLPASSFILT1 */
  2508. #define R367CAB_ALLPASSFILT1 0xf440
  2509. #define F367CAB_ALLPASSFILT_COEFF1_LO 0xf44000ff
  2510. /* ALLPASSFILT2 */
  2511. #define R367CAB_ALLPASSFILT2 0xf441
  2512. #define F367CAB_ALLPASSFILT_COEFF1_ME 0xf44100ff
  2513. /* ALLPASSFILT3 */
  2514. #define R367CAB_ALLPASSFILT3 0xf442
  2515. #define F367CAB_ALLPASSFILT_COEFF2_LO 0xf44200c0
  2516. #define F367CAB_ALLPASSFILT_COEFF1_HI 0xf442003f
  2517. /* ALLPASSFILT4 */
  2518. #define R367CAB_ALLPASSFILT4 0xf443
  2519. #define F367CAB_ALLPASSFILT_COEFF2_MEL 0xf44300ff
  2520. /* ALLPASSFILT5 */
  2521. #define R367CAB_ALLPASSFILT5 0xf444
  2522. #define F367CAB_ALLPASSFILT_COEFF2_MEH 0xf44400ff
  2523. /* ALLPASSFILT6 */
  2524. #define R367CAB_ALLPASSFILT6 0xf445
  2525. #define F367CAB_ALLPASSFILT_COEFF3_LO 0xf44500f0
  2526. #define F367CAB_ALLPASSFILT_COEFF2_HI 0xf445000f
  2527. /* ALLPASSFILT7 */
  2528. #define R367CAB_ALLPASSFILT7 0xf446
  2529. #define F367CAB_ALLPASSFILT_COEFF3_MEL 0xf44600ff
  2530. /* ALLPASSFILT8 */
  2531. #define R367CAB_ALLPASSFILT8 0xf447
  2532. #define F367CAB_ALLPASSFILT_COEFF3_MEH 0xf44700ff
  2533. /* ALLPASSFILT9 */
  2534. #define R367CAB_ALLPASSFILT9 0xf448
  2535. #define F367CAB_ALLPASSFILT_COEFF4_LO 0xf44800fc
  2536. #define F367CAB_ALLPASSFILT_COEFF3_HI 0xf4480003
  2537. /* ALLPASSFILT10 */
  2538. #define R367CAB_ALLPASSFILT10 0xf449
  2539. #define F367CAB_ALLPASSFILT_COEFF4_ME 0xf44900ff
  2540. /* ALLPASSFILT11 */
  2541. #define R367CAB_ALLPASSFILT11 0xf44a
  2542. #define F367CAB_ALLPASSFILT_COEFF4_HI 0xf44a00ff
  2543. /* TRL_AGC_CFG */
  2544. #define R367CAB_TRL_AGC_CFG 0xf450
  2545. #define F367CAB_TRL_AGC_FREEZE 0xf4500080
  2546. #define F367CAB_TRL_AGC_REF 0xf450007f
  2547. /* TRL_LPF_CFG */
  2548. #define R367CAB_TRL_LPF_CFG 0xf454
  2549. #define F367CAB_NYQPOINT_INV 0xf4540040
  2550. #define F367CAB_TRL_SHIFT 0xf4540030
  2551. #define F367CAB_NYQ_COEFF_SEL 0xf454000c
  2552. #define F367CAB_TRL_LPF_FREEZE 0xf4540002
  2553. #define F367CAB_TRL_LPF_CRT 0xf4540001
  2554. /* TRL_LPF_ACQ_GAIN */
  2555. #define R367CAB_TRL_LPF_ACQ_GAIN 0xf455
  2556. #define F367CAB_TRL_GDIR_ACQ 0xf4550070
  2557. #define F367CAB_TRL_GINT_ACQ 0xf4550007
  2558. /* TRL_LPF_TRK_GAIN */
  2559. #define R367CAB_TRL_LPF_TRK_GAIN 0xf456
  2560. #define F367CAB_TRL_GDIR_TRK 0xf4560070
  2561. #define F367CAB_TRL_GINT_TRK 0xf4560007
  2562. /* TRL_LPF_OUT_GAIN */
  2563. #define R367CAB_TRL_LPF_OUT_GAIN 0xf457
  2564. #define F367CAB_TRL_GAIN_OUT 0xf4570007
  2565. /* TRL_LOCKDET_LTH */
  2566. #define R367CAB_TRL_LOCKDET_LTH 0xf458
  2567. #define F367CAB_TRL_LCK_THLO 0xf4580007
  2568. /* TRL_LOCKDET_HTH */
  2569. #define R367CAB_TRL_LOCKDET_HTH 0xf459
  2570. #define F367CAB_TRL_LCK_THHI 0xf45900ff
  2571. /* TRL_LOCKDET_TRGVAL */
  2572. #define R367CAB_TRL_LOCKDET_TRGVAL 0xf45a
  2573. #define F367CAB_TRL_LCK_TRG 0xf45a00ff
  2574. /* IQ_QAM */
  2575. #define R367CAB_IQ_QAM 0xf45c
  2576. #define F367CAB_IQ_INPUT 0xf45c0008
  2577. #define F367CAB_DETECT_MODE 0xf45c0007
  2578. /* FSM_STATE */
  2579. #define R367CAB_FSM_STATE 0xf460
  2580. #define F367CAB_CRL_DFE 0xf4600080
  2581. #define F367CAB_DFE_START 0xf4600040
  2582. #define F367CAB_CTRLG_START 0xf4600030
  2583. #define F367CAB_FSM_FORCESTATE 0xf460000f
  2584. /* FSM_CTL */
  2585. #define R367CAB_FSM_CTL 0xf461
  2586. #define F367CAB_FEC2_EN 0xf4610040
  2587. #define F367CAB_SIT_EN 0xf4610020
  2588. #define F367CAB_TRL_AHEAD 0xf4610010
  2589. #define F367CAB_TRL2_EN 0xf4610008
  2590. #define F367CAB_FSM_EQA1_EN 0xf4610004
  2591. #define F367CAB_FSM_BKP_DIS 0xf4610002
  2592. #define F367CAB_FSM_FORCE_EN 0xf4610001
  2593. /* FSM_STS */
  2594. #define R367CAB_FSM_STS 0xf462
  2595. #define F367CAB_FSM_STATUS 0xf462000f
  2596. /* FSM_SNR0_HTH */
  2597. #define R367CAB_FSM_SNR0_HTH 0xf463
  2598. #define F367CAB_SNR0_HTH 0xf46300ff
  2599. /* FSM_SNR1_HTH */
  2600. #define R367CAB_FSM_SNR1_HTH 0xf464
  2601. #define F367CAB_SNR1_HTH 0xf46400ff
  2602. /* FSM_SNR2_HTH */
  2603. #define R367CAB_FSM_SNR2_HTH 0xf465
  2604. #define F367CAB_SNR2_HTH 0xf46500ff
  2605. /* FSM_SNR0_LTH */
  2606. #define R367CAB_FSM_SNR0_LTH 0xf466
  2607. #define F367CAB_SNR0_LTH 0xf46600ff
  2608. /* FSM_SNR1_LTH */
  2609. #define R367CAB_FSM_SNR1_LTH 0xf467
  2610. #define F367CAB_SNR1_LTH 0xf46700ff
  2611. /* FSM_EQA1_HTH */
  2612. #define R367CAB_FSM_EQA1_HTH 0xf468
  2613. #define F367CAB_SNR3_HTH_LO 0xf46800f0
  2614. #define F367CAB_EQA1_HTH 0xf468000f
  2615. /* FSM_TEMPO */
  2616. #define R367CAB_FSM_TEMPO 0xf469
  2617. #define F367CAB_SIT 0xf46900c0
  2618. #define F367CAB_WST 0xf4690038
  2619. #define F367CAB_ELT 0xf4690006
  2620. #define F367CAB_SNR3_HTH_HI 0xf4690001
  2621. /* FSM_CONFIG */
  2622. #define R367CAB_FSM_CONFIG 0xf46a
  2623. #define F367CAB_FEC2_DFEOFF 0xf46a0004
  2624. #define F367CAB_PRIT_STATE 0xf46a0002
  2625. #define F367CAB_MODMAP_STATE 0xf46a0001
  2626. /* EQU_I_TESTTAP_L */
  2627. #define R367CAB_EQU_I_TESTTAP_L 0xf474
  2628. #define F367CAB_I_TEST_TAP_L 0xf47400ff
  2629. /* EQU_I_TESTTAP_M */
  2630. #define R367CAB_EQU_I_TESTTAP_M 0xf475
  2631. #define F367CAB_I_TEST_TAP_M 0xf47500ff
  2632. /* EQU_I_TESTTAP_H */
  2633. #define R367CAB_EQU_I_TESTTAP_H 0xf476
  2634. #define F367CAB_I_TEST_TAP_H 0xf476001f
  2635. /* EQU_TESTAP_CFG */
  2636. #define R367CAB_EQU_TESTAP_CFG 0xf477
  2637. #define F367CAB_TEST_FFE_DFE_SEL 0xf4770040
  2638. #define F367CAB_TEST_TAP_SELECT 0xf477003f
  2639. /* EQU_Q_TESTTAP_L */
  2640. #define R367CAB_EQU_Q_TESTTAP_L 0xf478
  2641. #define F367CAB_Q_TEST_TAP_L 0xf47800ff
  2642. /* EQU_Q_TESTTAP_M */
  2643. #define R367CAB_EQU_Q_TESTTAP_M 0xf479
  2644. #define F367CAB_Q_TEST_TAP_M 0xf47900ff
  2645. /* EQU_Q_TESTTAP_H */
  2646. #define R367CAB_EQU_Q_TESTTAP_H 0xf47a
  2647. #define F367CAB_Q_TEST_TAP_H 0xf47a001f
  2648. /* EQU_TAP_CTRL */
  2649. #define R367CAB_EQU_TAP_CTRL 0xf47b
  2650. #define F367CAB_MTAP_FRZ 0xf47b0010
  2651. #define F367CAB_PRE_FREEZE 0xf47b0008
  2652. #define F367CAB_DFE_TAPMON_EN 0xf47b0004
  2653. #define F367CAB_FFE_TAPMON_EN 0xf47b0002
  2654. #define F367CAB_MTAP_ONLY 0xf47b0001
  2655. /* EQU_CTR_CRL_CONTROL_L */
  2656. #define R367CAB_EQU_CTR_CRL_CONTROL_L 0xf47c
  2657. #define F367CAB_EQU_CTR_CRL_CONTROL_LO 0xf47c00ff
  2658. /* EQU_CTR_CRL_CONTROL_H */
  2659. #define R367CAB_EQU_CTR_CRL_CONTROL_H 0xf47d
  2660. #define F367CAB_EQU_CTR_CRL_CONTROL_HI 0xf47d00ff
  2661. /* EQU_CTR_HIPOW_L */
  2662. #define R367CAB_EQU_CTR_HIPOW_L 0xf47e
  2663. #define F367CAB_CTR_HIPOW_L 0xf47e00ff
  2664. /* EQU_CTR_HIPOW_H */
  2665. #define R367CAB_EQU_CTR_HIPOW_H 0xf47f
  2666. #define F367CAB_CTR_HIPOW_H 0xf47f00ff
  2667. /* EQU_I_EQU_LO */
  2668. #define R367CAB_EQU_I_EQU_LO 0xf480
  2669. #define F367CAB_EQU_I_EQU_L 0xf48000ff
  2670. /* EQU_I_EQU_HI */
  2671. #define R367CAB_EQU_I_EQU_HI 0xf481
  2672. #define F367CAB_EQU_I_EQU_H 0xf4810003
  2673. /* EQU_Q_EQU_LO */
  2674. #define R367CAB_EQU_Q_EQU_LO 0xf482
  2675. #define F367CAB_EQU_Q_EQU_L 0xf48200ff
  2676. /* EQU_Q_EQU_HI */
  2677. #define R367CAB_EQU_Q_EQU_HI 0xf483
  2678. #define F367CAB_EQU_Q_EQU_H 0xf4830003
  2679. /* EQU_MAPPER */
  2680. #define R367CAB_EQU_MAPPER 0xf484
  2681. #define F367CAB_QUAD_AUTO 0xf4840080
  2682. #define F367CAB_QUAD_INV 0xf4840040
  2683. #define F367CAB_QAM_MODE 0xf4840007
  2684. /* EQU_SWEEP_RATE */
  2685. #define R367CAB_EQU_SWEEP_RATE 0xf485
  2686. #define F367CAB_SNR_PER 0xf48500c0
  2687. #define F367CAB_SWEEP_RATE 0xf485003f
  2688. /* EQU_SNR_LO */
  2689. #define R367CAB_EQU_SNR_LO 0xf486
  2690. #define F367CAB_SNR_LO 0xf48600ff
  2691. /* EQU_SNR_HI */
  2692. #define R367CAB_EQU_SNR_HI 0xf487
  2693. #define F367CAB_SNR_HI 0xf48700ff
  2694. /* EQU_GAMMA_LO */
  2695. #define R367CAB_EQU_GAMMA_LO 0xf488
  2696. #define F367CAB_GAMMA_LO 0xf48800ff
  2697. /* EQU_GAMMA_HI */
  2698. #define R367CAB_EQU_GAMMA_HI 0xf489
  2699. #define F367CAB_GAMMA_ME 0xf48900ff
  2700. /* EQU_ERR_GAIN */
  2701. #define R367CAB_EQU_ERR_GAIN 0xf48a
  2702. #define F367CAB_EQA1MU 0xf48a0070
  2703. #define F367CAB_CRL2MU 0xf48a000e
  2704. #define F367CAB_GAMMA_HI 0xf48a0001
  2705. /* EQU_RADIUS */
  2706. #define R367CAB_EQU_RADIUS 0xf48b
  2707. #define F367CAB_RADIUS 0xf48b00ff
  2708. /* EQU_FFE_MAINTAP */
  2709. #define R367CAB_EQU_FFE_MAINTAP 0xf48c
  2710. #define F367CAB_FFE_MAINTAP_INIT 0xf48c00ff
  2711. /* EQU_FFE_LEAKAGE */
  2712. #define R367CAB_EQU_FFE_LEAKAGE 0xf48e
  2713. #define F367CAB_LEAK_PER 0xf48e00f0
  2714. #define F367CAB_EQU_OUTSEL 0xf48e0002
  2715. #define F367CAB_PNT2dFE 0xf48e0001
  2716. /* EQU_FFE_MAINTAP_POS */
  2717. #define R367CAB_EQU_FFE_MAINTAP_POS 0xf48f
  2718. #define F367CAB_FFE_LEAK_EN 0xf48f0080
  2719. #define F367CAB_DFE_LEAK_EN 0xf48f0040
  2720. #define F367CAB_FFE_MAINTAP_POS 0xf48f003f
  2721. /* EQU_GAIN_WIDE */
  2722. #define R367CAB_EQU_GAIN_WIDE 0xf490
  2723. #define F367CAB_DFE_GAIN_WIDE 0xf49000f0
  2724. #define F367CAB_FFE_GAIN_WIDE 0xf490000f
  2725. /* EQU_GAIN_NARROW */
  2726. #define R367CAB_EQU_GAIN_NARROW 0xf491
  2727. #define F367CAB_DFE_GAIN_NARROW 0xf49100f0
  2728. #define F367CAB_FFE_GAIN_NARROW 0xf491000f
  2729. /* EQU_CTR_LPF_GAIN */
  2730. #define R367CAB_EQU_CTR_LPF_GAIN 0xf492
  2731. #define F367CAB_CTR_GTO 0xf4920080
  2732. #define F367CAB_CTR_GDIR 0xf4920070
  2733. #define F367CAB_SWEEP_EN 0xf4920008
  2734. #define F367CAB_CTR_GINT 0xf4920007
  2735. /* EQU_CRL_LPF_GAIN */
  2736. #define R367CAB_EQU_CRL_LPF_GAIN 0xf493
  2737. #define F367CAB_CRL_GTO 0xf4930080
  2738. #define F367CAB_CRL_GDIR 0xf4930070
  2739. #define F367CAB_SWEEP_DIR 0xf4930008
  2740. #define F367CAB_CRL_GINT 0xf4930007
  2741. /* EQU_GLOBAL_GAIN */
  2742. #define R367CAB_EQU_GLOBAL_GAIN 0xf494
  2743. #define F367CAB_CRL_GAIN 0xf49400f8
  2744. #define F367CAB_CTR_INC_GAIN 0xf4940004
  2745. #define F367CAB_CTR_FRAC 0xf4940003
  2746. /* EQU_CRL_LD_SEN */
  2747. #define R367CAB_EQU_CRL_LD_SEN 0xf495
  2748. #define F367CAB_CTR_BADPOINT_EN 0xf4950080
  2749. #define F367CAB_CTR_GAIN 0xf4950070
  2750. #define F367CAB_LIMANEN 0xf4950008
  2751. #define F367CAB_CRL_LD_SEN 0xf4950007
  2752. /* EQU_CRL_LD_VAL */
  2753. #define R367CAB_EQU_CRL_LD_VAL 0xf496
  2754. #define F367CAB_CRL_BISTH_LIMIT 0xf4960080
  2755. #define F367CAB_CARE_EN 0xf4960040
  2756. #define F367CAB_CRL_LD_PER 0xf4960030
  2757. #define F367CAB_CRL_LD_WST 0xf496000c
  2758. #define F367CAB_CRL_LD_TFS 0xf4960003
  2759. /* EQU_CRL_TFR */
  2760. #define R367CAB_EQU_CRL_TFR 0xf497
  2761. #define F367CAB_CRL_LD_TFR 0xf49700ff
  2762. /* EQU_CRL_BISTH_LO */
  2763. #define R367CAB_EQU_CRL_BISTH_LO 0xf498
  2764. #define F367CAB_CRL_BISTH_LO 0xf49800ff
  2765. /* EQU_CRL_BISTH_HI */
  2766. #define R367CAB_EQU_CRL_BISTH_HI 0xf499
  2767. #define F367CAB_CRL_BISTH_HI 0xf49900ff
  2768. /* EQU_SWEEP_RANGE_LO */
  2769. #define R367CAB_EQU_SWEEP_RANGE_LO 0xf49a
  2770. #define F367CAB_SWEEP_RANGE_LO 0xf49a00ff
  2771. /* EQU_SWEEP_RANGE_HI */
  2772. #define R367CAB_EQU_SWEEP_RANGE_HI 0xf49b
  2773. #define F367CAB_SWEEP_RANGE_HI 0xf49b00ff
  2774. /* EQU_CRL_LIMITER */
  2775. #define R367CAB_EQU_CRL_LIMITER 0xf49c
  2776. #define F367CAB_BISECTOR_EN 0xf49c0080
  2777. #define F367CAB_PHEST128_EN 0xf49c0040
  2778. #define F367CAB_CRL_LIM 0xf49c003f
  2779. /* EQU_MODULUS_MAP */
  2780. #define R367CAB_EQU_MODULUS_MAP 0xf49d
  2781. #define F367CAB_PNT_DEPTH 0xf49d00e0
  2782. #define F367CAB_MODULUS_CMP 0xf49d001f
  2783. /* EQU_PNT_GAIN */
  2784. #define R367CAB_EQU_PNT_GAIN 0xf49e
  2785. #define F367CAB_PNT_EN 0xf49e0080
  2786. #define F367CAB_MODULUSMAP_EN 0xf49e0040
  2787. #define F367CAB_PNT_GAIN 0xf49e003f
  2788. /* FEC_AC_CTR_0 */
  2789. #define R367CAB_FEC_AC_CTR_0 0xf4a8
  2790. #define F367CAB_BE_BYPASS 0xf4a80020
  2791. #define F367CAB_REFRESH47 0xf4a80010
  2792. #define F367CAB_CT_NBST 0xf4a80008
  2793. #define F367CAB_TEI_ENA 0xf4a80004
  2794. #define F367CAB_DS_ENA 0xf4a80002
  2795. #define F367CAB_TSMF_EN 0xf4a80001
  2796. /* FEC_AC_CTR_1 */
  2797. #define R367CAB_FEC_AC_CTR_1 0xf4a9
  2798. #define F367CAB_DEINT_DEPTH 0xf4a900ff
  2799. /* FEC_AC_CTR_2 */
  2800. #define R367CAB_FEC_AC_CTR_2 0xf4aa
  2801. #define F367CAB_DEINT_M 0xf4aa00f8
  2802. #define F367CAB_DIS_UNLOCK 0xf4aa0004
  2803. #define F367CAB_DESCR_MODE 0xf4aa0003
  2804. /* FEC_AC_CTR_3 */
  2805. #define R367CAB_FEC_AC_CTR_3 0xf4ab
  2806. #define F367CAB_DI_UNLOCK 0xf4ab0080
  2807. #define F367CAB_DI_FREEZE 0xf4ab0040
  2808. #define F367CAB_MISMATCH 0xf4ab0030
  2809. #define F367CAB_ACQ_MODE 0xf4ab000c
  2810. #define F367CAB_TRK_MODE 0xf4ab0003
  2811. /* FEC_STATUS */
  2812. #define R367CAB_FEC_STATUS 0xf4ac
  2813. #define F367CAB_DEINT_SMCNTR 0xf4ac00e0
  2814. #define F367CAB_DEINT_SYNCSTATE 0xf4ac0018
  2815. #define F367CAB_DEINT_SYNLOST 0xf4ac0004
  2816. #define F367CAB_DESCR_SYNCSTATE 0xf4ac0002
  2817. /* RS_COUNTER_0 */
  2818. #define R367CAB_RS_COUNTER_0 0xf4ae
  2819. #define F367CAB_BK_CT_L 0xf4ae00ff
  2820. /* RS_COUNTER_1 */
  2821. #define R367CAB_RS_COUNTER_1 0xf4af
  2822. #define F367CAB_BK_CT_H 0xf4af00ff
  2823. /* RS_COUNTER_2 */
  2824. #define R367CAB_RS_COUNTER_2 0xf4b0
  2825. #define F367CAB_CORR_CT_L 0xf4b000ff
  2826. /* RS_COUNTER_3 */
  2827. #define R367CAB_RS_COUNTER_3 0xf4b1
  2828. #define F367CAB_CORR_CT_H 0xf4b100ff
  2829. /* RS_COUNTER_4 */
  2830. #define R367CAB_RS_COUNTER_4 0xf4b2
  2831. #define F367CAB_UNCORR_CT_L 0xf4b200ff
  2832. /* RS_COUNTER_5 */
  2833. #define R367CAB_RS_COUNTER_5 0xf4b3
  2834. #define F367CAB_UNCORR_CT_H 0xf4b300ff
  2835. /* BERT_0 */
  2836. #define R367CAB_BERT_0 0xf4b4
  2837. #define F367CAB_RS_NOCORR 0xf4b40004
  2838. #define F367CAB_CT_HOLD 0xf4b40002
  2839. #define F367CAB_CT_CLEAR 0xf4b40001
  2840. /* BERT_1 */
  2841. #define R367CAB_BERT_1 0xf4b5
  2842. #define F367CAB_BERT_ON 0xf4b50020
  2843. #define F367CAB_BERT_ERR_SRC 0xf4b50010
  2844. #define F367CAB_BERT_ERR_MODE 0xf4b50008
  2845. #define F367CAB_BERT_NBYTE 0xf4b50007
  2846. /* BERT_2 */
  2847. #define R367CAB_BERT_2 0xf4b6
  2848. #define F367CAB_BERT_ERRCOUNT_L 0xf4b600ff
  2849. /* BERT_3 */
  2850. #define R367CAB_BERT_3 0xf4b7
  2851. #define F367CAB_BERT_ERRCOUNT_H 0xf4b700ff
  2852. /* OUTFORMAT_0 */
  2853. #define R367CAB_OUTFORMAT_0 0xf4b8
  2854. #define F367CAB_CLK_POLARITY 0xf4b80080
  2855. #define F367CAB_FEC_TYPE 0xf4b80040
  2856. #define F367CAB_SYNC_STRIP 0xf4b80008
  2857. #define F367CAB_TS_SWAP 0xf4b80004
  2858. #define F367CAB_OUTFORMAT 0xf4b80003
  2859. /* OUTFORMAT_1 */
  2860. #define R367CAB_OUTFORMAT_1 0xf4b9
  2861. #define F367CAB_CI_DIVRANGE 0xf4b900ff
  2862. /* SMOOTHER_2 */
  2863. #define R367CAB_SMOOTHER_2 0xf4be
  2864. #define F367CAB_FIFO_BYPASS 0xf4be0020
  2865. /* TSMF_CTRL_0 */
  2866. #define R367CAB_TSMF_CTRL_0 0xf4c0
  2867. #define F367CAB_TS_NUMBER 0xf4c0001e
  2868. #define F367CAB_SEL_MODE 0xf4c00001
  2869. /* TSMF_CTRL_1 */
  2870. #define R367CAB_TSMF_CTRL_1 0xf4c1
  2871. #define F367CAB_CHECK_ERROR_BIT 0xf4c10080
  2872. #define F367CAB_CHCK_F_SYNC 0xf4c10040
  2873. #define F367CAB_H_MODE 0xf4c10008
  2874. #define F367CAB_D_V_MODE 0xf4c10004
  2875. #define F367CAB_MODE 0xf4c10003
  2876. /* TSMF_CTRL_3 */
  2877. #define R367CAB_TSMF_CTRL_3 0xf4c3
  2878. #define F367CAB_SYNC_IN_COUNT 0xf4c300f0
  2879. #define F367CAB_SYNC_OUT_COUNT 0xf4c3000f
  2880. /* TS_ON_ID_0 */
  2881. #define R367CAB_TS_ON_ID_0 0xf4c4
  2882. #define F367CAB_TS_ID_L 0xf4c400ff
  2883. /* TS_ON_ID_1 */
  2884. #define R367CAB_TS_ON_ID_1 0xf4c5
  2885. #define F367CAB_TS_ID_H 0xf4c500ff
  2886. /* TS_ON_ID_2 */
  2887. #define R367CAB_TS_ON_ID_2 0xf4c6
  2888. #define F367CAB_ON_ID_L 0xf4c600ff
  2889. /* TS_ON_ID_3 */
  2890. #define R367CAB_TS_ON_ID_3 0xf4c7
  2891. #define F367CAB_ON_ID_H 0xf4c700ff
  2892. /* RE_STATUS_0 */
  2893. #define R367CAB_RE_STATUS_0 0xf4c8
  2894. #define F367CAB_RECEIVE_STATUS_L 0xf4c800ff
  2895. /* RE_STATUS_1 */
  2896. #define R367CAB_RE_STATUS_1 0xf4c9
  2897. #define F367CAB_RECEIVE_STATUS_LH 0xf4c900ff
  2898. /* RE_STATUS_2 */
  2899. #define R367CAB_RE_STATUS_2 0xf4ca
  2900. #define F367CAB_RECEIVE_STATUS_HL 0xf4ca00ff
  2901. /* RE_STATUS_3 */
  2902. #define R367CAB_RE_STATUS_3 0xf4cb
  2903. #define F367CAB_RECEIVE_STATUS_HH 0xf4cb003f
  2904. /* TS_STATUS_0 */
  2905. #define R367CAB_TS_STATUS_0 0xf4cc
  2906. #define F367CAB_TS_STATUS_L 0xf4cc00ff
  2907. /* TS_STATUS_1 */
  2908. #define R367CAB_TS_STATUS_1 0xf4cd
  2909. #define F367CAB_TS_STATUS_H 0xf4cd007f
  2910. /* TS_STATUS_2 */
  2911. #define R367CAB_TS_STATUS_2 0xf4ce
  2912. #define F367CAB_ERROR 0xf4ce0080
  2913. #define F367CAB_EMERGENCY 0xf4ce0040
  2914. #define F367CAB_CRE_TS 0xf4ce0030
  2915. #define F367CAB_VER 0xf4ce000e
  2916. #define F367CAB_M_LOCK 0xf4ce0001
  2917. /* TS_STATUS_3 */
  2918. #define R367CAB_TS_STATUS_3 0xf4cf
  2919. #define F367CAB_UPDATE_READY 0xf4cf0080
  2920. #define F367CAB_END_FRAME_HEADER 0xf4cf0040
  2921. #define F367CAB_CONTCNT 0xf4cf0020
  2922. #define F367CAB_TS_IDENTIFIER_SEL 0xf4cf000f
  2923. /* T_O_ID_0 */
  2924. #define R367CAB_T_O_ID_0 0xf4d0
  2925. #define F367CAB_ON_ID_I_L 0xf4d000ff
  2926. /* T_O_ID_1 */
  2927. #define R367CAB_T_O_ID_1 0xf4d1
  2928. #define F367CAB_ON_ID_I_H 0xf4d100ff
  2929. /* T_O_ID_2 */
  2930. #define R367CAB_T_O_ID_2 0xf4d2
  2931. #define F367CAB_TS_ID_I_L 0xf4d200ff
  2932. /* T_O_ID_3 */
  2933. #define R367CAB_T_O_ID_3 0xf4d3
  2934. #define F367CAB_TS_ID_I_H 0xf4d300ff
  2935. #endif