horus3a.c 9.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * horus3a.h
  4. *
  5. * Sony Horus3A DVB-S/S2 tuner driver
  6. *
  7. * Copyright 2012 Sony Corporation
  8. * Copyright (C) 2014 NetUP Inc.
  9. * Copyright (C) 2014 Sergey Kozlov <serjk@netup.ru>
  10. * Copyright (C) 2014 Abylay Ospan <aospan@netup.ru>
  11. */
  12. #include <linux/slab.h>
  13. #include <linux/module.h>
  14. #include <linux/dvb/frontend.h>
  15. #include <linux/types.h>
  16. #include "horus3a.h"
  17. #include <media/dvb_frontend.h>
  18. #define MAX_WRITE_REGSIZE 5
  19. enum horus3a_state {
  20. STATE_UNKNOWN,
  21. STATE_SLEEP,
  22. STATE_ACTIVE
  23. };
  24. struct horus3a_priv {
  25. u32 frequency;
  26. u8 i2c_address;
  27. struct i2c_adapter *i2c;
  28. enum horus3a_state state;
  29. void *set_tuner_data;
  30. int (*set_tuner)(void *, int);
  31. };
  32. static void horus3a_i2c_debug(struct horus3a_priv *priv,
  33. u8 reg, u8 write, const u8 *data, u32 len)
  34. {
  35. dev_dbg(&priv->i2c->dev, "horus3a: I2C %s reg 0x%02x size %d\n",
  36. (write == 0 ? "read" : "write"), reg, len);
  37. print_hex_dump_bytes("horus3a: I2C data: ",
  38. DUMP_PREFIX_OFFSET, data, len);
  39. }
  40. static int horus3a_write_regs(struct horus3a_priv *priv,
  41. u8 reg, const u8 *data, u32 len)
  42. {
  43. int ret;
  44. u8 buf[MAX_WRITE_REGSIZE + 1];
  45. struct i2c_msg msg[1] = {
  46. {
  47. .addr = priv->i2c_address,
  48. .flags = 0,
  49. .len = len + 1,
  50. .buf = buf,
  51. }
  52. };
  53. if (len + 1 > sizeof(buf)) {
  54. dev_warn(&priv->i2c->dev,"wr reg=%04x: len=%d is too big!\n",
  55. reg, len + 1);
  56. return -E2BIG;
  57. }
  58. horus3a_i2c_debug(priv, reg, 1, data, len);
  59. buf[0] = reg;
  60. memcpy(&buf[1], data, len);
  61. ret = i2c_transfer(priv->i2c, msg, 1);
  62. if (ret >= 0 && ret != 1)
  63. ret = -EREMOTEIO;
  64. if (ret < 0) {
  65. dev_warn(&priv->i2c->dev,
  66. "%s: i2c wr failed=%d reg=%02x len=%d\n",
  67. KBUILD_MODNAME, ret, reg, len);
  68. return ret;
  69. }
  70. return 0;
  71. }
  72. static int horus3a_write_reg(struct horus3a_priv *priv, u8 reg, u8 val)
  73. {
  74. u8 tmp = val; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
  75. return horus3a_write_regs(priv, reg, &tmp, 1);
  76. }
  77. static int horus3a_enter_power_save(struct horus3a_priv *priv)
  78. {
  79. u8 data[2];
  80. dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
  81. if (priv->state == STATE_SLEEP)
  82. return 0;
  83. /* IQ Generator disable */
  84. horus3a_write_reg(priv, 0x2a, 0x79);
  85. /* MDIV_EN = 0 */
  86. horus3a_write_reg(priv, 0x29, 0x70);
  87. /* VCO disable preparation */
  88. horus3a_write_reg(priv, 0x28, 0x3e);
  89. /* VCO buffer disable */
  90. horus3a_write_reg(priv, 0x2a, 0x19);
  91. /* VCO calibration disable */
  92. horus3a_write_reg(priv, 0x1c, 0x00);
  93. /* Power save setting (xtal is not stopped) */
  94. data[0] = 0xC0;
  95. /* LNA is Disabled */
  96. data[1] = 0xA7;
  97. /* 0x11 - 0x12 */
  98. horus3a_write_regs(priv, 0x11, data, sizeof(data));
  99. priv->state = STATE_SLEEP;
  100. return 0;
  101. }
  102. static int horus3a_leave_power_save(struct horus3a_priv *priv)
  103. {
  104. u8 data[2];
  105. dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
  106. if (priv->state == STATE_ACTIVE)
  107. return 0;
  108. /* Leave power save */
  109. data[0] = 0x00;
  110. /* LNA is Disabled */
  111. data[1] = 0xa7;
  112. /* 0x11 - 0x12 */
  113. horus3a_write_regs(priv, 0x11, data, sizeof(data));
  114. /* VCO buffer enable */
  115. horus3a_write_reg(priv, 0x2a, 0x79);
  116. /* VCO calibration enable */
  117. horus3a_write_reg(priv, 0x1c, 0xc0);
  118. /* MDIV_EN = 1 */
  119. horus3a_write_reg(priv, 0x29, 0x71);
  120. usleep_range(5000, 7000);
  121. priv->state = STATE_ACTIVE;
  122. return 0;
  123. }
  124. static int horus3a_init(struct dvb_frontend *fe)
  125. {
  126. struct horus3a_priv *priv = fe->tuner_priv;
  127. dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
  128. return 0;
  129. }
  130. static void horus3a_release(struct dvb_frontend *fe)
  131. {
  132. struct horus3a_priv *priv = fe->tuner_priv;
  133. dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
  134. kfree(fe->tuner_priv);
  135. fe->tuner_priv = NULL;
  136. }
  137. static int horus3a_sleep(struct dvb_frontend *fe)
  138. {
  139. struct horus3a_priv *priv = fe->tuner_priv;
  140. dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
  141. horus3a_enter_power_save(priv);
  142. return 0;
  143. }
  144. static int horus3a_set_params(struct dvb_frontend *fe)
  145. {
  146. struct dtv_frontend_properties *p = &fe->dtv_property_cache;
  147. struct horus3a_priv *priv = fe->tuner_priv;
  148. u32 frequency = p->frequency;
  149. u32 symbol_rate = p->symbol_rate/1000;
  150. u8 mixdiv = 0;
  151. u8 mdiv = 0;
  152. u32 ms = 0;
  153. u8 f_ctl = 0;
  154. u8 g_ctl = 0;
  155. u8 fc_lpf = 0;
  156. u8 data[5];
  157. dev_dbg(&priv->i2c->dev, "%s(): frequency %dkHz symbol_rate %dksps\n",
  158. __func__, frequency, symbol_rate);
  159. if (priv->set_tuner)
  160. priv->set_tuner(priv->set_tuner_data, 0);
  161. if (priv->state == STATE_SLEEP)
  162. horus3a_leave_power_save(priv);
  163. /* frequency should be X MHz (X : integer) */
  164. frequency = DIV_ROUND_CLOSEST(frequency, 1000) * 1000;
  165. if (frequency <= 1155000) {
  166. mixdiv = 4;
  167. mdiv = 1;
  168. } else {
  169. mixdiv = 2;
  170. mdiv = 0;
  171. }
  172. /* Assumed that fREF == 1MHz (1000kHz) */
  173. ms = DIV_ROUND_CLOSEST((frequency * mixdiv) / 2, 1000);
  174. if (ms > 0x7FFF) { /* 15 bit */
  175. dev_err(&priv->i2c->dev, "horus3a: invalid frequency %d\n",
  176. frequency);
  177. return -EINVAL;
  178. }
  179. if (frequency < 975000) {
  180. /* F_CTL=11100 G_CTL=001 */
  181. f_ctl = 0x1C;
  182. g_ctl = 0x01;
  183. } else if (frequency < 1050000) {
  184. /* F_CTL=11000 G_CTL=010 */
  185. f_ctl = 0x18;
  186. g_ctl = 0x02;
  187. } else if (frequency < 1150000) {
  188. /* F_CTL=10100 G_CTL=010 */
  189. f_ctl = 0x14;
  190. g_ctl = 0x02;
  191. } else if (frequency < 1250000) {
  192. /* F_CTL=10000 G_CTL=011 */
  193. f_ctl = 0x10;
  194. g_ctl = 0x03;
  195. } else if (frequency < 1350000) {
  196. /* F_CTL=01100 G_CTL=100 */
  197. f_ctl = 0x0C;
  198. g_ctl = 0x04;
  199. } else if (frequency < 1450000) {
  200. /* F_CTL=01010 G_CTL=100 */
  201. f_ctl = 0x0A;
  202. g_ctl = 0x04;
  203. } else if (frequency < 1600000) {
  204. /* F_CTL=00111 G_CTL=101 */
  205. f_ctl = 0x07;
  206. g_ctl = 0x05;
  207. } else if (frequency < 1800000) {
  208. /* F_CTL=00100 G_CTL=010 */
  209. f_ctl = 0x04;
  210. g_ctl = 0x02;
  211. } else if (frequency < 2000000) {
  212. /* F_CTL=00010 G_CTL=001 */
  213. f_ctl = 0x02;
  214. g_ctl = 0x01;
  215. } else {
  216. /* F_CTL=00000 G_CTL=000 */
  217. f_ctl = 0x00;
  218. g_ctl = 0x00;
  219. }
  220. /* LPF cutoff frequency setting */
  221. if (p->delivery_system == SYS_DVBS) {
  222. /*
  223. * rolloff = 0.35
  224. * SR <= 4.3
  225. * fc_lpf = 5
  226. * 4.3 < SR <= 10
  227. * fc_lpf = SR * (1 + rolloff) / 2 + SR / 2 =
  228. * SR * 1.175 = SR * (47/40)
  229. * 10 < SR
  230. * fc_lpf = SR * (1 + rolloff) / 2 + 5 =
  231. * SR * 0.675 + 5 = SR * (27/40) + 5
  232. * NOTE: The result should be round up.
  233. */
  234. if (symbol_rate <= 4300)
  235. fc_lpf = 5;
  236. else if (symbol_rate <= 10000)
  237. fc_lpf = (u8)DIV_ROUND_UP(symbol_rate * 47, 40000);
  238. else
  239. fc_lpf = (u8)DIV_ROUND_UP(symbol_rate * 27, 40000) + 5;
  240. /* 5 <= fc_lpf <= 36 */
  241. if (fc_lpf > 36)
  242. fc_lpf = 36;
  243. } else if (p->delivery_system == SYS_DVBS2) {
  244. /*
  245. * SR <= 4.5:
  246. * fc_lpf = 5
  247. * 4.5 < SR <= 10:
  248. * fc_lpf = SR * (1 + rolloff) / 2 + SR / 2
  249. * 10 < SR:
  250. * fc_lpf = SR * (1 + rolloff) / 2 + 5
  251. * NOTE: The result should be round up.
  252. */
  253. if (symbol_rate <= 4500)
  254. fc_lpf = 5;
  255. else if (symbol_rate <= 10000)
  256. fc_lpf = (u8)((symbol_rate * 11 + (10000-1)) / 10000);
  257. else
  258. fc_lpf = (u8)((symbol_rate * 3 + (5000-1)) / 5000 + 5);
  259. /* 5 <= fc_lpf <= 36 is valid */
  260. if (fc_lpf > 36)
  261. fc_lpf = 36;
  262. } else {
  263. dev_err(&priv->i2c->dev,
  264. "horus3a: invalid delivery system %d\n",
  265. p->delivery_system);
  266. return -EINVAL;
  267. }
  268. /* 0x00 - 0x04 */
  269. data[0] = (u8)((ms >> 7) & 0xFF);
  270. data[1] = (u8)((ms << 1) & 0xFF);
  271. data[2] = 0x00;
  272. data[3] = 0x00;
  273. data[4] = (u8)(mdiv << 7);
  274. horus3a_write_regs(priv, 0x00, data, sizeof(data));
  275. /* Write G_CTL, F_CTL */
  276. horus3a_write_reg(priv, 0x09, (u8)((g_ctl << 5) | f_ctl));
  277. /* Write LPF cutoff frequency */
  278. horus3a_write_reg(priv, 0x37, (u8)(0x80 | (fc_lpf << 1)));
  279. /* Start Calibration */
  280. horus3a_write_reg(priv, 0x05, 0x80);
  281. /* IQ Generator enable */
  282. horus3a_write_reg(priv, 0x2a, 0x7b);
  283. /* tuner stabilization time */
  284. msleep(60);
  285. /* Store tuned frequency to the struct */
  286. priv->frequency = ms * 2 * 1000 / mixdiv;
  287. return 0;
  288. }
  289. static int horus3a_get_frequency(struct dvb_frontend *fe, u32 *frequency)
  290. {
  291. struct horus3a_priv *priv = fe->tuner_priv;
  292. *frequency = priv->frequency;
  293. return 0;
  294. }
  295. static const struct dvb_tuner_ops horus3a_tuner_ops = {
  296. .info = {
  297. .name = "Sony Horus3a",
  298. .frequency_min_hz = 950 * MHz,
  299. .frequency_max_hz = 2150 * MHz,
  300. .frequency_step_hz = 1 * MHz,
  301. },
  302. .init = horus3a_init,
  303. .release = horus3a_release,
  304. .sleep = horus3a_sleep,
  305. .set_params = horus3a_set_params,
  306. .get_frequency = horus3a_get_frequency,
  307. };
  308. struct dvb_frontend *horus3a_attach(struct dvb_frontend *fe,
  309. const struct horus3a_config *config,
  310. struct i2c_adapter *i2c)
  311. {
  312. u8 buf[3], val;
  313. struct horus3a_priv *priv = NULL;
  314. priv = kzalloc(sizeof(struct horus3a_priv), GFP_KERNEL);
  315. if (priv == NULL)
  316. return NULL;
  317. priv->i2c_address = (config->i2c_address >> 1);
  318. priv->i2c = i2c;
  319. priv->set_tuner_data = config->set_tuner_priv;
  320. priv->set_tuner = config->set_tuner_callback;
  321. if (fe->ops.i2c_gate_ctrl)
  322. fe->ops.i2c_gate_ctrl(fe, 1);
  323. /* wait 4ms after power on */
  324. usleep_range(4000, 6000);
  325. /* IQ Generator disable */
  326. horus3a_write_reg(priv, 0x2a, 0x79);
  327. /* REF_R = Xtal Frequency */
  328. buf[0] = config->xtal_freq_mhz;
  329. buf[1] = config->xtal_freq_mhz;
  330. buf[2] = 0;
  331. /* 0x6 - 0x8 */
  332. horus3a_write_regs(priv, 0x6, buf, 3);
  333. /* IQ Out = Single Ended */
  334. horus3a_write_reg(priv, 0x0a, 0x40);
  335. switch (config->xtal_freq_mhz) {
  336. case 27:
  337. val = 0x1f;
  338. break;
  339. case 24:
  340. val = 0x10;
  341. break;
  342. case 16:
  343. val = 0xc;
  344. break;
  345. default:
  346. val = 0;
  347. dev_warn(&priv->i2c->dev,
  348. "horus3a: invalid xtal frequency %dMHz\n",
  349. config->xtal_freq_mhz);
  350. break;
  351. }
  352. val <<= 2;
  353. horus3a_write_reg(priv, 0x0e, val);
  354. horus3a_enter_power_save(priv);
  355. usleep_range(3000, 5000);
  356. if (fe->ops.i2c_gate_ctrl)
  357. fe->ops.i2c_gate_ctrl(fe, 0);
  358. memcpy(&fe->ops.tuner_ops, &horus3a_tuner_ops,
  359. sizeof(struct dvb_tuner_ops));
  360. fe->tuner_priv = priv;
  361. dev_info(&priv->i2c->dev,
  362. "Sony HORUS3A attached on addr=%x at I2C adapter %p\n",
  363. priv->i2c_address, priv->i2c);
  364. return fe;
  365. }
  366. EXPORT_SYMBOL(horus3a_attach);
  367. MODULE_DESCRIPTION("Sony HORUS3A satellite tuner driver");
  368. MODULE_AUTHOR("Sergey Kozlov <serjk@netup.ru>");
  369. MODULE_LICENSE("GPL");