dib7000m.c 41 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Linux-DVB Driver for DiBcom's DiB7000M and
  4. * first generation DiB7000P-demodulator-family.
  5. *
  6. * Copyright (C) 2005-7 DiBcom (http://www.dibcom.fr/)
  7. */
  8. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  9. #include <linux/kernel.h>
  10. #include <linux/slab.h>
  11. #include <linux/i2c.h>
  12. #include <linux/mutex.h>
  13. #include <media/dvb_frontend.h>
  14. #include "dib7000m.h"
  15. static int debug;
  16. module_param(debug, int, 0644);
  17. MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
  18. #define dprintk(fmt, arg...) do { \
  19. if (debug) \
  20. printk(KERN_DEBUG pr_fmt("%s: " fmt), \
  21. __func__, ##arg); \
  22. } while (0)
  23. struct dib7000m_state {
  24. struct dvb_frontend demod;
  25. struct dib7000m_config cfg;
  26. u8 i2c_addr;
  27. struct i2c_adapter *i2c_adap;
  28. struct dibx000_i2c_master i2c_master;
  29. /* offset is 1 in case of the 7000MC */
  30. u8 reg_offs;
  31. u16 wbd_ref;
  32. u8 current_band;
  33. u32 current_bandwidth;
  34. struct dibx000_agc_config *current_agc;
  35. u32 timf;
  36. u32 timf_default;
  37. u32 internal_clk;
  38. u8 div_force_off : 1;
  39. u8 div_state : 1;
  40. u16 div_sync_wait;
  41. u16 revision;
  42. u8 agc_state;
  43. /* for the I2C transfer */
  44. struct i2c_msg msg[2];
  45. u8 i2c_write_buffer[4];
  46. u8 i2c_read_buffer[2];
  47. struct mutex i2c_buffer_lock;
  48. };
  49. enum dib7000m_power_mode {
  50. DIB7000M_POWER_ALL = 0,
  51. DIB7000M_POWER_NO,
  52. DIB7000M_POWER_INTERF_ANALOG_AGC,
  53. DIB7000M_POWER_COR4_DINTLV_ICIRM_EQUAL_CFROD,
  54. DIB7000M_POWER_COR4_CRY_ESRAM_MOUT_NUD,
  55. DIB7000M_POWER_INTERFACE_ONLY,
  56. };
  57. static u16 dib7000m_read_word(struct dib7000m_state *state, u16 reg)
  58. {
  59. u16 ret;
  60. if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
  61. dprintk("could not acquire lock\n");
  62. return 0;
  63. }
  64. state->i2c_write_buffer[0] = (reg >> 8) | 0x80;
  65. state->i2c_write_buffer[1] = reg & 0xff;
  66. memset(state->msg, 0, 2 * sizeof(struct i2c_msg));
  67. state->msg[0].addr = state->i2c_addr >> 1;
  68. state->msg[0].flags = 0;
  69. state->msg[0].buf = state->i2c_write_buffer;
  70. state->msg[0].len = 2;
  71. state->msg[1].addr = state->i2c_addr >> 1;
  72. state->msg[1].flags = I2C_M_RD;
  73. state->msg[1].buf = state->i2c_read_buffer;
  74. state->msg[1].len = 2;
  75. if (i2c_transfer(state->i2c_adap, state->msg, 2) != 2)
  76. dprintk("i2c read error on %d\n", reg);
  77. ret = (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1];
  78. mutex_unlock(&state->i2c_buffer_lock);
  79. return ret;
  80. }
  81. static int dib7000m_write_word(struct dib7000m_state *state, u16 reg, u16 val)
  82. {
  83. int ret;
  84. if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
  85. dprintk("could not acquire lock\n");
  86. return -EINVAL;
  87. }
  88. state->i2c_write_buffer[0] = (reg >> 8) & 0xff;
  89. state->i2c_write_buffer[1] = reg & 0xff;
  90. state->i2c_write_buffer[2] = (val >> 8) & 0xff;
  91. state->i2c_write_buffer[3] = val & 0xff;
  92. memset(&state->msg[0], 0, sizeof(struct i2c_msg));
  93. state->msg[0].addr = state->i2c_addr >> 1;
  94. state->msg[0].flags = 0;
  95. state->msg[0].buf = state->i2c_write_buffer;
  96. state->msg[0].len = 4;
  97. ret = (i2c_transfer(state->i2c_adap, state->msg, 1) != 1 ?
  98. -EREMOTEIO : 0);
  99. mutex_unlock(&state->i2c_buffer_lock);
  100. return ret;
  101. }
  102. static void dib7000m_write_tab(struct dib7000m_state *state, u16 *buf)
  103. {
  104. u16 l = 0, r, *n;
  105. n = buf;
  106. l = *n++;
  107. while (l) {
  108. r = *n++;
  109. if (state->reg_offs && (r >= 112 && r <= 331)) // compensate for 7000MC
  110. r++;
  111. do {
  112. dib7000m_write_word(state, r, *n++);
  113. r++;
  114. } while (--l);
  115. l = *n++;
  116. }
  117. }
  118. static int dib7000m_set_output_mode(struct dib7000m_state *state, int mode)
  119. {
  120. int ret = 0;
  121. u16 outreg, fifo_threshold, smo_mode,
  122. sram = 0x0005; /* by default SRAM output is disabled */
  123. outreg = 0;
  124. fifo_threshold = 1792;
  125. smo_mode = (dib7000m_read_word(state, 294 + state->reg_offs) & 0x0010) | (1 << 1);
  126. dprintk("setting output mode for demod %p to %d\n", &state->demod, mode);
  127. switch (mode) {
  128. case OUTMODE_MPEG2_PAR_GATED_CLK: // STBs with parallel gated clock
  129. outreg = (1 << 10); /* 0x0400 */
  130. break;
  131. case OUTMODE_MPEG2_PAR_CONT_CLK: // STBs with parallel continues clock
  132. outreg = (1 << 10) | (1 << 6); /* 0x0440 */
  133. break;
  134. case OUTMODE_MPEG2_SERIAL: // STBs with serial input
  135. outreg = (1 << 10) | (2 << 6) | (0 << 1); /* 0x0482 */
  136. break;
  137. case OUTMODE_DIVERSITY:
  138. if (state->cfg.hostbus_diversity)
  139. outreg = (1 << 10) | (4 << 6); /* 0x0500 */
  140. else
  141. sram |= 0x0c00;
  142. break;
  143. case OUTMODE_MPEG2_FIFO: // e.g. USB feeding
  144. smo_mode |= (3 << 1);
  145. fifo_threshold = 512;
  146. outreg = (1 << 10) | (5 << 6);
  147. break;
  148. case OUTMODE_HIGH_Z: // disable
  149. outreg = 0;
  150. break;
  151. default:
  152. dprintk("Unhandled output_mode passed to be set for demod %p\n", &state->demod);
  153. break;
  154. }
  155. if (state->cfg.output_mpeg2_in_188_bytes)
  156. smo_mode |= (1 << 5) ;
  157. ret |= dib7000m_write_word(state, 294 + state->reg_offs, smo_mode);
  158. ret |= dib7000m_write_word(state, 295 + state->reg_offs, fifo_threshold); /* synchronous fread */
  159. ret |= dib7000m_write_word(state, 1795, outreg);
  160. ret |= dib7000m_write_word(state, 1805, sram);
  161. if (state->revision == 0x4003) {
  162. u16 clk_cfg1 = dib7000m_read_word(state, 909) & 0xfffd;
  163. if (mode == OUTMODE_DIVERSITY)
  164. clk_cfg1 |= (1 << 1); // P_O_CLK_en
  165. dib7000m_write_word(state, 909, clk_cfg1);
  166. }
  167. return ret;
  168. }
  169. static void dib7000m_set_power_mode(struct dib7000m_state *state, enum dib7000m_power_mode mode)
  170. {
  171. /* by default everything is going to be powered off */
  172. u16 reg_903 = 0xffff, reg_904 = 0xffff, reg_905 = 0xffff, reg_906 = 0x3fff;
  173. u8 offset = 0;
  174. /* now, depending on the requested mode, we power on */
  175. switch (mode) {
  176. /* power up everything in the demod */
  177. case DIB7000M_POWER_ALL:
  178. reg_903 = 0x0000; reg_904 = 0x0000; reg_905 = 0x0000; reg_906 = 0x0000;
  179. break;
  180. /* just leave power on the control-interfaces: GPIO and (I2C or SDIO or SRAM) */
  181. case DIB7000M_POWER_INTERFACE_ONLY: /* TODO power up either SDIO or I2C or SRAM */
  182. reg_905 &= ~((1 << 7) | (1 << 6) | (1 << 5) | (1 << 2));
  183. break;
  184. case DIB7000M_POWER_INTERF_ANALOG_AGC:
  185. reg_903 &= ~((1 << 15) | (1 << 14) | (1 << 11) | (1 << 10));
  186. reg_905 &= ~((1 << 7) | (1 << 6) | (1 << 5) | (1 << 4) | (1 << 2));
  187. reg_906 &= ~((1 << 0));
  188. break;
  189. case DIB7000M_POWER_COR4_DINTLV_ICIRM_EQUAL_CFROD:
  190. reg_903 = 0x0000; reg_904 = 0x801f; reg_905 = 0x0000; reg_906 = 0x0000;
  191. break;
  192. case DIB7000M_POWER_COR4_CRY_ESRAM_MOUT_NUD:
  193. reg_903 = 0x0000; reg_904 = 0x8000; reg_905 = 0x010b; reg_906 = 0x0000;
  194. break;
  195. case DIB7000M_POWER_NO:
  196. break;
  197. }
  198. /* always power down unused parts */
  199. if (!state->cfg.mobile_mode)
  200. reg_904 |= (1 << 7) | (1 << 6) | (1 << 4) | (1 << 2) | (1 << 1);
  201. /* P_sdio_select_clk = 0 on MC and after*/
  202. if (state->revision != 0x4000)
  203. reg_906 <<= 1;
  204. if (state->revision == 0x4003)
  205. offset = 1;
  206. dib7000m_write_word(state, 903 + offset, reg_903);
  207. dib7000m_write_word(state, 904 + offset, reg_904);
  208. dib7000m_write_word(state, 905 + offset, reg_905);
  209. dib7000m_write_word(state, 906 + offset, reg_906);
  210. }
  211. static int dib7000m_set_adc_state(struct dib7000m_state *state, enum dibx000_adc_states no)
  212. {
  213. int ret = 0;
  214. u16 reg_913 = dib7000m_read_word(state, 913),
  215. reg_914 = dib7000m_read_word(state, 914);
  216. switch (no) {
  217. case DIBX000_SLOW_ADC_ON:
  218. reg_914 |= (1 << 1) | (1 << 0);
  219. ret |= dib7000m_write_word(state, 914, reg_914);
  220. reg_914 &= ~(1 << 1);
  221. break;
  222. case DIBX000_SLOW_ADC_OFF:
  223. reg_914 |= (1 << 1) | (1 << 0);
  224. break;
  225. case DIBX000_ADC_ON:
  226. if (state->revision == 0x4000) { // workaround for PA/MA
  227. // power-up ADC
  228. dib7000m_write_word(state, 913, 0);
  229. dib7000m_write_word(state, 914, reg_914 & 0x3);
  230. // power-down bandgag
  231. dib7000m_write_word(state, 913, (1 << 15));
  232. dib7000m_write_word(state, 914, reg_914 & 0x3);
  233. }
  234. reg_913 &= 0x0fff;
  235. reg_914 &= 0x0003;
  236. break;
  237. case DIBX000_ADC_OFF: // leave the VBG voltage on
  238. reg_913 |= (1 << 14) | (1 << 13) | (1 << 12);
  239. reg_914 |= (1 << 5) | (1 << 4) | (1 << 3) | (1 << 2);
  240. break;
  241. case DIBX000_VBG_ENABLE:
  242. reg_913 &= ~(1 << 15);
  243. break;
  244. case DIBX000_VBG_DISABLE:
  245. reg_913 |= (1 << 15);
  246. break;
  247. default:
  248. break;
  249. }
  250. // dprintk("913: %x, 914: %x\n", reg_913, reg_914);
  251. ret |= dib7000m_write_word(state, 913, reg_913);
  252. ret |= dib7000m_write_word(state, 914, reg_914);
  253. return ret;
  254. }
  255. static int dib7000m_set_bandwidth(struct dib7000m_state *state, u32 bw)
  256. {
  257. u32 timf;
  258. if (!bw)
  259. bw = 8000;
  260. // store the current bandwidth for later use
  261. state->current_bandwidth = bw;
  262. if (state->timf == 0) {
  263. dprintk("using default timf\n");
  264. timf = state->timf_default;
  265. } else {
  266. dprintk("using updated timf\n");
  267. timf = state->timf;
  268. }
  269. timf = timf * (bw / 50) / 160;
  270. dib7000m_write_word(state, 23, (u16) ((timf >> 16) & 0xffff));
  271. dib7000m_write_word(state, 24, (u16) ((timf ) & 0xffff));
  272. return 0;
  273. }
  274. static int dib7000m_set_diversity_in(struct dvb_frontend *demod, int onoff)
  275. {
  276. struct dib7000m_state *state = demod->demodulator_priv;
  277. if (state->div_force_off) {
  278. dprintk("diversity combination deactivated - forced by COFDM parameters\n");
  279. onoff = 0;
  280. }
  281. state->div_state = (u8)onoff;
  282. if (onoff) {
  283. dib7000m_write_word(state, 263 + state->reg_offs, 6);
  284. dib7000m_write_word(state, 264 + state->reg_offs, 6);
  285. dib7000m_write_word(state, 266 + state->reg_offs, (state->div_sync_wait << 4) | (1 << 2) | (2 << 0));
  286. } else {
  287. dib7000m_write_word(state, 263 + state->reg_offs, 1);
  288. dib7000m_write_word(state, 264 + state->reg_offs, 0);
  289. dib7000m_write_word(state, 266 + state->reg_offs, 0);
  290. }
  291. return 0;
  292. }
  293. static int dib7000m_sad_calib(struct dib7000m_state *state)
  294. {
  295. /* internal */
  296. // dib7000m_write_word(state, 928, (3 << 14) | (1 << 12) | (524 << 0)); // sampling clock of the SAD is writing in set_bandwidth
  297. dib7000m_write_word(state, 929, (0 << 1) | (0 << 0));
  298. dib7000m_write_word(state, 930, 776); // 0.625*3.3 / 4096
  299. /* do the calibration */
  300. dib7000m_write_word(state, 929, (1 << 0));
  301. dib7000m_write_word(state, 929, (0 << 0));
  302. msleep(1);
  303. return 0;
  304. }
  305. static void dib7000m_reset_pll_common(struct dib7000m_state *state, const struct dibx000_bandwidth_config *bw)
  306. {
  307. dib7000m_write_word(state, 18, (u16) (((bw->internal*1000) >> 16) & 0xffff));
  308. dib7000m_write_word(state, 19, (u16) ( (bw->internal*1000) & 0xffff));
  309. dib7000m_write_word(state, 21, (u16) ( (bw->ifreq >> 16) & 0xffff));
  310. dib7000m_write_word(state, 22, (u16) ( bw->ifreq & 0xffff));
  311. dib7000m_write_word(state, 928, bw->sad_cfg);
  312. }
  313. static void dib7000m_reset_pll(struct dib7000m_state *state)
  314. {
  315. const struct dibx000_bandwidth_config *bw = state->cfg.bw;
  316. u16 reg_907,reg_910;
  317. /* default */
  318. reg_907 = (bw->pll_bypass << 15) | (bw->modulo << 7) |
  319. (bw->ADClkSrc << 6) | (bw->IO_CLK_en_core << 5) | (bw->bypclk_div << 2) |
  320. (bw->enable_refdiv << 1) | (0 << 0);
  321. reg_910 = (((bw->pll_ratio >> 6) & 0x3) << 3) | (bw->pll_range << 1) | bw->pll_reset;
  322. // for this oscillator frequency should be 30 MHz for the Master (default values in the board_parameters give that value)
  323. // this is only working only for 30 MHz crystals
  324. if (!state->cfg.quartz_direct) {
  325. reg_910 |= (1 << 5); // forcing the predivider to 1
  326. // if the previous front-end is baseband, its output frequency is 15 MHz (prev freq divided by 2)
  327. if(state->cfg.input_clk_is_div_2)
  328. reg_907 |= (16 << 9);
  329. else // otherwise the previous front-end puts out its input (default 30MHz) - no extra division necessary
  330. reg_907 |= (8 << 9);
  331. } else {
  332. reg_907 |= (bw->pll_ratio & 0x3f) << 9;
  333. reg_910 |= (bw->pll_prediv << 5);
  334. }
  335. dib7000m_write_word(state, 910, reg_910); // pll cfg
  336. dib7000m_write_word(state, 907, reg_907); // clk cfg0
  337. dib7000m_write_word(state, 908, 0x0006); // clk_cfg1
  338. dib7000m_reset_pll_common(state, bw);
  339. }
  340. static void dib7000mc_reset_pll(struct dib7000m_state *state)
  341. {
  342. const struct dibx000_bandwidth_config *bw = state->cfg.bw;
  343. u16 clk_cfg1;
  344. // clk_cfg0
  345. dib7000m_write_word(state, 907, (bw->pll_prediv << 8) | (bw->pll_ratio << 0));
  346. // clk_cfg1
  347. //dib7000m_write_word(state, 908, (1 << 14) | (3 << 12) |(0 << 11) |
  348. clk_cfg1 = (0 << 14) | (3 << 12) |(0 << 11) |
  349. (bw->IO_CLK_en_core << 10) | (bw->bypclk_div << 5) | (bw->enable_refdiv << 4) |
  350. (1 << 3) | (bw->pll_range << 1) | (bw->pll_reset << 0);
  351. dib7000m_write_word(state, 908, clk_cfg1);
  352. clk_cfg1 = (clk_cfg1 & 0xfff7) | (bw->pll_bypass << 3);
  353. dib7000m_write_word(state, 908, clk_cfg1);
  354. // smpl_cfg
  355. dib7000m_write_word(state, 910, (1 << 12) | (2 << 10) | (bw->modulo << 8) | (bw->ADClkSrc << 7));
  356. dib7000m_reset_pll_common(state, bw);
  357. }
  358. static int dib7000m_reset_gpio(struct dib7000m_state *st)
  359. {
  360. /* reset the GPIOs */
  361. dib7000m_write_word(st, 773, st->cfg.gpio_dir);
  362. dib7000m_write_word(st, 774, st->cfg.gpio_val);
  363. /* TODO 782 is P_gpio_od */
  364. dib7000m_write_word(st, 775, st->cfg.gpio_pwm_pos);
  365. dib7000m_write_word(st, 780, st->cfg.pwm_freq_div);
  366. return 0;
  367. }
  368. static u16 dib7000m_defaults_common[] =
  369. {
  370. // auto search configuration
  371. 3, 2,
  372. 0x0004,
  373. 0x1000,
  374. 0x0814,
  375. 12, 6,
  376. 0x001b,
  377. 0x7740,
  378. 0x005b,
  379. 0x8d80,
  380. 0x01c9,
  381. 0xc380,
  382. 0x0000,
  383. 0x0080,
  384. 0x0000,
  385. 0x0090,
  386. 0x0001,
  387. 0xd4c0,
  388. 1, 26,
  389. 0x6680, // P_corm_thres Lock algorithms configuration
  390. 1, 170,
  391. 0x0410, // P_palf_alpha_regul, P_palf_filter_freeze, P_palf_filter_on
  392. 8, 173,
  393. 0,
  394. 0,
  395. 0,
  396. 0,
  397. 0,
  398. 0,
  399. 0,
  400. 0,
  401. 1, 182,
  402. 8192, // P_fft_nb_to_cut
  403. 2, 195,
  404. 0x0ccd, // P_pha3_thres
  405. 0, // P_cti_use_cpe, P_cti_use_prog
  406. 1, 205,
  407. 0x200f, // P_cspu_regul, P_cspu_win_cut
  408. 5, 214,
  409. 0x023d, // P_adp_regul_cnt
  410. 0x00a4, // P_adp_noise_cnt
  411. 0x00a4, // P_adp_regul_ext
  412. 0x7ff0, // P_adp_noise_ext
  413. 0x3ccc, // P_adp_fil
  414. 1, 226,
  415. 0, // P_2d_byp_ti_num
  416. 1, 255,
  417. 0x800, // P_equal_thres_wgn
  418. 1, 263,
  419. 0x0001,
  420. 1, 281,
  421. 0x0010, // P_fec_*
  422. 1, 294,
  423. 0x0062, // P_smo_mode, P_smo_rs_discard, P_smo_fifo_flush, P_smo_pid_parse, P_smo_error_discard
  424. 0
  425. };
  426. static u16 dib7000m_defaults[] =
  427. {
  428. /* set ADC level to -16 */
  429. 11, 76,
  430. (1 << 13) - 825 - 117,
  431. (1 << 13) - 837 - 117,
  432. (1 << 13) - 811 - 117,
  433. (1 << 13) - 766 - 117,
  434. (1 << 13) - 737 - 117,
  435. (1 << 13) - 693 - 117,
  436. (1 << 13) - 648 - 117,
  437. (1 << 13) - 619 - 117,
  438. (1 << 13) - 575 - 117,
  439. (1 << 13) - 531 - 117,
  440. (1 << 13) - 501 - 117,
  441. // Tuner IO bank: max drive (14mA)
  442. 1, 912,
  443. 0x2c8a,
  444. 1, 1817,
  445. 1,
  446. 0,
  447. };
  448. static int dib7000m_demod_reset(struct dib7000m_state *state)
  449. {
  450. dib7000m_set_power_mode(state, DIB7000M_POWER_ALL);
  451. /* always leave the VBG voltage on - it consumes almost nothing but takes a long time to start */
  452. dib7000m_set_adc_state(state, DIBX000_VBG_ENABLE);
  453. /* restart all parts */
  454. dib7000m_write_word(state, 898, 0xffff);
  455. dib7000m_write_word(state, 899, 0xffff);
  456. dib7000m_write_word(state, 900, 0xff0f);
  457. dib7000m_write_word(state, 901, 0xfffc);
  458. dib7000m_write_word(state, 898, 0);
  459. dib7000m_write_word(state, 899, 0);
  460. dib7000m_write_word(state, 900, 0);
  461. dib7000m_write_word(state, 901, 0);
  462. if (state->revision == 0x4000)
  463. dib7000m_reset_pll(state);
  464. else
  465. dib7000mc_reset_pll(state);
  466. if (dib7000m_reset_gpio(state) != 0)
  467. dprintk("GPIO reset was not successful.\n");
  468. if (dib7000m_set_output_mode(state, OUTMODE_HIGH_Z) != 0)
  469. dprintk("OUTPUT_MODE could not be reset.\n");
  470. /* unforce divstr regardless whether i2c enumeration was done or not */
  471. dib7000m_write_word(state, 1794, dib7000m_read_word(state, 1794) & ~(1 << 1) );
  472. dib7000m_set_bandwidth(state, 8000);
  473. dib7000m_set_adc_state(state, DIBX000_SLOW_ADC_ON);
  474. dib7000m_sad_calib(state);
  475. dib7000m_set_adc_state(state, DIBX000_SLOW_ADC_OFF);
  476. if (state->cfg.dvbt_mode)
  477. dib7000m_write_word(state, 1796, 0x0); // select DVB-T output
  478. if (state->cfg.mobile_mode)
  479. dib7000m_write_word(state, 261 + state->reg_offs, 2);
  480. else
  481. dib7000m_write_word(state, 224 + state->reg_offs, 1);
  482. // P_iqc_alpha_pha, P_iqc_alpha_amp, P_iqc_dcc_alpha, ...
  483. if(state->cfg.tuner_is_baseband)
  484. dib7000m_write_word(state, 36, 0x0755);
  485. else
  486. dib7000m_write_word(state, 36, 0x1f55);
  487. // P_divclksel=3 P_divbitsel=1
  488. if (state->revision == 0x4000)
  489. dib7000m_write_word(state, 909, (3 << 10) | (1 << 6));
  490. else
  491. dib7000m_write_word(state, 909, (3 << 4) | 1);
  492. dib7000m_write_tab(state, dib7000m_defaults_common);
  493. dib7000m_write_tab(state, dib7000m_defaults);
  494. dib7000m_set_power_mode(state, DIB7000M_POWER_INTERFACE_ONLY);
  495. state->internal_clk = state->cfg.bw->internal;
  496. return 0;
  497. }
  498. static void dib7000m_restart_agc(struct dib7000m_state *state)
  499. {
  500. // P_restart_iqc & P_restart_agc
  501. dib7000m_write_word(state, 898, 0x0c00);
  502. dib7000m_write_word(state, 898, 0x0000);
  503. }
  504. static int dib7000m_agc_soft_split(struct dib7000m_state *state)
  505. {
  506. u16 agc,split_offset;
  507. if(!state->current_agc || !state->current_agc->perform_agc_softsplit || state->current_agc->split.max == 0)
  508. return 0;
  509. // n_agc_global
  510. agc = dib7000m_read_word(state, 390);
  511. if (agc > state->current_agc->split.min_thres)
  512. split_offset = state->current_agc->split.min;
  513. else if (agc < state->current_agc->split.max_thres)
  514. split_offset = state->current_agc->split.max;
  515. else
  516. split_offset = state->current_agc->split.max *
  517. (agc - state->current_agc->split.min_thres) /
  518. (state->current_agc->split.max_thres - state->current_agc->split.min_thres);
  519. dprintk("AGC split_offset: %d\n", split_offset);
  520. // P_agc_force_split and P_agc_split_offset
  521. return dib7000m_write_word(state, 103, (dib7000m_read_word(state, 103) & 0xff00) | split_offset);
  522. }
  523. static int dib7000m_update_lna(struct dib7000m_state *state)
  524. {
  525. u16 dyn_gain;
  526. if (state->cfg.update_lna) {
  527. // read dyn_gain here (because it is demod-dependent and not fe)
  528. dyn_gain = dib7000m_read_word(state, 390);
  529. if (state->cfg.update_lna(&state->demod,dyn_gain)) { // LNA has changed
  530. dib7000m_restart_agc(state);
  531. return 1;
  532. }
  533. }
  534. return 0;
  535. }
  536. static int dib7000m_set_agc_config(struct dib7000m_state *state, u8 band)
  537. {
  538. struct dibx000_agc_config *agc = NULL;
  539. int i;
  540. if (state->current_band == band && state->current_agc != NULL)
  541. return 0;
  542. state->current_band = band;
  543. for (i = 0; i < state->cfg.agc_config_count; i++)
  544. if (state->cfg.agc[i].band_caps & band) {
  545. agc = &state->cfg.agc[i];
  546. break;
  547. }
  548. if (agc == NULL) {
  549. dprintk("no valid AGC configuration found for band 0x%02x\n", band);
  550. return -EINVAL;
  551. }
  552. state->current_agc = agc;
  553. /* AGC */
  554. dib7000m_write_word(state, 72 , agc->setup);
  555. dib7000m_write_word(state, 73 , agc->inv_gain);
  556. dib7000m_write_word(state, 74 , agc->time_stabiliz);
  557. dib7000m_write_word(state, 97 , (agc->alpha_level << 12) | agc->thlock);
  558. // Demod AGC loop configuration
  559. dib7000m_write_word(state, 98, (agc->alpha_mant << 5) | agc->alpha_exp);
  560. dib7000m_write_word(state, 99, (agc->beta_mant << 6) | agc->beta_exp);
  561. dprintk("WBD: ref: %d, sel: %d, active: %d, alpha: %d\n",
  562. state->wbd_ref != 0 ? state->wbd_ref : agc->wbd_ref, agc->wbd_sel, !agc->perform_agc_softsplit, agc->wbd_sel);
  563. /* AGC continued */
  564. if (state->wbd_ref != 0)
  565. dib7000m_write_word(state, 102, state->wbd_ref);
  566. else // use default
  567. dib7000m_write_word(state, 102, agc->wbd_ref);
  568. dib7000m_write_word(state, 103, (agc->wbd_alpha << 9) | (agc->perform_agc_softsplit << 8) );
  569. dib7000m_write_word(state, 104, agc->agc1_max);
  570. dib7000m_write_word(state, 105, agc->agc1_min);
  571. dib7000m_write_word(state, 106, agc->agc2_max);
  572. dib7000m_write_word(state, 107, agc->agc2_min);
  573. dib7000m_write_word(state, 108, (agc->agc1_pt1 << 8) | agc->agc1_pt2 );
  574. dib7000m_write_word(state, 109, (agc->agc1_slope1 << 8) | agc->agc1_slope2);
  575. dib7000m_write_word(state, 110, (agc->agc2_pt1 << 8) | agc->agc2_pt2);
  576. dib7000m_write_word(state, 111, (agc->agc2_slope1 << 8) | agc->agc2_slope2);
  577. if (state->revision > 0x4000) { // settings for the MC
  578. dib7000m_write_word(state, 71, agc->agc1_pt3);
  579. // dprintk("929: %x %d %d\n",
  580. // (dib7000m_read_word(state, 929) & 0xffe3) | (agc->wbd_inv << 4) | (agc->wbd_sel << 2), agc->wbd_inv, agc->wbd_sel);
  581. dib7000m_write_word(state, 929, (dib7000m_read_word(state, 929) & 0xffe3) | (agc->wbd_inv << 4) | (agc->wbd_sel << 2));
  582. } else {
  583. // wrong default values
  584. u16 b[9] = { 676, 696, 717, 737, 758, 778, 799, 819, 840 };
  585. for (i = 0; i < 9; i++)
  586. dib7000m_write_word(state, 88 + i, b[i]);
  587. }
  588. return 0;
  589. }
  590. static void dib7000m_update_timf(struct dib7000m_state *state)
  591. {
  592. u32 timf = (dib7000m_read_word(state, 436) << 16) | dib7000m_read_word(state, 437);
  593. state->timf = timf * 160 / (state->current_bandwidth / 50);
  594. dib7000m_write_word(state, 23, (u16) (timf >> 16));
  595. dib7000m_write_word(state, 24, (u16) (timf & 0xffff));
  596. dprintk("updated timf_frequency: %d (default: %d)\n", state->timf, state->timf_default);
  597. }
  598. static int dib7000m_agc_startup(struct dvb_frontend *demod)
  599. {
  600. struct dtv_frontend_properties *ch = &demod->dtv_property_cache;
  601. struct dib7000m_state *state = demod->demodulator_priv;
  602. u16 cfg_72 = dib7000m_read_word(state, 72);
  603. int ret = -1;
  604. u8 *agc_state = &state->agc_state;
  605. u8 agc_split;
  606. switch (state->agc_state) {
  607. case 0:
  608. // set power-up level: interf+analog+AGC
  609. dib7000m_set_power_mode(state, DIB7000M_POWER_INTERF_ANALOG_AGC);
  610. dib7000m_set_adc_state(state, DIBX000_ADC_ON);
  611. if (dib7000m_set_agc_config(state, BAND_OF_FREQUENCY(ch->frequency/1000)) != 0)
  612. return -1;
  613. ret = 7; /* ADC power up */
  614. (*agc_state)++;
  615. break;
  616. case 1:
  617. /* AGC initialization */
  618. if (state->cfg.agc_control)
  619. state->cfg.agc_control(&state->demod, 1);
  620. dib7000m_write_word(state, 75, 32768);
  621. if (!state->current_agc->perform_agc_softsplit) {
  622. /* we are using the wbd - so slow AGC startup */
  623. dib7000m_write_word(state, 103, 1 << 8); /* force 0 split on WBD and restart AGC */
  624. (*agc_state)++;
  625. ret = 5;
  626. } else {
  627. /* default AGC startup */
  628. (*agc_state) = 4;
  629. /* wait AGC rough lock time */
  630. ret = 7;
  631. }
  632. dib7000m_restart_agc(state);
  633. break;
  634. case 2: /* fast split search path after 5sec */
  635. dib7000m_write_word(state, 72, cfg_72 | (1 << 4)); /* freeze AGC loop */
  636. dib7000m_write_word(state, 103, 2 << 9); /* fast split search 0.25kHz */
  637. (*agc_state)++;
  638. ret = 14;
  639. break;
  640. case 3: /* split search ended */
  641. agc_split = (u8)dib7000m_read_word(state, 392); /* store the split value for the next time */
  642. dib7000m_write_word(state, 75, dib7000m_read_word(state, 390)); /* set AGC gain start value */
  643. dib7000m_write_word(state, 72, cfg_72 & ~(1 << 4)); /* std AGC loop */
  644. dib7000m_write_word(state, 103, (state->current_agc->wbd_alpha << 9) | agc_split); /* standard split search */
  645. dib7000m_restart_agc(state);
  646. dprintk("SPLIT %p: %hd\n", demod, agc_split);
  647. (*agc_state)++;
  648. ret = 5;
  649. break;
  650. case 4: /* LNA startup */
  651. /* wait AGC accurate lock time */
  652. ret = 7;
  653. if (dib7000m_update_lna(state))
  654. // wait only AGC rough lock time
  655. ret = 5;
  656. else
  657. (*agc_state)++;
  658. break;
  659. case 5:
  660. dib7000m_agc_soft_split(state);
  661. if (state->cfg.agc_control)
  662. state->cfg.agc_control(&state->demod, 0);
  663. (*agc_state)++;
  664. break;
  665. default:
  666. break;
  667. }
  668. return ret;
  669. }
  670. static void dib7000m_set_channel(struct dib7000m_state *state, struct dtv_frontend_properties *ch,
  671. u8 seq)
  672. {
  673. u16 value, est[4];
  674. dib7000m_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->bandwidth_hz));
  675. /* nfft, guard, qam, alpha */
  676. value = 0;
  677. switch (ch->transmission_mode) {
  678. case TRANSMISSION_MODE_2K: value |= (0 << 7); break;
  679. case TRANSMISSION_MODE_4K: value |= (2 << 7); break;
  680. default:
  681. case TRANSMISSION_MODE_8K: value |= (1 << 7); break;
  682. }
  683. switch (ch->guard_interval) {
  684. case GUARD_INTERVAL_1_32: value |= (0 << 5); break;
  685. case GUARD_INTERVAL_1_16: value |= (1 << 5); break;
  686. case GUARD_INTERVAL_1_4: value |= (3 << 5); break;
  687. default:
  688. case GUARD_INTERVAL_1_8: value |= (2 << 5); break;
  689. }
  690. switch (ch->modulation) {
  691. case QPSK: value |= (0 << 3); break;
  692. case QAM_16: value |= (1 << 3); break;
  693. default:
  694. case QAM_64: value |= (2 << 3); break;
  695. }
  696. switch (HIERARCHY_1) {
  697. case HIERARCHY_2: value |= 2; break;
  698. case HIERARCHY_4: value |= 4; break;
  699. default:
  700. case HIERARCHY_1: value |= 1; break;
  701. }
  702. dib7000m_write_word(state, 0, value);
  703. dib7000m_write_word(state, 5, (seq << 4));
  704. /* P_dintl_native, P_dintlv_inv, P_hrch, P_code_rate, P_select_hp */
  705. value = 0;
  706. if (1 != 0)
  707. value |= (1 << 6);
  708. if (ch->hierarchy == 1)
  709. value |= (1 << 4);
  710. if (1 == 1)
  711. value |= 1;
  712. switch ((ch->hierarchy == 0 || 1 == 1) ? ch->code_rate_HP : ch->code_rate_LP) {
  713. case FEC_2_3: value |= (2 << 1); break;
  714. case FEC_3_4: value |= (3 << 1); break;
  715. case FEC_5_6: value |= (5 << 1); break;
  716. case FEC_7_8: value |= (7 << 1); break;
  717. default:
  718. case FEC_1_2: value |= (1 << 1); break;
  719. }
  720. dib7000m_write_word(state, 267 + state->reg_offs, value);
  721. /* offset loop parameters */
  722. /* P_timf_alpha = 6, P_corm_alpha=6, P_corm_thres=0x80 */
  723. dib7000m_write_word(state, 26, (6 << 12) | (6 << 8) | 0x80);
  724. /* P_ctrl_inh_cor=0, P_ctrl_alpha_cor=4, P_ctrl_inh_isi=1, P_ctrl_alpha_isi=3, P_ctrl_inh_cor4=1, P_ctrl_alpha_cor4=3 */
  725. dib7000m_write_word(state, 29, (0 << 14) | (4 << 10) | (1 << 9) | (3 << 5) | (1 << 4) | (0x3));
  726. /* P_ctrl_freeze_pha_shift=0, P_ctrl_pha_off_max=3 */
  727. dib7000m_write_word(state, 32, (0 << 4) | 0x3);
  728. /* P_ctrl_sfreq_inh=0, P_ctrl_sfreq_step=5 */
  729. dib7000m_write_word(state, 33, (0 << 4) | 0x5);
  730. /* P_dvsy_sync_wait */
  731. switch (ch->transmission_mode) {
  732. case TRANSMISSION_MODE_8K: value = 256; break;
  733. case TRANSMISSION_MODE_4K: value = 128; break;
  734. case TRANSMISSION_MODE_2K:
  735. default: value = 64; break;
  736. }
  737. switch (ch->guard_interval) {
  738. case GUARD_INTERVAL_1_16: value *= 2; break;
  739. case GUARD_INTERVAL_1_8: value *= 4; break;
  740. case GUARD_INTERVAL_1_4: value *= 8; break;
  741. default:
  742. case GUARD_INTERVAL_1_32: value *= 1; break;
  743. }
  744. state->div_sync_wait = (value * 3) / 2 + 32; // add 50% SFN margin + compensate for one DVSY-fifo TODO
  745. /* deactivate the possibility of diversity reception if extended interleave - not for 7000MC */
  746. /* P_dvsy_sync_mode = 0, P_dvsy_sync_enable=1, P_dvcb_comb_mode=2 */
  747. if (1 == 1 || state->revision > 0x4000)
  748. state->div_force_off = 0;
  749. else
  750. state->div_force_off = 1;
  751. dib7000m_set_diversity_in(&state->demod, state->div_state);
  752. /* channel estimation fine configuration */
  753. switch (ch->modulation) {
  754. case QAM_64:
  755. est[0] = 0x0148; /* P_adp_regul_cnt 0.04 */
  756. est[1] = 0xfff0; /* P_adp_noise_cnt -0.002 */
  757. est[2] = 0x00a4; /* P_adp_regul_ext 0.02 */
  758. est[3] = 0xfff8; /* P_adp_noise_ext -0.001 */
  759. break;
  760. case QAM_16:
  761. est[0] = 0x023d; /* P_adp_regul_cnt 0.07 */
  762. est[1] = 0xffdf; /* P_adp_noise_cnt -0.004 */
  763. est[2] = 0x00a4; /* P_adp_regul_ext 0.02 */
  764. est[3] = 0xfff0; /* P_adp_noise_ext -0.002 */
  765. break;
  766. default:
  767. est[0] = 0x099a; /* P_adp_regul_cnt 0.3 */
  768. est[1] = 0xffae; /* P_adp_noise_cnt -0.01 */
  769. est[2] = 0x0333; /* P_adp_regul_ext 0.1 */
  770. est[3] = 0xfff8; /* P_adp_noise_ext -0.002 */
  771. break;
  772. }
  773. for (value = 0; value < 4; value++)
  774. dib7000m_write_word(state, 214 + value + state->reg_offs, est[value]);
  775. // set power-up level: autosearch
  776. dib7000m_set_power_mode(state, DIB7000M_POWER_COR4_DINTLV_ICIRM_EQUAL_CFROD);
  777. }
  778. static int dib7000m_autosearch_start(struct dvb_frontend *demod)
  779. {
  780. struct dtv_frontend_properties *ch = &demod->dtv_property_cache;
  781. struct dib7000m_state *state = demod->demodulator_priv;
  782. struct dtv_frontend_properties schan;
  783. int ret = 0;
  784. u32 value, factor;
  785. schan = *ch;
  786. schan.modulation = QAM_64;
  787. schan.guard_interval = GUARD_INTERVAL_1_32;
  788. schan.transmission_mode = TRANSMISSION_MODE_8K;
  789. schan.code_rate_HP = FEC_2_3;
  790. schan.code_rate_LP = FEC_3_4;
  791. schan.hierarchy = 0;
  792. dib7000m_set_channel(state, &schan, 7);
  793. factor = BANDWIDTH_TO_KHZ(schan.bandwidth_hz);
  794. if (factor >= 5000)
  795. factor = 1;
  796. else
  797. factor = 6;
  798. // always use the setting for 8MHz here lock_time for 7,6 MHz are longer
  799. value = 30 * state->internal_clk * factor;
  800. ret |= dib7000m_write_word(state, 6, (u16) ((value >> 16) & 0xffff)); // lock0 wait time
  801. ret |= dib7000m_write_word(state, 7, (u16) (value & 0xffff)); // lock0 wait time
  802. value = 100 * state->internal_clk * factor;
  803. ret |= dib7000m_write_word(state, 8, (u16) ((value >> 16) & 0xffff)); // lock1 wait time
  804. ret |= dib7000m_write_word(state, 9, (u16) (value & 0xffff)); // lock1 wait time
  805. value = 500 * state->internal_clk * factor;
  806. ret |= dib7000m_write_word(state, 10, (u16) ((value >> 16) & 0xffff)); // lock2 wait time
  807. ret |= dib7000m_write_word(state, 11, (u16) (value & 0xffff)); // lock2 wait time
  808. // start search
  809. value = dib7000m_read_word(state, 0);
  810. ret |= dib7000m_write_word(state, 0, (u16) (value | (1 << 9)));
  811. /* clear n_irq_pending */
  812. if (state->revision == 0x4000)
  813. dib7000m_write_word(state, 1793, 0);
  814. else
  815. dib7000m_read_word(state, 537);
  816. ret |= dib7000m_write_word(state, 0, (u16) value);
  817. return ret;
  818. }
  819. static int dib7000m_autosearch_irq(struct dib7000m_state *state, u16 reg)
  820. {
  821. u16 irq_pending = dib7000m_read_word(state, reg);
  822. if (irq_pending & 0x1) { // failed
  823. dprintk("autosearch failed\n");
  824. return 1;
  825. }
  826. if (irq_pending & 0x2) { // succeeded
  827. dprintk("autosearch succeeded\n");
  828. return 2;
  829. }
  830. return 0; // still pending
  831. }
  832. static int dib7000m_autosearch_is_irq(struct dvb_frontend *demod)
  833. {
  834. struct dib7000m_state *state = demod->demodulator_priv;
  835. if (state->revision == 0x4000)
  836. return dib7000m_autosearch_irq(state, 1793);
  837. else
  838. return dib7000m_autosearch_irq(state, 537);
  839. }
  840. static int dib7000m_tune(struct dvb_frontend *demod)
  841. {
  842. struct dtv_frontend_properties *ch = &demod->dtv_property_cache;
  843. struct dib7000m_state *state = demod->demodulator_priv;
  844. int ret = 0;
  845. u16 value;
  846. // we are already tuned - just resuming from suspend
  847. dib7000m_set_channel(state, ch, 0);
  848. // restart demod
  849. ret |= dib7000m_write_word(state, 898, 0x4000);
  850. ret |= dib7000m_write_word(state, 898, 0x0000);
  851. msleep(45);
  852. dib7000m_set_power_mode(state, DIB7000M_POWER_COR4_CRY_ESRAM_MOUT_NUD);
  853. /* P_ctrl_inh_cor=0, P_ctrl_alpha_cor=4, P_ctrl_inh_isi=0, P_ctrl_alpha_isi=3, P_ctrl_inh_cor4=1, P_ctrl_alpha_cor4=3 */
  854. ret |= dib7000m_write_word(state, 29, (0 << 14) | (4 << 10) | (0 << 9) | (3 << 5) | (1 << 4) | (0x3));
  855. // never achieved a lock before - wait for timfreq to update
  856. if (state->timf == 0)
  857. msleep(200);
  858. //dump_reg(state);
  859. /* P_timf_alpha, P_corm_alpha=6, P_corm_thres=0x80 */
  860. value = (6 << 8) | 0x80;
  861. switch (ch->transmission_mode) {
  862. case TRANSMISSION_MODE_2K: value |= (7 << 12); break;
  863. case TRANSMISSION_MODE_4K: value |= (8 << 12); break;
  864. default:
  865. case TRANSMISSION_MODE_8K: value |= (9 << 12); break;
  866. }
  867. ret |= dib7000m_write_word(state, 26, value);
  868. /* P_ctrl_freeze_pha_shift=0, P_ctrl_pha_off_max */
  869. value = (0 << 4);
  870. switch (ch->transmission_mode) {
  871. case TRANSMISSION_MODE_2K: value |= 0x6; break;
  872. case TRANSMISSION_MODE_4K: value |= 0x7; break;
  873. default:
  874. case TRANSMISSION_MODE_8K: value |= 0x8; break;
  875. }
  876. ret |= dib7000m_write_word(state, 32, value);
  877. /* P_ctrl_sfreq_inh=0, P_ctrl_sfreq_step */
  878. value = (0 << 4);
  879. switch (ch->transmission_mode) {
  880. case TRANSMISSION_MODE_2K: value |= 0x6; break;
  881. case TRANSMISSION_MODE_4K: value |= 0x7; break;
  882. default:
  883. case TRANSMISSION_MODE_8K: value |= 0x8; break;
  884. }
  885. ret |= dib7000m_write_word(state, 33, value);
  886. // we achieved a lock - it's time to update the timf freq
  887. if ((dib7000m_read_word(state, 535) >> 6) & 0x1)
  888. dib7000m_update_timf(state);
  889. dib7000m_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->bandwidth_hz));
  890. return ret;
  891. }
  892. static int dib7000m_wakeup(struct dvb_frontend *demod)
  893. {
  894. struct dib7000m_state *state = demod->demodulator_priv;
  895. dib7000m_set_power_mode(state, DIB7000M_POWER_ALL);
  896. if (dib7000m_set_adc_state(state, DIBX000_SLOW_ADC_ON) != 0)
  897. dprintk("could not start Slow ADC\n");
  898. return 0;
  899. }
  900. static int dib7000m_sleep(struct dvb_frontend *demod)
  901. {
  902. struct dib7000m_state *st = demod->demodulator_priv;
  903. dib7000m_set_output_mode(st, OUTMODE_HIGH_Z);
  904. dib7000m_set_power_mode(st, DIB7000M_POWER_INTERFACE_ONLY);
  905. return dib7000m_set_adc_state(st, DIBX000_SLOW_ADC_OFF) |
  906. dib7000m_set_adc_state(st, DIBX000_ADC_OFF);
  907. }
  908. static int dib7000m_identify(struct dib7000m_state *state)
  909. {
  910. u16 value;
  911. if ((value = dib7000m_read_word(state, 896)) != 0x01b3) {
  912. dprintk("wrong Vendor ID (0x%x)\n", value);
  913. return -EREMOTEIO;
  914. }
  915. state->revision = dib7000m_read_word(state, 897);
  916. if (state->revision != 0x4000 &&
  917. state->revision != 0x4001 &&
  918. state->revision != 0x4002 &&
  919. state->revision != 0x4003) {
  920. dprintk("wrong Device ID (0x%x)\n", value);
  921. return -EREMOTEIO;
  922. }
  923. /* protect this driver to be used with 7000PC */
  924. if (state->revision == 0x4000 && dib7000m_read_word(state, 769) == 0x4000) {
  925. dprintk("this driver does not work with DiB7000PC\n");
  926. return -EREMOTEIO;
  927. }
  928. switch (state->revision) {
  929. case 0x4000: dprintk("found DiB7000MA/PA/MB/PB\n"); break;
  930. case 0x4001: state->reg_offs = 1; dprintk("found DiB7000HC\n"); break;
  931. case 0x4002: state->reg_offs = 1; dprintk("found DiB7000MC\n"); break;
  932. case 0x4003: state->reg_offs = 1; dprintk("found DiB9000\n"); break;
  933. }
  934. return 0;
  935. }
  936. static int dib7000m_get_frontend(struct dvb_frontend* fe,
  937. struct dtv_frontend_properties *fep)
  938. {
  939. struct dib7000m_state *state = fe->demodulator_priv;
  940. u16 tps = dib7000m_read_word(state,480);
  941. fep->inversion = INVERSION_AUTO;
  942. fep->bandwidth_hz = BANDWIDTH_TO_HZ(state->current_bandwidth);
  943. switch ((tps >> 8) & 0x3) {
  944. case 0: fep->transmission_mode = TRANSMISSION_MODE_2K; break;
  945. case 1: fep->transmission_mode = TRANSMISSION_MODE_8K; break;
  946. /* case 2: fep->transmission_mode = TRANSMISSION_MODE_4K; break; */
  947. }
  948. switch (tps & 0x3) {
  949. case 0: fep->guard_interval = GUARD_INTERVAL_1_32; break;
  950. case 1: fep->guard_interval = GUARD_INTERVAL_1_16; break;
  951. case 2: fep->guard_interval = GUARD_INTERVAL_1_8; break;
  952. case 3: fep->guard_interval = GUARD_INTERVAL_1_4; break;
  953. }
  954. switch ((tps >> 14) & 0x3) {
  955. case 0: fep->modulation = QPSK; break;
  956. case 1: fep->modulation = QAM_16; break;
  957. case 2:
  958. default: fep->modulation = QAM_64; break;
  959. }
  960. /* as long as the frontend_param structure is fixed for hierarchical transmission I refuse to use it */
  961. /* (tps >> 13) & 0x1 == hrch is used, (tps >> 10) & 0x7 == alpha */
  962. fep->hierarchy = HIERARCHY_NONE;
  963. switch ((tps >> 5) & 0x7) {
  964. case 1: fep->code_rate_HP = FEC_1_2; break;
  965. case 2: fep->code_rate_HP = FEC_2_3; break;
  966. case 3: fep->code_rate_HP = FEC_3_4; break;
  967. case 5: fep->code_rate_HP = FEC_5_6; break;
  968. case 7:
  969. default: fep->code_rate_HP = FEC_7_8; break;
  970. }
  971. switch ((tps >> 2) & 0x7) {
  972. case 1: fep->code_rate_LP = FEC_1_2; break;
  973. case 2: fep->code_rate_LP = FEC_2_3; break;
  974. case 3: fep->code_rate_LP = FEC_3_4; break;
  975. case 5: fep->code_rate_LP = FEC_5_6; break;
  976. case 7:
  977. default: fep->code_rate_LP = FEC_7_8; break;
  978. }
  979. /* native interleaver: (dib7000m_read_word(state, 481) >> 5) & 0x1 */
  980. return 0;
  981. }
  982. static int dib7000m_set_frontend(struct dvb_frontend *fe)
  983. {
  984. struct dtv_frontend_properties *fep = &fe->dtv_property_cache;
  985. struct dib7000m_state *state = fe->demodulator_priv;
  986. int time, ret;
  987. dib7000m_set_output_mode(state, OUTMODE_HIGH_Z);
  988. dib7000m_set_bandwidth(state, BANDWIDTH_TO_KHZ(fep->bandwidth_hz));
  989. if (fe->ops.tuner_ops.set_params)
  990. fe->ops.tuner_ops.set_params(fe);
  991. /* start up the AGC */
  992. state->agc_state = 0;
  993. do {
  994. time = dib7000m_agc_startup(fe);
  995. if (time != -1)
  996. msleep(time);
  997. } while (time != -1);
  998. if (fep->transmission_mode == TRANSMISSION_MODE_AUTO ||
  999. fep->guard_interval == GUARD_INTERVAL_AUTO ||
  1000. fep->modulation == QAM_AUTO ||
  1001. fep->code_rate_HP == FEC_AUTO) {
  1002. int i = 800, found;
  1003. dib7000m_autosearch_start(fe);
  1004. do {
  1005. msleep(1);
  1006. found = dib7000m_autosearch_is_irq(fe);
  1007. } while (found == 0 && i--);
  1008. dprintk("autosearch returns: %d\n", found);
  1009. if (found == 0 || found == 1)
  1010. return 0; // no channel found
  1011. dib7000m_get_frontend(fe, fep);
  1012. }
  1013. ret = dib7000m_tune(fe);
  1014. /* make this a config parameter */
  1015. dib7000m_set_output_mode(state, OUTMODE_MPEG2_FIFO);
  1016. return ret;
  1017. }
  1018. static int dib7000m_read_status(struct dvb_frontend *fe, enum fe_status *stat)
  1019. {
  1020. struct dib7000m_state *state = fe->demodulator_priv;
  1021. u16 lock = dib7000m_read_word(state, 535);
  1022. *stat = 0;
  1023. if (lock & 0x8000)
  1024. *stat |= FE_HAS_SIGNAL;
  1025. if (lock & 0x3000)
  1026. *stat |= FE_HAS_CARRIER;
  1027. if (lock & 0x0100)
  1028. *stat |= FE_HAS_VITERBI;
  1029. if (lock & 0x0010)
  1030. *stat |= FE_HAS_SYNC;
  1031. if (lock & 0x0008)
  1032. *stat |= FE_HAS_LOCK;
  1033. return 0;
  1034. }
  1035. static int dib7000m_read_ber(struct dvb_frontend *fe, u32 *ber)
  1036. {
  1037. struct dib7000m_state *state = fe->demodulator_priv;
  1038. *ber = (dib7000m_read_word(state, 526) << 16) | dib7000m_read_word(state, 527);
  1039. return 0;
  1040. }
  1041. static int dib7000m_read_unc_blocks(struct dvb_frontend *fe, u32 *unc)
  1042. {
  1043. struct dib7000m_state *state = fe->demodulator_priv;
  1044. *unc = dib7000m_read_word(state, 534);
  1045. return 0;
  1046. }
  1047. static int dib7000m_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
  1048. {
  1049. struct dib7000m_state *state = fe->demodulator_priv;
  1050. u16 val = dib7000m_read_word(state, 390);
  1051. *strength = 65535 - val;
  1052. return 0;
  1053. }
  1054. static int dib7000m_read_snr(struct dvb_frontend* fe, u16 *snr)
  1055. {
  1056. *snr = 0x0000;
  1057. return 0;
  1058. }
  1059. static int dib7000m_fe_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings *tune)
  1060. {
  1061. tune->min_delay_ms = 1000;
  1062. return 0;
  1063. }
  1064. static void dib7000m_release(struct dvb_frontend *demod)
  1065. {
  1066. struct dib7000m_state *st = demod->demodulator_priv;
  1067. dibx000_exit_i2c_master(&st->i2c_master);
  1068. kfree(st);
  1069. }
  1070. struct i2c_adapter * dib7000m_get_i2c_master(struct dvb_frontend *demod, enum dibx000_i2c_interface intf, int gating)
  1071. {
  1072. struct dib7000m_state *st = demod->demodulator_priv;
  1073. return dibx000_get_i2c_adapter(&st->i2c_master, intf, gating);
  1074. }
  1075. EXPORT_SYMBOL(dib7000m_get_i2c_master);
  1076. int dib7000m_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff)
  1077. {
  1078. struct dib7000m_state *state = fe->demodulator_priv;
  1079. u16 val = dib7000m_read_word(state, 294 + state->reg_offs) & 0xffef;
  1080. val |= (onoff & 0x1) << 4;
  1081. dprintk("PID filter enabled %d\n", onoff);
  1082. return dib7000m_write_word(state, 294 + state->reg_offs, val);
  1083. }
  1084. EXPORT_SYMBOL(dib7000m_pid_filter_ctrl);
  1085. int dib7000m_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
  1086. {
  1087. struct dib7000m_state *state = fe->demodulator_priv;
  1088. dprintk("PID filter: index %x, PID %d, OnOff %d\n", id, pid, onoff);
  1089. return dib7000m_write_word(state, 300 + state->reg_offs + id,
  1090. onoff ? (1 << 13) | pid : 0);
  1091. }
  1092. EXPORT_SYMBOL(dib7000m_pid_filter);
  1093. #if 0
  1094. /* used with some prototype boards */
  1095. int dib7000m_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods,
  1096. u8 default_addr, struct dib7000m_config cfg[])
  1097. {
  1098. struct dib7000m_state st = { .i2c_adap = i2c };
  1099. int k = 0;
  1100. u8 new_addr = 0;
  1101. for (k = no_of_demods-1; k >= 0; k--) {
  1102. st.cfg = cfg[k];
  1103. /* designated i2c address */
  1104. new_addr = (0x40 + k) << 1;
  1105. st.i2c_addr = new_addr;
  1106. if (dib7000m_identify(&st) != 0) {
  1107. st.i2c_addr = default_addr;
  1108. if (dib7000m_identify(&st) != 0) {
  1109. dprintk("DiB7000M #%d: not identified\n", k);
  1110. return -EIO;
  1111. }
  1112. }
  1113. /* start diversity to pull_down div_str - just for i2c-enumeration */
  1114. dib7000m_set_output_mode(&st, OUTMODE_DIVERSITY);
  1115. dib7000m_write_word(&st, 1796, 0x0); // select DVB-T output
  1116. /* set new i2c address and force divstart */
  1117. dib7000m_write_word(&st, 1794, (new_addr << 2) | 0x2);
  1118. dprintk("IC %d initialized (to i2c_address 0x%x)\n", k, new_addr);
  1119. }
  1120. for (k = 0; k < no_of_demods; k++) {
  1121. st.cfg = cfg[k];
  1122. st.i2c_addr = (0x40 + k) << 1;
  1123. // unforce divstr
  1124. dib7000m_write_word(&st,1794, st.i2c_addr << 2);
  1125. /* deactivate div - it was just for i2c-enumeration */
  1126. dib7000m_set_output_mode(&st, OUTMODE_HIGH_Z);
  1127. }
  1128. return 0;
  1129. }
  1130. EXPORT_SYMBOL(dib7000m_i2c_enumeration);
  1131. #endif
  1132. static const struct dvb_frontend_ops dib7000m_ops;
  1133. struct dvb_frontend * dib7000m_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib7000m_config *cfg)
  1134. {
  1135. struct dvb_frontend *demod;
  1136. struct dib7000m_state *st;
  1137. st = kzalloc(sizeof(struct dib7000m_state), GFP_KERNEL);
  1138. if (st == NULL)
  1139. return NULL;
  1140. memcpy(&st->cfg, cfg, sizeof(struct dib7000m_config));
  1141. st->i2c_adap = i2c_adap;
  1142. st->i2c_addr = i2c_addr;
  1143. demod = &st->demod;
  1144. demod->demodulator_priv = st;
  1145. memcpy(&st->demod.ops, &dib7000m_ops, sizeof(struct dvb_frontend_ops));
  1146. mutex_init(&st->i2c_buffer_lock);
  1147. st->timf_default = cfg->bw->timf;
  1148. if (dib7000m_identify(st) != 0)
  1149. goto error;
  1150. if (st->revision == 0x4000)
  1151. dibx000_init_i2c_master(&st->i2c_master, DIB7000, st->i2c_adap, st->i2c_addr);
  1152. else
  1153. dibx000_init_i2c_master(&st->i2c_master, DIB7000MC, st->i2c_adap, st->i2c_addr);
  1154. dib7000m_demod_reset(st);
  1155. return demod;
  1156. error:
  1157. kfree(st);
  1158. return NULL;
  1159. }
  1160. EXPORT_SYMBOL(dib7000m_attach);
  1161. static const struct dvb_frontend_ops dib7000m_ops = {
  1162. .delsys = { SYS_DVBT },
  1163. .info = {
  1164. .name = "DiBcom 7000MA/MB/PA/PB/MC",
  1165. .frequency_min_hz = 44250 * kHz,
  1166. .frequency_max_hz = 867250 * kHz,
  1167. .frequency_stepsize_hz = 62500,
  1168. .caps = FE_CAN_INVERSION_AUTO |
  1169. FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
  1170. FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
  1171. FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
  1172. FE_CAN_TRANSMISSION_MODE_AUTO |
  1173. FE_CAN_GUARD_INTERVAL_AUTO |
  1174. FE_CAN_RECOVER |
  1175. FE_CAN_HIERARCHY_AUTO,
  1176. },
  1177. .release = dib7000m_release,
  1178. .init = dib7000m_wakeup,
  1179. .sleep = dib7000m_sleep,
  1180. .set_frontend = dib7000m_set_frontend,
  1181. .get_tune_settings = dib7000m_fe_get_tune_settings,
  1182. .get_frontend = dib7000m_get_frontend,
  1183. .read_status = dib7000m_read_status,
  1184. .read_ber = dib7000m_read_ber,
  1185. .read_signal_strength = dib7000m_read_signal_strength,
  1186. .read_snr = dib7000m_read_snr,
  1187. .read_ucblocks = dib7000m_read_unc_blocks,
  1188. };
  1189. MODULE_AUTHOR("Patrick Boettcher <patrick.boettcher@posteo.de>");
  1190. MODULE_DESCRIPTION("Driver for the DiBcom 7000MA/MB/PA/PB/MC COFDM demodulator");
  1191. MODULE_LICENSE("GPL");