omap_l3_noc.h 12 KB

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  1. /*
  2. * OMAP L3 Interconnect error handling driver header
  3. *
  4. * Copyright (C) 2011-2015 Texas Instruments Incorporated - http://www.ti.com/
  5. * Santosh Shilimkar <santosh.shilimkar@ti.com>
  6. * sricharan <r.sricharan@ti.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  13. * kind, whether express or implied; without even the implied warranty
  14. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. */
  17. #ifndef __OMAP_L3_NOC_H
  18. #define __OMAP_L3_NOC_H
  19. #define MAX_L3_MODULES 3
  20. #define MAX_CLKDM_TARGETS 31
  21. #define CLEAR_STDERR_LOG (1 << 31)
  22. #define CUSTOM_ERROR 0x2
  23. #define STANDARD_ERROR 0x0
  24. #define INBAND_ERROR 0x0
  25. #define L3_APPLICATION_ERROR 0x0
  26. #define L3_DEBUG_ERROR 0x1
  27. /* L3 TARG register offsets */
  28. #define L3_TARG_STDERRLOG_MAIN 0x48
  29. #define L3_TARG_STDERRLOG_HDR 0x4c
  30. #define L3_TARG_STDERRLOG_MSTADDR 0x50
  31. #define L3_TARG_STDERRLOG_INFO 0x58
  32. #define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c
  33. #define L3_TARG_STDERRLOG_CINFO_INFO 0x64
  34. #define L3_TARG_STDERRLOG_CINFO_MSTADDR 0x68
  35. #define L3_TARG_STDERRLOG_CINFO_OPCODE 0x6c
  36. #define L3_FLAGMUX_REGERR0 0xc
  37. #define L3_FLAGMUX_MASK0 0x8
  38. #define L3_TARGET_NOT_SUPPORTED NULL
  39. #define L3_BASE_IS_SUBMODULE ((void __iomem *)(1 << 0))
  40. static const char * const l3_transaction_type[] = {
  41. /* 0 0 0 */ "Idle",
  42. /* 0 0 1 */ "Write",
  43. /* 0 1 0 */ "Read",
  44. /* 0 1 1 */ "ReadEx",
  45. /* 1 0 0 */ "Read Link",
  46. /* 1 0 1 */ "Write Non-Posted",
  47. /* 1 1 0 */ "Write Conditional",
  48. /* 1 1 1 */ "Write Broadcast",
  49. };
  50. /**
  51. * struct l3_masters_data - L3 Master information
  52. * @id: ID of the L3 Master
  53. * @name: master name
  54. */
  55. struct l3_masters_data {
  56. u32 id;
  57. char *name;
  58. };
  59. /**
  60. * struct l3_target_data - L3 Target information
  61. * @offset: Offset from base for L3 Target
  62. * @name: Target name
  63. *
  64. * Target information is organized indexed by bit field definitions.
  65. */
  66. struct l3_target_data {
  67. u32 offset;
  68. char *name;
  69. };
  70. /**
  71. * struct l3_flagmux_data - Flag Mux information
  72. * @offset: offset from base for flagmux register
  73. * @l3_targ: array indexed by flagmux index (bit offset) pointing to the
  74. * target data. unsupported ones are marked with
  75. * L3_TARGET_NOT_SUPPORTED
  76. * @num_targ_data: number of entries in target data
  77. * @mask_app_bits: ignore these from raw application irq status
  78. * @mask_dbg_bits: ignore these from raw debug irq status
  79. */
  80. struct l3_flagmux_data {
  81. u32 offset;
  82. struct l3_target_data *l3_targ;
  83. u8 num_targ_data;
  84. u32 mask_app_bits;
  85. u32 mask_dbg_bits;
  86. };
  87. /**
  88. * struct omap_l3 - Description of data relevant for L3 bus.
  89. * @dev: device representing the bus (populated runtime)
  90. * @l3_base: base addresses of modules (populated runtime if 0)
  91. * if set to L3_BASE_IS_SUBMODULE, then uses previous
  92. * module index as the base address
  93. * @l3_flag_mux: array containing flag mux data per module
  94. * offset from corresponding module base indexed per
  95. * module.
  96. * @num_modules: number of clock domains / modules.
  97. * @l3_masters: array pointing to master data containing name and register
  98. * offset for the master.
  99. * @num_master: number of masters
  100. * @mst_addr_mask: Mask representing MSTADDR information of NTTP packet
  101. * @debug_irq: irq number of the debug interrupt (populated runtime)
  102. * @app_irq: irq number of the application interrupt (populated runtime)
  103. */
  104. struct omap_l3 {
  105. struct device *dev;
  106. void __iomem *l3_base[MAX_L3_MODULES];
  107. struct l3_flagmux_data **l3_flagmux;
  108. int num_modules;
  109. struct l3_masters_data *l3_masters;
  110. int num_masters;
  111. u32 mst_addr_mask;
  112. int debug_irq;
  113. int app_irq;
  114. };
  115. static struct l3_target_data omap_l3_target_data_clk1[] = {
  116. {0x100, "DMM1",},
  117. {0x200, "DMM2",},
  118. {0x300, "ABE",},
  119. {0x400, "L4CFG",},
  120. {0x600, "CLK2PWRDISC",},
  121. {0x0, "HOSTCLK1",},
  122. {0x900, "L4WAKEUP",},
  123. };
  124. static struct l3_flagmux_data omap_l3_flagmux_clk1 = {
  125. .offset = 0x500,
  126. .l3_targ = omap_l3_target_data_clk1,
  127. .num_targ_data = ARRAY_SIZE(omap_l3_target_data_clk1),
  128. };
  129. static struct l3_target_data omap_l3_target_data_clk2[] = {
  130. {0x500, "CORTEXM3",},
  131. {0x300, "DSS",},
  132. {0x100, "GPMC",},
  133. {0x400, "ISS",},
  134. {0x700, "IVAHD",},
  135. {0xD00, "AES1",},
  136. {0x900, "L4PER0",},
  137. {0x200, "OCMRAM",},
  138. {0x100, "GPMCsERROR",},
  139. {0x600, "SGX",},
  140. {0x800, "SL2",},
  141. {0x1600, "C2C",},
  142. {0x1100, "PWRDISCCLK1",},
  143. {0xF00, "SHA1",},
  144. {0xE00, "AES2",},
  145. {0xC00, "L4PER3",},
  146. {0xA00, "L4PER1",},
  147. {0xB00, "L4PER2",},
  148. {0x0, "HOSTCLK2",},
  149. {0x1800, "CAL",},
  150. {0x1700, "LLI",},
  151. };
  152. static struct l3_flagmux_data omap_l3_flagmux_clk2 = {
  153. .offset = 0x1000,
  154. .l3_targ = omap_l3_target_data_clk2,
  155. .num_targ_data = ARRAY_SIZE(omap_l3_target_data_clk2),
  156. };
  157. static struct l3_target_data omap4_l3_target_data_clk3[] = {
  158. {0x0100, "DEBUGSS",},
  159. };
  160. static struct l3_flagmux_data omap4_l3_flagmux_clk3 = {
  161. .offset = 0x0200,
  162. .l3_targ = omap4_l3_target_data_clk3,
  163. .num_targ_data = ARRAY_SIZE(omap4_l3_target_data_clk3),
  164. };
  165. static struct l3_masters_data omap_l3_masters[] = {
  166. { 0x00, "MPU"},
  167. { 0x04, "CS_ADP"},
  168. { 0x05, "xxx"},
  169. { 0x08, "DSP"},
  170. { 0x0C, "IVAHD"},
  171. { 0x10, "ISS"},
  172. { 0x11, "DucatiM3"},
  173. { 0x12, "FaceDetect"},
  174. { 0x14, "SDMA_Rd"},
  175. { 0x15, "SDMA_Wr"},
  176. { 0x16, "xxx"},
  177. { 0x17, "xxx"},
  178. { 0x18, "SGX"},
  179. { 0x1C, "DSS"},
  180. { 0x20, "C2C"},
  181. { 0x22, "xxx"},
  182. { 0x23, "xxx"},
  183. { 0x24, "HSI"},
  184. { 0x28, "MMC1"},
  185. { 0x29, "MMC2"},
  186. { 0x2A, "MMC6"},
  187. { 0x2C, "UNIPRO1"},
  188. { 0x30, "USBHOSTHS"},
  189. { 0x31, "USBOTGHS"},
  190. { 0x32, "USBHOSTFS"}
  191. };
  192. static struct l3_flagmux_data *omap4_l3_flagmux[] = {
  193. &omap_l3_flagmux_clk1,
  194. &omap_l3_flagmux_clk2,
  195. &omap4_l3_flagmux_clk3,
  196. };
  197. static const struct omap_l3 omap4_l3_data = {
  198. .l3_flagmux = omap4_l3_flagmux,
  199. .num_modules = ARRAY_SIZE(omap4_l3_flagmux),
  200. .l3_masters = omap_l3_masters,
  201. .num_masters = ARRAY_SIZE(omap_l3_masters),
  202. /* The 6 MSBs of register field used to distinguish initiator */
  203. .mst_addr_mask = 0xFC,
  204. };
  205. /* OMAP5 data */
  206. static struct l3_target_data omap5_l3_target_data_clk3[] = {
  207. {0x0100, "L3INSTR",},
  208. {0x0300, "DEBUGSS",},
  209. {0x0, "HOSTCLK3",},
  210. };
  211. static struct l3_flagmux_data omap5_l3_flagmux_clk3 = {
  212. .offset = 0x0200,
  213. .l3_targ = omap5_l3_target_data_clk3,
  214. .num_targ_data = ARRAY_SIZE(omap5_l3_target_data_clk3),
  215. };
  216. static struct l3_flagmux_data *omap5_l3_flagmux[] = {
  217. &omap_l3_flagmux_clk1,
  218. &omap_l3_flagmux_clk2,
  219. &omap5_l3_flagmux_clk3,
  220. };
  221. static const struct omap_l3 omap5_l3_data = {
  222. .l3_flagmux = omap5_l3_flagmux,
  223. .num_modules = ARRAY_SIZE(omap5_l3_flagmux),
  224. .l3_masters = omap_l3_masters,
  225. .num_masters = ARRAY_SIZE(omap_l3_masters),
  226. /* The 6 MSBs of register field used to distinguish initiator */
  227. .mst_addr_mask = 0x7E0,
  228. };
  229. /* DRA7 data */
  230. static struct l3_target_data dra_l3_target_data_clk1[] = {
  231. {0x2a00, "AES1",},
  232. {0x0200, "DMM_P1",},
  233. {0x0600, "DSP2_SDMA",},
  234. {0x0b00, "EVE2",},
  235. {0x1300, "DMM_P2",},
  236. {0x2c00, "AES2",},
  237. {0x0300, "DSP1_SDMA",},
  238. {0x0a00, "EVE1",},
  239. {0x0c00, "EVE3",},
  240. {0x0d00, "EVE4",},
  241. {0x2900, "DSS",},
  242. {0x0100, "GPMC",},
  243. {0x3700, "PCIE1",},
  244. {0x1600, "IVA_CONFIG",},
  245. {0x1800, "IVA_SL2IF",},
  246. {0x0500, "L4_CFG",},
  247. {0x1d00, "L4_WKUP",},
  248. {0x3800, "PCIE2",},
  249. {0x3300, "SHA2_1",},
  250. {0x1200, "GPU",},
  251. {0x1000, "IPU1",},
  252. {0x1100, "IPU2",},
  253. {0x2000, "TPCC_EDMA",},
  254. {0x2e00, "TPTC1_EDMA",},
  255. {0x2b00, "TPTC2_EDMA",},
  256. {0x0700, "VCP1",},
  257. {0x2500, "L4_PER2_P3",},
  258. {0x0e00, "L4_PER3_P3",},
  259. {0x2200, "MMU1",},
  260. {0x1400, "PRUSS1",},
  261. {0x1500, "PRUSS2"},
  262. {0x0800, "VCP1",},
  263. };
  264. static struct l3_flagmux_data dra_l3_flagmux_clk1 = {
  265. .offset = 0x803500,
  266. .l3_targ = dra_l3_target_data_clk1,
  267. .num_targ_data = ARRAY_SIZE(dra_l3_target_data_clk1),
  268. };
  269. static struct l3_target_data dra_l3_target_data_clk2[] = {
  270. {0x0, "HOST CLK1",},
  271. {0x800000, "HOST CLK2",},
  272. {0xdead, L3_TARGET_NOT_SUPPORTED,},
  273. {0x3400, "SHA2_2",},
  274. {0x0900, "BB2D",},
  275. {0xdead, L3_TARGET_NOT_SUPPORTED,},
  276. {0x2100, "L4_PER1_P3",},
  277. {0x1c00, "L4_PER1_P1",},
  278. {0x1f00, "L4_PER1_P2",},
  279. {0x2300, "L4_PER2_P1",},
  280. {0x2400, "L4_PER2_P2",},
  281. {0x2600, "L4_PER3_P1",},
  282. {0x2700, "L4_PER3_P2",},
  283. {0x2f00, "MCASP1",},
  284. {0x3000, "MCASP2",},
  285. {0x3100, "MCASP3",},
  286. {0x2800, "MMU2",},
  287. {0x0f00, "OCMC_RAM1",},
  288. {0x1700, "OCMC_RAM2",},
  289. {0x1900, "OCMC_RAM3",},
  290. {0x1e00, "OCMC_ROM",},
  291. {0x3900, "QSPI",},
  292. };
  293. static struct l3_flagmux_data dra_l3_flagmux_clk2 = {
  294. .offset = 0x803600,
  295. .l3_targ = dra_l3_target_data_clk2,
  296. .num_targ_data = ARRAY_SIZE(dra_l3_target_data_clk2),
  297. };
  298. static struct l3_target_data dra_l3_target_data_clk3[] = {
  299. {0x0100, "L3_INSTR"},
  300. {0x0300, "DEBUGSS_CT_TBR"},
  301. {0x0, "HOST CLK3"},
  302. };
  303. static struct l3_flagmux_data dra_l3_flagmux_clk3 = {
  304. .offset = 0x200,
  305. .l3_targ = dra_l3_target_data_clk3,
  306. .num_targ_data = ARRAY_SIZE(dra_l3_target_data_clk3),
  307. };
  308. static struct l3_masters_data dra_l3_masters[] = {
  309. { 0x0, "MPU" },
  310. { 0x4, "CS_DAP" },
  311. { 0x5, "IEEE1500_2_OCP" },
  312. { 0x8, "DSP1_MDMA" },
  313. { 0x9, "DSP1_CFG" },
  314. { 0xA, "DSP1_DMA" },
  315. { 0xB, "DSP2_MDMA" },
  316. { 0xC, "DSP2_CFG" },
  317. { 0xD, "DSP2_DMA" },
  318. { 0xE, "IVA" },
  319. { 0x10, "EVE1_P1" },
  320. { 0x11, "EVE2_P1" },
  321. { 0x12, "EVE3_P1" },
  322. { 0x13, "EVE4_P1" },
  323. { 0x14, "PRUSS1 PRU1" },
  324. { 0x15, "PRUSS1 PRU2" },
  325. { 0x16, "PRUSS2 PRU1" },
  326. { 0x17, "PRUSS2 PRU2" },
  327. { 0x18, "IPU1" },
  328. { 0x19, "IPU2" },
  329. { 0x1A, "SDMA" },
  330. { 0x1B, "CDMA" },
  331. { 0x1C, "TC1_EDMA" },
  332. { 0x1D, "TC2_EDMA" },
  333. { 0x20, "DSS" },
  334. { 0x21, "MMU1" },
  335. { 0x22, "PCIE1" },
  336. { 0x23, "MMU2" },
  337. { 0x24, "VIP1" },
  338. { 0x25, "VIP2" },
  339. { 0x26, "VIP3" },
  340. { 0x27, "VPE" },
  341. { 0x28, "GPU_P1" },
  342. { 0x29, "BB2D" },
  343. { 0x29, "GPU_P2" },
  344. { 0x2B, "GMAC_SW" },
  345. { 0x2C, "USB3" },
  346. { 0x2D, "USB2_SS" },
  347. { 0x2E, "USB2_ULPI_SS1" },
  348. { 0x2F, "USB2_ULPI_SS2" },
  349. { 0x30, "CSI2_1" },
  350. { 0x31, "CSI2_2" },
  351. { 0x33, "SATA" },
  352. { 0x34, "EVE1_P2" },
  353. { 0x35, "EVE2_P2" },
  354. { 0x36, "EVE3_P2" },
  355. { 0x37, "EVE4_P2" }
  356. };
  357. static struct l3_flagmux_data *dra_l3_flagmux[] = {
  358. &dra_l3_flagmux_clk1,
  359. &dra_l3_flagmux_clk2,
  360. &dra_l3_flagmux_clk3,
  361. };
  362. static const struct omap_l3 dra_l3_data = {
  363. .l3_base = { [1] = L3_BASE_IS_SUBMODULE },
  364. .l3_flagmux = dra_l3_flagmux,
  365. .num_modules = ARRAY_SIZE(dra_l3_flagmux),
  366. .l3_masters = dra_l3_masters,
  367. .num_masters = ARRAY_SIZE(dra_l3_masters),
  368. /* The 6 MSBs of register field used to distinguish initiator */
  369. .mst_addr_mask = 0xFC,
  370. };
  371. /* AM4372 data */
  372. static struct l3_target_data am4372_l3_target_data_200f[] = {
  373. {0xf00, "EMIF",},
  374. {0x1200, "DES",},
  375. {0x400, "OCMCRAM",},
  376. {0x700, "TPTC0",},
  377. {0x800, "TPTC1",},
  378. {0x900, "TPTC2"},
  379. {0xb00, "TPCC",},
  380. {0xd00, "DEBUGSS",},
  381. {0xdead, L3_TARGET_NOT_SUPPORTED,},
  382. {0x200, "SHA",},
  383. {0xc00, "SGX530",},
  384. {0x500, "AES0",},
  385. {0xa00, "L4_FAST",},
  386. {0x300, "MPUSS_L2_RAM",},
  387. {0x100, "ICSS",},
  388. };
  389. static struct l3_flagmux_data am4372_l3_flagmux_200f = {
  390. .offset = 0x1000,
  391. .l3_targ = am4372_l3_target_data_200f,
  392. .num_targ_data = ARRAY_SIZE(am4372_l3_target_data_200f),
  393. };
  394. static struct l3_target_data am4372_l3_target_data_100s[] = {
  395. {0x100, "L4_PER_0",},
  396. {0x200, "L4_PER_1",},
  397. {0x300, "L4_PER_2",},
  398. {0x400, "L4_PER_3",},
  399. {0x800, "McASP0",},
  400. {0x900, "McASP1",},
  401. {0xC00, "MMCHS2",},
  402. {0x700, "GPMC",},
  403. {0xD00, "L4_FW",},
  404. {0xdead, L3_TARGET_NOT_SUPPORTED,},
  405. {0x500, "ADCTSC",},
  406. {0xE00, "L4_WKUP",},
  407. {0xA00, "MAG_CARD",},
  408. };
  409. static struct l3_flagmux_data am4372_l3_flagmux_100s = {
  410. .offset = 0x600,
  411. .l3_targ = am4372_l3_target_data_100s,
  412. .num_targ_data = ARRAY_SIZE(am4372_l3_target_data_100s),
  413. };
  414. static struct l3_masters_data am4372_l3_masters[] = {
  415. { 0x0, "M1 (128-bit)"},
  416. { 0x1, "M2 (64-bit)"},
  417. { 0x4, "DAP"},
  418. { 0x5, "P1500"},
  419. { 0xC, "ICSS0"},
  420. { 0xD, "ICSS1"},
  421. { 0x14, "Wakeup Processor"},
  422. { 0x18, "TPTC0 Read"},
  423. { 0x19, "TPTC0 Write"},
  424. { 0x1A, "TPTC1 Read"},
  425. { 0x1B, "TPTC1 Write"},
  426. { 0x1C, "TPTC2 Read"},
  427. { 0x1D, "TPTC2 Write"},
  428. { 0x20, "SGX530"},
  429. { 0x21, "OCP WP Traffic Probe"},
  430. { 0x22, "OCP WP DMA Profiling"},
  431. { 0x23, "OCP WP Event Trace"},
  432. { 0x25, "DSS"},
  433. { 0x28, "Crypto DMA RD"},
  434. { 0x29, "Crypto DMA WR"},
  435. { 0x2C, "VPFE0"},
  436. { 0x2D, "VPFE1"},
  437. { 0x30, "GEMAC"},
  438. { 0x34, "USB0 RD"},
  439. { 0x35, "USB0 WR"},
  440. { 0x36, "USB1 RD"},
  441. { 0x37, "USB1 WR"},
  442. };
  443. static struct l3_flagmux_data *am4372_l3_flagmux[] = {
  444. &am4372_l3_flagmux_200f,
  445. &am4372_l3_flagmux_100s,
  446. };
  447. static const struct omap_l3 am4372_l3_data = {
  448. .l3_flagmux = am4372_l3_flagmux,
  449. .num_modules = ARRAY_SIZE(am4372_l3_flagmux),
  450. .l3_masters = am4372_l3_masters,
  451. .num_masters = ARRAY_SIZE(am4372_l3_masters),
  452. /* All 6 bits of register field used to distinguish initiator */
  453. .mst_addr_mask = 0x3F,
  454. };
  455. #endif /* __OMAP_L3_NOC_H */