reg.h 2.1 KB

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  1. /*
  2. * Copyright 2014, Michael Ellerman, IBM Corp.
  3. * Licensed under GPLv2.
  4. */
  5. #ifndef _SELFTESTS_POWERPC_REG_H
  6. #define _SELFTESTS_POWERPC_REG_H
  7. #define __stringify_1(x) #x
  8. #define __stringify(x) __stringify_1(x)
  9. #define mfspr(rn) ({unsigned long rval; \
  10. asm volatile("mfspr %0," _str(rn) \
  11. : "=r" (rval)); rval; })
  12. #define mtspr(rn, v) asm volatile("mtspr " _str(rn) ",%0" : \
  13. : "r" ((unsigned long)(v)) \
  14. : "memory")
  15. #define mb() asm volatile("sync" : : : "memory");
  16. #define SPRN_MMCR2 769
  17. #define SPRN_MMCRA 770
  18. #define SPRN_MMCR0 779
  19. #define MMCR0_PMAO 0x00000080
  20. #define MMCR0_PMAE 0x04000000
  21. #define MMCR0_FC 0x80000000
  22. #define SPRN_EBBHR 804
  23. #define SPRN_EBBRR 805
  24. #define SPRN_BESCR 806 /* Branch event status & control register */
  25. #define SPRN_BESCRS 800 /* Branch event status & control set (1 bits set to 1) */
  26. #define SPRN_BESCRSU 801 /* Branch event status & control set upper */
  27. #define SPRN_BESCRR 802 /* Branch event status & control REset (1 bits set to 0) */
  28. #define SPRN_BESCRRU 803 /* Branch event status & control REset upper */
  29. #define BESCR_PMEO 0x1 /* PMU Event-based exception Occurred */
  30. #define BESCR_PME (0x1ul << 32) /* PMU Event-based exception Enable */
  31. #define BESCR_LME (0x1ul << 34) /* Load Monitor Enable */
  32. #define BESCR_LMEO (0x1ul << 2) /* Load Monitor Exception Occurred */
  33. #define SPRN_LMRR 813 /* Load Monitor Region Register */
  34. #define SPRN_LMSER 814 /* Load Monitor Section Enable Register */
  35. #define SPRN_PMC1 771
  36. #define SPRN_PMC2 772
  37. #define SPRN_PMC3 773
  38. #define SPRN_PMC4 774
  39. #define SPRN_PMC5 775
  40. #define SPRN_PMC6 776
  41. #define SPRN_SIAR 780
  42. #define SPRN_SDAR 781
  43. #define SPRN_SIER 768
  44. #define SPRN_TEXASR 0x82
  45. #define SPRN_TFIAR 0x81 /* Transaction Failure Inst Addr */
  46. #define SPRN_TFHAR 0x80 /* Transaction Failure Handler Addr */
  47. #define TEXASR_FS 0x08000000
  48. #define SPRN_TAR 0x32f
  49. #endif /* _SELFTESTS_POWERPC_REG_H */