devices.c 25 KB

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  1. #include <linux/module.h>
  2. #include <linux/kernel.h>
  3. #include <linux/init.h>
  4. #include <linux/platform_device.h>
  5. #include <linux/dma-mapping.h>
  6. #include <linux/spi/pxa2xx_spi.h>
  7. #include <linux/i2c/pxa-i2c.h>
  8. #include "udc.h"
  9. #include <linux/platform_data/usb-pxa3xx-ulpi.h>
  10. #include <linux/platform_data/video-pxafb.h>
  11. #include <linux/platform_data/mmc-pxamci.h>
  12. #include <linux/platform_data/irda-pxaficp.h>
  13. #include <mach/irqs.h>
  14. #include <linux/platform_data/usb-ohci-pxa27x.h>
  15. #include <linux/platform_data/keypad-pxa27x.h>
  16. #include <linux/platform_data/media/camera-pxa.h>
  17. #include <mach/audio.h>
  18. #include <mach/hardware.h>
  19. #include <linux/platform_data/mmp_dma.h>
  20. #include <linux/platform_data/mtd-nand-pxa3xx.h>
  21. #include "devices.h"
  22. #include "generic.h"
  23. void __init pxa_register_device(struct platform_device *dev, void *data)
  24. {
  25. int ret;
  26. dev->dev.platform_data = data;
  27. ret = platform_device_register(dev);
  28. if (ret)
  29. dev_err(&dev->dev, "unable to register device: %d\n", ret);
  30. }
  31. static struct resource pxa_resource_pmu = {
  32. .start = IRQ_PMU,
  33. .end = IRQ_PMU,
  34. .flags = IORESOURCE_IRQ,
  35. };
  36. struct platform_device pxa_device_pmu = {
  37. .name = "xscale-pmu",
  38. .id = -1,
  39. .resource = &pxa_resource_pmu,
  40. .num_resources = 1,
  41. };
  42. static struct resource pxamci_resources[] = {
  43. [0] = {
  44. .start = 0x41100000,
  45. .end = 0x41100fff,
  46. .flags = IORESOURCE_MEM,
  47. },
  48. [1] = {
  49. .start = IRQ_MMC,
  50. .end = IRQ_MMC,
  51. .flags = IORESOURCE_IRQ,
  52. },
  53. [2] = {
  54. .start = 21,
  55. .end = 21,
  56. .flags = IORESOURCE_DMA,
  57. },
  58. [3] = {
  59. .start = 22,
  60. .end = 22,
  61. .flags = IORESOURCE_DMA,
  62. },
  63. };
  64. static u64 pxamci_dmamask = 0xffffffffUL;
  65. struct platform_device pxa_device_mci = {
  66. .name = "pxa2xx-mci",
  67. .id = 0,
  68. .dev = {
  69. .dma_mask = &pxamci_dmamask,
  70. .coherent_dma_mask = 0xffffffff,
  71. },
  72. .num_resources = ARRAY_SIZE(pxamci_resources),
  73. .resource = pxamci_resources,
  74. };
  75. void __init pxa_set_mci_info(struct pxamci_platform_data *info)
  76. {
  77. pxa_register_device(&pxa_device_mci, info);
  78. }
  79. static struct pxa2xx_udc_mach_info pxa_udc_info = {
  80. .gpio_pullup = -1,
  81. };
  82. void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
  83. {
  84. memcpy(&pxa_udc_info, info, sizeof *info);
  85. }
  86. static struct resource pxa2xx_udc_resources[] = {
  87. [0] = {
  88. .start = 0x40600000,
  89. .end = 0x4060ffff,
  90. .flags = IORESOURCE_MEM,
  91. },
  92. [1] = {
  93. .start = IRQ_USB,
  94. .end = IRQ_USB,
  95. .flags = IORESOURCE_IRQ,
  96. },
  97. };
  98. static u64 udc_dma_mask = ~(u32)0;
  99. struct platform_device pxa25x_device_udc = {
  100. .name = "pxa25x-udc",
  101. .id = -1,
  102. .resource = pxa2xx_udc_resources,
  103. .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
  104. .dev = {
  105. .platform_data = &pxa_udc_info,
  106. .dma_mask = &udc_dma_mask,
  107. }
  108. };
  109. struct platform_device pxa27x_device_udc = {
  110. .name = "pxa27x-udc",
  111. .id = -1,
  112. .resource = pxa2xx_udc_resources,
  113. .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
  114. .dev = {
  115. .platform_data = &pxa_udc_info,
  116. .dma_mask = &udc_dma_mask,
  117. }
  118. };
  119. #ifdef CONFIG_PXA3xx
  120. static struct resource pxa3xx_u2d_resources[] = {
  121. [0] = {
  122. .start = 0x54100000,
  123. .end = 0x54100fff,
  124. .flags = IORESOURCE_MEM,
  125. },
  126. [1] = {
  127. .start = IRQ_USB2,
  128. .end = IRQ_USB2,
  129. .flags = IORESOURCE_IRQ,
  130. },
  131. };
  132. struct platform_device pxa3xx_device_u2d = {
  133. .name = "pxa3xx-u2d",
  134. .id = -1,
  135. .resource = pxa3xx_u2d_resources,
  136. .num_resources = ARRAY_SIZE(pxa3xx_u2d_resources),
  137. };
  138. void __init pxa3xx_set_u2d_info(struct pxa3xx_u2d_platform_data *info)
  139. {
  140. pxa_register_device(&pxa3xx_device_u2d, info);
  141. }
  142. #endif /* CONFIG_PXA3xx */
  143. static struct resource pxafb_resources[] = {
  144. [0] = {
  145. .start = 0x44000000,
  146. .end = 0x4400ffff,
  147. .flags = IORESOURCE_MEM,
  148. },
  149. [1] = {
  150. .start = IRQ_LCD,
  151. .end = IRQ_LCD,
  152. .flags = IORESOURCE_IRQ,
  153. },
  154. };
  155. static u64 fb_dma_mask = ~(u64)0;
  156. struct platform_device pxa_device_fb = {
  157. .name = "pxa2xx-fb",
  158. .id = -1,
  159. .dev = {
  160. .dma_mask = &fb_dma_mask,
  161. .coherent_dma_mask = 0xffffffff,
  162. },
  163. .num_resources = ARRAY_SIZE(pxafb_resources),
  164. .resource = pxafb_resources,
  165. };
  166. void __init pxa_set_fb_info(struct device *parent, struct pxafb_mach_info *info)
  167. {
  168. pxa_device_fb.dev.parent = parent;
  169. pxa_register_device(&pxa_device_fb, info);
  170. }
  171. static struct resource pxa_resource_ffuart[] = {
  172. {
  173. .start = 0x40100000,
  174. .end = 0x40100023,
  175. .flags = IORESOURCE_MEM,
  176. }, {
  177. .start = IRQ_FFUART,
  178. .end = IRQ_FFUART,
  179. .flags = IORESOURCE_IRQ,
  180. }
  181. };
  182. struct platform_device pxa_device_ffuart = {
  183. .name = "pxa2xx-uart",
  184. .id = 0,
  185. .resource = pxa_resource_ffuart,
  186. .num_resources = ARRAY_SIZE(pxa_resource_ffuart),
  187. };
  188. void __init pxa_set_ffuart_info(void *info)
  189. {
  190. pxa_register_device(&pxa_device_ffuart, info);
  191. }
  192. static struct resource pxa_resource_btuart[] = {
  193. {
  194. .start = 0x40200000,
  195. .end = 0x40200023,
  196. .flags = IORESOURCE_MEM,
  197. }, {
  198. .start = IRQ_BTUART,
  199. .end = IRQ_BTUART,
  200. .flags = IORESOURCE_IRQ,
  201. }
  202. };
  203. struct platform_device pxa_device_btuart = {
  204. .name = "pxa2xx-uart",
  205. .id = 1,
  206. .resource = pxa_resource_btuart,
  207. .num_resources = ARRAY_SIZE(pxa_resource_btuart),
  208. };
  209. void __init pxa_set_btuart_info(void *info)
  210. {
  211. pxa_register_device(&pxa_device_btuart, info);
  212. }
  213. static struct resource pxa_resource_stuart[] = {
  214. {
  215. .start = 0x40700000,
  216. .end = 0x40700023,
  217. .flags = IORESOURCE_MEM,
  218. }, {
  219. .start = IRQ_STUART,
  220. .end = IRQ_STUART,
  221. .flags = IORESOURCE_IRQ,
  222. }
  223. };
  224. struct platform_device pxa_device_stuart = {
  225. .name = "pxa2xx-uart",
  226. .id = 2,
  227. .resource = pxa_resource_stuart,
  228. .num_resources = ARRAY_SIZE(pxa_resource_stuart),
  229. };
  230. void __init pxa_set_stuart_info(void *info)
  231. {
  232. pxa_register_device(&pxa_device_stuart, info);
  233. }
  234. static struct resource pxa_resource_hwuart[] = {
  235. {
  236. .start = 0x41600000,
  237. .end = 0x4160002F,
  238. .flags = IORESOURCE_MEM,
  239. }, {
  240. .start = IRQ_HWUART,
  241. .end = IRQ_HWUART,
  242. .flags = IORESOURCE_IRQ,
  243. }
  244. };
  245. struct platform_device pxa_device_hwuart = {
  246. .name = "pxa2xx-uart",
  247. .id = 3,
  248. .resource = pxa_resource_hwuart,
  249. .num_resources = ARRAY_SIZE(pxa_resource_hwuart),
  250. };
  251. void __init pxa_set_hwuart_info(void *info)
  252. {
  253. if (cpu_is_pxa255())
  254. pxa_register_device(&pxa_device_hwuart, info);
  255. else
  256. pr_info("UART: Ignoring attempt to register HWUART on non-PXA255 hardware");
  257. }
  258. static struct resource pxai2c_resources[] = {
  259. {
  260. .start = 0x40301680,
  261. .end = 0x403016a3,
  262. .flags = IORESOURCE_MEM,
  263. }, {
  264. .start = IRQ_I2C,
  265. .end = IRQ_I2C,
  266. .flags = IORESOURCE_IRQ,
  267. },
  268. };
  269. struct platform_device pxa_device_i2c = {
  270. .name = "pxa2xx-i2c",
  271. .id = 0,
  272. .resource = pxai2c_resources,
  273. .num_resources = ARRAY_SIZE(pxai2c_resources),
  274. };
  275. void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
  276. {
  277. pxa_register_device(&pxa_device_i2c, info);
  278. }
  279. #ifdef CONFIG_PXA27x
  280. static struct resource pxa27x_resources_i2c_power[] = {
  281. {
  282. .start = 0x40f00180,
  283. .end = 0x40f001a3,
  284. .flags = IORESOURCE_MEM,
  285. }, {
  286. .start = IRQ_PWRI2C,
  287. .end = IRQ_PWRI2C,
  288. .flags = IORESOURCE_IRQ,
  289. },
  290. };
  291. struct platform_device pxa27x_device_i2c_power = {
  292. .name = "pxa2xx-i2c",
  293. .id = 1,
  294. .resource = pxa27x_resources_i2c_power,
  295. .num_resources = ARRAY_SIZE(pxa27x_resources_i2c_power),
  296. };
  297. #endif
  298. static struct resource pxai2s_resources[] = {
  299. {
  300. .start = 0x40400000,
  301. .end = 0x40400083,
  302. .flags = IORESOURCE_MEM,
  303. }, {
  304. .start = IRQ_I2S,
  305. .end = IRQ_I2S,
  306. .flags = IORESOURCE_IRQ,
  307. },
  308. };
  309. struct platform_device pxa_device_i2s = {
  310. .name = "pxa2xx-i2s",
  311. .id = -1,
  312. .resource = pxai2s_resources,
  313. .num_resources = ARRAY_SIZE(pxai2s_resources),
  314. };
  315. struct platform_device pxa_device_asoc_ssp1 = {
  316. .name = "pxa-ssp-dai",
  317. .id = 0,
  318. };
  319. struct platform_device pxa_device_asoc_ssp2= {
  320. .name = "pxa-ssp-dai",
  321. .id = 1,
  322. };
  323. struct platform_device pxa_device_asoc_ssp3 = {
  324. .name = "pxa-ssp-dai",
  325. .id = 2,
  326. };
  327. struct platform_device pxa_device_asoc_ssp4 = {
  328. .name = "pxa-ssp-dai",
  329. .id = 3,
  330. };
  331. struct platform_device pxa_device_asoc_platform = {
  332. .name = "pxa-pcm-audio",
  333. .id = -1,
  334. };
  335. static u64 pxaficp_dmamask = ~(u32)0;
  336. static struct resource pxa_ir_resources[] = {
  337. [0] = {
  338. .start = IRQ_STUART,
  339. .end = IRQ_STUART,
  340. .flags = IORESOURCE_IRQ,
  341. },
  342. [1] = {
  343. .start = IRQ_ICP,
  344. .end = IRQ_ICP,
  345. .flags = IORESOURCE_IRQ,
  346. },
  347. [3] = {
  348. .start = 0x40800000,
  349. .end = 0x4080001b,
  350. .flags = IORESOURCE_MEM,
  351. },
  352. [4] = {
  353. .start = 0x40700000,
  354. .end = 0x40700023,
  355. .flags = IORESOURCE_MEM,
  356. },
  357. [5] = {
  358. .start = 17,
  359. .end = 17,
  360. .flags = IORESOURCE_DMA,
  361. },
  362. [6] = {
  363. .start = 18,
  364. .end = 18,
  365. .flags = IORESOURCE_DMA,
  366. },
  367. };
  368. struct platform_device pxa_device_ficp = {
  369. .name = "pxa2xx-ir",
  370. .id = -1,
  371. .num_resources = ARRAY_SIZE(pxa_ir_resources),
  372. .resource = pxa_ir_resources,
  373. .dev = {
  374. .dma_mask = &pxaficp_dmamask,
  375. .coherent_dma_mask = 0xffffffff,
  376. },
  377. };
  378. void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
  379. {
  380. pxa_register_device(&pxa_device_ficp, info);
  381. }
  382. static struct resource pxa_rtc_resources[] = {
  383. [0] = {
  384. .start = 0x40900000,
  385. .end = 0x40900000 + 0x3b,
  386. .flags = IORESOURCE_MEM,
  387. },
  388. [1] = {
  389. .start = IRQ_RTC1Hz,
  390. .end = IRQ_RTC1Hz,
  391. .name = "rtc 1Hz",
  392. .flags = IORESOURCE_IRQ,
  393. },
  394. [2] = {
  395. .start = IRQ_RTCAlrm,
  396. .end = IRQ_RTCAlrm,
  397. .name = "rtc alarm",
  398. .flags = IORESOURCE_IRQ,
  399. },
  400. };
  401. struct platform_device pxa_device_rtc = {
  402. .name = "pxa-rtc",
  403. .id = -1,
  404. .num_resources = ARRAY_SIZE(pxa_rtc_resources),
  405. .resource = pxa_rtc_resources,
  406. };
  407. struct platform_device sa1100_device_rtc = {
  408. .name = "sa1100-rtc",
  409. .id = -1,
  410. .num_resources = ARRAY_SIZE(pxa_rtc_resources),
  411. .resource = pxa_rtc_resources,
  412. };
  413. static struct resource pxa_ac97_resources[] = {
  414. [0] = {
  415. .start = 0x40500000,
  416. .end = 0x40500000 + 0xfff,
  417. .flags = IORESOURCE_MEM,
  418. },
  419. [1] = {
  420. .start = IRQ_AC97,
  421. .end = IRQ_AC97,
  422. .flags = IORESOURCE_IRQ,
  423. },
  424. };
  425. static u64 pxa_ac97_dmamask = 0xffffffffUL;
  426. struct platform_device pxa_device_ac97 = {
  427. .name = "pxa2xx-ac97",
  428. .id = -1,
  429. .dev = {
  430. .dma_mask = &pxa_ac97_dmamask,
  431. .coherent_dma_mask = 0xffffffff,
  432. },
  433. .num_resources = ARRAY_SIZE(pxa_ac97_resources),
  434. .resource = pxa_ac97_resources,
  435. };
  436. void __init pxa_set_ac97_info(pxa2xx_audio_ops_t *ops)
  437. {
  438. pxa_register_device(&pxa_device_ac97, ops);
  439. }
  440. #ifdef CONFIG_PXA25x
  441. static struct resource pxa25x_resource_pwm0[] = {
  442. [0] = {
  443. .start = 0x40b00000,
  444. .end = 0x40b0000f,
  445. .flags = IORESOURCE_MEM,
  446. },
  447. };
  448. struct platform_device pxa25x_device_pwm0 = {
  449. .name = "pxa25x-pwm",
  450. .id = 0,
  451. .resource = pxa25x_resource_pwm0,
  452. .num_resources = ARRAY_SIZE(pxa25x_resource_pwm0),
  453. };
  454. static struct resource pxa25x_resource_pwm1[] = {
  455. [0] = {
  456. .start = 0x40c00000,
  457. .end = 0x40c0000f,
  458. .flags = IORESOURCE_MEM,
  459. },
  460. };
  461. struct platform_device pxa25x_device_pwm1 = {
  462. .name = "pxa25x-pwm",
  463. .id = 1,
  464. .resource = pxa25x_resource_pwm1,
  465. .num_resources = ARRAY_SIZE(pxa25x_resource_pwm1),
  466. };
  467. static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
  468. static struct resource pxa25x_resource_ssp[] = {
  469. [0] = {
  470. .start = 0x41000000,
  471. .end = 0x4100001f,
  472. .flags = IORESOURCE_MEM,
  473. },
  474. [1] = {
  475. .start = IRQ_SSP,
  476. .end = IRQ_SSP,
  477. .flags = IORESOURCE_IRQ,
  478. },
  479. [2] = {
  480. /* DRCMR for RX */
  481. .start = 13,
  482. .end = 13,
  483. .flags = IORESOURCE_DMA,
  484. },
  485. [3] = {
  486. /* DRCMR for TX */
  487. .start = 14,
  488. .end = 14,
  489. .flags = IORESOURCE_DMA,
  490. },
  491. };
  492. struct platform_device pxa25x_device_ssp = {
  493. .name = "pxa25x-ssp",
  494. .id = 0,
  495. .dev = {
  496. .dma_mask = &pxa25x_ssp_dma_mask,
  497. .coherent_dma_mask = DMA_BIT_MASK(32),
  498. },
  499. .resource = pxa25x_resource_ssp,
  500. .num_resources = ARRAY_SIZE(pxa25x_resource_ssp),
  501. };
  502. static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);
  503. static struct resource pxa25x_resource_nssp[] = {
  504. [0] = {
  505. .start = 0x41400000,
  506. .end = 0x4140002f,
  507. .flags = IORESOURCE_MEM,
  508. },
  509. [1] = {
  510. .start = IRQ_NSSP,
  511. .end = IRQ_NSSP,
  512. .flags = IORESOURCE_IRQ,
  513. },
  514. [2] = {
  515. /* DRCMR for RX */
  516. .start = 15,
  517. .end = 15,
  518. .flags = IORESOURCE_DMA,
  519. },
  520. [3] = {
  521. /* DRCMR for TX */
  522. .start = 16,
  523. .end = 16,
  524. .flags = IORESOURCE_DMA,
  525. },
  526. };
  527. struct platform_device pxa25x_device_nssp = {
  528. .name = "pxa25x-nssp",
  529. .id = 1,
  530. .dev = {
  531. .dma_mask = &pxa25x_nssp_dma_mask,
  532. .coherent_dma_mask = DMA_BIT_MASK(32),
  533. },
  534. .resource = pxa25x_resource_nssp,
  535. .num_resources = ARRAY_SIZE(pxa25x_resource_nssp),
  536. };
  537. static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);
  538. static struct resource pxa25x_resource_assp[] = {
  539. [0] = {
  540. .start = 0x41500000,
  541. .end = 0x4150002f,
  542. .flags = IORESOURCE_MEM,
  543. },
  544. [1] = {
  545. .start = IRQ_ASSP,
  546. .end = IRQ_ASSP,
  547. .flags = IORESOURCE_IRQ,
  548. },
  549. [2] = {
  550. /* DRCMR for RX */
  551. .start = 23,
  552. .end = 23,
  553. .flags = IORESOURCE_DMA,
  554. },
  555. [3] = {
  556. /* DRCMR for TX */
  557. .start = 24,
  558. .end = 24,
  559. .flags = IORESOURCE_DMA,
  560. },
  561. };
  562. struct platform_device pxa25x_device_assp = {
  563. /* ASSP is basically equivalent to NSSP */
  564. .name = "pxa25x-nssp",
  565. .id = 2,
  566. .dev = {
  567. .dma_mask = &pxa25x_assp_dma_mask,
  568. .coherent_dma_mask = DMA_BIT_MASK(32),
  569. },
  570. .resource = pxa25x_resource_assp,
  571. .num_resources = ARRAY_SIZE(pxa25x_resource_assp),
  572. };
  573. #endif /* CONFIG_PXA25x */
  574. #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
  575. static struct resource pxa27x_resource_camera[] = {
  576. [0] = {
  577. .start = 0x50000000,
  578. .end = 0x50000fff,
  579. .flags = IORESOURCE_MEM,
  580. },
  581. [1] = {
  582. .start = IRQ_CAMERA,
  583. .end = IRQ_CAMERA,
  584. .flags = IORESOURCE_IRQ,
  585. },
  586. };
  587. static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32);
  588. static struct platform_device pxa27x_device_camera = {
  589. .name = "pxa27x-camera",
  590. .id = 0, /* This is used to put cameras on this interface */
  591. .dev = {
  592. .dma_mask = &pxa27x_dma_mask_camera,
  593. .coherent_dma_mask = 0xffffffff,
  594. },
  595. .num_resources = ARRAY_SIZE(pxa27x_resource_camera),
  596. .resource = pxa27x_resource_camera,
  597. };
  598. void __init pxa_set_camera_info(struct pxacamera_platform_data *info)
  599. {
  600. pxa_register_device(&pxa27x_device_camera, info);
  601. }
  602. static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
  603. static struct resource pxa27x_resource_ohci[] = {
  604. [0] = {
  605. .start = 0x4C000000,
  606. .end = 0x4C00ff6f,
  607. .flags = IORESOURCE_MEM,
  608. },
  609. [1] = {
  610. .start = IRQ_USBH1,
  611. .end = IRQ_USBH1,
  612. .flags = IORESOURCE_IRQ,
  613. },
  614. };
  615. struct platform_device pxa27x_device_ohci = {
  616. .name = "pxa27x-ohci",
  617. .id = -1,
  618. .dev = {
  619. .dma_mask = &pxa27x_ohci_dma_mask,
  620. .coherent_dma_mask = DMA_BIT_MASK(32),
  621. },
  622. .num_resources = ARRAY_SIZE(pxa27x_resource_ohci),
  623. .resource = pxa27x_resource_ohci,
  624. };
  625. void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
  626. {
  627. pxa_register_device(&pxa27x_device_ohci, info);
  628. }
  629. #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
  630. #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
  631. static struct resource pxa27x_resource_keypad[] = {
  632. [0] = {
  633. .start = 0x41500000,
  634. .end = 0x4150004c,
  635. .flags = IORESOURCE_MEM,
  636. },
  637. [1] = {
  638. .start = IRQ_KEYPAD,
  639. .end = IRQ_KEYPAD,
  640. .flags = IORESOURCE_IRQ,
  641. },
  642. };
  643. struct platform_device pxa27x_device_keypad = {
  644. .name = "pxa27x-keypad",
  645. .id = -1,
  646. .resource = pxa27x_resource_keypad,
  647. .num_resources = ARRAY_SIZE(pxa27x_resource_keypad),
  648. };
  649. void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info)
  650. {
  651. pxa_register_device(&pxa27x_device_keypad, info);
  652. }
  653. static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
  654. static struct resource pxa27x_resource_ssp1[] = {
  655. [0] = {
  656. .start = 0x41000000,
  657. .end = 0x4100003f,
  658. .flags = IORESOURCE_MEM,
  659. },
  660. [1] = {
  661. .start = IRQ_SSP,
  662. .end = IRQ_SSP,
  663. .flags = IORESOURCE_IRQ,
  664. },
  665. [2] = {
  666. /* DRCMR for RX */
  667. .start = 13,
  668. .end = 13,
  669. .flags = IORESOURCE_DMA,
  670. },
  671. [3] = {
  672. /* DRCMR for TX */
  673. .start = 14,
  674. .end = 14,
  675. .flags = IORESOURCE_DMA,
  676. },
  677. };
  678. struct platform_device pxa27x_device_ssp1 = {
  679. .name = "pxa27x-ssp",
  680. .id = 0,
  681. .dev = {
  682. .dma_mask = &pxa27x_ssp1_dma_mask,
  683. .coherent_dma_mask = DMA_BIT_MASK(32),
  684. },
  685. .resource = pxa27x_resource_ssp1,
  686. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp1),
  687. };
  688. static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);
  689. static struct resource pxa27x_resource_ssp2[] = {
  690. [0] = {
  691. .start = 0x41700000,
  692. .end = 0x4170003f,
  693. .flags = IORESOURCE_MEM,
  694. },
  695. [1] = {
  696. .start = IRQ_SSP2,
  697. .end = IRQ_SSP2,
  698. .flags = IORESOURCE_IRQ,
  699. },
  700. [2] = {
  701. /* DRCMR for RX */
  702. .start = 15,
  703. .end = 15,
  704. .flags = IORESOURCE_DMA,
  705. },
  706. [3] = {
  707. /* DRCMR for TX */
  708. .start = 16,
  709. .end = 16,
  710. .flags = IORESOURCE_DMA,
  711. },
  712. };
  713. struct platform_device pxa27x_device_ssp2 = {
  714. .name = "pxa27x-ssp",
  715. .id = 1,
  716. .dev = {
  717. .dma_mask = &pxa27x_ssp2_dma_mask,
  718. .coherent_dma_mask = DMA_BIT_MASK(32),
  719. },
  720. .resource = pxa27x_resource_ssp2,
  721. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp2),
  722. };
  723. static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);
  724. static struct resource pxa27x_resource_ssp3[] = {
  725. [0] = {
  726. .start = 0x41900000,
  727. .end = 0x4190003f,
  728. .flags = IORESOURCE_MEM,
  729. },
  730. [1] = {
  731. .start = IRQ_SSP3,
  732. .end = IRQ_SSP3,
  733. .flags = IORESOURCE_IRQ,
  734. },
  735. [2] = {
  736. /* DRCMR for RX */
  737. .start = 66,
  738. .end = 66,
  739. .flags = IORESOURCE_DMA,
  740. },
  741. [3] = {
  742. /* DRCMR for TX */
  743. .start = 67,
  744. .end = 67,
  745. .flags = IORESOURCE_DMA,
  746. },
  747. };
  748. struct platform_device pxa27x_device_ssp3 = {
  749. .name = "pxa27x-ssp",
  750. .id = 2,
  751. .dev = {
  752. .dma_mask = &pxa27x_ssp3_dma_mask,
  753. .coherent_dma_mask = DMA_BIT_MASK(32),
  754. },
  755. .resource = pxa27x_resource_ssp3,
  756. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
  757. };
  758. static struct resource pxa27x_resource_pwm0[] = {
  759. [0] = {
  760. .start = 0x40b00000,
  761. .end = 0x40b0001f,
  762. .flags = IORESOURCE_MEM,
  763. },
  764. };
  765. struct platform_device pxa27x_device_pwm0 = {
  766. .name = "pxa27x-pwm",
  767. .id = 0,
  768. .resource = pxa27x_resource_pwm0,
  769. .num_resources = ARRAY_SIZE(pxa27x_resource_pwm0),
  770. };
  771. static struct resource pxa27x_resource_pwm1[] = {
  772. [0] = {
  773. .start = 0x40c00000,
  774. .end = 0x40c0001f,
  775. .flags = IORESOURCE_MEM,
  776. },
  777. };
  778. struct platform_device pxa27x_device_pwm1 = {
  779. .name = "pxa27x-pwm",
  780. .id = 1,
  781. .resource = pxa27x_resource_pwm1,
  782. .num_resources = ARRAY_SIZE(pxa27x_resource_pwm1),
  783. };
  784. #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
  785. #ifdef CONFIG_PXA3xx
  786. static struct resource pxa3xx_resources_mci2[] = {
  787. [0] = {
  788. .start = 0x42000000,
  789. .end = 0x42000fff,
  790. .flags = IORESOURCE_MEM,
  791. },
  792. [1] = {
  793. .start = IRQ_MMC2,
  794. .end = IRQ_MMC2,
  795. .flags = IORESOURCE_IRQ,
  796. },
  797. [2] = {
  798. .start = 93,
  799. .end = 93,
  800. .flags = IORESOURCE_DMA,
  801. },
  802. [3] = {
  803. .start = 94,
  804. .end = 94,
  805. .flags = IORESOURCE_DMA,
  806. },
  807. };
  808. struct platform_device pxa3xx_device_mci2 = {
  809. .name = "pxa2xx-mci",
  810. .id = 1,
  811. .dev = {
  812. .dma_mask = &pxamci_dmamask,
  813. .coherent_dma_mask = 0xffffffff,
  814. },
  815. .num_resources = ARRAY_SIZE(pxa3xx_resources_mci2),
  816. .resource = pxa3xx_resources_mci2,
  817. };
  818. void __init pxa3xx_set_mci2_info(struct pxamci_platform_data *info)
  819. {
  820. pxa_register_device(&pxa3xx_device_mci2, info);
  821. }
  822. static struct resource pxa3xx_resources_mci3[] = {
  823. [0] = {
  824. .start = 0x42500000,
  825. .end = 0x42500fff,
  826. .flags = IORESOURCE_MEM,
  827. },
  828. [1] = {
  829. .start = IRQ_MMC3,
  830. .end = IRQ_MMC3,
  831. .flags = IORESOURCE_IRQ,
  832. },
  833. [2] = {
  834. .start = 100,
  835. .end = 100,
  836. .flags = IORESOURCE_DMA,
  837. },
  838. [3] = {
  839. .start = 101,
  840. .end = 101,
  841. .flags = IORESOURCE_DMA,
  842. },
  843. };
  844. struct platform_device pxa3xx_device_mci3 = {
  845. .name = "pxa2xx-mci",
  846. .id = 2,
  847. .dev = {
  848. .dma_mask = &pxamci_dmamask,
  849. .coherent_dma_mask = 0xffffffff,
  850. },
  851. .num_resources = ARRAY_SIZE(pxa3xx_resources_mci3),
  852. .resource = pxa3xx_resources_mci3,
  853. };
  854. void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info)
  855. {
  856. pxa_register_device(&pxa3xx_device_mci3, info);
  857. }
  858. static struct resource pxa3xx_resources_gcu[] = {
  859. {
  860. .start = 0x54000000,
  861. .end = 0x54000fff,
  862. .flags = IORESOURCE_MEM,
  863. },
  864. {
  865. .start = IRQ_GCU,
  866. .end = IRQ_GCU,
  867. .flags = IORESOURCE_IRQ,
  868. },
  869. };
  870. static u64 pxa3xx_gcu_dmamask = DMA_BIT_MASK(32);
  871. struct platform_device pxa3xx_device_gcu = {
  872. .name = "pxa3xx-gcu",
  873. .id = -1,
  874. .num_resources = ARRAY_SIZE(pxa3xx_resources_gcu),
  875. .resource = pxa3xx_resources_gcu,
  876. .dev = {
  877. .dma_mask = &pxa3xx_gcu_dmamask,
  878. .coherent_dma_mask = 0xffffffff,
  879. },
  880. };
  881. #endif /* CONFIG_PXA3xx */
  882. #if defined(CONFIG_PXA3xx)
  883. static struct resource pxa3xx_resources_i2c_power[] = {
  884. {
  885. .start = 0x40f500c0,
  886. .end = 0x40f500d3,
  887. .flags = IORESOURCE_MEM,
  888. }, {
  889. .start = IRQ_PWRI2C,
  890. .end = IRQ_PWRI2C,
  891. .flags = IORESOURCE_IRQ,
  892. },
  893. };
  894. struct platform_device pxa3xx_device_i2c_power = {
  895. .name = "pxa3xx-pwri2c",
  896. .id = 1,
  897. .resource = pxa3xx_resources_i2c_power,
  898. .num_resources = ARRAY_SIZE(pxa3xx_resources_i2c_power),
  899. };
  900. static struct resource pxa3xx_resources_nand[] = {
  901. [0] = {
  902. .start = 0x43100000,
  903. .end = 0x43100053,
  904. .flags = IORESOURCE_MEM,
  905. },
  906. [1] = {
  907. .start = IRQ_NAND,
  908. .end = IRQ_NAND,
  909. .flags = IORESOURCE_IRQ,
  910. },
  911. [2] = {
  912. /* DRCMR for Data DMA */
  913. .start = 97,
  914. .end = 97,
  915. .flags = IORESOURCE_DMA,
  916. },
  917. [3] = {
  918. /* DRCMR for Command DMA */
  919. .start = 99,
  920. .end = 99,
  921. .flags = IORESOURCE_DMA,
  922. },
  923. };
  924. static u64 pxa3xx_nand_dma_mask = DMA_BIT_MASK(32);
  925. struct platform_device pxa3xx_device_nand = {
  926. .name = "pxa3xx-nand",
  927. .id = -1,
  928. .dev = {
  929. .dma_mask = &pxa3xx_nand_dma_mask,
  930. .coherent_dma_mask = DMA_BIT_MASK(32),
  931. },
  932. .num_resources = ARRAY_SIZE(pxa3xx_resources_nand),
  933. .resource = pxa3xx_resources_nand,
  934. };
  935. void __init pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info)
  936. {
  937. pxa_register_device(&pxa3xx_device_nand, info);
  938. }
  939. static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
  940. static struct resource pxa3xx_resource_ssp4[] = {
  941. [0] = {
  942. .start = 0x41a00000,
  943. .end = 0x41a0003f,
  944. .flags = IORESOURCE_MEM,
  945. },
  946. [1] = {
  947. .start = IRQ_SSP4,
  948. .end = IRQ_SSP4,
  949. .flags = IORESOURCE_IRQ,
  950. },
  951. [2] = {
  952. /* DRCMR for RX */
  953. .start = 2,
  954. .end = 2,
  955. .flags = IORESOURCE_DMA,
  956. },
  957. [3] = {
  958. /* DRCMR for TX */
  959. .start = 3,
  960. .end = 3,
  961. .flags = IORESOURCE_DMA,
  962. },
  963. };
  964. /*
  965. * PXA3xx SSP is basically equivalent to PXA27x.
  966. * However, we need to register the device by the correct name in order to
  967. * make the driver set the correct internal type, hence we provide specific
  968. * platform_devices for each of them.
  969. */
  970. struct platform_device pxa3xx_device_ssp1 = {
  971. .name = "pxa3xx-ssp",
  972. .id = 0,
  973. .dev = {
  974. .dma_mask = &pxa27x_ssp1_dma_mask,
  975. .coherent_dma_mask = DMA_BIT_MASK(32),
  976. },
  977. .resource = pxa27x_resource_ssp1,
  978. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp1),
  979. };
  980. struct platform_device pxa3xx_device_ssp2 = {
  981. .name = "pxa3xx-ssp",
  982. .id = 1,
  983. .dev = {
  984. .dma_mask = &pxa27x_ssp2_dma_mask,
  985. .coherent_dma_mask = DMA_BIT_MASK(32),
  986. },
  987. .resource = pxa27x_resource_ssp2,
  988. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp2),
  989. };
  990. struct platform_device pxa3xx_device_ssp3 = {
  991. .name = "pxa3xx-ssp",
  992. .id = 2,
  993. .dev = {
  994. .dma_mask = &pxa27x_ssp3_dma_mask,
  995. .coherent_dma_mask = DMA_BIT_MASK(32),
  996. },
  997. .resource = pxa27x_resource_ssp3,
  998. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
  999. };
  1000. struct platform_device pxa3xx_device_ssp4 = {
  1001. .name = "pxa3xx-ssp",
  1002. .id = 3,
  1003. .dev = {
  1004. .dma_mask = &pxa3xx_ssp4_dma_mask,
  1005. .coherent_dma_mask = DMA_BIT_MASK(32),
  1006. },
  1007. .resource = pxa3xx_resource_ssp4,
  1008. .num_resources = ARRAY_SIZE(pxa3xx_resource_ssp4),
  1009. };
  1010. #endif /* CONFIG_PXA3xx */
  1011. struct resource pxa_resource_gpio[] = {
  1012. {
  1013. .start = 0x40e00000,
  1014. .end = 0x40e0ffff,
  1015. .flags = IORESOURCE_MEM,
  1016. }, {
  1017. .start = IRQ_GPIO0,
  1018. .end = IRQ_GPIO0,
  1019. .name = "gpio0",
  1020. .flags = IORESOURCE_IRQ,
  1021. }, {
  1022. .start = IRQ_GPIO1,
  1023. .end = IRQ_GPIO1,
  1024. .name = "gpio1",
  1025. .flags = IORESOURCE_IRQ,
  1026. }, {
  1027. .start = IRQ_GPIO_2_x,
  1028. .end = IRQ_GPIO_2_x,
  1029. .name = "gpio_mux",
  1030. .flags = IORESOURCE_IRQ,
  1031. },
  1032. };
  1033. struct platform_device pxa25x_device_gpio = {
  1034. #ifdef CONFIG_CPU_PXA26x
  1035. .name = "pxa26x-gpio",
  1036. #else
  1037. .name = "pxa25x-gpio",
  1038. #endif
  1039. .id = -1,
  1040. .num_resources = ARRAY_SIZE(pxa_resource_gpio),
  1041. .resource = pxa_resource_gpio,
  1042. };
  1043. struct platform_device pxa27x_device_gpio = {
  1044. .name = "pxa27x-gpio",
  1045. .id = -1,
  1046. .num_resources = ARRAY_SIZE(pxa_resource_gpio),
  1047. .resource = pxa_resource_gpio,
  1048. };
  1049. struct platform_device pxa3xx_device_gpio = {
  1050. .name = "pxa3xx-gpio",
  1051. .id = -1,
  1052. .num_resources = ARRAY_SIZE(pxa_resource_gpio),
  1053. .resource = pxa_resource_gpio,
  1054. };
  1055. struct platform_device pxa93x_device_gpio = {
  1056. .name = "pxa93x-gpio",
  1057. .id = -1,
  1058. .num_resources = ARRAY_SIZE(pxa_resource_gpio),
  1059. .resource = pxa_resource_gpio,
  1060. };
  1061. /* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1.
  1062. * See comment in arch/arm/mach-pxa/ssp.c::ssp_probe() */
  1063. void __init pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info)
  1064. {
  1065. struct platform_device *pd;
  1066. pd = platform_device_alloc("pxa2xx-spi", id);
  1067. if (pd == NULL) {
  1068. printk(KERN_ERR "pxa2xx-spi: failed to allocate device id %d\n",
  1069. id);
  1070. return;
  1071. }
  1072. pd->dev.platform_data = info;
  1073. platform_device_add(pd);
  1074. }
  1075. static struct mmp_dma_platdata pxa_dma_pdata = {
  1076. .dma_channels = 0,
  1077. .nb_requestors = 0,
  1078. };
  1079. static struct resource pxa_dma_resource[] = {
  1080. [0] = {
  1081. .start = 0x40000000,
  1082. .end = 0x4000ffff,
  1083. .flags = IORESOURCE_MEM,
  1084. },
  1085. [1] = {
  1086. .start = IRQ_DMA,
  1087. .end = IRQ_DMA,
  1088. .flags = IORESOURCE_IRQ,
  1089. },
  1090. };
  1091. static u64 pxadma_dmamask = 0xffffffffUL;
  1092. static struct platform_device pxa2xx_pxa_dma = {
  1093. .name = "pxa-dma",
  1094. .id = 0,
  1095. .dev = {
  1096. .dma_mask = &pxadma_dmamask,
  1097. .coherent_dma_mask = 0xffffffff,
  1098. },
  1099. .num_resources = ARRAY_SIZE(pxa_dma_resource),
  1100. .resource = pxa_dma_resource,
  1101. };
  1102. void __init pxa2xx_set_dmac_info(int nb_channels, int nb_requestors)
  1103. {
  1104. pxa_dma_pdata.dma_channels = nb_channels;
  1105. pxa_dma_pdata.nb_requestors = nb_requestors;
  1106. pxa_register_device(&pxa2xx_pxa_dma, &pxa_dma_pdata);
  1107. }