buttox/arch/powerpc/boot/dts/fsl/bsc9132qds.dtsi

/*
 * BSC9132 QDS Device Tree Source stub (no addresses or top-level ranges)
 *
 * Copyright 2014 Freescale Semiconductor Inc.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *     * Redistributions of source code must retain the above copyright
 *       notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copyright
 *       notice, this list of conditions and the following disclaimer in the
 *       documentation and/or other materials provided with the distribution.
 *     * Neither the name of Freescale Semiconductor nor the
 *       names of its contributors may be used to endorse or promote products
 *       derived from this software without specific prior written permission.
 *
 *
 * ALTERNATIVELY, this software may be distributed under the terms of the
 * GNU General Public License ("GPL") as published by the Free Software
 * Foundation, either version 2 of that License or (at your option) any
 * later version.
 *
 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

&ifc {
	nor@0,0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "cfi-flash";
		reg = <0x0 0x0 0x8000000>;
		bank-width = <2>;
		device-width = <1>;
	};

	nand@1,0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "fsl,ifc-nand";
		reg = <0x1 0x0 0x4000>;
	};
};

&soc {
	spi@7000 {
		flash@0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "spansion,s25sl12801", "jedec,spi-nor";
			reg = <0>;
			spi-max-frequency = <30000000>;
		};
	};

	i2c@3000 {
		fpga: fpga@66 {
			compatible = "fsl,bsc9132qds-fpga", "fsl,fpga-qixis-i2c";
			reg = <0x66>;
		};
	};

	usb@22000 {
		phy_type = "ulpi";
	};

	mdio@24000 {
		phy0: ethernet-phy@0 {
			reg = <0x0>;
		};

		phy1: ethernet-phy@1 {
			reg = <0x1>;
		};

		tbi0: tbi-phy@11 {
			reg = <0x1f>;
			device_type = "tbi-phy";
		};
	};

	ptp_clock@b0e00 {
		compatible = "fsl,etsec-ptp";
		reg = <0xb0e00 0xb0>;
		interrupts = <68 2 0 0 69 2 0 0>;
		fsl,tclk-period	= <5>;
		fsl,tmr-prsc	= <2>;
		fsl,tmr-add	= <0xcccccccd>;
		fsl,tmr-fiper1	= <999999995>;
		fsl,tmr-fiper2	= <99990>;
		fsl,max-adj	= <249999999>;
	};

	enet0: ethernet@b0000 {
		phy-handle = <&phy0>;
		tbi-handle = <&tbi0>;
		phy-connection-type = "sgmii";
	};

	enet1: ethernet@b1000 {
		phy-handle = <&phy1>;
		tbi-handle = <&tbi0>;
		phy-connection-type = "sgmii";
	};
};