bsc9131si-post.dtsi 4.5 KB

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  1. /*
  2. * BSC9131 Silicon/SoC Device Tree Source (post include)
  3. *
  4. * Copyright 2011-2012 Freescale Semiconductor Inc.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions are met:
  8. * * Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * * Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in the
  12. * documentation and/or other materials provided with the distribution.
  13. * * Neither the name of Freescale Semiconductor nor the
  14. * names of its contributors may be used to endorse or promote products
  15. * derived from this software without specific prior written permission.
  16. *
  17. *
  18. * ALTERNATIVELY, this software may be distributed under the terms of the
  19. * GNU General Public License ("GPL") as published by the Free Software
  20. * Foundation, either version 2 of that License or (at your option) any
  21. * later version.
  22. *
  23. * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24. * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26. * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33. */
  34. &ifc {
  35. #address-cells = <2>;
  36. #size-cells = <1>;
  37. compatible = "fsl,ifc", "simple-bus";
  38. interrupts = <16 2 0 0 20 2 0 0>;
  39. };
  40. &soc {
  41. #address-cells = <1>;
  42. #size-cells = <1>;
  43. device_type = "soc";
  44. compatible = "fsl,bsc9131-immr", "simple-bus";
  45. bus-frequency = <0>; // Filled out by uboot.
  46. ecm-law@0 {
  47. compatible = "fsl,ecm-law";
  48. reg = <0x0 0x1000>;
  49. fsl,num-laws = <12>;
  50. };
  51. ecm@1000 {
  52. compatible = "fsl,bsc9131-ecm", "fsl,ecm";
  53. reg = <0x1000 0x1000>;
  54. interrupts = <16 2 0 0>;
  55. };
  56. memory-controller@2000 {
  57. compatible = "fsl,bsc9131-memory-controller";
  58. reg = <0x2000 0x1000>;
  59. interrupts = <16 2 0 0>;
  60. };
  61. /include/ "pq3-i2c-0.dtsi"
  62. i2c@3000 {
  63. interrupts = <17 2 0 0>;
  64. };
  65. /include/ "pq3-i2c-1.dtsi"
  66. i2c@3100 {
  67. interrupts = <17 2 0 0>;
  68. };
  69. /include/ "pq3-duart-0.dtsi"
  70. serial0: serial@4500 {
  71. interrupts = <18 2 0 0>;
  72. };
  73. serial1: serial@4600 {
  74. interrupts = <18 2 0 0 >;
  75. };
  76. /include/ "pq3-espi-0.dtsi"
  77. spi0: spi@7000 {
  78. fsl,espi-num-chipselects = <1>;
  79. interrupts = <22 0x2 0 0>;
  80. };
  81. /include/ "pq3-gpio-0.dtsi"
  82. gpio-controller@f000 {
  83. interrupts = <19 0x2 0 0>;
  84. };
  85. L2: l2-cache-controller@20000 {
  86. compatible = "fsl,bsc9131-l2-cache-controller";
  87. reg = <0x20000 0x1000>;
  88. cache-line-size = <32>; // 32 bytes
  89. cache-size = <0x40000>; // L2,256K
  90. interrupts = <16 2 0 0>;
  91. };
  92. /include/ "pq3-dma-0.dtsi"
  93. dma@21300 {
  94. dma-channel@0 {
  95. interrupts = <62 2 0 0>;
  96. };
  97. dma-channel@80 {
  98. interrupts = <63 2 0 0>;
  99. };
  100. dma-channel@100 {
  101. interrupts = <64 2 0 0>;
  102. };
  103. dma-channel@180 {
  104. interrupts = <65 2 0 0>;
  105. };
  106. };
  107. /include/ "pq3-usb2-dr-0.dtsi"
  108. usb@22000 {
  109. compatible = "fsl-usb2-dr","fsl-usb2-dr-v2.2";
  110. interrupts = <40 0x2 0 0>;
  111. };
  112. /include/ "pq3-esdhc-0.dtsi"
  113. sdhc@2e000 {
  114. sdhci,auto-cmd12;
  115. interrupts = <41 0x2 0 0>;
  116. };
  117. /include/ "pq3-sec4.4-0.dtsi"
  118. crypto@30000 {
  119. interrupts = <57 2 0 0>;
  120. sec_jr0: jr@1000 {
  121. interrupts = <58 2 0 0>;
  122. };
  123. sec_jr1: jr@2000 {
  124. interrupts = <59 2 0 0>;
  125. };
  126. sec_jr2: jr@3000 {
  127. interrupts = <60 2 0 0>;
  128. };
  129. sec_jr3: jr@4000 {
  130. interrupts = <61 2 0 0>;
  131. };
  132. };
  133. /include/ "pq3-mpic.dtsi"
  134. timer@41100 {
  135. compatible = "fsl,mpic-v1.2-msgr", "fsl,mpic-msg";
  136. reg = <0x41400 0x200>;
  137. interrupts = <
  138. 0xb0 2
  139. 0xb1 2
  140. 0xb2 2
  141. 0xb3 2>;
  142. };
  143. /include/ "pq3-etsec2-0.dtsi"
  144. enet0: ethernet@b0000 {
  145. queue-group@b0000 {
  146. fsl,rx-bit-map = <0xff>;
  147. fsl,tx-bit-map = <0xff>;
  148. interrupts = <26 2 0 0 27 2 0 0 28 2 0 0>;
  149. };
  150. };
  151. /include/ "pq3-etsec2-1.dtsi"
  152. enet1: ethernet@b1000 {
  153. queue-group@b1000 {
  154. fsl,rx-bit-map = <0xff>;
  155. fsl,tx-bit-map = <0xff>;
  156. interrupts = <33 2 0 0 34 2 0 0 35 2 0 0>;
  157. };
  158. };
  159. global-utilities@e0000 {
  160. compatible = "fsl,bsc9131-guts";
  161. reg = <0xe0000 0x1000>;
  162. fsl,has-rstcr;
  163. };
  164. };