ac14xx.dts 7.9 KB

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  1. /*
  2. * Device Tree Source for the MPC5121e based ac14xx board
  3. *
  4. * Copyright 2012 Anatolij Gustschin <agust@denx.de>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. #include <mpc5121.dtsi>
  12. / {
  13. model = "ac14xx";
  14. compatible = "ifm,ac14xx", "fsl,mpc5121";
  15. #address-cells = <1>;
  16. #size-cells = <1>;
  17. aliases {
  18. serial0 = &serial0;
  19. serial1 = &serial7;
  20. spi4 = &spi4;
  21. spi5 = &spi5;
  22. };
  23. cpus {
  24. PowerPC,5121@0 {
  25. timebase-frequency = <40000000>; /* 40 MHz (csb/4) */
  26. bus-frequency = <160000000>; /* 160 MHz csb bus */
  27. clock-frequency = <400000000>; /* 400 MHz ppc core */
  28. };
  29. };
  30. memory {
  31. reg = <0x00000000 0x10000000>; /* 256MB at 0 */
  32. };
  33. nfc@40000000 {
  34. status = "disabled";
  35. };
  36. localbus@80000020 {
  37. ranges = <0x0 0x0 0xfc000000 0x04000000 /* CS0: NOR flash */
  38. 0x1 0x0 0xe0000000 0x00010000 /* CS1: FRAM */
  39. 0x2 0x0 0xe0100000 0x00080000 /* CS2: asi1 */
  40. 0x3 0x0 0xe0300000 0x00020000 /* CS3: comm */
  41. 0x5 0x0 0xe0400000 0x00010000 /* CS5: safety */
  42. 0x6 0x0 0xe0200000 0x00080000>; /* CS6: asi2 */
  43. flash@0,0 {
  44. compatible = "cfi-flash";
  45. reg = <0 0x00000000 0x04000000>;
  46. #address-cells = <1>;
  47. #size-cells = <1>;
  48. bank-width = <2>;
  49. device-width = <2>;
  50. partition@0 {
  51. label = "dtb-kernel-production";
  52. reg = <0x00000000 0x00400000>;
  53. };
  54. partition@1 {
  55. label = "filesystem-production";
  56. reg = <0x00400000 0x03400000>;
  57. };
  58. partition@2 {
  59. label = "recovery";
  60. reg = <0x03800000 0x00700000>;
  61. };
  62. partition@3 {
  63. label = "uboot-code";
  64. reg = <0x03f00000 0x00040000>;
  65. };
  66. partition@4 {
  67. label = "uboot-env1";
  68. reg = <0x03f40000 0x00020000>;
  69. };
  70. partition@5 {
  71. label = "uboot-env2";
  72. reg = <0x03f60000 0x00020000>;
  73. };
  74. };
  75. fram@1,0 {
  76. compatible = "ifm,ac14xx-fram", "linux,uio-pdrv-genirq";
  77. reg = <1 0x00000000 0x00010000>;
  78. };
  79. asi@2,0 {
  80. /* masters mapping: CS, CS offset, size */
  81. reg = <2 0x00000000 0x00080000
  82. 6 0x00000000 0x00080000>;
  83. #address-cells = <1>;
  84. #size-cells = <1>;
  85. compatible = "ifm,ac14xx-asi-fpga";
  86. gpios = <
  87. &gpio_pic 26 0 /* prog */
  88. &gpio_pic 27 0 /* done */
  89. &gpio_pic 10 0 /* reset */
  90. >;
  91. master@1 {
  92. interrupts = <20 0x2>;
  93. interrupt-parent = <&gpio_pic>;
  94. chipselect = <2 0x00009000 0x00009100>;
  95. label = "AS-i master 1";
  96. };
  97. master@2 {
  98. interrupts = <21 0x2>;
  99. interrupt-parent = <&gpio_pic>;
  100. chipselect = <6 0x00009000 0x00009100>;
  101. label = "AS-i master 2";
  102. };
  103. };
  104. netx@3,0 {
  105. compatible = "ifm,netx";
  106. reg = <0x3 0x00000000 0x00020000>;
  107. chipselect = <3 0x00101140 0x00203100>;
  108. interrupts = <17 0x8>;
  109. gpios = <&gpio_pic 15 0>;
  110. };
  111. safety@5,0 {
  112. compatible = "ifm,safety";
  113. reg = <0x5 0x00000000 0x00010000>;
  114. chipselect = <5 0x00009000 0x00009100>;
  115. interrupts = <22 0x2>;
  116. interrupt-parent = <&gpio_pic>;
  117. gpios = <
  118. &gpio_pic 12 0 /* prog */
  119. &gpio_pic 11 0 /* done */
  120. >;
  121. };
  122. };
  123. clocks {
  124. osc {
  125. clock-frequency = <25000000>;
  126. };
  127. };
  128. soc@80000000 {
  129. bus-frequency = <80000000>; /* 80 MHz ips bus */
  130. clock@f00 {
  131. compatible = "fsl,mpc5121rev2-clock", "fsl,mpc5121-clock";
  132. };
  133. /*
  134. * GPIO PIC:
  135. * interrupts cell = <pin nr, sense>
  136. * sense == 8: Level, low assertion
  137. * sense == 2: Edge, high-to-low change
  138. */
  139. gpio_pic: gpio@1100 {
  140. gpio-controller;
  141. #gpio-cells = <2>;
  142. interrupt-controller;
  143. #interrupt-cells = <2>;
  144. };
  145. sdhc@1500 {
  146. cd-gpios = <&gpio_pic 23 0>; /* card detect */
  147. wp-gpios = <&gpio_pic 24 0>; /* write protect */
  148. wp-inverted; /* WP active high */
  149. };
  150. i2c@1700 {
  151. /* use Fast-mode */
  152. clock-frequency = <400000>;
  153. at24@30 {
  154. compatible = "at24,24c01";
  155. reg = <0x30>;
  156. };
  157. at24@31 {
  158. compatible = "at24,24c01";
  159. reg = <0x31>;
  160. };
  161. temp@48 {
  162. compatible = "ad,ad7414";
  163. reg = <0x48>;
  164. };
  165. at24@50 {
  166. compatible = "at24,24c01";
  167. reg = <0x50>;
  168. };
  169. at24@51 {
  170. compatible = "at24,24c01";
  171. reg = <0x51>;
  172. };
  173. at24@52 {
  174. compatible = "at24,24c01";
  175. reg = <0x52>;
  176. };
  177. at24@53 {
  178. compatible = "at24,24c01";
  179. reg = <0x53>;
  180. };
  181. at24@54 {
  182. compatible = "at24,24c01";
  183. reg = <0x54>;
  184. };
  185. at24@55 {
  186. compatible = "at24,24c01";
  187. reg = <0x55>;
  188. };
  189. at24@56 {
  190. compatible = "at24,24c01";
  191. reg = <0x56>;
  192. };
  193. at24@57 {
  194. compatible = "at24,24c01";
  195. reg = <0x57>;
  196. };
  197. rtc@68 {
  198. compatible = "st,m41t00";
  199. reg = <0x68>;
  200. };
  201. };
  202. axe_pic: axe-base@2000 {
  203. compatible = "fsl,mpc5121-axe-base";
  204. reg = <0x2000 0x100>;
  205. interrupts = <42 0x8>;
  206. interrupt-controller;
  207. #interrupt-cells = <2>;
  208. };
  209. axe-app {
  210. compatible = "fsl,mpc5121-axe-app";
  211. interrupt-parent = <&axe_pic>;
  212. interrupts = <
  213. /* soft interrupts */
  214. 0 0x0 1 0x0 2 0x0 3 0x0
  215. 4 0x0 5 0x0 6 0x0 7 0x0
  216. /* fifo interrupts */
  217. 8 0x0 9 0x0 10 0x0 11 0x0
  218. >;
  219. };
  220. display@2100 {
  221. edid = [00 FF FF FF FF FF FF 00 14 94 00 00 00 00 00 00
  222. 0A 12 01 03 80 1C 23 78 CA 88 FF 94 52 54 8E 27
  223. 1E 4C 50 00 00 00 01 01 01 01 01 01 01 01 01 01
  224. 01 01 01 01 01 01 FB 00 B0 14 00 DC 05 00 08 04
  225. 21 00 1C 23 00 00 00 18 00 00 00 FD 00 38 3C 1F
  226. 3C 01 0A 20 20 20 20 20 20 20 00 00 00 FC 00 45
  227. 54 30 31 38 30 30 33 44 4D 55 0A 0A 00 00 00 10
  228. 00 41 30 30 30 30 30 30 30 30 30 30 30 31 00 D5];
  229. };
  230. can@2300 {
  231. status = "disabled";
  232. };
  233. can@2380 {
  234. status = "disabled";
  235. };
  236. viu@2400 {
  237. status = "disabled";
  238. };
  239. mdio@2800 {
  240. phy0: ethernet-phy@1f {
  241. compatible = "smsc,lan8700";
  242. reg = <0x1f>;
  243. };
  244. };
  245. enet: ethernet@2800 {
  246. phy-handle = <&phy0>;
  247. };
  248. usb@3000 {
  249. status = "disabled";
  250. };
  251. usb@4000 {
  252. status = "disabled";
  253. };
  254. /* PSC3 serial port A, aka ttyPSC0 */
  255. serial0: psc@11300 {
  256. compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
  257. fsl,rx-fifo-size = <512>;
  258. fsl,tx-fifo-size = <512>;
  259. };
  260. /* PSC4 in SPI mode */
  261. spi4: psc@11400 {
  262. compatible = "fsl,mpc5121-psc-spi", "fsl,mpc5121-psc";
  263. fsl,rx-fifo-size = <768>;
  264. fsl,tx-fifo-size = <768>;
  265. #address-cells = <1>;
  266. #size-cells = <0>;
  267. num-cs = <1>;
  268. cs-gpios = <&gpio_pic 25 0>;
  269. flash: m25p128@0 {
  270. compatible = "st,m25p128";
  271. spi-max-frequency = <20000000>;
  272. reg = <0>;
  273. #address-cells = <1>;
  274. #size-cells = <1>;
  275. partition@0 {
  276. label = "spi-flash0";
  277. reg = <0x00000000 0x01000000>;
  278. };
  279. };
  280. };
  281. /* PSC5 in SPI mode */
  282. spi5: psc@11500 {
  283. compatible = "fsl,mpc5121-psc-spi", "fsl,mpc5121-psc";
  284. fsl,mode = "spi-master";
  285. fsl,rx-fifo-size = <128>;
  286. fsl,tx-fifo-size = <128>;
  287. #address-cells = <1>;
  288. #size-cells = <0>;
  289. lcd@0 {
  290. compatible = "ilitek,ili922x";
  291. reg = <0>;
  292. spi-max-frequency = <100000>;
  293. spi-cpol;
  294. spi-cpha;
  295. };
  296. };
  297. /* PSC7 serial port C, aka ttyPSC2 */
  298. serial7: psc@11700 {
  299. compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
  300. fsl,rx-fifo-size = <512>;
  301. fsl,tx-fifo-size = <512>;
  302. };
  303. matrix_keypad@0 {
  304. compatible = "gpio-matrix-keypad";
  305. debounce-delay-ms = <5>;
  306. col-scan-delay-us = <1>;
  307. gpio-activelow;
  308. col-gpios-binary;
  309. col-switch-delay-ms = <200>;
  310. col-gpios = <&gpio_pic 1 0>; /* pin1 */
  311. row-gpios = <&gpio_pic 2 0 /* pin2 */
  312. &gpio_pic 3 0 /* pin3 */
  313. &gpio_pic 4 0>; /* pin4 */
  314. linux,keymap = <0x0000006e /* FN LEFT */
  315. 0x01000067 /* UP */
  316. 0x02000066 /* FN RIGHT */
  317. 0x00010069 /* LEFT */
  318. 0x0101006a /* DOWN */
  319. 0x0201006c>; /* RIGHT */
  320. };
  321. };
  322. leds {
  323. compatible = "gpio-leds";
  324. backlight {
  325. label = "backlight";
  326. gpios = <&gpio_pic 0 0>;
  327. default-state = "keep";
  328. };
  329. green {
  330. label = "green";
  331. gpios = <&gpio_pic 18 0>;
  332. default-state = "keep";
  333. };
  334. red {
  335. label = "red";
  336. gpios = <&gpio_pic 19 0>;
  337. default-state = "keep";
  338. };
  339. };
  340. };