platsmp.c 4.6 KB

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  1. /*
  2. * Symmetric Multi Processing (SMP) support for Armada XP
  3. *
  4. * Copyright (C) 2012 Marvell
  5. *
  6. * Lior Amsalem <alior@marvell.com>
  7. * Yehuda Yitschak <yehuday@marvell.com>
  8. * Gregory CLEMENT <gregory.clement@free-electrons.com>
  9. * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  10. *
  11. * This file is licensed under the terms of the GNU General Public
  12. * License version 2. This program is licensed "as is" without any
  13. * warranty of any kind, whether express or implied.
  14. *
  15. * The Armada XP SoC has 4 ARMv7 PJ4B CPUs running in full HW coherency
  16. * This file implements the routines for preparing the SMP infrastructure
  17. * and waking up the secondary CPUs
  18. */
  19. #include <linux/init.h>
  20. #include <linux/smp.h>
  21. #include <linux/clk.h>
  22. #include <linux/of.h>
  23. #include <linux/of_address.h>
  24. #include <linux/mbus.h>
  25. #include <asm/cacheflush.h>
  26. #include <asm/smp_plat.h>
  27. #include "common.h"
  28. #include "armada-370-xp.h"
  29. #include "pmsu.h"
  30. #include "coherency.h"
  31. #define ARMADA_XP_MAX_CPUS 4
  32. #define AXP_BOOTROM_BASE 0xfff00000
  33. #define AXP_BOOTROM_SIZE 0x100000
  34. static struct clk *get_cpu_clk(int cpu)
  35. {
  36. struct clk *cpu_clk;
  37. struct device_node *np = of_get_cpu_node(cpu, NULL);
  38. if (WARN(!np, "missing cpu node\n"))
  39. return NULL;
  40. cpu_clk = of_clk_get(np, 0);
  41. if (WARN_ON(IS_ERR(cpu_clk)))
  42. return NULL;
  43. return cpu_clk;
  44. }
  45. static void set_secondary_cpu_clock(unsigned int cpu)
  46. {
  47. int thiscpu;
  48. unsigned long rate;
  49. struct clk *cpu_clk;
  50. thiscpu = get_cpu();
  51. cpu_clk = get_cpu_clk(thiscpu);
  52. if (!cpu_clk)
  53. goto out;
  54. clk_prepare_enable(cpu_clk);
  55. rate = clk_get_rate(cpu_clk);
  56. cpu_clk = get_cpu_clk(cpu);
  57. if (!cpu_clk)
  58. goto out;
  59. clk_set_rate(cpu_clk, rate);
  60. clk_prepare_enable(cpu_clk);
  61. out:
  62. put_cpu();
  63. }
  64. static int armada_xp_boot_secondary(unsigned int cpu, struct task_struct *idle)
  65. {
  66. int ret, hw_cpu;
  67. pr_info("Booting CPU %d\n", cpu);
  68. hw_cpu = cpu_logical_map(cpu);
  69. set_secondary_cpu_clock(hw_cpu);
  70. mvebu_pmsu_set_cpu_boot_addr(hw_cpu, armada_xp_secondary_startup);
  71. /*
  72. * This is needed to wake up CPUs in the offline state after
  73. * using CPU hotplug.
  74. */
  75. arch_send_wakeup_ipi_mask(cpumask_of(cpu));
  76. /*
  77. * This is needed to take secondary CPUs out of reset on the
  78. * initial boot.
  79. */
  80. ret = mvebu_cpu_reset_deassert(hw_cpu);
  81. if (ret) {
  82. pr_warn("unable to boot CPU: %d\n", ret);
  83. return ret;
  84. }
  85. return 0;
  86. }
  87. /*
  88. * When a CPU is brought back online, either through CPU hotplug, or
  89. * because of the boot of a kexec'ed kernel, the PMSU configuration
  90. * for this CPU might be in the deep idle state, preventing this CPU
  91. * from receiving interrupts. Here, we therefore take out the current
  92. * CPU from this state, which was entered by armada_xp_cpu_die()
  93. * below.
  94. */
  95. static void armada_xp_secondary_init(unsigned int cpu)
  96. {
  97. mvebu_v7_pmsu_idle_exit();
  98. }
  99. static void __init armada_xp_smp_init_cpus(void)
  100. {
  101. unsigned int ncores = num_possible_cpus();
  102. if (ncores == 0 || ncores > ARMADA_XP_MAX_CPUS)
  103. panic("Invalid number of CPUs in DT\n");
  104. }
  105. static void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus)
  106. {
  107. struct device_node *node;
  108. struct resource res;
  109. int err;
  110. flush_cache_all();
  111. set_cpu_coherent();
  112. /*
  113. * In order to boot the secondary CPUs we need to ensure
  114. * the bootROM is mapped at the correct address.
  115. */
  116. node = of_find_compatible_node(NULL, NULL, "marvell,bootrom");
  117. if (!node)
  118. panic("Cannot find 'marvell,bootrom' compatible node");
  119. err = of_address_to_resource(node, 0, &res);
  120. of_node_put(node);
  121. if (err < 0)
  122. panic("Cannot get 'bootrom' node address");
  123. if (res.start != AXP_BOOTROM_BASE ||
  124. resource_size(&res) != AXP_BOOTROM_SIZE)
  125. panic("The address for the BootROM is incorrect");
  126. }
  127. #ifdef CONFIG_HOTPLUG_CPU
  128. static void armada_xp_cpu_die(unsigned int cpu)
  129. {
  130. /*
  131. * CPU hotplug is implemented by putting offline CPUs into the
  132. * deep idle sleep state.
  133. */
  134. armada_370_xp_pmsu_idle_enter(true);
  135. }
  136. /*
  137. * We need a dummy function, so that platform_can_cpu_hotplug() knows
  138. * we support CPU hotplug. However, the function does not need to do
  139. * anything, because CPUs going offline can enter the deep idle state
  140. * by themselves, without any help from a still alive CPU.
  141. */
  142. static int armada_xp_cpu_kill(unsigned int cpu)
  143. {
  144. return 1;
  145. }
  146. #endif
  147. const struct smp_operations armada_xp_smp_ops __initconst = {
  148. .smp_init_cpus = armada_xp_smp_init_cpus,
  149. .smp_prepare_cpus = armada_xp_smp_prepare_cpus,
  150. .smp_boot_secondary = armada_xp_boot_secondary,
  151. .smp_secondary_init = armada_xp_secondary_init,
  152. #ifdef CONFIG_HOTPLUG_CPU
  153. .cpu_die = armada_xp_cpu_die,
  154. .cpu_kill = armada_xp_cpu_kill,
  155. #endif
  156. };
  157. CPU_METHOD_OF_DECLARE(armada_xp_smp, "marvell,armada-xp-smp",
  158. &armada_xp_smp_ops);