mtd-davinci.h 2.9 KB

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  1. /*
  2. * mach-davinci/nand.h
  3. *
  4. * Copyright © 2006 Texas Instruments.
  5. *
  6. * Ported to 2.6.23 Copyright © 2008 by
  7. * Sander Huijsen <Shuijsen@optelecom-nkf.com>
  8. * Troy Kisky <troy.kisky@boundarydevices.com>
  9. * Dirk Behme <Dirk.Behme@gmail.com>
  10. *
  11. * --------------------------------------------------------------------------
  12. *
  13. * This program is free software; you can redistribute it and/or modify
  14. * it under the terms of the GNU General Public License as published by
  15. * the Free Software Foundation; either version 2 of the License, or
  16. * (at your option) any later version.
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. *
  23. * You should have received a copy of the GNU General Public License
  24. * along with this program; if not, write to the Free Software
  25. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  26. */
  27. #ifndef __ARCH_ARM_DAVINCI_NAND_H
  28. #define __ARCH_ARM_DAVINCI_NAND_H
  29. #include <linux/mtd/rawnand.h>
  30. #define NANDFCR_OFFSET 0x60
  31. #define NANDFSR_OFFSET 0x64
  32. #define NANDF1ECC_OFFSET 0x70
  33. /* 4-bit ECC syndrome registers */
  34. #define NAND_4BIT_ECC_LOAD_OFFSET 0xbc
  35. #define NAND_4BIT_ECC1_OFFSET 0xc0
  36. #define NAND_4BIT_ECC2_OFFSET 0xc4
  37. #define NAND_4BIT_ECC3_OFFSET 0xc8
  38. #define NAND_4BIT_ECC4_OFFSET 0xcc
  39. #define NAND_ERR_ADD1_OFFSET 0xd0
  40. #define NAND_ERR_ADD2_OFFSET 0xd4
  41. #define NAND_ERR_ERRVAL1_OFFSET 0xd8
  42. #define NAND_ERR_ERRVAL2_OFFSET 0xdc
  43. /* NOTE: boards don't need to use these address bits
  44. * for ALE/CLE unless they support booting from NAND.
  45. * They're used unless platform data overrides them.
  46. */
  47. #define MASK_ALE 0x08
  48. #define MASK_CLE 0x10
  49. struct davinci_nand_pdata { /* platform_data */
  50. uint32_t mask_ale;
  51. uint32_t mask_cle;
  52. /*
  53. * 0-indexed chip-select number of the asynchronous
  54. * interface to which the NAND device has been connected.
  55. *
  56. * So, if you have NAND connected to CS3 of DA850, you
  57. * will pass '1' here. Since the asynchronous interface
  58. * on DA850 starts from CS2.
  59. */
  60. uint32_t core_chipsel;
  61. /* for packages using two chipselects */
  62. uint32_t mask_chipsel;
  63. /* board's default static partition info */
  64. struct mtd_partition *parts;
  65. unsigned nr_parts;
  66. /* none == NAND_ECC_NONE (strongly *not* advised!!)
  67. * soft == NAND_ECC_SOFT
  68. * else == NAND_ECC_HW, according to ecc_bits
  69. *
  70. * All DaVinci-family chips support 1-bit hardware ECC.
  71. * Newer ones also support 4-bit ECC, but are awkward
  72. * using it with large page chips.
  73. */
  74. nand_ecc_modes_t ecc_mode;
  75. u8 ecc_bits;
  76. /* e.g. NAND_BUSWIDTH_16 */
  77. unsigned options;
  78. /* e.g. NAND_BBT_USE_FLASH */
  79. unsigned bbt_options;
  80. /* Main and mirror bbt descriptor overrides */
  81. struct nand_bbt_descr *bbt_td;
  82. struct nand_bbt_descr *bbt_md;
  83. /* Access timings */
  84. struct davinci_aemif_timing *timing;
  85. };
  86. #endif /* __ARCH_ARM_DAVINCI_NAND_H */