fotg210-udc.c 29 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * FOTG210 UDC Driver supports Bulk transfer so far
  4. *
  5. * Copyright (C) 2013 Faraday Technology Corporation
  6. *
  7. * Author : Yuan-Hsin Chen <yhchen@faraday-tech.com>
  8. */
  9. #include <linux/dma-mapping.h>
  10. #include <linux/err.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/io.h>
  13. #include <linux/module.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/usb/ch9.h>
  16. #include <linux/usb/gadget.h>
  17. #include "fotg210.h"
  18. #define DRIVER_DESC "FOTG210 USB Device Controller Driver"
  19. #define DRIVER_VERSION "30-April-2013"
  20. static const char udc_name[] = "fotg210_udc";
  21. static const char * const fotg210_ep_name[] = {
  22. "ep0", "ep1", "ep2", "ep3", "ep4"};
  23. static void fotg210_disable_fifo_int(struct fotg210_ep *ep)
  24. {
  25. u32 value = ioread32(ep->fotg210->reg + FOTG210_DMISGR1);
  26. if (ep->dir_in)
  27. value |= DMISGR1_MF_IN_INT(ep->epnum - 1);
  28. else
  29. value |= DMISGR1_MF_OUTSPK_INT(ep->epnum - 1);
  30. iowrite32(value, ep->fotg210->reg + FOTG210_DMISGR1);
  31. }
  32. static void fotg210_enable_fifo_int(struct fotg210_ep *ep)
  33. {
  34. u32 value = ioread32(ep->fotg210->reg + FOTG210_DMISGR1);
  35. if (ep->dir_in)
  36. value &= ~DMISGR1_MF_IN_INT(ep->epnum - 1);
  37. else
  38. value &= ~DMISGR1_MF_OUTSPK_INT(ep->epnum - 1);
  39. iowrite32(value, ep->fotg210->reg + FOTG210_DMISGR1);
  40. }
  41. static void fotg210_set_cxdone(struct fotg210_udc *fotg210)
  42. {
  43. u32 value = ioread32(fotg210->reg + FOTG210_DCFESR);
  44. value |= DCFESR_CX_DONE;
  45. iowrite32(value, fotg210->reg + FOTG210_DCFESR);
  46. }
  47. static void fotg210_done(struct fotg210_ep *ep, struct fotg210_request *req,
  48. int status)
  49. {
  50. list_del_init(&req->queue);
  51. /* don't modify queue heads during completion callback */
  52. if (ep->fotg210->gadget.speed == USB_SPEED_UNKNOWN)
  53. req->req.status = -ESHUTDOWN;
  54. else
  55. req->req.status = status;
  56. spin_unlock(&ep->fotg210->lock);
  57. usb_gadget_giveback_request(&ep->ep, &req->req);
  58. spin_lock(&ep->fotg210->lock);
  59. if (ep->epnum) {
  60. if (list_empty(&ep->queue))
  61. fotg210_disable_fifo_int(ep);
  62. } else {
  63. fotg210_set_cxdone(ep->fotg210);
  64. }
  65. }
  66. static void fotg210_fifo_ep_mapping(struct fotg210_ep *ep, u32 epnum,
  67. u32 dir_in)
  68. {
  69. struct fotg210_udc *fotg210 = ep->fotg210;
  70. u32 val;
  71. /* Driver should map an ep to a fifo and then map the fifo
  72. * to the ep. What a brain-damaged design!
  73. */
  74. /* map a fifo to an ep */
  75. val = ioread32(fotg210->reg + FOTG210_EPMAP);
  76. val &= ~EPMAP_FIFONOMSK(epnum, dir_in);
  77. val |= EPMAP_FIFONO(epnum, dir_in);
  78. iowrite32(val, fotg210->reg + FOTG210_EPMAP);
  79. /* map the ep to the fifo */
  80. val = ioread32(fotg210->reg + FOTG210_FIFOMAP);
  81. val &= ~FIFOMAP_EPNOMSK(epnum);
  82. val |= FIFOMAP_EPNO(epnum);
  83. iowrite32(val, fotg210->reg + FOTG210_FIFOMAP);
  84. /* enable fifo */
  85. val = ioread32(fotg210->reg + FOTG210_FIFOCF);
  86. val |= FIFOCF_FIFO_EN(epnum - 1);
  87. iowrite32(val, fotg210->reg + FOTG210_FIFOCF);
  88. }
  89. static void fotg210_set_fifo_dir(struct fotg210_ep *ep, u32 epnum, u32 dir_in)
  90. {
  91. struct fotg210_udc *fotg210 = ep->fotg210;
  92. u32 val;
  93. val = ioread32(fotg210->reg + FOTG210_FIFOMAP);
  94. val |= (dir_in ? FIFOMAP_DIRIN(epnum - 1) : FIFOMAP_DIROUT(epnum - 1));
  95. iowrite32(val, fotg210->reg + FOTG210_FIFOMAP);
  96. }
  97. static void fotg210_set_tfrtype(struct fotg210_ep *ep, u32 epnum, u32 type)
  98. {
  99. struct fotg210_udc *fotg210 = ep->fotg210;
  100. u32 val;
  101. val = ioread32(fotg210->reg + FOTG210_FIFOCF);
  102. val |= FIFOCF_TYPE(type, epnum - 1);
  103. iowrite32(val, fotg210->reg + FOTG210_FIFOCF);
  104. }
  105. static void fotg210_set_mps(struct fotg210_ep *ep, u32 epnum, u32 mps,
  106. u32 dir_in)
  107. {
  108. struct fotg210_udc *fotg210 = ep->fotg210;
  109. u32 val;
  110. u32 offset = dir_in ? FOTG210_INEPMPSR(epnum) :
  111. FOTG210_OUTEPMPSR(epnum);
  112. val = ioread32(fotg210->reg + offset);
  113. val |= INOUTEPMPSR_MPS(mps);
  114. iowrite32(val, fotg210->reg + offset);
  115. }
  116. static int fotg210_config_ep(struct fotg210_ep *ep,
  117. const struct usb_endpoint_descriptor *desc)
  118. {
  119. struct fotg210_udc *fotg210 = ep->fotg210;
  120. fotg210_set_fifo_dir(ep, ep->epnum, ep->dir_in);
  121. fotg210_set_tfrtype(ep, ep->epnum, ep->type);
  122. fotg210_set_mps(ep, ep->epnum, ep->ep.maxpacket, ep->dir_in);
  123. fotg210_fifo_ep_mapping(ep, ep->epnum, ep->dir_in);
  124. fotg210->ep[ep->epnum] = ep;
  125. return 0;
  126. }
  127. static int fotg210_ep_enable(struct usb_ep *_ep,
  128. const struct usb_endpoint_descriptor *desc)
  129. {
  130. struct fotg210_ep *ep;
  131. ep = container_of(_ep, struct fotg210_ep, ep);
  132. ep->desc = desc;
  133. ep->epnum = usb_endpoint_num(desc);
  134. ep->type = usb_endpoint_type(desc);
  135. ep->dir_in = usb_endpoint_dir_in(desc);
  136. ep->ep.maxpacket = usb_endpoint_maxp(desc);
  137. return fotg210_config_ep(ep, desc);
  138. }
  139. static void fotg210_reset_tseq(struct fotg210_udc *fotg210, u8 epnum)
  140. {
  141. struct fotg210_ep *ep = fotg210->ep[epnum];
  142. u32 value;
  143. void __iomem *reg;
  144. reg = (ep->dir_in) ?
  145. fotg210->reg + FOTG210_INEPMPSR(epnum) :
  146. fotg210->reg + FOTG210_OUTEPMPSR(epnum);
  147. /* Note: Driver needs to set and clear INOUTEPMPSR_RESET_TSEQ
  148. * bit. Controller wouldn't clear this bit. WTF!!!
  149. */
  150. value = ioread32(reg);
  151. value |= INOUTEPMPSR_RESET_TSEQ;
  152. iowrite32(value, reg);
  153. value = ioread32(reg);
  154. value &= ~INOUTEPMPSR_RESET_TSEQ;
  155. iowrite32(value, reg);
  156. }
  157. static int fotg210_ep_release(struct fotg210_ep *ep)
  158. {
  159. if (!ep->epnum)
  160. return 0;
  161. ep->epnum = 0;
  162. ep->stall = 0;
  163. ep->wedged = 0;
  164. fotg210_reset_tseq(ep->fotg210, ep->epnum);
  165. return 0;
  166. }
  167. static int fotg210_ep_disable(struct usb_ep *_ep)
  168. {
  169. struct fotg210_ep *ep;
  170. struct fotg210_request *req;
  171. unsigned long flags;
  172. BUG_ON(!_ep);
  173. ep = container_of(_ep, struct fotg210_ep, ep);
  174. while (!list_empty(&ep->queue)) {
  175. req = list_entry(ep->queue.next,
  176. struct fotg210_request, queue);
  177. spin_lock_irqsave(&ep->fotg210->lock, flags);
  178. fotg210_done(ep, req, -ECONNRESET);
  179. spin_unlock_irqrestore(&ep->fotg210->lock, flags);
  180. }
  181. return fotg210_ep_release(ep);
  182. }
  183. static struct usb_request *fotg210_ep_alloc_request(struct usb_ep *_ep,
  184. gfp_t gfp_flags)
  185. {
  186. struct fotg210_request *req;
  187. req = kzalloc(sizeof(struct fotg210_request), gfp_flags);
  188. if (!req)
  189. return NULL;
  190. INIT_LIST_HEAD(&req->queue);
  191. return &req->req;
  192. }
  193. static void fotg210_ep_free_request(struct usb_ep *_ep,
  194. struct usb_request *_req)
  195. {
  196. struct fotg210_request *req;
  197. req = container_of(_req, struct fotg210_request, req);
  198. kfree(req);
  199. }
  200. static void fotg210_enable_dma(struct fotg210_ep *ep,
  201. dma_addr_t d, u32 len)
  202. {
  203. u32 value;
  204. struct fotg210_udc *fotg210 = ep->fotg210;
  205. /* set transfer length and direction */
  206. value = ioread32(fotg210->reg + FOTG210_DMACPSR1);
  207. value &= ~(DMACPSR1_DMA_LEN(0xFFFF) | DMACPSR1_DMA_TYPE(1));
  208. value |= DMACPSR1_DMA_LEN(len) | DMACPSR1_DMA_TYPE(ep->dir_in);
  209. iowrite32(value, fotg210->reg + FOTG210_DMACPSR1);
  210. /* set device DMA target FIFO number */
  211. value = ioread32(fotg210->reg + FOTG210_DMATFNR);
  212. if (ep->epnum)
  213. value |= DMATFNR_ACC_FN(ep->epnum - 1);
  214. else
  215. value |= DMATFNR_ACC_CXF;
  216. iowrite32(value, fotg210->reg + FOTG210_DMATFNR);
  217. /* set DMA memory address */
  218. iowrite32(d, fotg210->reg + FOTG210_DMACPSR2);
  219. /* enable MDMA_EROR and MDMA_CMPLT interrupt */
  220. value = ioread32(fotg210->reg + FOTG210_DMISGR2);
  221. value &= ~(DMISGR2_MDMA_CMPLT | DMISGR2_MDMA_ERROR);
  222. iowrite32(value, fotg210->reg + FOTG210_DMISGR2);
  223. /* start DMA */
  224. value = ioread32(fotg210->reg + FOTG210_DMACPSR1);
  225. value |= DMACPSR1_DMA_START;
  226. iowrite32(value, fotg210->reg + FOTG210_DMACPSR1);
  227. }
  228. static void fotg210_disable_dma(struct fotg210_ep *ep)
  229. {
  230. iowrite32(DMATFNR_DISDMA, ep->fotg210->reg + FOTG210_DMATFNR);
  231. }
  232. static void fotg210_wait_dma_done(struct fotg210_ep *ep)
  233. {
  234. u32 value;
  235. do {
  236. value = ioread32(ep->fotg210->reg + FOTG210_DISGR2);
  237. if ((value & DISGR2_USBRST_INT) ||
  238. (value & DISGR2_DMA_ERROR))
  239. goto dma_reset;
  240. } while (!(value & DISGR2_DMA_CMPLT));
  241. value &= ~DISGR2_DMA_CMPLT;
  242. iowrite32(value, ep->fotg210->reg + FOTG210_DISGR2);
  243. return;
  244. dma_reset:
  245. value = ioread32(ep->fotg210->reg + FOTG210_DMACPSR1);
  246. value |= DMACPSR1_DMA_ABORT;
  247. iowrite32(value, ep->fotg210->reg + FOTG210_DMACPSR1);
  248. /* reset fifo */
  249. if (ep->epnum) {
  250. value = ioread32(ep->fotg210->reg +
  251. FOTG210_FIBCR(ep->epnum - 1));
  252. value |= FIBCR_FFRST;
  253. iowrite32(value, ep->fotg210->reg +
  254. FOTG210_FIBCR(ep->epnum - 1));
  255. } else {
  256. value = ioread32(ep->fotg210->reg + FOTG210_DCFESR);
  257. value |= DCFESR_CX_CLR;
  258. iowrite32(value, ep->fotg210->reg + FOTG210_DCFESR);
  259. }
  260. }
  261. static void fotg210_start_dma(struct fotg210_ep *ep,
  262. struct fotg210_request *req)
  263. {
  264. dma_addr_t d;
  265. u8 *buffer;
  266. u32 length;
  267. if (ep->epnum) {
  268. if (ep->dir_in) {
  269. buffer = req->req.buf;
  270. length = req->req.length;
  271. } else {
  272. buffer = req->req.buf + req->req.actual;
  273. length = ioread32(ep->fotg210->reg +
  274. FOTG210_FIBCR(ep->epnum - 1));
  275. length &= FIBCR_BCFX;
  276. }
  277. } else {
  278. buffer = req->req.buf + req->req.actual;
  279. if (req->req.length - req->req.actual > ep->ep.maxpacket)
  280. length = ep->ep.maxpacket;
  281. else
  282. length = req->req.length;
  283. }
  284. d = dma_map_single(NULL, buffer, length,
  285. ep->dir_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  286. if (dma_mapping_error(NULL, d)) {
  287. pr_err("dma_mapping_error\n");
  288. return;
  289. }
  290. dma_sync_single_for_device(NULL, d, length,
  291. ep->dir_in ? DMA_TO_DEVICE :
  292. DMA_FROM_DEVICE);
  293. fotg210_enable_dma(ep, d, length);
  294. /* check if dma is done */
  295. fotg210_wait_dma_done(ep);
  296. fotg210_disable_dma(ep);
  297. /* update actual transfer length */
  298. req->req.actual += length;
  299. dma_unmap_single(NULL, d, length, DMA_TO_DEVICE);
  300. }
  301. static void fotg210_ep0_queue(struct fotg210_ep *ep,
  302. struct fotg210_request *req)
  303. {
  304. if (!req->req.length) {
  305. fotg210_done(ep, req, 0);
  306. return;
  307. }
  308. if (ep->dir_in) { /* if IN */
  309. fotg210_start_dma(ep, req);
  310. if ((req->req.length == req->req.actual) ||
  311. (req->req.actual < ep->ep.maxpacket))
  312. fotg210_done(ep, req, 0);
  313. } else { /* OUT */
  314. u32 value = ioread32(ep->fotg210->reg + FOTG210_DMISGR0);
  315. value &= ~DMISGR0_MCX_OUT_INT;
  316. iowrite32(value, ep->fotg210->reg + FOTG210_DMISGR0);
  317. }
  318. }
  319. static int fotg210_ep_queue(struct usb_ep *_ep, struct usb_request *_req,
  320. gfp_t gfp_flags)
  321. {
  322. struct fotg210_ep *ep;
  323. struct fotg210_request *req;
  324. unsigned long flags;
  325. int request = 0;
  326. ep = container_of(_ep, struct fotg210_ep, ep);
  327. req = container_of(_req, struct fotg210_request, req);
  328. if (ep->fotg210->gadget.speed == USB_SPEED_UNKNOWN)
  329. return -ESHUTDOWN;
  330. spin_lock_irqsave(&ep->fotg210->lock, flags);
  331. if (list_empty(&ep->queue))
  332. request = 1;
  333. list_add_tail(&req->queue, &ep->queue);
  334. req->req.actual = 0;
  335. req->req.status = -EINPROGRESS;
  336. if (!ep->epnum) /* ep0 */
  337. fotg210_ep0_queue(ep, req);
  338. else if (request && !ep->stall)
  339. fotg210_enable_fifo_int(ep);
  340. spin_unlock_irqrestore(&ep->fotg210->lock, flags);
  341. return 0;
  342. }
  343. static int fotg210_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  344. {
  345. struct fotg210_ep *ep;
  346. struct fotg210_request *req;
  347. unsigned long flags;
  348. ep = container_of(_ep, struct fotg210_ep, ep);
  349. req = container_of(_req, struct fotg210_request, req);
  350. spin_lock_irqsave(&ep->fotg210->lock, flags);
  351. if (!list_empty(&ep->queue))
  352. fotg210_done(ep, req, -ECONNRESET);
  353. spin_unlock_irqrestore(&ep->fotg210->lock, flags);
  354. return 0;
  355. }
  356. static void fotg210_set_epnstall(struct fotg210_ep *ep)
  357. {
  358. struct fotg210_udc *fotg210 = ep->fotg210;
  359. u32 value;
  360. void __iomem *reg;
  361. /* check if IN FIFO is empty before stall */
  362. if (ep->dir_in) {
  363. do {
  364. value = ioread32(fotg210->reg + FOTG210_DCFESR);
  365. } while (!(value & DCFESR_FIFO_EMPTY(ep->epnum - 1)));
  366. }
  367. reg = (ep->dir_in) ?
  368. fotg210->reg + FOTG210_INEPMPSR(ep->epnum) :
  369. fotg210->reg + FOTG210_OUTEPMPSR(ep->epnum);
  370. value = ioread32(reg);
  371. value |= INOUTEPMPSR_STL_EP;
  372. iowrite32(value, reg);
  373. }
  374. static void fotg210_clear_epnstall(struct fotg210_ep *ep)
  375. {
  376. struct fotg210_udc *fotg210 = ep->fotg210;
  377. u32 value;
  378. void __iomem *reg;
  379. reg = (ep->dir_in) ?
  380. fotg210->reg + FOTG210_INEPMPSR(ep->epnum) :
  381. fotg210->reg + FOTG210_OUTEPMPSR(ep->epnum);
  382. value = ioread32(reg);
  383. value &= ~INOUTEPMPSR_STL_EP;
  384. iowrite32(value, reg);
  385. }
  386. static int fotg210_set_halt_and_wedge(struct usb_ep *_ep, int value, int wedge)
  387. {
  388. struct fotg210_ep *ep;
  389. struct fotg210_udc *fotg210;
  390. unsigned long flags;
  391. int ret = 0;
  392. ep = container_of(_ep, struct fotg210_ep, ep);
  393. fotg210 = ep->fotg210;
  394. spin_lock_irqsave(&ep->fotg210->lock, flags);
  395. if (value) {
  396. fotg210_set_epnstall(ep);
  397. ep->stall = 1;
  398. if (wedge)
  399. ep->wedged = 1;
  400. } else {
  401. fotg210_reset_tseq(fotg210, ep->epnum);
  402. fotg210_clear_epnstall(ep);
  403. ep->stall = 0;
  404. ep->wedged = 0;
  405. if (!list_empty(&ep->queue))
  406. fotg210_enable_fifo_int(ep);
  407. }
  408. spin_unlock_irqrestore(&ep->fotg210->lock, flags);
  409. return ret;
  410. }
  411. static int fotg210_ep_set_halt(struct usb_ep *_ep, int value)
  412. {
  413. return fotg210_set_halt_and_wedge(_ep, value, 0);
  414. }
  415. static int fotg210_ep_set_wedge(struct usb_ep *_ep)
  416. {
  417. return fotg210_set_halt_and_wedge(_ep, 1, 1);
  418. }
  419. static void fotg210_ep_fifo_flush(struct usb_ep *_ep)
  420. {
  421. }
  422. static const struct usb_ep_ops fotg210_ep_ops = {
  423. .enable = fotg210_ep_enable,
  424. .disable = fotg210_ep_disable,
  425. .alloc_request = fotg210_ep_alloc_request,
  426. .free_request = fotg210_ep_free_request,
  427. .queue = fotg210_ep_queue,
  428. .dequeue = fotg210_ep_dequeue,
  429. .set_halt = fotg210_ep_set_halt,
  430. .fifo_flush = fotg210_ep_fifo_flush,
  431. .set_wedge = fotg210_ep_set_wedge,
  432. };
  433. static void fotg210_clear_tx0byte(struct fotg210_udc *fotg210)
  434. {
  435. u32 value = ioread32(fotg210->reg + FOTG210_TX0BYTE);
  436. value &= ~(TX0BYTE_EP1 | TX0BYTE_EP2 | TX0BYTE_EP3
  437. | TX0BYTE_EP4);
  438. iowrite32(value, fotg210->reg + FOTG210_TX0BYTE);
  439. }
  440. static void fotg210_clear_rx0byte(struct fotg210_udc *fotg210)
  441. {
  442. u32 value = ioread32(fotg210->reg + FOTG210_RX0BYTE);
  443. value &= ~(RX0BYTE_EP1 | RX0BYTE_EP2 | RX0BYTE_EP3
  444. | RX0BYTE_EP4);
  445. iowrite32(value, fotg210->reg + FOTG210_RX0BYTE);
  446. }
  447. /* read 8-byte setup packet only */
  448. static void fotg210_rdsetupp(struct fotg210_udc *fotg210,
  449. u8 *buffer)
  450. {
  451. int i = 0;
  452. u8 *tmp = buffer;
  453. u32 data;
  454. u32 length = 8;
  455. iowrite32(DMATFNR_ACC_CXF, fotg210->reg + FOTG210_DMATFNR);
  456. for (i = (length >> 2); i > 0; i--) {
  457. data = ioread32(fotg210->reg + FOTG210_CXPORT);
  458. *tmp = data & 0xFF;
  459. *(tmp + 1) = (data >> 8) & 0xFF;
  460. *(tmp + 2) = (data >> 16) & 0xFF;
  461. *(tmp + 3) = (data >> 24) & 0xFF;
  462. tmp = tmp + 4;
  463. }
  464. switch (length % 4) {
  465. case 1:
  466. data = ioread32(fotg210->reg + FOTG210_CXPORT);
  467. *tmp = data & 0xFF;
  468. break;
  469. case 2:
  470. data = ioread32(fotg210->reg + FOTG210_CXPORT);
  471. *tmp = data & 0xFF;
  472. *(tmp + 1) = (data >> 8) & 0xFF;
  473. break;
  474. case 3:
  475. data = ioread32(fotg210->reg + FOTG210_CXPORT);
  476. *tmp = data & 0xFF;
  477. *(tmp + 1) = (data >> 8) & 0xFF;
  478. *(tmp + 2) = (data >> 16) & 0xFF;
  479. break;
  480. default:
  481. break;
  482. }
  483. iowrite32(DMATFNR_DISDMA, fotg210->reg + FOTG210_DMATFNR);
  484. }
  485. static void fotg210_set_configuration(struct fotg210_udc *fotg210)
  486. {
  487. u32 value = ioread32(fotg210->reg + FOTG210_DAR);
  488. value |= DAR_AFT_CONF;
  489. iowrite32(value, fotg210->reg + FOTG210_DAR);
  490. }
  491. static void fotg210_set_dev_addr(struct fotg210_udc *fotg210, u32 addr)
  492. {
  493. u32 value = ioread32(fotg210->reg + FOTG210_DAR);
  494. value |= (addr & 0x7F);
  495. iowrite32(value, fotg210->reg + FOTG210_DAR);
  496. }
  497. static void fotg210_set_cxstall(struct fotg210_udc *fotg210)
  498. {
  499. u32 value = ioread32(fotg210->reg + FOTG210_DCFESR);
  500. value |= DCFESR_CX_STL;
  501. iowrite32(value, fotg210->reg + FOTG210_DCFESR);
  502. }
  503. static void fotg210_request_error(struct fotg210_udc *fotg210)
  504. {
  505. fotg210_set_cxstall(fotg210);
  506. pr_err("request error!!\n");
  507. }
  508. static void fotg210_set_address(struct fotg210_udc *fotg210,
  509. struct usb_ctrlrequest *ctrl)
  510. {
  511. if (ctrl->wValue >= 0x0100) {
  512. fotg210_request_error(fotg210);
  513. } else {
  514. fotg210_set_dev_addr(fotg210, ctrl->wValue);
  515. fotg210_set_cxdone(fotg210);
  516. }
  517. }
  518. static void fotg210_set_feature(struct fotg210_udc *fotg210,
  519. struct usb_ctrlrequest *ctrl)
  520. {
  521. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  522. case USB_RECIP_DEVICE:
  523. fotg210_set_cxdone(fotg210);
  524. break;
  525. case USB_RECIP_INTERFACE:
  526. fotg210_set_cxdone(fotg210);
  527. break;
  528. case USB_RECIP_ENDPOINT: {
  529. u8 epnum;
  530. epnum = le16_to_cpu(ctrl->wIndex) & USB_ENDPOINT_NUMBER_MASK;
  531. if (epnum)
  532. fotg210_set_epnstall(fotg210->ep[epnum]);
  533. else
  534. fotg210_set_cxstall(fotg210);
  535. fotg210_set_cxdone(fotg210);
  536. }
  537. break;
  538. default:
  539. fotg210_request_error(fotg210);
  540. break;
  541. }
  542. }
  543. static void fotg210_clear_feature(struct fotg210_udc *fotg210,
  544. struct usb_ctrlrequest *ctrl)
  545. {
  546. struct fotg210_ep *ep =
  547. fotg210->ep[ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK];
  548. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  549. case USB_RECIP_DEVICE:
  550. fotg210_set_cxdone(fotg210);
  551. break;
  552. case USB_RECIP_INTERFACE:
  553. fotg210_set_cxdone(fotg210);
  554. break;
  555. case USB_RECIP_ENDPOINT:
  556. if (ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK) {
  557. if (ep->wedged) {
  558. fotg210_set_cxdone(fotg210);
  559. break;
  560. }
  561. if (ep->stall)
  562. fotg210_set_halt_and_wedge(&ep->ep, 0, 0);
  563. }
  564. fotg210_set_cxdone(fotg210);
  565. break;
  566. default:
  567. fotg210_request_error(fotg210);
  568. break;
  569. }
  570. }
  571. static int fotg210_is_epnstall(struct fotg210_ep *ep)
  572. {
  573. struct fotg210_udc *fotg210 = ep->fotg210;
  574. u32 value;
  575. void __iomem *reg;
  576. reg = (ep->dir_in) ?
  577. fotg210->reg + FOTG210_INEPMPSR(ep->epnum) :
  578. fotg210->reg + FOTG210_OUTEPMPSR(ep->epnum);
  579. value = ioread32(reg);
  580. return value & INOUTEPMPSR_STL_EP ? 1 : 0;
  581. }
  582. static void fotg210_get_status(struct fotg210_udc *fotg210,
  583. struct usb_ctrlrequest *ctrl)
  584. {
  585. u8 epnum;
  586. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  587. case USB_RECIP_DEVICE:
  588. fotg210->ep0_data = 1 << USB_DEVICE_SELF_POWERED;
  589. break;
  590. case USB_RECIP_INTERFACE:
  591. fotg210->ep0_data = 0;
  592. break;
  593. case USB_RECIP_ENDPOINT:
  594. epnum = ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK;
  595. if (epnum)
  596. fotg210->ep0_data =
  597. fotg210_is_epnstall(fotg210->ep[epnum])
  598. << USB_ENDPOINT_HALT;
  599. else
  600. fotg210_request_error(fotg210);
  601. break;
  602. default:
  603. fotg210_request_error(fotg210);
  604. return; /* exit */
  605. }
  606. fotg210->ep0_req->buf = &fotg210->ep0_data;
  607. fotg210->ep0_req->length = 2;
  608. spin_unlock(&fotg210->lock);
  609. fotg210_ep_queue(fotg210->gadget.ep0, fotg210->ep0_req, GFP_ATOMIC);
  610. spin_lock(&fotg210->lock);
  611. }
  612. static int fotg210_setup_packet(struct fotg210_udc *fotg210,
  613. struct usb_ctrlrequest *ctrl)
  614. {
  615. u8 *p = (u8 *)ctrl;
  616. u8 ret = 0;
  617. fotg210_rdsetupp(fotg210, p);
  618. fotg210->ep[0]->dir_in = ctrl->bRequestType & USB_DIR_IN;
  619. if (fotg210->gadget.speed == USB_SPEED_UNKNOWN) {
  620. u32 value = ioread32(fotg210->reg + FOTG210_DMCR);
  621. fotg210->gadget.speed = value & DMCR_HS_EN ?
  622. USB_SPEED_HIGH : USB_SPEED_FULL;
  623. }
  624. /* check request */
  625. if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
  626. switch (ctrl->bRequest) {
  627. case USB_REQ_GET_STATUS:
  628. fotg210_get_status(fotg210, ctrl);
  629. break;
  630. case USB_REQ_CLEAR_FEATURE:
  631. fotg210_clear_feature(fotg210, ctrl);
  632. break;
  633. case USB_REQ_SET_FEATURE:
  634. fotg210_set_feature(fotg210, ctrl);
  635. break;
  636. case USB_REQ_SET_ADDRESS:
  637. fotg210_set_address(fotg210, ctrl);
  638. break;
  639. case USB_REQ_SET_CONFIGURATION:
  640. fotg210_set_configuration(fotg210);
  641. ret = 1;
  642. break;
  643. default:
  644. ret = 1;
  645. break;
  646. }
  647. } else {
  648. ret = 1;
  649. }
  650. return ret;
  651. }
  652. static void fotg210_ep0out(struct fotg210_udc *fotg210)
  653. {
  654. struct fotg210_ep *ep = fotg210->ep[0];
  655. if (!list_empty(&ep->queue) && !ep->dir_in) {
  656. struct fotg210_request *req;
  657. req = list_first_entry(&ep->queue,
  658. struct fotg210_request, queue);
  659. if (req->req.length)
  660. fotg210_start_dma(ep, req);
  661. if ((req->req.length - req->req.actual) < ep->ep.maxpacket)
  662. fotg210_done(ep, req, 0);
  663. } else {
  664. pr_err("%s : empty queue\n", __func__);
  665. }
  666. }
  667. static void fotg210_ep0in(struct fotg210_udc *fotg210)
  668. {
  669. struct fotg210_ep *ep = fotg210->ep[0];
  670. if ((!list_empty(&ep->queue)) && (ep->dir_in)) {
  671. struct fotg210_request *req;
  672. req = list_entry(ep->queue.next,
  673. struct fotg210_request, queue);
  674. if (req->req.length)
  675. fotg210_start_dma(ep, req);
  676. if ((req->req.length - req->req.actual) < ep->ep.maxpacket)
  677. fotg210_done(ep, req, 0);
  678. } else {
  679. fotg210_set_cxdone(fotg210);
  680. }
  681. }
  682. static void fotg210_clear_comabt_int(struct fotg210_udc *fotg210)
  683. {
  684. u32 value = ioread32(fotg210->reg + FOTG210_DISGR0);
  685. value &= ~DISGR0_CX_COMABT_INT;
  686. iowrite32(value, fotg210->reg + FOTG210_DISGR0);
  687. }
  688. static void fotg210_in_fifo_handler(struct fotg210_ep *ep)
  689. {
  690. struct fotg210_request *req = list_entry(ep->queue.next,
  691. struct fotg210_request, queue);
  692. if (req->req.length)
  693. fotg210_start_dma(ep, req);
  694. fotg210_done(ep, req, 0);
  695. }
  696. static void fotg210_out_fifo_handler(struct fotg210_ep *ep)
  697. {
  698. struct fotg210_request *req = list_entry(ep->queue.next,
  699. struct fotg210_request, queue);
  700. fotg210_start_dma(ep, req);
  701. /* finish out transfer */
  702. if (req->req.length == req->req.actual ||
  703. req->req.actual < ep->ep.maxpacket)
  704. fotg210_done(ep, req, 0);
  705. }
  706. static irqreturn_t fotg210_irq(int irq, void *_fotg210)
  707. {
  708. struct fotg210_udc *fotg210 = _fotg210;
  709. u32 int_grp = ioread32(fotg210->reg + FOTG210_DIGR);
  710. u32 int_msk = ioread32(fotg210->reg + FOTG210_DMIGR);
  711. int_grp &= ~int_msk;
  712. spin_lock(&fotg210->lock);
  713. if (int_grp & DIGR_INT_G2) {
  714. void __iomem *reg = fotg210->reg + FOTG210_DISGR2;
  715. u32 int_grp2 = ioread32(reg);
  716. u32 int_msk2 = ioread32(fotg210->reg + FOTG210_DMISGR2);
  717. u32 value;
  718. int_grp2 &= ~int_msk2;
  719. if (int_grp2 & DISGR2_USBRST_INT) {
  720. value = ioread32(reg);
  721. value &= ~DISGR2_USBRST_INT;
  722. iowrite32(value, reg);
  723. pr_info("fotg210 udc reset\n");
  724. }
  725. if (int_grp2 & DISGR2_SUSP_INT) {
  726. value = ioread32(reg);
  727. value &= ~DISGR2_SUSP_INT;
  728. iowrite32(value, reg);
  729. pr_info("fotg210 udc suspend\n");
  730. }
  731. if (int_grp2 & DISGR2_RESM_INT) {
  732. value = ioread32(reg);
  733. value &= ~DISGR2_RESM_INT;
  734. iowrite32(value, reg);
  735. pr_info("fotg210 udc resume\n");
  736. }
  737. if (int_grp2 & DISGR2_ISO_SEQ_ERR_INT) {
  738. value = ioread32(reg);
  739. value &= ~DISGR2_ISO_SEQ_ERR_INT;
  740. iowrite32(value, reg);
  741. pr_info("fotg210 iso sequence error\n");
  742. }
  743. if (int_grp2 & DISGR2_ISO_SEQ_ABORT_INT) {
  744. value = ioread32(reg);
  745. value &= ~DISGR2_ISO_SEQ_ABORT_INT;
  746. iowrite32(value, reg);
  747. pr_info("fotg210 iso sequence abort\n");
  748. }
  749. if (int_grp2 & DISGR2_TX0BYTE_INT) {
  750. fotg210_clear_tx0byte(fotg210);
  751. value = ioread32(reg);
  752. value &= ~DISGR2_TX0BYTE_INT;
  753. iowrite32(value, reg);
  754. pr_info("fotg210 transferred 0 byte\n");
  755. }
  756. if (int_grp2 & DISGR2_RX0BYTE_INT) {
  757. fotg210_clear_rx0byte(fotg210);
  758. value = ioread32(reg);
  759. value &= ~DISGR2_RX0BYTE_INT;
  760. iowrite32(value, reg);
  761. pr_info("fotg210 received 0 byte\n");
  762. }
  763. if (int_grp2 & DISGR2_DMA_ERROR) {
  764. value = ioread32(reg);
  765. value &= ~DISGR2_DMA_ERROR;
  766. iowrite32(value, reg);
  767. }
  768. }
  769. if (int_grp & DIGR_INT_G0) {
  770. void __iomem *reg = fotg210->reg + FOTG210_DISGR0;
  771. u32 int_grp0 = ioread32(reg);
  772. u32 int_msk0 = ioread32(fotg210->reg + FOTG210_DMISGR0);
  773. struct usb_ctrlrequest ctrl;
  774. int_grp0 &= ~int_msk0;
  775. /* the highest priority in this source register */
  776. if (int_grp0 & DISGR0_CX_COMABT_INT) {
  777. fotg210_clear_comabt_int(fotg210);
  778. pr_info("fotg210 CX command abort\n");
  779. }
  780. if (int_grp0 & DISGR0_CX_SETUP_INT) {
  781. if (fotg210_setup_packet(fotg210, &ctrl)) {
  782. spin_unlock(&fotg210->lock);
  783. if (fotg210->driver->setup(&fotg210->gadget,
  784. &ctrl) < 0)
  785. fotg210_set_cxstall(fotg210);
  786. spin_lock(&fotg210->lock);
  787. }
  788. }
  789. if (int_grp0 & DISGR0_CX_COMEND_INT)
  790. pr_info("fotg210 cmd end\n");
  791. if (int_grp0 & DISGR0_CX_IN_INT)
  792. fotg210_ep0in(fotg210);
  793. if (int_grp0 & DISGR0_CX_OUT_INT)
  794. fotg210_ep0out(fotg210);
  795. if (int_grp0 & DISGR0_CX_COMFAIL_INT) {
  796. fotg210_set_cxstall(fotg210);
  797. pr_info("fotg210 ep0 fail\n");
  798. }
  799. }
  800. if (int_grp & DIGR_INT_G1) {
  801. void __iomem *reg = fotg210->reg + FOTG210_DISGR1;
  802. u32 int_grp1 = ioread32(reg);
  803. u32 int_msk1 = ioread32(fotg210->reg + FOTG210_DMISGR1);
  804. int fifo;
  805. int_grp1 &= ~int_msk1;
  806. for (fifo = 0; fifo < FOTG210_MAX_FIFO_NUM; fifo++) {
  807. if (int_grp1 & DISGR1_IN_INT(fifo))
  808. fotg210_in_fifo_handler(fotg210->ep[fifo + 1]);
  809. if ((int_grp1 & DISGR1_OUT_INT(fifo)) ||
  810. (int_grp1 & DISGR1_SPK_INT(fifo)))
  811. fotg210_out_fifo_handler(fotg210->ep[fifo + 1]);
  812. }
  813. }
  814. spin_unlock(&fotg210->lock);
  815. return IRQ_HANDLED;
  816. }
  817. static void fotg210_disable_unplug(struct fotg210_udc *fotg210)
  818. {
  819. u32 reg = ioread32(fotg210->reg + FOTG210_PHYTMSR);
  820. reg &= ~PHYTMSR_UNPLUG;
  821. iowrite32(reg, fotg210->reg + FOTG210_PHYTMSR);
  822. }
  823. static int fotg210_udc_start(struct usb_gadget *g,
  824. struct usb_gadget_driver *driver)
  825. {
  826. struct fotg210_udc *fotg210 = gadget_to_fotg210(g);
  827. u32 value;
  828. /* hook up the driver */
  829. driver->driver.bus = NULL;
  830. fotg210->driver = driver;
  831. /* enable device global interrupt */
  832. value = ioread32(fotg210->reg + FOTG210_DMCR);
  833. value |= DMCR_GLINT_EN;
  834. iowrite32(value, fotg210->reg + FOTG210_DMCR);
  835. return 0;
  836. }
  837. static void fotg210_init(struct fotg210_udc *fotg210)
  838. {
  839. u32 value;
  840. /* disable global interrupt and set int polarity to active high */
  841. iowrite32(GMIR_MHC_INT | GMIR_MOTG_INT | GMIR_INT_POLARITY,
  842. fotg210->reg + FOTG210_GMIR);
  843. /* disable device global interrupt */
  844. value = ioread32(fotg210->reg + FOTG210_DMCR);
  845. value &= ~DMCR_GLINT_EN;
  846. iowrite32(value, fotg210->reg + FOTG210_DMCR);
  847. /* disable all fifo interrupt */
  848. iowrite32(~(u32)0, fotg210->reg + FOTG210_DMISGR1);
  849. /* disable cmd end */
  850. value = ioread32(fotg210->reg + FOTG210_DMISGR0);
  851. value |= DMISGR0_MCX_COMEND;
  852. iowrite32(value, fotg210->reg + FOTG210_DMISGR0);
  853. }
  854. static int fotg210_udc_stop(struct usb_gadget *g)
  855. {
  856. struct fotg210_udc *fotg210 = gadget_to_fotg210(g);
  857. unsigned long flags;
  858. spin_lock_irqsave(&fotg210->lock, flags);
  859. fotg210_init(fotg210);
  860. fotg210->driver = NULL;
  861. spin_unlock_irqrestore(&fotg210->lock, flags);
  862. return 0;
  863. }
  864. static const struct usb_gadget_ops fotg210_gadget_ops = {
  865. .udc_start = fotg210_udc_start,
  866. .udc_stop = fotg210_udc_stop,
  867. };
  868. static int fotg210_udc_remove(struct platform_device *pdev)
  869. {
  870. struct fotg210_udc *fotg210 = platform_get_drvdata(pdev);
  871. int i;
  872. usb_del_gadget_udc(&fotg210->gadget);
  873. iounmap(fotg210->reg);
  874. free_irq(platform_get_irq(pdev, 0), fotg210);
  875. fotg210_ep_free_request(&fotg210->ep[0]->ep, fotg210->ep0_req);
  876. for (i = 0; i < FOTG210_MAX_NUM_EP; i++)
  877. kfree(fotg210->ep[i]);
  878. kfree(fotg210);
  879. return 0;
  880. }
  881. static int fotg210_udc_probe(struct platform_device *pdev)
  882. {
  883. struct resource *res, *ires;
  884. struct fotg210_udc *fotg210 = NULL;
  885. struct fotg210_ep *_ep[FOTG210_MAX_NUM_EP];
  886. int ret = 0;
  887. int i;
  888. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  889. if (!res) {
  890. pr_err("platform_get_resource error.\n");
  891. return -ENODEV;
  892. }
  893. ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  894. if (!ires) {
  895. pr_err("platform_get_resource IORESOURCE_IRQ error.\n");
  896. return -ENODEV;
  897. }
  898. ret = -ENOMEM;
  899. /* initialize udc */
  900. fotg210 = kzalloc(sizeof(struct fotg210_udc), GFP_KERNEL);
  901. if (fotg210 == NULL)
  902. goto err;
  903. for (i = 0; i < FOTG210_MAX_NUM_EP; i++) {
  904. _ep[i] = kzalloc(sizeof(struct fotg210_ep), GFP_KERNEL);
  905. if (_ep[i] == NULL)
  906. goto err_alloc;
  907. fotg210->ep[i] = _ep[i];
  908. }
  909. fotg210->reg = ioremap(res->start, resource_size(res));
  910. if (fotg210->reg == NULL) {
  911. pr_err("ioremap error.\n");
  912. goto err_alloc;
  913. }
  914. spin_lock_init(&fotg210->lock);
  915. platform_set_drvdata(pdev, fotg210);
  916. fotg210->gadget.ops = &fotg210_gadget_ops;
  917. fotg210->gadget.max_speed = USB_SPEED_HIGH;
  918. fotg210->gadget.dev.parent = &pdev->dev;
  919. fotg210->gadget.dev.dma_mask = pdev->dev.dma_mask;
  920. fotg210->gadget.name = udc_name;
  921. INIT_LIST_HEAD(&fotg210->gadget.ep_list);
  922. for (i = 0; i < FOTG210_MAX_NUM_EP; i++) {
  923. struct fotg210_ep *ep = fotg210->ep[i];
  924. if (i) {
  925. INIT_LIST_HEAD(&fotg210->ep[i]->ep.ep_list);
  926. list_add_tail(&fotg210->ep[i]->ep.ep_list,
  927. &fotg210->gadget.ep_list);
  928. }
  929. ep->fotg210 = fotg210;
  930. INIT_LIST_HEAD(&ep->queue);
  931. ep->ep.name = fotg210_ep_name[i];
  932. ep->ep.ops = &fotg210_ep_ops;
  933. usb_ep_set_maxpacket_limit(&ep->ep, (unsigned short) ~0);
  934. if (i == 0) {
  935. ep->ep.caps.type_control = true;
  936. } else {
  937. ep->ep.caps.type_iso = true;
  938. ep->ep.caps.type_bulk = true;
  939. ep->ep.caps.type_int = true;
  940. }
  941. ep->ep.caps.dir_in = true;
  942. ep->ep.caps.dir_out = true;
  943. }
  944. usb_ep_set_maxpacket_limit(&fotg210->ep[0]->ep, 0x40);
  945. fotg210->gadget.ep0 = &fotg210->ep[0]->ep;
  946. INIT_LIST_HEAD(&fotg210->gadget.ep0->ep_list);
  947. fotg210->ep0_req = fotg210_ep_alloc_request(&fotg210->ep[0]->ep,
  948. GFP_KERNEL);
  949. if (fotg210->ep0_req == NULL)
  950. goto err_map;
  951. fotg210_init(fotg210);
  952. fotg210_disable_unplug(fotg210);
  953. ret = request_irq(ires->start, fotg210_irq, IRQF_SHARED,
  954. udc_name, fotg210);
  955. if (ret < 0) {
  956. pr_err("request_irq error (%d)\n", ret);
  957. goto err_req;
  958. }
  959. ret = usb_add_gadget_udc(&pdev->dev, &fotg210->gadget);
  960. if (ret)
  961. goto err_add_udc;
  962. dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION);
  963. return 0;
  964. err_add_udc:
  965. free_irq(ires->start, fotg210);
  966. err_req:
  967. fotg210_ep_free_request(&fotg210->ep[0]->ep, fotg210->ep0_req);
  968. err_map:
  969. iounmap(fotg210->reg);
  970. err_alloc:
  971. for (i = 0; i < FOTG210_MAX_NUM_EP; i++)
  972. kfree(fotg210->ep[i]);
  973. kfree(fotg210);
  974. err:
  975. return ret;
  976. }
  977. static struct platform_driver fotg210_driver = {
  978. .driver = {
  979. .name = (char *)udc_name,
  980. },
  981. .probe = fotg210_udc_probe,
  982. .remove = fotg210_udc_remove,
  983. };
  984. module_platform_driver(fotg210_driver);
  985. MODULE_AUTHOR("Yuan-Hsin Chen, Feng-Hsin Chiang <john453@faraday-tech.com>");
  986. MODULE_LICENSE("GPL");
  987. MODULE_DESCRIPTION(DRIVER_DESC);