qcom-spmi-temp-alarm.c 8.2 KB

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  1. /*
  2. * Copyright (c) 2011-2015, 2017, The Linux Foundation. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 and
  6. * only version 2 as published by the Free Software Foundation.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. */
  13. #include <linux/bitops.h>
  14. #include <linux/delay.h>
  15. #include <linux/err.h>
  16. #include <linux/iio/consumer.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/module.h>
  19. #include <linux/of.h>
  20. #include <linux/of_device.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/regmap.h>
  23. #include <linux/thermal.h>
  24. #define QPNP_TM_REG_TYPE 0x04
  25. #define QPNP_TM_REG_SUBTYPE 0x05
  26. #define QPNP_TM_REG_STATUS 0x08
  27. #define QPNP_TM_REG_SHUTDOWN_CTRL1 0x40
  28. #define QPNP_TM_REG_ALARM_CTRL 0x46
  29. #define QPNP_TM_TYPE 0x09
  30. #define QPNP_TM_SUBTYPE_GEN1 0x08
  31. #define QPNP_TM_SUBTYPE_GEN2 0x09
  32. #define STATUS_GEN1_STAGE_MASK GENMASK(1, 0)
  33. #define STATUS_GEN2_STATE_MASK GENMASK(6, 4)
  34. #define STATUS_GEN2_STATE_SHIFT 4
  35. #define SHUTDOWN_CTRL1_OVERRIDE_MASK GENMASK(7, 6)
  36. #define SHUTDOWN_CTRL1_THRESHOLD_MASK GENMASK(1, 0)
  37. #define ALARM_CTRL_FORCE_ENABLE BIT(7)
  38. /*
  39. * Trip point values based on threshold control
  40. * 0 = {105 C, 125 C, 145 C}
  41. * 1 = {110 C, 130 C, 150 C}
  42. * 2 = {115 C, 135 C, 155 C}
  43. * 3 = {120 C, 140 C, 160 C}
  44. */
  45. #define TEMP_STAGE_STEP 20000 /* Stage step: 20.000 C */
  46. #define TEMP_STAGE_HYSTERESIS 2000
  47. #define TEMP_THRESH_MIN 105000 /* Threshold Min: 105 C */
  48. #define TEMP_THRESH_STEP 5000 /* Threshold step: 5 C */
  49. #define THRESH_MIN 0
  50. /* Temperature in Milli Celsius reported during stage 0 if no ADC is present */
  51. #define DEFAULT_TEMP 37000
  52. struct qpnp_tm_chip {
  53. struct regmap *map;
  54. struct thermal_zone_device *tz_dev;
  55. unsigned int subtype;
  56. long temp;
  57. unsigned int thresh;
  58. unsigned int stage;
  59. unsigned int prev_stage;
  60. unsigned int base;
  61. struct iio_channel *adc;
  62. };
  63. /* This array maps from GEN2 alarm state to GEN1 alarm stage */
  64. static const unsigned int alarm_state_map[8] = {0, 1, 1, 2, 2, 3, 3, 3};
  65. static int qpnp_tm_read(struct qpnp_tm_chip *chip, u16 addr, u8 *data)
  66. {
  67. unsigned int val;
  68. int ret;
  69. ret = regmap_read(chip->map, chip->base + addr, &val);
  70. if (ret < 0)
  71. return ret;
  72. *data = val;
  73. return 0;
  74. }
  75. static int qpnp_tm_write(struct qpnp_tm_chip *chip, u16 addr, u8 data)
  76. {
  77. return regmap_write(chip->map, chip->base + addr, data);
  78. }
  79. /**
  80. * qpnp_tm_get_temp_stage() - return over-temperature stage
  81. * @chip: Pointer to the qpnp_tm chip
  82. *
  83. * Return: stage (GEN1) or state (GEN2) on success, or errno on failure.
  84. */
  85. static int qpnp_tm_get_temp_stage(struct qpnp_tm_chip *chip)
  86. {
  87. int ret;
  88. u8 reg = 0;
  89. ret = qpnp_tm_read(chip, QPNP_TM_REG_STATUS, &reg);
  90. if (ret < 0)
  91. return ret;
  92. if (chip->subtype == QPNP_TM_SUBTYPE_GEN1)
  93. ret = reg & STATUS_GEN1_STAGE_MASK;
  94. else
  95. ret = (reg & STATUS_GEN2_STATE_MASK) >> STATUS_GEN2_STATE_SHIFT;
  96. return ret;
  97. }
  98. /*
  99. * This function updates the internal temp value based on the
  100. * current thermal stage and threshold as well as the previous stage
  101. */
  102. static int qpnp_tm_update_temp_no_adc(struct qpnp_tm_chip *chip)
  103. {
  104. unsigned int stage, stage_new, stage_old;
  105. int ret;
  106. ret = qpnp_tm_get_temp_stage(chip);
  107. if (ret < 0)
  108. return ret;
  109. stage = ret;
  110. if (chip->subtype == QPNP_TM_SUBTYPE_GEN1) {
  111. stage_new = stage;
  112. stage_old = chip->stage;
  113. } else {
  114. stage_new = alarm_state_map[stage];
  115. stage_old = alarm_state_map[chip->stage];
  116. }
  117. if (stage_new > stage_old) {
  118. /* increasing stage, use lower bound */
  119. chip->temp = (stage_new - 1) * TEMP_STAGE_STEP +
  120. chip->thresh * TEMP_THRESH_STEP +
  121. TEMP_STAGE_HYSTERESIS + TEMP_THRESH_MIN;
  122. } else if (stage_new < stage_old) {
  123. /* decreasing stage, use upper bound */
  124. chip->temp = stage_new * TEMP_STAGE_STEP +
  125. chip->thresh * TEMP_THRESH_STEP -
  126. TEMP_STAGE_HYSTERESIS + TEMP_THRESH_MIN;
  127. }
  128. chip->stage = stage;
  129. return 0;
  130. }
  131. static int qpnp_tm_get_temp(void *data, int *temp)
  132. {
  133. struct qpnp_tm_chip *chip = data;
  134. int ret, mili_celsius;
  135. if (!temp)
  136. return -EINVAL;
  137. if (!chip->adc) {
  138. ret = qpnp_tm_update_temp_no_adc(chip);
  139. if (ret < 0)
  140. return ret;
  141. } else {
  142. ret = iio_read_channel_processed(chip->adc, &mili_celsius);
  143. if (ret < 0)
  144. return ret;
  145. chip->temp = mili_celsius;
  146. }
  147. *temp = chip->temp < 0 ? 0 : chip->temp;
  148. return 0;
  149. }
  150. static const struct thermal_zone_of_device_ops qpnp_tm_sensor_ops = {
  151. .get_temp = qpnp_tm_get_temp,
  152. };
  153. static irqreturn_t qpnp_tm_isr(int irq, void *data)
  154. {
  155. struct qpnp_tm_chip *chip = data;
  156. thermal_zone_device_update(chip->tz_dev, THERMAL_EVENT_UNSPECIFIED);
  157. return IRQ_HANDLED;
  158. }
  159. /*
  160. * This function initializes the internal temp value based on only the
  161. * current thermal stage and threshold. Setup threshold control and
  162. * disable shutdown override.
  163. */
  164. static int qpnp_tm_init(struct qpnp_tm_chip *chip)
  165. {
  166. unsigned int stage;
  167. int ret;
  168. u8 reg = 0;
  169. ret = qpnp_tm_read(chip, QPNP_TM_REG_SHUTDOWN_CTRL1, &reg);
  170. if (ret < 0)
  171. return ret;
  172. chip->thresh = reg & SHUTDOWN_CTRL1_THRESHOLD_MASK;
  173. chip->temp = DEFAULT_TEMP;
  174. ret = qpnp_tm_get_temp_stage(chip);
  175. if (ret < 0)
  176. return ret;
  177. chip->stage = ret;
  178. stage = chip->subtype == QPNP_TM_SUBTYPE_GEN1
  179. ? chip->stage : alarm_state_map[chip->stage];
  180. if (stage)
  181. chip->temp = chip->thresh * TEMP_THRESH_STEP +
  182. (stage - 1) * TEMP_STAGE_STEP +
  183. TEMP_THRESH_MIN;
  184. /*
  185. * Set threshold and disable software override of stage 2 and 3
  186. * shutdowns.
  187. */
  188. chip->thresh = THRESH_MIN;
  189. reg &= ~(SHUTDOWN_CTRL1_OVERRIDE_MASK | SHUTDOWN_CTRL1_THRESHOLD_MASK);
  190. reg |= chip->thresh & SHUTDOWN_CTRL1_THRESHOLD_MASK;
  191. ret = qpnp_tm_write(chip, QPNP_TM_REG_SHUTDOWN_CTRL1, reg);
  192. if (ret < 0)
  193. return ret;
  194. /* Enable the thermal alarm PMIC module in always-on mode. */
  195. reg = ALARM_CTRL_FORCE_ENABLE;
  196. ret = qpnp_tm_write(chip, QPNP_TM_REG_ALARM_CTRL, reg);
  197. return ret;
  198. }
  199. static int qpnp_tm_probe(struct platform_device *pdev)
  200. {
  201. struct qpnp_tm_chip *chip;
  202. struct device_node *node;
  203. u8 type, subtype;
  204. u32 res;
  205. int ret, irq;
  206. node = pdev->dev.of_node;
  207. chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
  208. if (!chip)
  209. return -ENOMEM;
  210. dev_set_drvdata(&pdev->dev, chip);
  211. chip->map = dev_get_regmap(pdev->dev.parent, NULL);
  212. if (!chip->map)
  213. return -ENXIO;
  214. ret = of_property_read_u32(node, "reg", &res);
  215. if (ret < 0)
  216. return ret;
  217. irq = platform_get_irq(pdev, 0);
  218. if (irq < 0)
  219. return irq;
  220. /* ADC based measurements are optional */
  221. chip->adc = devm_iio_channel_get(&pdev->dev, "thermal");
  222. if (IS_ERR(chip->adc)) {
  223. ret = PTR_ERR(chip->adc);
  224. chip->adc = NULL;
  225. if (ret == -EPROBE_DEFER)
  226. return ret;
  227. }
  228. chip->base = res;
  229. ret = qpnp_tm_read(chip, QPNP_TM_REG_TYPE, &type);
  230. if (ret < 0) {
  231. dev_err(&pdev->dev, "could not read type\n");
  232. return ret;
  233. }
  234. ret = qpnp_tm_read(chip, QPNP_TM_REG_SUBTYPE, &subtype);
  235. if (ret < 0) {
  236. dev_err(&pdev->dev, "could not read subtype\n");
  237. return ret;
  238. }
  239. if (type != QPNP_TM_TYPE || (subtype != QPNP_TM_SUBTYPE_GEN1
  240. && subtype != QPNP_TM_SUBTYPE_GEN2)) {
  241. dev_err(&pdev->dev, "invalid type 0x%02x or subtype 0x%02x\n",
  242. type, subtype);
  243. return -ENODEV;
  244. }
  245. chip->subtype = subtype;
  246. ret = qpnp_tm_init(chip);
  247. if (ret < 0) {
  248. dev_err(&pdev->dev, "init failed\n");
  249. return ret;
  250. }
  251. ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, qpnp_tm_isr,
  252. IRQF_ONESHOT, node->name, chip);
  253. if (ret < 0)
  254. return ret;
  255. chip->tz_dev = devm_thermal_zone_of_sensor_register(&pdev->dev, 0, chip,
  256. &qpnp_tm_sensor_ops);
  257. if (IS_ERR(chip->tz_dev)) {
  258. dev_err(&pdev->dev, "failed to register sensor\n");
  259. return PTR_ERR(chip->tz_dev);
  260. }
  261. return 0;
  262. }
  263. static const struct of_device_id qpnp_tm_match_table[] = {
  264. { .compatible = "qcom,spmi-temp-alarm" },
  265. { }
  266. };
  267. MODULE_DEVICE_TABLE(of, qpnp_tm_match_table);
  268. static struct platform_driver qpnp_tm_driver = {
  269. .driver = {
  270. .name = "spmi-temp-alarm",
  271. .of_match_table = qpnp_tm_match_table,
  272. },
  273. .probe = qpnp_tm_probe,
  274. };
  275. module_platform_driver(qpnp_tm_driver);
  276. MODULE_ALIAS("platform:spmi-temp-alarm");
  277. MODULE_DESCRIPTION("QPNP PMIC Temperature Alarm driver");
  278. MODULE_LICENSE("GPL v2");