pwrseqcmd.h 2.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /******************************************************************************
  3. *
  4. * Copyright(c) 2009-2012 Realtek Corporation.
  5. *
  6. * Contact Information:
  7. * wlanfae <wlanfae@realtek.com>
  8. * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  9. * Hsinchu 300, Taiwan.
  10. *
  11. * Larry Finger <Larry.Finger@lwfinger.net>
  12. *
  13. *****************************************************************************/
  14. #ifndef __RTL8723E_PWRSEQCMD_H__
  15. #define __RTL8723E_PWRSEQCMD_H__
  16. #include "wifi.h"
  17. /*---------------------------------------------
  18. * 3 The value of cmd: 4 bits
  19. *---------------------------------------------
  20. */
  21. #define PWR_CMD_READ 0x00
  22. #define PWR_CMD_WRITE 0x01
  23. #define PWR_CMD_POLLING 0x02
  24. #define PWR_CMD_DELAY 0x03
  25. #define PWR_CMD_END 0x04
  26. /* define the base address of each block */
  27. #define PWR_BASEADDR_MAC 0x00
  28. #define PWR_BASEADDR_USB 0x01
  29. #define PWR_BASEADDR_PCIE 0x02
  30. #define PWR_BASEADDR_SDIO 0x03
  31. #define PWR_INTF_SDIO_MSK BIT(0)
  32. #define PWR_INTF_USB_MSK BIT(1)
  33. #define PWR_INTF_PCI_MSK BIT(2)
  34. #define PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
  35. #define PWR_FAB_TSMC_MSK BIT(0)
  36. #define PWR_FAB_UMC_MSK BIT(1)
  37. #define PWR_FAB_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
  38. #define PWR_CUT_TESTCHIP_MSK BIT(0)
  39. #define PWR_CUT_A_MSK BIT(1)
  40. #define PWR_CUT_B_MSK BIT(2)
  41. #define PWR_CUT_C_MSK BIT(3)
  42. #define PWR_CUT_D_MSK BIT(4)
  43. #define PWR_CUT_E_MSK BIT(5)
  44. #define PWR_CUT_F_MSK BIT(6)
  45. #define PWR_CUT_G_MSK BIT(7)
  46. #define PWR_CUT_ALL_MSK 0xFF
  47. enum pwrseq_delay_unit {
  48. PWRSEQ_DELAY_US,
  49. PWRSEQ_DELAY_MS,
  50. };
  51. struct wlan_pwr_cfg {
  52. u16 offset;
  53. u8 cut_msk;
  54. u8 fab_msk:4;
  55. u8 interface_msk:4;
  56. u8 base:4;
  57. u8 cmd:4;
  58. u8 msk;
  59. u8 value;
  60. };
  61. #define GET_PWR_CFG_OFFSET(__PWR_CMD) (__PWR_CMD.offset)
  62. #define GET_PWR_CFG_CUT_MASK(__PWR_CMD) (__PWR_CMD.cut_msk)
  63. #define GET_PWR_CFG_FAB_MASK(__PWR_CMD) (__PWR_CMD.fab_msk)
  64. #define GET_PWR_CFG_INTF_MASK(__PWR_CMD) (__PWR_CMD.interface_msk)
  65. #define GET_PWR_CFG_BASE(__PWR_CMD) (__PWR_CMD.base)
  66. #define GET_PWR_CFG_CMD(__PWR_CMD) (__PWR_CMD.cmd)
  67. #define GET_PWR_CFG_MASK(__PWR_CMD) (__PWR_CMD.msk)
  68. #define GET_PWR_CFG_VALUE(__PWR_CMD) (__PWR_CMD.value)
  69. bool rtl_hal_pwrseqcmdparsing(struct rtl_priv *rtlpriv, u8 cut_version,
  70. u8 fab_version, u8 interface_type,
  71. struct wlan_pwr_cfg pwrcfgcmd[]);
  72. #endif