ethernet-rx.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * This file is based on code from OCTEON SDK by Cavium Networks.
  4. *
  5. * Copyright (c) 2003-2010 Cavium Networks
  6. */
  7. #include <linux/module.h>
  8. #include <linux/kernel.h>
  9. #include <linux/cache.h>
  10. #include <linux/cpumask.h>
  11. #include <linux/netdevice.h>
  12. #include <linux/etherdevice.h>
  13. #include <linux/ip.h>
  14. #include <linux/string.h>
  15. #include <linux/prefetch.h>
  16. #include <linux/ratelimit.h>
  17. #include <linux/smp.h>
  18. #include <linux/interrupt.h>
  19. #include <net/dst.h>
  20. #ifdef CONFIG_XFRM
  21. #include <linux/xfrm.h>
  22. #include <net/xfrm.h>
  23. #endif /* CONFIG_XFRM */
  24. #include <asm/octeon/octeon.h>
  25. #include "ethernet-defines.h"
  26. #include "ethernet-mem.h"
  27. #include "ethernet-rx.h"
  28. #include "octeon-ethernet.h"
  29. #include "ethernet-util.h"
  30. #include <asm/octeon/cvmx-helper.h>
  31. #include <asm/octeon/cvmx-wqe.h>
  32. #include <asm/octeon/cvmx-fau.h>
  33. #include <asm/octeon/cvmx-pow.h>
  34. #include <asm/octeon/cvmx-pip.h>
  35. #include <asm/octeon/cvmx-scratch.h>
  36. #include <asm/octeon/cvmx-gmxx-defs.h>
  37. static atomic_t oct_rx_ready = ATOMIC_INIT(0);
  38. static struct oct_rx_group {
  39. int irq;
  40. int group;
  41. struct napi_struct napi;
  42. } oct_rx_group[16];
  43. /**
  44. * cvm_oct_do_interrupt - interrupt handler.
  45. * @irq: Interrupt number.
  46. * @napi_id: Cookie to identify the NAPI instance.
  47. *
  48. * The interrupt occurs whenever the POW has packets in our group.
  49. *
  50. */
  51. static irqreturn_t cvm_oct_do_interrupt(int irq, void *napi_id)
  52. {
  53. /* Disable the IRQ and start napi_poll. */
  54. disable_irq_nosync(irq);
  55. napi_schedule(napi_id);
  56. return IRQ_HANDLED;
  57. }
  58. /**
  59. * cvm_oct_check_rcv_error - process receive errors
  60. * @work: Work queue entry pointing to the packet.
  61. *
  62. * Returns Non-zero if the packet can be dropped, zero otherwise.
  63. */
  64. static inline int cvm_oct_check_rcv_error(cvmx_wqe_t *work)
  65. {
  66. int port;
  67. if (octeon_has_feature(OCTEON_FEATURE_PKND))
  68. port = work->word0.pip.cn68xx.pknd;
  69. else
  70. port = work->word1.cn38xx.ipprt;
  71. if ((work->word2.snoip.err_code == 10) && (work->word1.len <= 64)) {
  72. /*
  73. * Ignore length errors on min size packets. Some
  74. * equipment incorrectly pads packets to 64+4FCS
  75. * instead of 60+4FCS. Note these packets still get
  76. * counted as frame errors.
  77. */
  78. } else if (work->word2.snoip.err_code == 5 ||
  79. work->word2.snoip.err_code == 7) {
  80. /*
  81. * We received a packet with either an alignment error
  82. * or a FCS error. This may be signalling that we are
  83. * running 10Mbps with GMXX_RXX_FRM_CTL[PRE_CHK]
  84. * off. If this is the case we need to parse the
  85. * packet to determine if we can remove a non spec
  86. * preamble and generate a correct packet.
  87. */
  88. int interface = cvmx_helper_get_interface_num(port);
  89. int index = cvmx_helper_get_interface_index_num(port);
  90. union cvmx_gmxx_rxx_frm_ctl gmxx_rxx_frm_ctl;
  91. gmxx_rxx_frm_ctl.u64 =
  92. cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL(index, interface));
  93. if (gmxx_rxx_frm_ctl.s.pre_chk == 0) {
  94. u8 *ptr =
  95. cvmx_phys_to_ptr(work->packet_ptr.s.addr);
  96. int i = 0;
  97. while (i < work->word1.len - 1) {
  98. if (*ptr != 0x55)
  99. break;
  100. ptr++;
  101. i++;
  102. }
  103. if (*ptr == 0xd5) {
  104. /* Port received 0xd5 preamble */
  105. work->packet_ptr.s.addr += i + 1;
  106. work->word1.len -= i + 5;
  107. } else if ((*ptr & 0xf) == 0xd) {
  108. /* Port received 0xd preamble */
  109. work->packet_ptr.s.addr += i;
  110. work->word1.len -= i + 4;
  111. for (i = 0; i < work->word1.len; i++) {
  112. *ptr =
  113. ((*ptr & 0xf0) >> 4) |
  114. ((*(ptr + 1) & 0xf) << 4);
  115. ptr++;
  116. }
  117. } else {
  118. printk_ratelimited("Port %d unknown preamble, packet dropped\n",
  119. port);
  120. cvm_oct_free_work(work);
  121. return 1;
  122. }
  123. }
  124. } else {
  125. printk_ratelimited("Port %d receive error code %d, packet dropped\n",
  126. port, work->word2.snoip.err_code);
  127. cvm_oct_free_work(work);
  128. return 1;
  129. }
  130. return 0;
  131. }
  132. static void copy_segments_to_skb(cvmx_wqe_t *work, struct sk_buff *skb)
  133. {
  134. int segments = work->word2.s.bufs;
  135. union cvmx_buf_ptr segment_ptr = work->packet_ptr;
  136. int len = work->word1.len;
  137. int segment_size;
  138. while (segments--) {
  139. union cvmx_buf_ptr next_ptr;
  140. next_ptr = *(union cvmx_buf_ptr *)
  141. cvmx_phys_to_ptr(segment_ptr.s.addr - 8);
  142. /*
  143. * Octeon Errata PKI-100: The segment size is wrong.
  144. *
  145. * Until it is fixed, calculate the segment size based on
  146. * the packet pool buffer size.
  147. * When it is fixed, the following line should be replaced
  148. * with this one:
  149. * int segment_size = segment_ptr.s.size;
  150. */
  151. segment_size =
  152. CVMX_FPA_PACKET_POOL_SIZE -
  153. (segment_ptr.s.addr -
  154. (((segment_ptr.s.addr >> 7) -
  155. segment_ptr.s.back) << 7));
  156. /* Don't copy more than what is left in the packet */
  157. if (segment_size > len)
  158. segment_size = len;
  159. /* Copy the data into the packet */
  160. skb_put_data(skb, cvmx_phys_to_ptr(segment_ptr.s.addr),
  161. segment_size);
  162. len -= segment_size;
  163. segment_ptr = next_ptr;
  164. }
  165. }
  166. static int cvm_oct_poll(struct oct_rx_group *rx_group, int budget)
  167. {
  168. const int coreid = cvmx_get_core_num();
  169. u64 old_group_mask;
  170. u64 old_scratch;
  171. int rx_count = 0;
  172. int did_work_request = 0;
  173. int packet_not_copied;
  174. /* Prefetch cvm_oct_device since we know we need it soon */
  175. prefetch(cvm_oct_device);
  176. if (USE_ASYNC_IOBDMA) {
  177. /* Save scratch in case userspace is using it */
  178. CVMX_SYNCIOBDMA;
  179. old_scratch = cvmx_scratch_read64(CVMX_SCR_SCRATCH);
  180. }
  181. /* Only allow work for our group (and preserve priorities) */
  182. if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
  183. old_group_mask = cvmx_read_csr(CVMX_SSO_PPX_GRP_MSK(coreid));
  184. cvmx_write_csr(CVMX_SSO_PPX_GRP_MSK(coreid),
  185. BIT(rx_group->group));
  186. cvmx_read_csr(CVMX_SSO_PPX_GRP_MSK(coreid)); /* Flush */
  187. } else {
  188. old_group_mask = cvmx_read_csr(CVMX_POW_PP_GRP_MSKX(coreid));
  189. cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(coreid),
  190. (old_group_mask & ~0xFFFFull) |
  191. BIT(rx_group->group));
  192. }
  193. if (USE_ASYNC_IOBDMA) {
  194. cvmx_pow_work_request_async(CVMX_SCR_SCRATCH, CVMX_POW_NO_WAIT);
  195. did_work_request = 1;
  196. }
  197. while (rx_count < budget) {
  198. struct sk_buff *skb = NULL;
  199. struct sk_buff **pskb = NULL;
  200. int skb_in_hw;
  201. cvmx_wqe_t *work;
  202. int port;
  203. if (USE_ASYNC_IOBDMA && did_work_request)
  204. work = cvmx_pow_work_response_async(CVMX_SCR_SCRATCH);
  205. else
  206. work = cvmx_pow_work_request_sync(CVMX_POW_NO_WAIT);
  207. prefetch(work);
  208. did_work_request = 0;
  209. if (!work) {
  210. if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
  211. cvmx_write_csr(CVMX_SSO_WQ_IQ_DIS,
  212. BIT(rx_group->group));
  213. cvmx_write_csr(CVMX_SSO_WQ_INT,
  214. BIT(rx_group->group));
  215. } else {
  216. union cvmx_pow_wq_int wq_int;
  217. wq_int.u64 = 0;
  218. wq_int.s.iq_dis = BIT(rx_group->group);
  219. wq_int.s.wq_int = BIT(rx_group->group);
  220. cvmx_write_csr(CVMX_POW_WQ_INT, wq_int.u64);
  221. }
  222. break;
  223. }
  224. pskb = (struct sk_buff **)
  225. (cvm_oct_get_buffer_ptr(work->packet_ptr) -
  226. sizeof(void *));
  227. prefetch(pskb);
  228. if (USE_ASYNC_IOBDMA && rx_count < (budget - 1)) {
  229. cvmx_pow_work_request_async_nocheck(CVMX_SCR_SCRATCH,
  230. CVMX_POW_NO_WAIT);
  231. did_work_request = 1;
  232. }
  233. rx_count++;
  234. skb_in_hw = work->word2.s.bufs == 1;
  235. if (likely(skb_in_hw)) {
  236. skb = *pskb;
  237. prefetch(&skb->head);
  238. prefetch(&skb->len);
  239. }
  240. if (octeon_has_feature(OCTEON_FEATURE_PKND))
  241. port = work->word0.pip.cn68xx.pknd;
  242. else
  243. port = work->word1.cn38xx.ipprt;
  244. prefetch(cvm_oct_device[port]);
  245. /* Immediately throw away all packets with receive errors */
  246. if (unlikely(work->word2.snoip.rcv_error)) {
  247. if (cvm_oct_check_rcv_error(work))
  248. continue;
  249. }
  250. /*
  251. * We can only use the zero copy path if skbuffs are
  252. * in the FPA pool and the packet fits in a single
  253. * buffer.
  254. */
  255. if (likely(skb_in_hw)) {
  256. skb->data = skb->head + work->packet_ptr.s.addr -
  257. cvmx_ptr_to_phys(skb->head);
  258. prefetch(skb->data);
  259. skb->len = work->word1.len;
  260. skb_set_tail_pointer(skb, skb->len);
  261. packet_not_copied = 1;
  262. } else {
  263. /*
  264. * We have to copy the packet. First allocate
  265. * an skbuff for it.
  266. */
  267. skb = dev_alloc_skb(work->word1.len);
  268. if (!skb) {
  269. cvm_oct_free_work(work);
  270. continue;
  271. }
  272. /*
  273. * Check if we've received a packet that was
  274. * entirely stored in the work entry.
  275. */
  276. if (unlikely(work->word2.s.bufs == 0)) {
  277. u8 *ptr = work->packet_data;
  278. if (likely(!work->word2.s.not_IP)) {
  279. /*
  280. * The beginning of the packet
  281. * moves for IP packets.
  282. */
  283. if (work->word2.s.is_v6)
  284. ptr += 2;
  285. else
  286. ptr += 6;
  287. }
  288. skb_put_data(skb, ptr, work->word1.len);
  289. /* No packet buffers to free */
  290. } else {
  291. copy_segments_to_skb(work, skb);
  292. }
  293. packet_not_copied = 0;
  294. }
  295. if (likely((port < TOTAL_NUMBER_OF_PORTS) &&
  296. cvm_oct_device[port])) {
  297. struct net_device *dev = cvm_oct_device[port];
  298. /*
  299. * Only accept packets for devices that are
  300. * currently up.
  301. */
  302. if (likely(dev->flags & IFF_UP)) {
  303. skb->protocol = eth_type_trans(skb, dev);
  304. skb->dev = dev;
  305. if (unlikely(work->word2.s.not_IP ||
  306. work->word2.s.IP_exc ||
  307. work->word2.s.L4_error ||
  308. !work->word2.s.tcp_or_udp))
  309. skb->ip_summed = CHECKSUM_NONE;
  310. else
  311. skb->ip_summed = CHECKSUM_UNNECESSARY;
  312. /* Increment RX stats for virtual ports */
  313. if (port >= CVMX_PIP_NUM_INPUT_PORTS) {
  314. dev->stats.rx_packets++;
  315. dev->stats.rx_bytes += skb->len;
  316. }
  317. netif_receive_skb(skb);
  318. } else {
  319. /*
  320. * Drop any packet received for a device that
  321. * isn't up.
  322. */
  323. dev->stats.rx_dropped++;
  324. dev_kfree_skb_irq(skb);
  325. }
  326. } else {
  327. /*
  328. * Drop any packet received for a device that
  329. * doesn't exist.
  330. */
  331. printk_ratelimited("Port %d not controlled by Linux, packet dropped\n",
  332. port);
  333. dev_kfree_skb_irq(skb);
  334. }
  335. /*
  336. * Check to see if the skbuff and work share the same
  337. * packet buffer.
  338. */
  339. if (likely(packet_not_copied)) {
  340. /*
  341. * This buffer needs to be replaced, increment
  342. * the number of buffers we need to free by
  343. * one.
  344. */
  345. cvmx_fau_atomic_add32(FAU_NUM_PACKET_BUFFERS_TO_FREE,
  346. 1);
  347. cvmx_fpa_free(work, CVMX_FPA_WQE_POOL, 1);
  348. } else {
  349. cvm_oct_free_work(work);
  350. }
  351. }
  352. /* Restore the original POW group mask */
  353. if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
  354. cvmx_write_csr(CVMX_SSO_PPX_GRP_MSK(coreid), old_group_mask);
  355. cvmx_read_csr(CVMX_SSO_PPX_GRP_MSK(coreid)); /* Flush */
  356. } else {
  357. cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(coreid), old_group_mask);
  358. }
  359. if (USE_ASYNC_IOBDMA) {
  360. /* Restore the scratch area */
  361. cvmx_scratch_write64(CVMX_SCR_SCRATCH, old_scratch);
  362. }
  363. cvm_oct_rx_refill_pool(0);
  364. return rx_count;
  365. }
  366. /**
  367. * cvm_oct_napi_poll - the NAPI poll function.
  368. * @napi: The NAPI instance.
  369. * @budget: Maximum number of packets to receive.
  370. *
  371. * Returns the number of packets processed.
  372. */
  373. static int cvm_oct_napi_poll(struct napi_struct *napi, int budget)
  374. {
  375. struct oct_rx_group *rx_group = container_of(napi, struct oct_rx_group,
  376. napi);
  377. int rx_count;
  378. rx_count = cvm_oct_poll(rx_group, budget);
  379. if (rx_count < budget) {
  380. /* No more work */
  381. napi_complete_done(napi, rx_count);
  382. enable_irq(rx_group->irq);
  383. }
  384. return rx_count;
  385. }
  386. #ifdef CONFIG_NET_POLL_CONTROLLER
  387. /**
  388. * cvm_oct_poll_controller - poll for receive packets
  389. * device.
  390. *
  391. * @dev: Device to poll. Unused
  392. */
  393. void cvm_oct_poll_controller(struct net_device *dev)
  394. {
  395. int i;
  396. if (!atomic_read(&oct_rx_ready))
  397. return;
  398. for (i = 0; i < ARRAY_SIZE(oct_rx_group); i++) {
  399. if (!(pow_receive_groups & BIT(i)))
  400. continue;
  401. cvm_oct_poll(&oct_rx_group[i], 16);
  402. }
  403. }
  404. #endif
  405. void cvm_oct_rx_initialize(void)
  406. {
  407. int i;
  408. struct net_device *dev_for_napi = NULL;
  409. for (i = 0; i < TOTAL_NUMBER_OF_PORTS; i++) {
  410. if (cvm_oct_device[i]) {
  411. dev_for_napi = cvm_oct_device[i];
  412. break;
  413. }
  414. }
  415. if (!dev_for_napi)
  416. panic("No net_devices were allocated.");
  417. for (i = 0; i < ARRAY_SIZE(oct_rx_group); i++) {
  418. int ret;
  419. if (!(pow_receive_groups & BIT(i)))
  420. continue;
  421. netif_napi_add(dev_for_napi, &oct_rx_group[i].napi,
  422. cvm_oct_napi_poll, rx_napi_weight);
  423. napi_enable(&oct_rx_group[i].napi);
  424. oct_rx_group[i].irq = OCTEON_IRQ_WORKQ0 + i;
  425. oct_rx_group[i].group = i;
  426. /* Register an IRQ handler to receive POW interrupts */
  427. ret = request_irq(oct_rx_group[i].irq, cvm_oct_do_interrupt, 0,
  428. "Ethernet", &oct_rx_group[i].napi);
  429. if (ret)
  430. panic("Could not acquire Ethernet IRQ %d\n",
  431. oct_rx_group[i].irq);
  432. disable_irq_nosync(oct_rx_group[i].irq);
  433. /* Enable POW interrupt when our port has at least one packet */
  434. if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
  435. union cvmx_sso_wq_int_thrx int_thr;
  436. union cvmx_pow_wq_int_pc int_pc;
  437. int_thr.u64 = 0;
  438. int_thr.s.tc_en = 1;
  439. int_thr.s.tc_thr = 1;
  440. cvmx_write_csr(CVMX_SSO_WQ_INT_THRX(i), int_thr.u64);
  441. int_pc.u64 = 0;
  442. int_pc.s.pc_thr = 5;
  443. cvmx_write_csr(CVMX_SSO_WQ_INT_PC, int_pc.u64);
  444. } else {
  445. union cvmx_pow_wq_int_thrx int_thr;
  446. union cvmx_pow_wq_int_pc int_pc;
  447. int_thr.u64 = 0;
  448. int_thr.s.tc_en = 1;
  449. int_thr.s.tc_thr = 1;
  450. cvmx_write_csr(CVMX_POW_WQ_INT_THRX(i), int_thr.u64);
  451. int_pc.u64 = 0;
  452. int_pc.s.pc_thr = 5;
  453. cvmx_write_csr(CVMX_POW_WQ_INT_PC, int_pc.u64);
  454. }
  455. /* Schedule NAPI now. This will indirectly enable the
  456. * interrupt.
  457. */
  458. napi_schedule(&oct_rx_group[i].napi);
  459. }
  460. atomic_inc(&oct_rx_ready);
  461. }
  462. void cvm_oct_rx_shutdown(void)
  463. {
  464. int i;
  465. for (i = 0; i < ARRAY_SIZE(oct_rx_group); i++) {
  466. if (!(pow_receive_groups & BIT(i)))
  467. continue;
  468. /* Disable POW interrupt */
  469. if (OCTEON_IS_MODEL(OCTEON_CN68XX))
  470. cvmx_write_csr(CVMX_SSO_WQ_INT_THRX(i), 0);
  471. else
  472. cvmx_write_csr(CVMX_POW_WQ_INT_THRX(i), 0);
  473. /* Free the interrupt handler */
  474. free_irq(oct_rx_group[i].irq, cvm_oct_device);
  475. netif_napi_del(&oct_rx_group[i].napi);
  476. }
  477. }