spi-mt7621.c 11 KB

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  1. /*
  2. * spi-mt7621.c -- MediaTek MT7621 SPI controller driver
  3. *
  4. * Copyright (C) 2011 Sergiy <piratfm@gmail.com>
  5. * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
  6. * Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
  7. *
  8. * Some parts are based on spi-orion.c:
  9. * Author: Shadi Ammouri <shadi@marvell.com>
  10. * Copyright (C) 2007-2008 Marvell Ltd.
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of the GNU General Public License version 2 as
  14. * published by the Free Software Foundation.
  15. */
  16. #include <linux/init.h>
  17. #include <linux/module.h>
  18. #include <linux/clk.h>
  19. #include <linux/err.h>
  20. #include <linux/delay.h>
  21. #include <linux/io.h>
  22. #include <linux/reset.h>
  23. #include <linux/spi/spi.h>
  24. #include <linux/of_device.h>
  25. #include <linux/platform_device.h>
  26. #include <linux/swab.h>
  27. #include <ralink_regs.h>
  28. #define SPI_BPW_MASK(bits) BIT((bits) - 1)
  29. #define DRIVER_NAME "spi-mt7621"
  30. /* in usec */
  31. #define RALINK_SPI_WAIT_MAX_LOOP 2000
  32. /* SPISTAT register bit field */
  33. #define SPISTAT_BUSY BIT(0)
  34. #define MT7621_SPI_TRANS 0x00
  35. #define SPITRANS_BUSY BIT(16)
  36. #define MT7621_SPI_OPCODE 0x04
  37. #define MT7621_SPI_DATA0 0x08
  38. #define MT7621_SPI_DATA4 0x18
  39. #define SPI_CTL_TX_RX_CNT_MASK 0xff
  40. #define SPI_CTL_START BIT(8)
  41. #define MT7621_SPI_POLAR 0x38
  42. #define MT7621_SPI_MASTER 0x28
  43. #define MT7621_SPI_MOREBUF 0x2c
  44. #define MT7621_SPI_SPACE 0x3c
  45. #define MT7621_CPHA BIT(5)
  46. #define MT7621_CPOL BIT(4)
  47. #define MT7621_LSB_FIRST BIT(3)
  48. #define RT2880_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | \
  49. SPI_LSB_FIRST | SPI_CS_HIGH)
  50. struct mt7621_spi;
  51. struct mt7621_spi {
  52. struct spi_master *master;
  53. void __iomem *base;
  54. unsigned int sys_freq;
  55. unsigned int speed;
  56. struct clk *clk;
  57. int pending_write;
  58. struct mt7621_spi_ops *ops;
  59. };
  60. static inline struct mt7621_spi *spidev_to_mt7621_spi(struct spi_device *spi)
  61. {
  62. return spi_master_get_devdata(spi->master);
  63. }
  64. static inline u32 mt7621_spi_read(struct mt7621_spi *rs, u32 reg)
  65. {
  66. return ioread32(rs->base + reg);
  67. }
  68. static inline void mt7621_spi_write(struct mt7621_spi *rs, u32 reg, u32 val)
  69. {
  70. iowrite32(val, rs->base + reg);
  71. }
  72. static void mt7621_spi_reset(struct mt7621_spi *rs, int duplex)
  73. {
  74. u32 master = mt7621_spi_read(rs, MT7621_SPI_MASTER);
  75. master |= 7 << 29;
  76. master |= 1 << 2;
  77. if (duplex)
  78. master |= 1 << 10;
  79. else
  80. master &= ~(1 << 10);
  81. mt7621_spi_write(rs, MT7621_SPI_MASTER, master);
  82. rs->pending_write = 0;
  83. }
  84. static void mt7621_spi_set_cs(struct spi_device *spi, int enable)
  85. {
  86. struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
  87. int cs = spi->chip_select;
  88. u32 polar = 0;
  89. mt7621_spi_reset(rs, cs);
  90. if (enable)
  91. polar = BIT(cs);
  92. mt7621_spi_write(rs, MT7621_SPI_POLAR, polar);
  93. }
  94. static int mt7621_spi_prepare(struct spi_device *spi, unsigned int speed)
  95. {
  96. struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
  97. u32 rate;
  98. u32 reg;
  99. dev_dbg(&spi->dev, "speed:%u\n", speed);
  100. rate = DIV_ROUND_UP(rs->sys_freq, speed);
  101. dev_dbg(&spi->dev, "rate-1:%u\n", rate);
  102. if (rate > 4097)
  103. return -EINVAL;
  104. if (rate < 2)
  105. rate = 2;
  106. reg = mt7621_spi_read(rs, MT7621_SPI_MASTER);
  107. reg &= ~(0xfff << 16);
  108. reg |= (rate - 2) << 16;
  109. rs->speed = speed;
  110. reg &= ~MT7621_LSB_FIRST;
  111. if (spi->mode & SPI_LSB_FIRST)
  112. reg |= MT7621_LSB_FIRST;
  113. reg &= ~(MT7621_CPHA | MT7621_CPOL);
  114. switch (spi->mode & (SPI_CPOL | SPI_CPHA)) {
  115. case SPI_MODE_0:
  116. break;
  117. case SPI_MODE_1:
  118. reg |= MT7621_CPHA;
  119. break;
  120. case SPI_MODE_2:
  121. reg |= MT7621_CPOL;
  122. break;
  123. case SPI_MODE_3:
  124. reg |= MT7621_CPOL | MT7621_CPHA;
  125. break;
  126. }
  127. mt7621_spi_write(rs, MT7621_SPI_MASTER, reg);
  128. return 0;
  129. }
  130. static inline int mt7621_spi_wait_till_ready(struct mt7621_spi *rs)
  131. {
  132. int i;
  133. for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
  134. u32 status;
  135. status = mt7621_spi_read(rs, MT7621_SPI_TRANS);
  136. if ((status & SPITRANS_BUSY) == 0)
  137. return 0;
  138. cpu_relax();
  139. udelay(1);
  140. }
  141. return -ETIMEDOUT;
  142. }
  143. static void mt7621_spi_read_half_duplex(struct mt7621_spi *rs,
  144. int rx_len, u8 *buf)
  145. {
  146. /* Combine with any pending write, and perform one or
  147. * more half-duplex transactions reading 'len' bytes.
  148. * Data to be written is already in MT7621_SPI_DATA*
  149. */
  150. int tx_len = rs->pending_write;
  151. rs->pending_write = 0;
  152. while (rx_len || tx_len) {
  153. int i;
  154. u32 val = (min(tx_len, 4) * 8) << 24;
  155. int rx = min(rx_len, 32);
  156. if (tx_len > 4)
  157. val |= (tx_len - 4) * 8;
  158. val |= (rx * 8) << 12;
  159. mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
  160. tx_len = 0;
  161. val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
  162. val |= SPI_CTL_START;
  163. mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
  164. mt7621_spi_wait_till_ready(rs);
  165. for (i = 0; i < rx; i++) {
  166. if ((i % 4) == 0)
  167. val = mt7621_spi_read(rs, MT7621_SPI_DATA0 + i);
  168. *buf++ = val & 0xff;
  169. val >>= 8;
  170. }
  171. rx_len -= i;
  172. }
  173. }
  174. static inline void mt7621_spi_flush(struct mt7621_spi *rs)
  175. {
  176. mt7621_spi_read_half_duplex(rs, 0, NULL);
  177. }
  178. static void mt7621_spi_write_half_duplex(struct mt7621_spi *rs,
  179. int tx_len, const u8 *buf)
  180. {
  181. int val = 0;
  182. int len = rs->pending_write;
  183. if (len & 3) {
  184. val = mt7621_spi_read(rs, MT7621_SPI_OPCODE + (len & ~3));
  185. if (len < 4) {
  186. val <<= (4 - len) * 8;
  187. val = swab32(val);
  188. }
  189. }
  190. while (tx_len > 0) {
  191. if (len >= 36) {
  192. rs->pending_write = len;
  193. mt7621_spi_flush(rs);
  194. len = 0;
  195. }
  196. val |= *buf++ << (8 * (len & 3));
  197. len++;
  198. if ((len & 3) == 0) {
  199. if (len == 4)
  200. /* The byte-order of the opcode is weird! */
  201. val = swab32(val);
  202. mt7621_spi_write(rs, MT7621_SPI_OPCODE + len - 4, val);
  203. val = 0;
  204. }
  205. tx_len -= 1;
  206. }
  207. if (len & 3) {
  208. if (len < 4) {
  209. val = swab32(val);
  210. val >>= (4 - len) * 8;
  211. }
  212. mt7621_spi_write(rs, MT7621_SPI_OPCODE + (len & ~3), val);
  213. }
  214. rs->pending_write = len;
  215. }
  216. static int mt7621_spi_transfer_half_duplex(struct spi_master *master,
  217. struct spi_message *m)
  218. {
  219. struct mt7621_spi *rs = spi_master_get_devdata(master);
  220. struct spi_device *spi = m->spi;
  221. unsigned int speed = spi->max_speed_hz;
  222. struct spi_transfer *t = NULL;
  223. int status = 0;
  224. mt7621_spi_wait_till_ready(rs);
  225. list_for_each_entry(t, &m->transfers, transfer_list)
  226. if (t->speed_hz < speed)
  227. speed = t->speed_hz;
  228. if (mt7621_spi_prepare(spi, speed)) {
  229. status = -EIO;
  230. goto msg_done;
  231. }
  232. mt7621_spi_set_cs(spi, 1);
  233. m->actual_length = 0;
  234. list_for_each_entry(t, &m->transfers, transfer_list) {
  235. if (t->rx_buf)
  236. mt7621_spi_read_half_duplex(rs, t->len, t->rx_buf);
  237. else if (t->tx_buf)
  238. mt7621_spi_write_half_duplex(rs, t->len, t->tx_buf);
  239. m->actual_length += t->len;
  240. }
  241. mt7621_spi_flush(rs);
  242. mt7621_spi_set_cs(spi, 0);
  243. msg_done:
  244. m->status = status;
  245. spi_finalize_current_message(master);
  246. return 0;
  247. }
  248. static int mt7621_spi_transfer_full_duplex(struct spi_master *master,
  249. struct spi_message *m)
  250. {
  251. struct mt7621_spi *rs = spi_master_get_devdata(master);
  252. struct spi_device *spi = m->spi;
  253. unsigned int speed = spi->max_speed_hz;
  254. struct spi_transfer *t = NULL;
  255. int status = 0;
  256. int i, len = 0;
  257. int rx_len = 0;
  258. u32 data[9] = { 0 };
  259. u32 val = 0;
  260. mt7621_spi_wait_till_ready(rs);
  261. list_for_each_entry(t, &m->transfers, transfer_list) {
  262. const u8 *buf = t->tx_buf;
  263. if (t->rx_buf)
  264. rx_len += t->len;
  265. if (!buf)
  266. continue;
  267. if (WARN_ON(len + t->len > 16)) {
  268. status = -EIO;
  269. goto msg_done;
  270. }
  271. for (i = 0; i < t->len; i++, len++)
  272. data[len / 4] |= buf[i] << (8 * (len & 3));
  273. if (speed > t->speed_hz)
  274. speed = t->speed_hz;
  275. }
  276. if (WARN_ON(rx_len > 16)) {
  277. status = -EIO;
  278. goto msg_done;
  279. }
  280. if (mt7621_spi_prepare(spi, speed)) {
  281. status = -EIO;
  282. goto msg_done;
  283. }
  284. for (i = 0; i < len; i += 4)
  285. mt7621_spi_write(rs, MT7621_SPI_DATA0 + i, data[i / 4]);
  286. val |= len * 8;
  287. val |= (rx_len * 8) << 12;
  288. mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
  289. mt7621_spi_set_cs(spi, 1);
  290. val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
  291. val |= SPI_CTL_START;
  292. mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
  293. mt7621_spi_wait_till_ready(rs);
  294. mt7621_spi_set_cs(spi, 0);
  295. for (i = 0; i < rx_len; i += 4)
  296. data[i / 4] = mt7621_spi_read(rs, MT7621_SPI_DATA4 + i);
  297. m->actual_length = rx_len;
  298. len = 0;
  299. list_for_each_entry(t, &m->transfers, transfer_list) {
  300. u8 *buf = t->rx_buf;
  301. if (!buf)
  302. continue;
  303. for (i = 0; i < t->len; i++, len++)
  304. buf[i] = data[len / 4] >> (8 * (len & 3));
  305. }
  306. msg_done:
  307. m->status = status;
  308. spi_finalize_current_message(master);
  309. return 0;
  310. }
  311. static int mt7621_spi_transfer_one_message(struct spi_master *master,
  312. struct spi_message *m)
  313. {
  314. struct spi_device *spi = m->spi;
  315. int cs = spi->chip_select;
  316. if (cs)
  317. return mt7621_spi_transfer_full_duplex(master, m);
  318. return mt7621_spi_transfer_half_duplex(master, m);
  319. }
  320. static int mt7621_spi_setup(struct spi_device *spi)
  321. {
  322. struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
  323. if ((spi->max_speed_hz == 0) ||
  324. (spi->max_speed_hz > (rs->sys_freq / 2)))
  325. spi->max_speed_hz = (rs->sys_freq / 2);
  326. if (spi->max_speed_hz < (rs->sys_freq / 4097)) {
  327. dev_err(&spi->dev, "setup: requested speed is too low %d Hz\n",
  328. spi->max_speed_hz);
  329. return -EINVAL;
  330. }
  331. return 0;
  332. }
  333. static const struct of_device_id mt7621_spi_match[] = {
  334. { .compatible = "ralink,mt7621-spi" },
  335. {},
  336. };
  337. MODULE_DEVICE_TABLE(of, mt7621_spi_match);
  338. static int mt7621_spi_probe(struct platform_device *pdev)
  339. {
  340. const struct of_device_id *match;
  341. struct spi_master *master;
  342. struct mt7621_spi *rs;
  343. void __iomem *base;
  344. struct resource *r;
  345. int status = 0;
  346. struct clk *clk;
  347. struct mt7621_spi_ops *ops;
  348. int ret;
  349. match = of_match_device(mt7621_spi_match, &pdev->dev);
  350. if (!match)
  351. return -EINVAL;
  352. ops = (struct mt7621_spi_ops *)match->data;
  353. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  354. base = devm_ioremap_resource(&pdev->dev, r);
  355. if (IS_ERR(base))
  356. return PTR_ERR(base);
  357. clk = devm_clk_get(&pdev->dev, NULL);
  358. if (IS_ERR(clk)) {
  359. dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n",
  360. status);
  361. return PTR_ERR(clk);
  362. }
  363. status = clk_prepare_enable(clk);
  364. if (status)
  365. return status;
  366. master = spi_alloc_master(&pdev->dev, sizeof(*rs));
  367. if (master == NULL) {
  368. dev_info(&pdev->dev, "master allocation failed\n");
  369. return -ENOMEM;
  370. }
  371. master->mode_bits = RT2880_SPI_MODE_BITS;
  372. master->setup = mt7621_spi_setup;
  373. master->transfer_one_message = mt7621_spi_transfer_one_message;
  374. master->bits_per_word_mask = SPI_BPW_MASK(8);
  375. master->dev.of_node = pdev->dev.of_node;
  376. master->num_chipselect = 2;
  377. dev_set_drvdata(&pdev->dev, master);
  378. rs = spi_master_get_devdata(master);
  379. rs->base = base;
  380. rs->clk = clk;
  381. rs->master = master;
  382. rs->sys_freq = clk_get_rate(rs->clk);
  383. rs->ops = ops;
  384. rs->pending_write = 0;
  385. dev_info(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
  386. ret = device_reset(&pdev->dev);
  387. if (ret) {
  388. dev_err(&pdev->dev, "SPI reset failed!\n");
  389. return ret;
  390. }
  391. mt7621_spi_reset(rs, 0);
  392. return spi_register_master(master);
  393. }
  394. static int mt7621_spi_remove(struct platform_device *pdev)
  395. {
  396. struct spi_master *master;
  397. struct mt7621_spi *rs;
  398. master = dev_get_drvdata(&pdev->dev);
  399. rs = spi_master_get_devdata(master);
  400. clk_disable(rs->clk);
  401. spi_unregister_master(master);
  402. return 0;
  403. }
  404. MODULE_ALIAS("platform:" DRIVER_NAME);
  405. static struct platform_driver mt7621_spi_driver = {
  406. .driver = {
  407. .name = DRIVER_NAME,
  408. .of_match_table = mt7621_spi_match,
  409. },
  410. .probe = mt7621_spi_probe,
  411. .remove = mt7621_spi_remove,
  412. };
  413. module_platform_driver(mt7621_spi_driver);
  414. MODULE_DESCRIPTION("MT7621 SPI driver");
  415. MODULE_AUTHOR("Felix Fietkau <nbd@nbd.name>");
  416. MODULE_LICENSE("GPL");