scan.c 10 KB

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  1. /*
  2. * Sonics Silicon Backplane
  3. * Bus scanning
  4. *
  5. * Copyright (C) 2005-2007 Michael Buesch <m@bues.ch>
  6. * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
  7. * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
  8. * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
  9. * Copyright (C) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
  10. * Copyright (C) 2006 Broadcom Corporation.
  11. *
  12. * Licensed under the GNU/GPL. See COPYING for details.
  13. */
  14. #include "ssb_private.h"
  15. #include <linux/ssb/ssb.h>
  16. #include <linux/ssb/ssb_regs.h>
  17. #include <linux/pci.h>
  18. #include <linux/io.h>
  19. #include <pcmcia/cistpl.h>
  20. #include <pcmcia/ds.h>
  21. const char *ssb_core_name(u16 coreid)
  22. {
  23. switch (coreid) {
  24. case SSB_DEV_CHIPCOMMON:
  25. return "ChipCommon";
  26. case SSB_DEV_ILINE20:
  27. return "ILine 20";
  28. case SSB_DEV_SDRAM:
  29. return "SDRAM";
  30. case SSB_DEV_PCI:
  31. return "PCI";
  32. case SSB_DEV_MIPS:
  33. return "MIPS";
  34. case SSB_DEV_ETHERNET:
  35. return "Fast Ethernet";
  36. case SSB_DEV_V90:
  37. return "V90";
  38. case SSB_DEV_USB11_HOSTDEV:
  39. return "USB 1.1 Hostdev";
  40. case SSB_DEV_ADSL:
  41. return "ADSL";
  42. case SSB_DEV_ILINE100:
  43. return "ILine 100";
  44. case SSB_DEV_IPSEC:
  45. return "IPSEC";
  46. case SSB_DEV_PCMCIA:
  47. return "PCMCIA";
  48. case SSB_DEV_INTERNAL_MEM:
  49. return "Internal Memory";
  50. case SSB_DEV_MEMC_SDRAM:
  51. return "MEMC SDRAM";
  52. case SSB_DEV_EXTIF:
  53. return "EXTIF";
  54. case SSB_DEV_80211:
  55. return "IEEE 802.11";
  56. case SSB_DEV_MIPS_3302:
  57. return "MIPS 3302";
  58. case SSB_DEV_USB11_HOST:
  59. return "USB 1.1 Host";
  60. case SSB_DEV_USB11_DEV:
  61. return "USB 1.1 Device";
  62. case SSB_DEV_USB20_HOST:
  63. return "USB 2.0 Host";
  64. case SSB_DEV_USB20_DEV:
  65. return "USB 2.0 Device";
  66. case SSB_DEV_SDIO_HOST:
  67. return "SDIO Host";
  68. case SSB_DEV_ROBOSWITCH:
  69. return "Roboswitch";
  70. case SSB_DEV_PARA_ATA:
  71. return "PATA";
  72. case SSB_DEV_SATA_XORDMA:
  73. return "SATA XOR-DMA";
  74. case SSB_DEV_ETHERNET_GBIT:
  75. return "GBit Ethernet";
  76. case SSB_DEV_PCIE:
  77. return "PCI-E";
  78. case SSB_DEV_MIMO_PHY:
  79. return "MIMO PHY";
  80. case SSB_DEV_SRAM_CTRLR:
  81. return "SRAM Controller";
  82. case SSB_DEV_MINI_MACPHY:
  83. return "Mini MACPHY";
  84. case SSB_DEV_ARM_1176:
  85. return "ARM 1176";
  86. case SSB_DEV_ARM_7TDMI:
  87. return "ARM 7TDMI";
  88. case SSB_DEV_ARM_CM3:
  89. return "ARM Cortex M3";
  90. }
  91. return "UNKNOWN";
  92. }
  93. static u16 pcidev_to_chipid(struct pci_dev *pci_dev)
  94. {
  95. u16 chipid_fallback = 0;
  96. switch (pci_dev->device) {
  97. case 0x4301:
  98. chipid_fallback = 0x4301;
  99. break;
  100. case 0x4305 ... 0x4307:
  101. chipid_fallback = 0x4307;
  102. break;
  103. case 0x4403:
  104. chipid_fallback = 0x4402;
  105. break;
  106. case 0x4610 ... 0x4615:
  107. chipid_fallback = 0x4610;
  108. break;
  109. case 0x4710 ... 0x4715:
  110. chipid_fallback = 0x4710;
  111. break;
  112. case 0x4320 ... 0x4325:
  113. chipid_fallback = 0x4309;
  114. break;
  115. case PCI_DEVICE_ID_BCM4401:
  116. case PCI_DEVICE_ID_BCM4401B0:
  117. case PCI_DEVICE_ID_BCM4401B1:
  118. chipid_fallback = 0x4401;
  119. break;
  120. default:
  121. dev_err(&pci_dev->dev, "PCI-ID not in fallback list\n");
  122. }
  123. return chipid_fallback;
  124. }
  125. static u8 chipid_to_nrcores(u16 chipid)
  126. {
  127. switch (chipid) {
  128. case 0x5365:
  129. return 7;
  130. case 0x4306:
  131. return 6;
  132. case 0x4310:
  133. return 8;
  134. case 0x4307:
  135. case 0x4301:
  136. return 5;
  137. case 0x4401:
  138. case 0x4402:
  139. return 3;
  140. case 0x4710:
  141. case 0x4610:
  142. case 0x4704:
  143. return 9;
  144. default:
  145. pr_err("CHIPID not in nrcores fallback list\n");
  146. }
  147. return 1;
  148. }
  149. static u32 scan_read32(struct ssb_bus *bus, u8 current_coreidx,
  150. u16 offset)
  151. {
  152. u32 lo, hi;
  153. switch (bus->bustype) {
  154. case SSB_BUSTYPE_SSB:
  155. offset += current_coreidx * SSB_CORE_SIZE;
  156. break;
  157. case SSB_BUSTYPE_PCI:
  158. break;
  159. case SSB_BUSTYPE_PCMCIA:
  160. if (offset >= 0x800) {
  161. ssb_pcmcia_switch_segment(bus, 1);
  162. offset -= 0x800;
  163. } else
  164. ssb_pcmcia_switch_segment(bus, 0);
  165. lo = readw(bus->mmio + offset);
  166. hi = readw(bus->mmio + offset + 2);
  167. return lo | (hi << 16);
  168. case SSB_BUSTYPE_SDIO:
  169. offset += current_coreidx * SSB_CORE_SIZE;
  170. return ssb_sdio_scan_read32(bus, offset);
  171. }
  172. return readl(bus->mmio + offset);
  173. }
  174. static int scan_switchcore(struct ssb_bus *bus, u8 coreidx)
  175. {
  176. switch (bus->bustype) {
  177. case SSB_BUSTYPE_SSB:
  178. break;
  179. case SSB_BUSTYPE_PCI:
  180. return ssb_pci_switch_coreidx(bus, coreidx);
  181. case SSB_BUSTYPE_PCMCIA:
  182. return ssb_pcmcia_switch_coreidx(bus, coreidx);
  183. case SSB_BUSTYPE_SDIO:
  184. return ssb_sdio_scan_switch_coreidx(bus, coreidx);
  185. }
  186. return 0;
  187. }
  188. void ssb_iounmap(struct ssb_bus *bus)
  189. {
  190. switch (bus->bustype) {
  191. case SSB_BUSTYPE_SSB:
  192. case SSB_BUSTYPE_PCMCIA:
  193. iounmap(bus->mmio);
  194. break;
  195. case SSB_BUSTYPE_PCI:
  196. #ifdef CONFIG_SSB_PCIHOST
  197. pci_iounmap(bus->host_pci, bus->mmio);
  198. #else
  199. WARN_ON(1); /* Can't reach this code. */
  200. #endif
  201. break;
  202. case SSB_BUSTYPE_SDIO:
  203. break;
  204. }
  205. bus->mmio = NULL;
  206. bus->mapped_device = NULL;
  207. }
  208. static void __iomem *ssb_ioremap(struct ssb_bus *bus,
  209. unsigned long baseaddr)
  210. {
  211. void __iomem *mmio = NULL;
  212. switch (bus->bustype) {
  213. case SSB_BUSTYPE_SSB:
  214. /* Only map the first core for now. */
  215. /* fallthrough... */
  216. case SSB_BUSTYPE_PCMCIA:
  217. mmio = ioremap(baseaddr, SSB_CORE_SIZE);
  218. break;
  219. case SSB_BUSTYPE_PCI:
  220. #ifdef CONFIG_SSB_PCIHOST
  221. mmio = pci_iomap(bus->host_pci, 0, ~0UL);
  222. #else
  223. WARN_ON(1); /* Can't reach this code. */
  224. #endif
  225. break;
  226. case SSB_BUSTYPE_SDIO:
  227. /* Nothing to ioremap in the SDIO case, just fake it */
  228. mmio = (void __iomem *)baseaddr;
  229. break;
  230. }
  231. return mmio;
  232. }
  233. static int we_support_multiple_80211_cores(struct ssb_bus *bus)
  234. {
  235. /* More than one 802.11 core is only supported by special chips.
  236. * There are chips with two 802.11 cores, but with dangling
  237. * pins on the second core. Be careful and reject them here.
  238. */
  239. #ifdef CONFIG_SSB_PCIHOST
  240. if (bus->bustype == SSB_BUSTYPE_PCI) {
  241. if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM &&
  242. ((bus->host_pci->device == 0x4313) ||
  243. (bus->host_pci->device == 0x431A) ||
  244. (bus->host_pci->device == 0x4321) ||
  245. (bus->host_pci->device == 0x4324)))
  246. return 1;
  247. }
  248. #endif /* CONFIG_SSB_PCIHOST */
  249. return 0;
  250. }
  251. int ssb_bus_scan(struct ssb_bus *bus,
  252. unsigned long baseaddr)
  253. {
  254. int err = -ENOMEM;
  255. void __iomem *mmio;
  256. u32 idhi, cc, rev, tmp;
  257. int dev_i, i;
  258. struct ssb_device *dev;
  259. int nr_80211_cores = 0;
  260. mmio = ssb_ioremap(bus, baseaddr);
  261. if (!mmio)
  262. goto out;
  263. bus->mmio = mmio;
  264. err = scan_switchcore(bus, 0); /* Switch to first core */
  265. if (err)
  266. goto err_unmap;
  267. idhi = scan_read32(bus, 0, SSB_IDHIGH);
  268. cc = (idhi & SSB_IDHIGH_CC) >> SSB_IDHIGH_CC_SHIFT;
  269. rev = (idhi & SSB_IDHIGH_RCLO);
  270. rev |= (idhi & SSB_IDHIGH_RCHI) >> SSB_IDHIGH_RCHI_SHIFT;
  271. bus->nr_devices = 0;
  272. if (cc == SSB_DEV_CHIPCOMMON) {
  273. tmp = scan_read32(bus, 0, SSB_CHIPCO_CHIPID);
  274. bus->chip_id = (tmp & SSB_CHIPCO_IDMASK);
  275. bus->chip_rev = (tmp & SSB_CHIPCO_REVMASK) >>
  276. SSB_CHIPCO_REVSHIFT;
  277. bus->chip_package = (tmp & SSB_CHIPCO_PACKMASK) >>
  278. SSB_CHIPCO_PACKSHIFT;
  279. if (rev >= 4) {
  280. bus->nr_devices = (tmp & SSB_CHIPCO_NRCORESMASK) >>
  281. SSB_CHIPCO_NRCORESSHIFT;
  282. }
  283. tmp = scan_read32(bus, 0, SSB_CHIPCO_CAP);
  284. bus->chipco.capabilities = tmp;
  285. } else {
  286. if (bus->bustype == SSB_BUSTYPE_PCI) {
  287. bus->chip_id = pcidev_to_chipid(bus->host_pci);
  288. bus->chip_rev = bus->host_pci->revision;
  289. bus->chip_package = 0;
  290. } else {
  291. bus->chip_id = 0x4710;
  292. bus->chip_rev = 0;
  293. bus->chip_package = 0;
  294. }
  295. }
  296. pr_info("Found chip with id 0x%04X, rev 0x%02X and package 0x%02X\n",
  297. bus->chip_id, bus->chip_rev, bus->chip_package);
  298. if (!bus->nr_devices)
  299. bus->nr_devices = chipid_to_nrcores(bus->chip_id);
  300. if (bus->nr_devices > ARRAY_SIZE(bus->devices)) {
  301. pr_err("More than %d ssb cores found (%d)\n",
  302. SSB_MAX_NR_CORES, bus->nr_devices);
  303. goto err_unmap;
  304. }
  305. if (bus->bustype == SSB_BUSTYPE_SSB) {
  306. /* Now that we know the number of cores,
  307. * remap the whole IO space for all cores.
  308. */
  309. err = -ENOMEM;
  310. iounmap(mmio);
  311. mmio = ioremap(baseaddr, SSB_CORE_SIZE * bus->nr_devices);
  312. if (!mmio)
  313. goto out;
  314. bus->mmio = mmio;
  315. }
  316. /* Fetch basic information about each core/device */
  317. for (i = 0, dev_i = 0; i < bus->nr_devices; i++) {
  318. err = scan_switchcore(bus, i);
  319. if (err)
  320. goto err_unmap;
  321. dev = &(bus->devices[dev_i]);
  322. idhi = scan_read32(bus, i, SSB_IDHIGH);
  323. dev->id.coreid = (idhi & SSB_IDHIGH_CC) >> SSB_IDHIGH_CC_SHIFT;
  324. dev->id.revision = (idhi & SSB_IDHIGH_RCLO);
  325. dev->id.revision |= (idhi & SSB_IDHIGH_RCHI) >> SSB_IDHIGH_RCHI_SHIFT;
  326. dev->id.vendor = (idhi & SSB_IDHIGH_VC) >> SSB_IDHIGH_VC_SHIFT;
  327. dev->core_index = i;
  328. dev->bus = bus;
  329. dev->ops = bus->ops;
  330. pr_debug("Core %d found: %s (cc 0x%03X, rev 0x%02X, vendor 0x%04X)\n",
  331. i, ssb_core_name(dev->id.coreid),
  332. dev->id.coreid, dev->id.revision, dev->id.vendor);
  333. switch (dev->id.coreid) {
  334. case SSB_DEV_80211:
  335. nr_80211_cores++;
  336. if (nr_80211_cores > 1) {
  337. if (!we_support_multiple_80211_cores(bus)) {
  338. pr_debug("Ignoring additional 802.11 core\n");
  339. continue;
  340. }
  341. }
  342. break;
  343. case SSB_DEV_EXTIF:
  344. #ifdef CONFIG_SSB_DRIVER_EXTIF
  345. if (bus->extif.dev) {
  346. pr_warn("WARNING: Multiple EXTIFs found\n");
  347. break;
  348. }
  349. bus->extif.dev = dev;
  350. #endif /* CONFIG_SSB_DRIVER_EXTIF */
  351. break;
  352. case SSB_DEV_CHIPCOMMON:
  353. if (bus->chipco.dev) {
  354. pr_warn("WARNING: Multiple ChipCommon found\n");
  355. break;
  356. }
  357. bus->chipco.dev = dev;
  358. break;
  359. case SSB_DEV_MIPS:
  360. case SSB_DEV_MIPS_3302:
  361. #ifdef CONFIG_SSB_DRIVER_MIPS
  362. if (bus->mipscore.dev) {
  363. pr_warn("WARNING: Multiple MIPS cores found\n");
  364. break;
  365. }
  366. bus->mipscore.dev = dev;
  367. #endif /* CONFIG_SSB_DRIVER_MIPS */
  368. break;
  369. case SSB_DEV_PCI:
  370. case SSB_DEV_PCIE:
  371. #ifdef CONFIG_SSB_DRIVER_PCICORE
  372. if (bus->bustype == SSB_BUSTYPE_PCI) {
  373. /* Ignore PCI cores on PCI-E cards.
  374. * Ignore PCI-E cores on PCI cards. */
  375. if (dev->id.coreid == SSB_DEV_PCI) {
  376. if (pci_is_pcie(bus->host_pci))
  377. continue;
  378. } else {
  379. if (!pci_is_pcie(bus->host_pci))
  380. continue;
  381. }
  382. }
  383. if (bus->pcicore.dev) {
  384. pr_warn("WARNING: Multiple PCI(E) cores found\n");
  385. break;
  386. }
  387. bus->pcicore.dev = dev;
  388. #endif /* CONFIG_SSB_DRIVER_PCICORE */
  389. break;
  390. case SSB_DEV_ETHERNET:
  391. if (bus->bustype == SSB_BUSTYPE_PCI) {
  392. if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM &&
  393. (bus->host_pci->device & 0xFF00) == 0x4300) {
  394. /* This is a dangling ethernet core on a
  395. * wireless device. Ignore it. */
  396. continue;
  397. }
  398. }
  399. break;
  400. default:
  401. break;
  402. }
  403. dev_i++;
  404. }
  405. bus->nr_devices = dev_i;
  406. err = 0;
  407. out:
  408. return err;
  409. err_unmap:
  410. ssb_iounmap(bus);
  411. goto out;
  412. }