ufshcd.c 218 KB

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  1. /*
  2. * Universal Flash Storage Host controller driver Core
  3. *
  4. * This code is based on drivers/scsi/ufs/ufshcd.c
  5. * Copyright (C) 2011-2013 Samsung India Software Operations
  6. * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
  7. *
  8. * Authors:
  9. * Santosh Yaraganavi <santosh.sy@samsung.com>
  10. * Vinayak Holikatti <h.vinayak@samsung.com>
  11. *
  12. * This program is free software; you can redistribute it and/or
  13. * modify it under the terms of the GNU General Public License
  14. * as published by the Free Software Foundation; either version 2
  15. * of the License, or (at your option) any later version.
  16. * See the COPYING file in the top-level directory or visit
  17. * <http://www.gnu.org/licenses/gpl-2.0.html>
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. *
  24. * This program is provided "AS IS" and "WITH ALL FAULTS" and
  25. * without warranty of any kind. You are solely responsible for
  26. * determining the appropriateness of using and distributing
  27. * the program and assume all risks associated with your exercise
  28. * of rights with respect to the program, including but not limited
  29. * to infringement of third party rights, the risks and costs of
  30. * program errors, damage to or loss of data, programs or equipment,
  31. * and unavailability or interruption of operations. Under no
  32. * circumstances will the contributor of this Program be liable for
  33. * any damages of any kind arising from your use or distribution of
  34. * this program.
  35. *
  36. * The Linux Foundation chooses to take subject only to the GPLv2
  37. * license terms, and distributes only under these terms.
  38. */
  39. #include <linux/async.h>
  40. #include <linux/devfreq.h>
  41. #include <linux/nls.h>
  42. #include <linux/of.h>
  43. #include <linux/bitfield.h>
  44. #include "ufshcd.h"
  45. #include "ufs_quirks.h"
  46. #include "unipro.h"
  47. #include "ufs-sysfs.h"
  48. #define CREATE_TRACE_POINTS
  49. #include <trace/events/ufs.h>
  50. #define UFSHCD_REQ_SENSE_SIZE 18
  51. #define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
  52. UTP_TASK_REQ_COMPL |\
  53. UFSHCD_ERROR_MASK)
  54. /* UIC command timeout, unit: ms */
  55. #define UIC_CMD_TIMEOUT 500
  56. /* NOP OUT retries waiting for NOP IN response */
  57. #define NOP_OUT_RETRIES 10
  58. /* Timeout after 30 msecs if NOP OUT hangs without response */
  59. #define NOP_OUT_TIMEOUT 30 /* msecs */
  60. /* Query request retries */
  61. #define QUERY_REQ_RETRIES 3
  62. /* Query request timeout */
  63. #define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */
  64. /* Task management command timeout */
  65. #define TM_CMD_TIMEOUT 100 /* msecs */
  66. /* maximum number of retries for a general UIC command */
  67. #define UFS_UIC_COMMAND_RETRIES 3
  68. /* maximum number of link-startup retries */
  69. #define DME_LINKSTARTUP_RETRIES 3
  70. /* Maximum retries for Hibern8 enter */
  71. #define UIC_HIBERN8_ENTER_RETRIES 3
  72. /* maximum number of reset retries before giving up */
  73. #define MAX_HOST_RESET_RETRIES 5
  74. /* Expose the flag value from utp_upiu_query.value */
  75. #define MASK_QUERY_UPIU_FLAG_LOC 0xFF
  76. /* Interrupt aggregation default timeout, unit: 40us */
  77. #define INT_AGGR_DEF_TO 0x02
  78. #define ufshcd_toggle_vreg(_dev, _vreg, _on) \
  79. ({ \
  80. int _ret; \
  81. if (_on) \
  82. _ret = ufshcd_enable_vreg(_dev, _vreg); \
  83. else \
  84. _ret = ufshcd_disable_vreg(_dev, _vreg); \
  85. _ret; \
  86. })
  87. #define ufshcd_hex_dump(prefix_str, buf, len) do { \
  88. size_t __len = (len); \
  89. print_hex_dump(KERN_ERR, prefix_str, \
  90. __len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE,\
  91. 16, 4, buf, __len, false); \
  92. } while (0)
  93. int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len,
  94. const char *prefix)
  95. {
  96. u32 *regs;
  97. size_t pos;
  98. if (offset % 4 != 0 || len % 4 != 0) /* keep readl happy */
  99. return -EINVAL;
  100. regs = kzalloc(len, GFP_KERNEL);
  101. if (!regs)
  102. return -ENOMEM;
  103. for (pos = 0; pos < len; pos += 4)
  104. regs[pos / 4] = ufshcd_readl(hba, offset + pos);
  105. ufshcd_hex_dump(prefix, regs, len);
  106. kfree(regs);
  107. return 0;
  108. }
  109. EXPORT_SYMBOL_GPL(ufshcd_dump_regs);
  110. enum {
  111. UFSHCD_MAX_CHANNEL = 0,
  112. UFSHCD_MAX_ID = 1,
  113. UFSHCD_CMD_PER_LUN = 32,
  114. UFSHCD_CAN_QUEUE = 32,
  115. };
  116. /* UFSHCD states */
  117. enum {
  118. UFSHCD_STATE_RESET,
  119. UFSHCD_STATE_ERROR,
  120. UFSHCD_STATE_OPERATIONAL,
  121. UFSHCD_STATE_EH_SCHEDULED,
  122. };
  123. /* UFSHCD error handling flags */
  124. enum {
  125. UFSHCD_EH_IN_PROGRESS = (1 << 0),
  126. };
  127. /* UFSHCD UIC layer error flags */
  128. enum {
  129. UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */
  130. UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */
  131. UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */
  132. UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */
  133. UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */
  134. UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */
  135. };
  136. #define ufshcd_set_eh_in_progress(h) \
  137. ((h)->eh_flags |= UFSHCD_EH_IN_PROGRESS)
  138. #define ufshcd_eh_in_progress(h) \
  139. ((h)->eh_flags & UFSHCD_EH_IN_PROGRESS)
  140. #define ufshcd_clear_eh_in_progress(h) \
  141. ((h)->eh_flags &= ~UFSHCD_EH_IN_PROGRESS)
  142. #define ufshcd_set_ufs_dev_active(h) \
  143. ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE)
  144. #define ufshcd_set_ufs_dev_sleep(h) \
  145. ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE)
  146. #define ufshcd_set_ufs_dev_poweroff(h) \
  147. ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE)
  148. #define ufshcd_is_ufs_dev_active(h) \
  149. ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE)
  150. #define ufshcd_is_ufs_dev_sleep(h) \
  151. ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE)
  152. #define ufshcd_is_ufs_dev_poweroff(h) \
  153. ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE)
  154. struct ufs_pm_lvl_states ufs_pm_lvl_states[] = {
  155. {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE},
  156. {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE},
  157. {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE},
  158. {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE},
  159. {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE},
  160. {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE},
  161. };
  162. static inline enum ufs_dev_pwr_mode
  163. ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)
  164. {
  165. return ufs_pm_lvl_states[lvl].dev_state;
  166. }
  167. static inline enum uic_link_state
  168. ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)
  169. {
  170. return ufs_pm_lvl_states[lvl].link_state;
  171. }
  172. static inline enum ufs_pm_level
  173. ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state,
  174. enum uic_link_state link_state)
  175. {
  176. enum ufs_pm_level lvl;
  177. for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) {
  178. if ((ufs_pm_lvl_states[lvl].dev_state == dev_state) &&
  179. (ufs_pm_lvl_states[lvl].link_state == link_state))
  180. return lvl;
  181. }
  182. /* if no match found, return the level 0 */
  183. return UFS_PM_LVL_0;
  184. }
  185. static struct ufs_dev_fix ufs_fixups[] = {
  186. /* UFS cards deviations table */
  187. UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
  188. UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
  189. UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL, UFS_DEVICE_NO_VCCQ),
  190. UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
  191. UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS),
  192. UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
  193. UFS_DEVICE_NO_FASTAUTO),
  194. UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
  195. UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE),
  196. UFS_FIX(UFS_VENDOR_TOSHIBA, UFS_ANY_MODEL,
  197. UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
  198. UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9C8KBADG",
  199. UFS_DEVICE_QUIRK_PA_TACTIVATE),
  200. UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9D8KBADG",
  201. UFS_DEVICE_QUIRK_PA_TACTIVATE),
  202. UFS_FIX(UFS_VENDOR_SKHYNIX, UFS_ANY_MODEL, UFS_DEVICE_NO_VCCQ),
  203. UFS_FIX(UFS_VENDOR_SKHYNIX, UFS_ANY_MODEL,
  204. UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME),
  205. UFS_FIX(UFS_VENDOR_SKHYNIX, "hB8aL1" /*H28U62301AMR*/,
  206. UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME),
  207. END_FIX
  208. };
  209. static void ufshcd_tmc_handler(struct ufs_hba *hba);
  210. static void ufshcd_async_scan(void *data, async_cookie_t cookie);
  211. static int ufshcd_reset_and_restore(struct ufs_hba *hba);
  212. static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd);
  213. static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
  214. static void ufshcd_hba_exit(struct ufs_hba *hba);
  215. static int ufshcd_probe_hba(struct ufs_hba *hba);
  216. static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
  217. bool skip_ref_clk);
  218. static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
  219. static int ufshcd_set_vccq_rail_unused(struct ufs_hba *hba, bool unused);
  220. static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
  221. static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
  222. static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
  223. static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
  224. static void ufshcd_resume_clkscaling(struct ufs_hba *hba);
  225. static void ufshcd_suspend_clkscaling(struct ufs_hba *hba);
  226. static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba);
  227. static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up);
  228. static irqreturn_t ufshcd_intr(int irq, void *__hba);
  229. static int ufshcd_change_power_mode(struct ufs_hba *hba,
  230. struct ufs_pa_layer_attr *pwr_mode);
  231. static inline bool ufshcd_valid_tag(struct ufs_hba *hba, int tag)
  232. {
  233. return tag >= 0 && tag < hba->nutrs;
  234. }
  235. static inline int ufshcd_enable_irq(struct ufs_hba *hba)
  236. {
  237. int ret = 0;
  238. if (!hba->is_irq_enabled) {
  239. ret = request_irq(hba->irq, ufshcd_intr, IRQF_SHARED, UFSHCD,
  240. hba);
  241. if (ret)
  242. dev_err(hba->dev, "%s: request_irq failed, ret=%d\n",
  243. __func__, ret);
  244. hba->is_irq_enabled = true;
  245. }
  246. return ret;
  247. }
  248. static inline void ufshcd_disable_irq(struct ufs_hba *hba)
  249. {
  250. if (hba->is_irq_enabled) {
  251. free_irq(hba->irq, hba);
  252. hba->is_irq_enabled = false;
  253. }
  254. }
  255. static void ufshcd_scsi_unblock_requests(struct ufs_hba *hba)
  256. {
  257. if (atomic_dec_and_test(&hba->scsi_block_reqs_cnt))
  258. scsi_unblock_requests(hba->host);
  259. }
  260. static void ufshcd_scsi_block_requests(struct ufs_hba *hba)
  261. {
  262. if (atomic_inc_return(&hba->scsi_block_reqs_cnt) == 1)
  263. scsi_block_requests(hba->host);
  264. }
  265. /* replace non-printable or non-ASCII characters with spaces */
  266. static inline void ufshcd_remove_non_printable(char *val)
  267. {
  268. if (!val)
  269. return;
  270. if (*val < 0x20 || *val > 0x7e)
  271. *val = ' ';
  272. }
  273. static void ufshcd_add_cmd_upiu_trace(struct ufs_hba *hba, unsigned int tag,
  274. const char *str)
  275. {
  276. struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr;
  277. trace_ufshcd_upiu(dev_name(hba->dev), str, &rq->header, &rq->sc.cdb);
  278. }
  279. static void ufshcd_add_query_upiu_trace(struct ufs_hba *hba, unsigned int tag,
  280. const char *str)
  281. {
  282. struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr;
  283. trace_ufshcd_upiu(dev_name(hba->dev), str, &rq->header, &rq->qr);
  284. }
  285. static void ufshcd_add_tm_upiu_trace(struct ufs_hba *hba, unsigned int tag,
  286. const char *str)
  287. {
  288. struct utp_task_req_desc *descp;
  289. struct utp_upiu_task_req *task_req;
  290. int off = (int)tag - hba->nutrs;
  291. descp = &hba->utmrdl_base_addr[off];
  292. task_req = (struct utp_upiu_task_req *)descp->task_req_upiu;
  293. trace_ufshcd_upiu(dev_name(hba->dev), str, &task_req->header,
  294. &task_req->input_param1);
  295. }
  296. static void ufshcd_add_command_trace(struct ufs_hba *hba,
  297. unsigned int tag, const char *str)
  298. {
  299. sector_t lba = -1;
  300. u8 opcode = 0;
  301. u32 intr, doorbell;
  302. struct ufshcd_lrb *lrbp = &hba->lrb[tag];
  303. int transfer_len = -1;
  304. if (!trace_ufshcd_command_enabled()) {
  305. /* trace UPIU W/O tracing command */
  306. if (lrbp->cmd)
  307. ufshcd_add_cmd_upiu_trace(hba, tag, str);
  308. return;
  309. }
  310. if (lrbp->cmd) { /* data phase exists */
  311. /* trace UPIU also */
  312. ufshcd_add_cmd_upiu_trace(hba, tag, str);
  313. opcode = (u8)(*lrbp->cmd->cmnd);
  314. if ((opcode == READ_10) || (opcode == WRITE_10)) {
  315. /*
  316. * Currently we only fully trace read(10) and write(10)
  317. * commands
  318. */
  319. if (lrbp->cmd->request && lrbp->cmd->request->bio)
  320. lba =
  321. lrbp->cmd->request->bio->bi_iter.bi_sector;
  322. transfer_len = be32_to_cpu(
  323. lrbp->ucd_req_ptr->sc.exp_data_transfer_len);
  324. }
  325. }
  326. intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
  327. doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
  328. trace_ufshcd_command(dev_name(hba->dev), str, tag,
  329. doorbell, transfer_len, intr, lba, opcode);
  330. }
  331. static void ufshcd_print_clk_freqs(struct ufs_hba *hba)
  332. {
  333. struct ufs_clk_info *clki;
  334. struct list_head *head = &hba->clk_list_head;
  335. if (list_empty(head))
  336. return;
  337. list_for_each_entry(clki, head, list) {
  338. if (!IS_ERR_OR_NULL(clki->clk) && clki->min_freq &&
  339. clki->max_freq)
  340. dev_err(hba->dev, "clk: %s, rate: %u\n",
  341. clki->name, clki->curr_freq);
  342. }
  343. }
  344. static void ufshcd_print_uic_err_hist(struct ufs_hba *hba,
  345. struct ufs_uic_err_reg_hist *err_hist, char *err_name)
  346. {
  347. int i;
  348. for (i = 0; i < UIC_ERR_REG_HIST_LENGTH; i++) {
  349. int p = (i + err_hist->pos - 1) % UIC_ERR_REG_HIST_LENGTH;
  350. if (err_hist->reg[p] == 0)
  351. continue;
  352. dev_err(hba->dev, "%s[%d] = 0x%x at %lld us\n", err_name, i,
  353. err_hist->reg[p], ktime_to_us(err_hist->tstamp[p]));
  354. }
  355. }
  356. static void ufshcd_print_host_regs(struct ufs_hba *hba)
  357. {
  358. ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: ");
  359. dev_err(hba->dev, "hba->ufs_version = 0x%x, hba->capabilities = 0x%x\n",
  360. hba->ufs_version, hba->capabilities);
  361. dev_err(hba->dev,
  362. "hba->outstanding_reqs = 0x%x, hba->outstanding_tasks = 0x%x\n",
  363. (u32)hba->outstanding_reqs, (u32)hba->outstanding_tasks);
  364. dev_err(hba->dev,
  365. "last_hibern8_exit_tstamp at %lld us, hibern8_exit_cnt = %d\n",
  366. ktime_to_us(hba->ufs_stats.last_hibern8_exit_tstamp),
  367. hba->ufs_stats.hibern8_exit_cnt);
  368. ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.pa_err, "pa_err");
  369. ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.dl_err, "dl_err");
  370. ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.nl_err, "nl_err");
  371. ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.tl_err, "tl_err");
  372. ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.dme_err, "dme_err");
  373. ufshcd_print_clk_freqs(hba);
  374. if (hba->vops && hba->vops->dbg_register_dump)
  375. hba->vops->dbg_register_dump(hba);
  376. }
  377. static
  378. void ufshcd_print_trs(struct ufs_hba *hba, unsigned long bitmap, bool pr_prdt)
  379. {
  380. struct ufshcd_lrb *lrbp;
  381. int prdt_length;
  382. int tag;
  383. for_each_set_bit(tag, &bitmap, hba->nutrs) {
  384. lrbp = &hba->lrb[tag];
  385. dev_err(hba->dev, "UPIU[%d] - issue time %lld us\n",
  386. tag, ktime_to_us(lrbp->issue_time_stamp));
  387. dev_err(hba->dev, "UPIU[%d] - complete time %lld us\n",
  388. tag, ktime_to_us(lrbp->compl_time_stamp));
  389. dev_err(hba->dev,
  390. "UPIU[%d] - Transfer Request Descriptor phys@0x%llx\n",
  391. tag, (u64)lrbp->utrd_dma_addr);
  392. ufshcd_hex_dump("UPIU TRD: ", lrbp->utr_descriptor_ptr,
  393. sizeof(struct utp_transfer_req_desc));
  394. dev_err(hba->dev, "UPIU[%d] - Request UPIU phys@0x%llx\n", tag,
  395. (u64)lrbp->ucd_req_dma_addr);
  396. ufshcd_hex_dump("UPIU REQ: ", lrbp->ucd_req_ptr,
  397. sizeof(struct utp_upiu_req));
  398. dev_err(hba->dev, "UPIU[%d] - Response UPIU phys@0x%llx\n", tag,
  399. (u64)lrbp->ucd_rsp_dma_addr);
  400. ufshcd_hex_dump("UPIU RSP: ", lrbp->ucd_rsp_ptr,
  401. sizeof(struct utp_upiu_rsp));
  402. prdt_length = le16_to_cpu(
  403. lrbp->utr_descriptor_ptr->prd_table_length);
  404. dev_err(hba->dev,
  405. "UPIU[%d] - PRDT - %d entries phys@0x%llx\n",
  406. tag, prdt_length,
  407. (u64)lrbp->ucd_prdt_dma_addr);
  408. if (pr_prdt)
  409. ufshcd_hex_dump("UPIU PRDT: ", lrbp->ucd_prdt_ptr,
  410. sizeof(struct ufshcd_sg_entry) * prdt_length);
  411. }
  412. }
  413. static void ufshcd_print_tmrs(struct ufs_hba *hba, unsigned long bitmap)
  414. {
  415. struct utp_task_req_desc *tmrdp;
  416. int tag;
  417. for_each_set_bit(tag, &bitmap, hba->nutmrs) {
  418. tmrdp = &hba->utmrdl_base_addr[tag];
  419. dev_err(hba->dev, "TM[%d] - Task Management Header\n", tag);
  420. ufshcd_hex_dump("TM TRD: ", &tmrdp->header,
  421. sizeof(struct request_desc_header));
  422. dev_err(hba->dev, "TM[%d] - Task Management Request UPIU\n",
  423. tag);
  424. ufshcd_hex_dump("TM REQ: ", tmrdp->task_req_upiu,
  425. sizeof(struct utp_upiu_req));
  426. dev_err(hba->dev, "TM[%d] - Task Management Response UPIU\n",
  427. tag);
  428. ufshcd_hex_dump("TM RSP: ", tmrdp->task_rsp_upiu,
  429. sizeof(struct utp_task_req_desc));
  430. }
  431. }
  432. static void ufshcd_print_host_state(struct ufs_hba *hba)
  433. {
  434. dev_err(hba->dev, "UFS Host state=%d\n", hba->ufshcd_state);
  435. dev_err(hba->dev, "lrb in use=0x%lx, outstanding reqs=0x%lx tasks=0x%lx\n",
  436. hba->lrb_in_use, hba->outstanding_reqs, hba->outstanding_tasks);
  437. dev_err(hba->dev, "saved_err=0x%x, saved_uic_err=0x%x\n",
  438. hba->saved_err, hba->saved_uic_err);
  439. dev_err(hba->dev, "Device power mode=%d, UIC link state=%d\n",
  440. hba->curr_dev_pwr_mode, hba->uic_link_state);
  441. dev_err(hba->dev, "PM in progress=%d, sys. suspended=%d\n",
  442. hba->pm_op_in_progress, hba->is_sys_suspended);
  443. dev_err(hba->dev, "Auto BKOPS=%d, Host self-block=%d\n",
  444. hba->auto_bkops_enabled, hba->host->host_self_blocked);
  445. dev_err(hba->dev, "Clk gate=%d\n", hba->clk_gating.state);
  446. dev_err(hba->dev, "error handling flags=0x%x, req. abort count=%d\n",
  447. hba->eh_flags, hba->req_abort_count);
  448. dev_err(hba->dev, "Host capabilities=0x%x, caps=0x%x\n",
  449. hba->capabilities, hba->caps);
  450. dev_err(hba->dev, "quirks=0x%x, dev. quirks=0x%x\n", hba->quirks,
  451. hba->dev_quirks);
  452. }
  453. /**
  454. * ufshcd_print_pwr_info - print power params as saved in hba
  455. * power info
  456. * @hba: per-adapter instance
  457. */
  458. static void ufshcd_print_pwr_info(struct ufs_hba *hba)
  459. {
  460. static const char * const names[] = {
  461. "INVALID MODE",
  462. "FAST MODE",
  463. "SLOW_MODE",
  464. "INVALID MODE",
  465. "FASTAUTO_MODE",
  466. "SLOWAUTO_MODE",
  467. "INVALID MODE",
  468. };
  469. dev_err(hba->dev, "%s:[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n",
  470. __func__,
  471. hba->pwr_info.gear_rx, hba->pwr_info.gear_tx,
  472. hba->pwr_info.lane_rx, hba->pwr_info.lane_tx,
  473. names[hba->pwr_info.pwr_rx],
  474. names[hba->pwr_info.pwr_tx],
  475. hba->pwr_info.hs_rate);
  476. }
  477. /*
  478. * ufshcd_wait_for_register - wait for register value to change
  479. * @hba - per-adapter interface
  480. * @reg - mmio register offset
  481. * @mask - mask to apply to read register value
  482. * @val - wait condition
  483. * @interval_us - polling interval in microsecs
  484. * @timeout_ms - timeout in millisecs
  485. * @can_sleep - perform sleep or just spin
  486. *
  487. * Returns -ETIMEDOUT on error, zero on success
  488. */
  489. int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
  490. u32 val, unsigned long interval_us,
  491. unsigned long timeout_ms, bool can_sleep)
  492. {
  493. int err = 0;
  494. unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
  495. /* ignore bits that we don't intend to wait on */
  496. val = val & mask;
  497. while ((ufshcd_readl(hba, reg) & mask) != val) {
  498. if (can_sleep)
  499. usleep_range(interval_us, interval_us + 50);
  500. else
  501. udelay(interval_us);
  502. if (time_after(jiffies, timeout)) {
  503. if ((ufshcd_readl(hba, reg) & mask) != val)
  504. err = -ETIMEDOUT;
  505. break;
  506. }
  507. }
  508. return err;
  509. }
  510. /**
  511. * ufshcd_get_intr_mask - Get the interrupt bit mask
  512. * @hba: Pointer to adapter instance
  513. *
  514. * Returns interrupt bit mask per version
  515. */
  516. static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
  517. {
  518. u32 intr_mask = 0;
  519. switch (hba->ufs_version) {
  520. case UFSHCI_VERSION_10:
  521. intr_mask = INTERRUPT_MASK_ALL_VER_10;
  522. break;
  523. case UFSHCI_VERSION_11:
  524. case UFSHCI_VERSION_20:
  525. intr_mask = INTERRUPT_MASK_ALL_VER_11;
  526. break;
  527. case UFSHCI_VERSION_21:
  528. default:
  529. intr_mask = INTERRUPT_MASK_ALL_VER_21;
  530. break;
  531. }
  532. return intr_mask;
  533. }
  534. /**
  535. * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
  536. * @hba: Pointer to adapter instance
  537. *
  538. * Returns UFSHCI version supported by the controller
  539. */
  540. static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
  541. {
  542. if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION)
  543. return ufshcd_vops_get_ufs_hci_version(hba);
  544. return ufshcd_readl(hba, REG_UFS_VERSION);
  545. }
  546. /**
  547. * ufshcd_is_device_present - Check if any device connected to
  548. * the host controller
  549. * @hba: pointer to adapter instance
  550. *
  551. * Returns true if device present, false if no device detected
  552. */
  553. static inline bool ufshcd_is_device_present(struct ufs_hba *hba)
  554. {
  555. return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) &
  556. DEVICE_PRESENT) ? true : false;
  557. }
  558. /**
  559. * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
  560. * @lrbp: pointer to local command reference block
  561. *
  562. * This function is used to get the OCS field from UTRD
  563. * Returns the OCS field in the UTRD
  564. */
  565. static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
  566. {
  567. return le32_to_cpu(lrbp->utr_descriptor_ptr->header.dword_2) & MASK_OCS;
  568. }
  569. /**
  570. * ufshcd_get_tmr_ocs - Get the UTMRD Overall Command Status
  571. * @task_req_descp: pointer to utp_task_req_desc structure
  572. *
  573. * This function is used to get the OCS field from UTMRD
  574. * Returns the OCS field in the UTMRD
  575. */
  576. static inline int
  577. ufshcd_get_tmr_ocs(struct utp_task_req_desc *task_req_descp)
  578. {
  579. return le32_to_cpu(task_req_descp->header.dword_2) & MASK_OCS;
  580. }
  581. /**
  582. * ufshcd_get_tm_free_slot - get a free slot for task management request
  583. * @hba: per adapter instance
  584. * @free_slot: pointer to variable with available slot value
  585. *
  586. * Get a free tag and lock it until ufshcd_put_tm_slot() is called.
  587. * Returns 0 if free slot is not available, else return 1 with tag value
  588. * in @free_slot.
  589. */
  590. static bool ufshcd_get_tm_free_slot(struct ufs_hba *hba, int *free_slot)
  591. {
  592. int tag;
  593. bool ret = false;
  594. if (!free_slot)
  595. goto out;
  596. do {
  597. tag = find_first_zero_bit(&hba->tm_slots_in_use, hba->nutmrs);
  598. if (tag >= hba->nutmrs)
  599. goto out;
  600. } while (test_and_set_bit_lock(tag, &hba->tm_slots_in_use));
  601. *free_slot = tag;
  602. ret = true;
  603. out:
  604. return ret;
  605. }
  606. static inline void ufshcd_put_tm_slot(struct ufs_hba *hba, int slot)
  607. {
  608. clear_bit_unlock(slot, &hba->tm_slots_in_use);
  609. }
  610. /**
  611. * ufshcd_utrl_clear - Clear a bit in UTRLCLR register
  612. * @hba: per adapter instance
  613. * @pos: position of the bit to be cleared
  614. */
  615. static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
  616. {
  617. if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
  618. ufshcd_writel(hba, (1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
  619. else
  620. ufshcd_writel(hba, ~(1 << pos),
  621. REG_UTP_TRANSFER_REQ_LIST_CLEAR);
  622. }
  623. /**
  624. * ufshcd_utmrl_clear - Clear a bit in UTRMLCLR register
  625. * @hba: per adapter instance
  626. * @pos: position of the bit to be cleared
  627. */
  628. static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos)
  629. {
  630. if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
  631. ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
  632. else
  633. ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
  634. }
  635. /**
  636. * ufshcd_outstanding_req_clear - Clear a bit in outstanding request field
  637. * @hba: per adapter instance
  638. * @tag: position of the bit to be cleared
  639. */
  640. static inline void ufshcd_outstanding_req_clear(struct ufs_hba *hba, int tag)
  641. {
  642. __clear_bit(tag, &hba->outstanding_reqs);
  643. }
  644. /**
  645. * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
  646. * @reg: Register value of host controller status
  647. *
  648. * Returns integer, 0 on Success and positive value if failed
  649. */
  650. static inline int ufshcd_get_lists_status(u32 reg)
  651. {
  652. return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY);
  653. }
  654. /**
  655. * ufshcd_get_uic_cmd_result - Get the UIC command result
  656. * @hba: Pointer to adapter instance
  657. *
  658. * This function gets the result of UIC command completion
  659. * Returns 0 on success, non zero value on error
  660. */
  661. static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
  662. {
  663. return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
  664. MASK_UIC_COMMAND_RESULT;
  665. }
  666. /**
  667. * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
  668. * @hba: Pointer to adapter instance
  669. *
  670. * This function gets UIC command argument3
  671. * Returns 0 on success, non zero value on error
  672. */
  673. static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
  674. {
  675. return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
  676. }
  677. /**
  678. * ufshcd_get_req_rsp - returns the TR response transaction type
  679. * @ucd_rsp_ptr: pointer to response UPIU
  680. */
  681. static inline int
  682. ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
  683. {
  684. return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
  685. }
  686. /**
  687. * ufshcd_get_rsp_upiu_result - Get the result from response UPIU
  688. * @ucd_rsp_ptr: pointer to response UPIU
  689. *
  690. * This function gets the response status and scsi_status from response UPIU
  691. * Returns the response result code.
  692. */
  693. static inline int
  694. ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
  695. {
  696. return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
  697. }
  698. /*
  699. * ufshcd_get_rsp_upiu_data_seg_len - Get the data segment length
  700. * from response UPIU
  701. * @ucd_rsp_ptr: pointer to response UPIU
  702. *
  703. * Return the data segment length.
  704. */
  705. static inline unsigned int
  706. ufshcd_get_rsp_upiu_data_seg_len(struct utp_upiu_rsp *ucd_rsp_ptr)
  707. {
  708. return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
  709. MASK_RSP_UPIU_DATA_SEG_LEN;
  710. }
  711. /**
  712. * ufshcd_is_exception_event - Check if the device raised an exception event
  713. * @ucd_rsp_ptr: pointer to response UPIU
  714. *
  715. * The function checks if the device raised an exception event indicated in
  716. * the Device Information field of response UPIU.
  717. *
  718. * Returns true if exception is raised, false otherwise.
  719. */
  720. static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr)
  721. {
  722. return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
  723. MASK_RSP_EXCEPTION_EVENT ? true : false;
  724. }
  725. /**
  726. * ufshcd_reset_intr_aggr - Reset interrupt aggregation values.
  727. * @hba: per adapter instance
  728. */
  729. static inline void
  730. ufshcd_reset_intr_aggr(struct ufs_hba *hba)
  731. {
  732. ufshcd_writel(hba, INT_AGGR_ENABLE |
  733. INT_AGGR_COUNTER_AND_TIMER_RESET,
  734. REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
  735. }
  736. /**
  737. * ufshcd_config_intr_aggr - Configure interrupt aggregation values.
  738. * @hba: per adapter instance
  739. * @cnt: Interrupt aggregation counter threshold
  740. * @tmout: Interrupt aggregation timeout value
  741. */
  742. static inline void
  743. ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout)
  744. {
  745. ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
  746. INT_AGGR_COUNTER_THLD_VAL(cnt) |
  747. INT_AGGR_TIMEOUT_VAL(tmout),
  748. REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
  749. }
  750. /**
  751. * ufshcd_disable_intr_aggr - Disables interrupt aggregation.
  752. * @hba: per adapter instance
  753. */
  754. static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba)
  755. {
  756. ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
  757. }
  758. /**
  759. * ufshcd_enable_run_stop_reg - Enable run-stop registers,
  760. * When run-stop registers are set to 1, it indicates the
  761. * host controller that it can process the requests
  762. * @hba: per adapter instance
  763. */
  764. static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
  765. {
  766. ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
  767. REG_UTP_TASK_REQ_LIST_RUN_STOP);
  768. ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
  769. REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
  770. }
  771. /**
  772. * ufshcd_hba_start - Start controller initialization sequence
  773. * @hba: per adapter instance
  774. */
  775. static inline void ufshcd_hba_start(struct ufs_hba *hba)
  776. {
  777. ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE);
  778. }
  779. /**
  780. * ufshcd_is_hba_active - Get controller state
  781. * @hba: per adapter instance
  782. *
  783. * Returns false if controller is active, true otherwise
  784. */
  785. static inline bool ufshcd_is_hba_active(struct ufs_hba *hba)
  786. {
  787. return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE)
  788. ? false : true;
  789. }
  790. u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba)
  791. {
  792. /* HCI version 1.0 and 1.1 supports UniPro 1.41 */
  793. if ((hba->ufs_version == UFSHCI_VERSION_10) ||
  794. (hba->ufs_version == UFSHCI_VERSION_11))
  795. return UFS_UNIPRO_VER_1_41;
  796. else
  797. return UFS_UNIPRO_VER_1_6;
  798. }
  799. EXPORT_SYMBOL(ufshcd_get_local_unipro_ver);
  800. static bool ufshcd_is_unipro_pa_params_tuning_req(struct ufs_hba *hba)
  801. {
  802. /*
  803. * If both host and device support UniPro ver1.6 or later, PA layer
  804. * parameters tuning happens during link startup itself.
  805. *
  806. * We can manually tune PA layer parameters if either host or device
  807. * doesn't support UniPro ver 1.6 or later. But to keep manual tuning
  808. * logic simple, we will only do manual tuning if local unipro version
  809. * doesn't support ver1.6 or later.
  810. */
  811. if (ufshcd_get_local_unipro_ver(hba) < UFS_UNIPRO_VER_1_6)
  812. return true;
  813. else
  814. return false;
  815. }
  816. static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up)
  817. {
  818. int ret = 0;
  819. struct ufs_clk_info *clki;
  820. struct list_head *head = &hba->clk_list_head;
  821. ktime_t start = ktime_get();
  822. bool clk_state_changed = false;
  823. if (list_empty(head))
  824. goto out;
  825. ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE);
  826. if (ret)
  827. return ret;
  828. list_for_each_entry(clki, head, list) {
  829. if (!IS_ERR_OR_NULL(clki->clk)) {
  830. if (scale_up && clki->max_freq) {
  831. if (clki->curr_freq == clki->max_freq)
  832. continue;
  833. clk_state_changed = true;
  834. ret = clk_set_rate(clki->clk, clki->max_freq);
  835. if (ret) {
  836. dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
  837. __func__, clki->name,
  838. clki->max_freq, ret);
  839. break;
  840. }
  841. trace_ufshcd_clk_scaling(dev_name(hba->dev),
  842. "scaled up", clki->name,
  843. clki->curr_freq,
  844. clki->max_freq);
  845. clki->curr_freq = clki->max_freq;
  846. } else if (!scale_up && clki->min_freq) {
  847. if (clki->curr_freq == clki->min_freq)
  848. continue;
  849. clk_state_changed = true;
  850. ret = clk_set_rate(clki->clk, clki->min_freq);
  851. if (ret) {
  852. dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
  853. __func__, clki->name,
  854. clki->min_freq, ret);
  855. break;
  856. }
  857. trace_ufshcd_clk_scaling(dev_name(hba->dev),
  858. "scaled down", clki->name,
  859. clki->curr_freq,
  860. clki->min_freq);
  861. clki->curr_freq = clki->min_freq;
  862. }
  863. }
  864. dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__,
  865. clki->name, clk_get_rate(clki->clk));
  866. }
  867. ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
  868. out:
  869. if (clk_state_changed)
  870. trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
  871. (scale_up ? "up" : "down"),
  872. ktime_to_us(ktime_sub(ktime_get(), start)), ret);
  873. return ret;
  874. }
  875. /**
  876. * ufshcd_is_devfreq_scaling_required - check if scaling is required or not
  877. * @hba: per adapter instance
  878. * @scale_up: True if scaling up and false if scaling down
  879. *
  880. * Returns true if scaling is required, false otherwise.
  881. */
  882. static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba,
  883. bool scale_up)
  884. {
  885. struct ufs_clk_info *clki;
  886. struct list_head *head = &hba->clk_list_head;
  887. if (list_empty(head))
  888. return false;
  889. list_for_each_entry(clki, head, list) {
  890. if (!IS_ERR_OR_NULL(clki->clk)) {
  891. if (scale_up && clki->max_freq) {
  892. if (clki->curr_freq == clki->max_freq)
  893. continue;
  894. return true;
  895. } else if (!scale_up && clki->min_freq) {
  896. if (clki->curr_freq == clki->min_freq)
  897. continue;
  898. return true;
  899. }
  900. }
  901. }
  902. return false;
  903. }
  904. static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba,
  905. u64 wait_timeout_us)
  906. {
  907. unsigned long flags;
  908. int ret = 0;
  909. u32 tm_doorbell;
  910. u32 tr_doorbell;
  911. bool timeout = false, do_last_check = false;
  912. ktime_t start;
  913. ufshcd_hold(hba, false);
  914. spin_lock_irqsave(hba->host->host_lock, flags);
  915. /*
  916. * Wait for all the outstanding tasks/transfer requests.
  917. * Verify by checking the doorbell registers are clear.
  918. */
  919. start = ktime_get();
  920. do {
  921. if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) {
  922. ret = -EBUSY;
  923. goto out;
  924. }
  925. tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
  926. tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
  927. if (!tm_doorbell && !tr_doorbell) {
  928. timeout = false;
  929. break;
  930. } else if (do_last_check) {
  931. break;
  932. }
  933. spin_unlock_irqrestore(hba->host->host_lock, flags);
  934. schedule();
  935. if (ktime_to_us(ktime_sub(ktime_get(), start)) >
  936. wait_timeout_us) {
  937. timeout = true;
  938. /*
  939. * We might have scheduled out for long time so make
  940. * sure to check if doorbells are cleared by this time
  941. * or not.
  942. */
  943. do_last_check = true;
  944. }
  945. spin_lock_irqsave(hba->host->host_lock, flags);
  946. } while (tm_doorbell || tr_doorbell);
  947. if (timeout) {
  948. dev_err(hba->dev,
  949. "%s: timedout waiting for doorbell to clear (tm=0x%x, tr=0x%x)\n",
  950. __func__, tm_doorbell, tr_doorbell);
  951. ret = -EBUSY;
  952. }
  953. out:
  954. spin_unlock_irqrestore(hba->host->host_lock, flags);
  955. ufshcd_release(hba);
  956. return ret;
  957. }
  958. /**
  959. * ufshcd_scale_gear - scale up/down UFS gear
  960. * @hba: per adapter instance
  961. * @scale_up: True for scaling up gear and false for scaling down
  962. *
  963. * Returns 0 for success,
  964. * Returns -EBUSY if scaling can't happen at this time
  965. * Returns non-zero for any other errors
  966. */
  967. static int ufshcd_scale_gear(struct ufs_hba *hba, bool scale_up)
  968. {
  969. #define UFS_MIN_GEAR_TO_SCALE_DOWN UFS_HS_G1
  970. int ret = 0;
  971. struct ufs_pa_layer_attr new_pwr_info;
  972. if (scale_up) {
  973. memcpy(&new_pwr_info, &hba->clk_scaling.saved_pwr_info.info,
  974. sizeof(struct ufs_pa_layer_attr));
  975. } else {
  976. memcpy(&new_pwr_info, &hba->pwr_info,
  977. sizeof(struct ufs_pa_layer_attr));
  978. if (hba->pwr_info.gear_tx > UFS_MIN_GEAR_TO_SCALE_DOWN
  979. || hba->pwr_info.gear_rx > UFS_MIN_GEAR_TO_SCALE_DOWN) {
  980. /* save the current power mode */
  981. memcpy(&hba->clk_scaling.saved_pwr_info.info,
  982. &hba->pwr_info,
  983. sizeof(struct ufs_pa_layer_attr));
  984. /* scale down gear */
  985. new_pwr_info.gear_tx = UFS_MIN_GEAR_TO_SCALE_DOWN;
  986. new_pwr_info.gear_rx = UFS_MIN_GEAR_TO_SCALE_DOWN;
  987. }
  988. }
  989. /* check if the power mode needs to be changed or not? */
  990. ret = ufshcd_change_power_mode(hba, &new_pwr_info);
  991. if (ret)
  992. dev_err(hba->dev, "%s: failed err %d, old gear: (tx %d rx %d), new gear: (tx %d rx %d)",
  993. __func__, ret,
  994. hba->pwr_info.gear_tx, hba->pwr_info.gear_rx,
  995. new_pwr_info.gear_tx, new_pwr_info.gear_rx);
  996. return ret;
  997. }
  998. static int ufshcd_clock_scaling_prepare(struct ufs_hba *hba)
  999. {
  1000. #define DOORBELL_CLR_TOUT_US (1000 * 1000) /* 1 sec */
  1001. int ret = 0;
  1002. /*
  1003. * make sure that there are no outstanding requests when
  1004. * clock scaling is in progress
  1005. */
  1006. ufshcd_scsi_block_requests(hba);
  1007. down_write(&hba->clk_scaling_lock);
  1008. if (ufshcd_wait_for_doorbell_clr(hba, DOORBELL_CLR_TOUT_US)) {
  1009. ret = -EBUSY;
  1010. up_write(&hba->clk_scaling_lock);
  1011. ufshcd_scsi_unblock_requests(hba);
  1012. }
  1013. return ret;
  1014. }
  1015. static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba)
  1016. {
  1017. up_write(&hba->clk_scaling_lock);
  1018. ufshcd_scsi_unblock_requests(hba);
  1019. }
  1020. /**
  1021. * ufshcd_devfreq_scale - scale up/down UFS clocks and gear
  1022. * @hba: per adapter instance
  1023. * @scale_up: True for scaling up and false for scalin down
  1024. *
  1025. * Returns 0 for success,
  1026. * Returns -EBUSY if scaling can't happen at this time
  1027. * Returns non-zero for any other errors
  1028. */
  1029. static int ufshcd_devfreq_scale(struct ufs_hba *hba, bool scale_up)
  1030. {
  1031. int ret = 0;
  1032. /* let's not get into low power until clock scaling is completed */
  1033. ufshcd_hold(hba, false);
  1034. ret = ufshcd_clock_scaling_prepare(hba);
  1035. if (ret)
  1036. return ret;
  1037. /* scale down the gear before scaling down clocks */
  1038. if (!scale_up) {
  1039. ret = ufshcd_scale_gear(hba, false);
  1040. if (ret)
  1041. goto out;
  1042. }
  1043. ret = ufshcd_scale_clks(hba, scale_up);
  1044. if (ret) {
  1045. if (!scale_up)
  1046. ufshcd_scale_gear(hba, true);
  1047. goto out;
  1048. }
  1049. /* scale up the gear after scaling up clocks */
  1050. if (scale_up) {
  1051. ret = ufshcd_scale_gear(hba, true);
  1052. if (ret) {
  1053. ufshcd_scale_clks(hba, false);
  1054. goto out;
  1055. }
  1056. }
  1057. ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
  1058. out:
  1059. ufshcd_clock_scaling_unprepare(hba);
  1060. ufshcd_release(hba);
  1061. return ret;
  1062. }
  1063. static void ufshcd_clk_scaling_suspend_work(struct work_struct *work)
  1064. {
  1065. struct ufs_hba *hba = container_of(work, struct ufs_hba,
  1066. clk_scaling.suspend_work);
  1067. unsigned long irq_flags;
  1068. spin_lock_irqsave(hba->host->host_lock, irq_flags);
  1069. if (hba->clk_scaling.active_reqs || hba->clk_scaling.is_suspended) {
  1070. spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
  1071. return;
  1072. }
  1073. hba->clk_scaling.is_suspended = true;
  1074. spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
  1075. __ufshcd_suspend_clkscaling(hba);
  1076. }
  1077. static void ufshcd_clk_scaling_resume_work(struct work_struct *work)
  1078. {
  1079. struct ufs_hba *hba = container_of(work, struct ufs_hba,
  1080. clk_scaling.resume_work);
  1081. unsigned long irq_flags;
  1082. spin_lock_irqsave(hba->host->host_lock, irq_flags);
  1083. if (!hba->clk_scaling.is_suspended) {
  1084. spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
  1085. return;
  1086. }
  1087. hba->clk_scaling.is_suspended = false;
  1088. spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
  1089. devfreq_resume_device(hba->devfreq);
  1090. }
  1091. static int ufshcd_devfreq_target(struct device *dev,
  1092. unsigned long *freq, u32 flags)
  1093. {
  1094. int ret = 0;
  1095. struct ufs_hba *hba = dev_get_drvdata(dev);
  1096. ktime_t start;
  1097. bool scale_up, sched_clk_scaling_suspend_work = false;
  1098. struct list_head *clk_list = &hba->clk_list_head;
  1099. struct ufs_clk_info *clki;
  1100. unsigned long irq_flags;
  1101. if (!ufshcd_is_clkscaling_supported(hba))
  1102. return -EINVAL;
  1103. spin_lock_irqsave(hba->host->host_lock, irq_flags);
  1104. if (ufshcd_eh_in_progress(hba)) {
  1105. spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
  1106. return 0;
  1107. }
  1108. if (!hba->clk_scaling.active_reqs)
  1109. sched_clk_scaling_suspend_work = true;
  1110. if (list_empty(clk_list)) {
  1111. spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
  1112. goto out;
  1113. }
  1114. clki = list_first_entry(&hba->clk_list_head, struct ufs_clk_info, list);
  1115. scale_up = (*freq == clki->max_freq) ? true : false;
  1116. if (!ufshcd_is_devfreq_scaling_required(hba, scale_up)) {
  1117. spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
  1118. ret = 0;
  1119. goto out; /* no state change required */
  1120. }
  1121. spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
  1122. start = ktime_get();
  1123. ret = ufshcd_devfreq_scale(hba, scale_up);
  1124. trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
  1125. (scale_up ? "up" : "down"),
  1126. ktime_to_us(ktime_sub(ktime_get(), start)), ret);
  1127. out:
  1128. if (sched_clk_scaling_suspend_work)
  1129. queue_work(hba->clk_scaling.workq,
  1130. &hba->clk_scaling.suspend_work);
  1131. return ret;
  1132. }
  1133. static int ufshcd_devfreq_get_dev_status(struct device *dev,
  1134. struct devfreq_dev_status *stat)
  1135. {
  1136. struct ufs_hba *hba = dev_get_drvdata(dev);
  1137. struct ufs_clk_scaling *scaling = &hba->clk_scaling;
  1138. unsigned long flags;
  1139. if (!ufshcd_is_clkscaling_supported(hba))
  1140. return -EINVAL;
  1141. memset(stat, 0, sizeof(*stat));
  1142. spin_lock_irqsave(hba->host->host_lock, flags);
  1143. if (!scaling->window_start_t)
  1144. goto start_window;
  1145. if (scaling->is_busy_started)
  1146. scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
  1147. scaling->busy_start_t));
  1148. stat->total_time = jiffies_to_usecs((long)jiffies -
  1149. (long)scaling->window_start_t);
  1150. stat->busy_time = scaling->tot_busy_t;
  1151. start_window:
  1152. scaling->window_start_t = jiffies;
  1153. scaling->tot_busy_t = 0;
  1154. if (hba->outstanding_reqs) {
  1155. scaling->busy_start_t = ktime_get();
  1156. scaling->is_busy_started = true;
  1157. } else {
  1158. scaling->busy_start_t = 0;
  1159. scaling->is_busy_started = false;
  1160. }
  1161. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1162. return 0;
  1163. }
  1164. static struct devfreq_dev_profile ufs_devfreq_profile = {
  1165. .polling_ms = 100,
  1166. .target = ufshcd_devfreq_target,
  1167. .get_dev_status = ufshcd_devfreq_get_dev_status,
  1168. };
  1169. static int ufshcd_devfreq_init(struct ufs_hba *hba)
  1170. {
  1171. struct list_head *clk_list = &hba->clk_list_head;
  1172. struct ufs_clk_info *clki;
  1173. struct devfreq *devfreq;
  1174. int ret;
  1175. /* Skip devfreq if we don't have any clocks in the list */
  1176. if (list_empty(clk_list))
  1177. return 0;
  1178. clki = list_first_entry(clk_list, struct ufs_clk_info, list);
  1179. dev_pm_opp_add(hba->dev, clki->min_freq, 0);
  1180. dev_pm_opp_add(hba->dev, clki->max_freq, 0);
  1181. devfreq = devfreq_add_device(hba->dev,
  1182. &ufs_devfreq_profile,
  1183. DEVFREQ_GOV_SIMPLE_ONDEMAND,
  1184. NULL);
  1185. if (IS_ERR(devfreq)) {
  1186. ret = PTR_ERR(devfreq);
  1187. dev_err(hba->dev, "Unable to register with devfreq %d\n", ret);
  1188. dev_pm_opp_remove(hba->dev, clki->min_freq);
  1189. dev_pm_opp_remove(hba->dev, clki->max_freq);
  1190. return ret;
  1191. }
  1192. hba->devfreq = devfreq;
  1193. return 0;
  1194. }
  1195. static void ufshcd_devfreq_remove(struct ufs_hba *hba)
  1196. {
  1197. struct list_head *clk_list = &hba->clk_list_head;
  1198. struct ufs_clk_info *clki;
  1199. if (!hba->devfreq)
  1200. return;
  1201. devfreq_remove_device(hba->devfreq);
  1202. hba->devfreq = NULL;
  1203. clki = list_first_entry(clk_list, struct ufs_clk_info, list);
  1204. dev_pm_opp_remove(hba->dev, clki->min_freq);
  1205. dev_pm_opp_remove(hba->dev, clki->max_freq);
  1206. }
  1207. static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba)
  1208. {
  1209. unsigned long flags;
  1210. devfreq_suspend_device(hba->devfreq);
  1211. spin_lock_irqsave(hba->host->host_lock, flags);
  1212. hba->clk_scaling.window_start_t = 0;
  1213. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1214. }
  1215. static void ufshcd_suspend_clkscaling(struct ufs_hba *hba)
  1216. {
  1217. unsigned long flags;
  1218. bool suspend = false;
  1219. if (!ufshcd_is_clkscaling_supported(hba))
  1220. return;
  1221. spin_lock_irqsave(hba->host->host_lock, flags);
  1222. if (!hba->clk_scaling.is_suspended) {
  1223. suspend = true;
  1224. hba->clk_scaling.is_suspended = true;
  1225. }
  1226. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1227. if (suspend)
  1228. __ufshcd_suspend_clkscaling(hba);
  1229. }
  1230. static void ufshcd_resume_clkscaling(struct ufs_hba *hba)
  1231. {
  1232. unsigned long flags;
  1233. bool resume = false;
  1234. if (!ufshcd_is_clkscaling_supported(hba))
  1235. return;
  1236. spin_lock_irqsave(hba->host->host_lock, flags);
  1237. if (hba->clk_scaling.is_suspended) {
  1238. resume = true;
  1239. hba->clk_scaling.is_suspended = false;
  1240. }
  1241. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1242. if (resume)
  1243. devfreq_resume_device(hba->devfreq);
  1244. }
  1245. static ssize_t ufshcd_clkscale_enable_show(struct device *dev,
  1246. struct device_attribute *attr, char *buf)
  1247. {
  1248. struct ufs_hba *hba = dev_get_drvdata(dev);
  1249. return snprintf(buf, PAGE_SIZE, "%d\n", hba->clk_scaling.is_allowed);
  1250. }
  1251. static ssize_t ufshcd_clkscale_enable_store(struct device *dev,
  1252. struct device_attribute *attr, const char *buf, size_t count)
  1253. {
  1254. struct ufs_hba *hba = dev_get_drvdata(dev);
  1255. u32 value;
  1256. int err;
  1257. if (kstrtou32(buf, 0, &value))
  1258. return -EINVAL;
  1259. value = !!value;
  1260. if (value == hba->clk_scaling.is_allowed)
  1261. goto out;
  1262. pm_runtime_get_sync(hba->dev);
  1263. ufshcd_hold(hba, false);
  1264. cancel_work_sync(&hba->clk_scaling.suspend_work);
  1265. cancel_work_sync(&hba->clk_scaling.resume_work);
  1266. hba->clk_scaling.is_allowed = value;
  1267. if (value) {
  1268. ufshcd_resume_clkscaling(hba);
  1269. } else {
  1270. ufshcd_suspend_clkscaling(hba);
  1271. err = ufshcd_devfreq_scale(hba, true);
  1272. if (err)
  1273. dev_err(hba->dev, "%s: failed to scale clocks up %d\n",
  1274. __func__, err);
  1275. }
  1276. ufshcd_release(hba);
  1277. pm_runtime_put_sync(hba->dev);
  1278. out:
  1279. return count;
  1280. }
  1281. static void ufshcd_clkscaling_init_sysfs(struct ufs_hba *hba)
  1282. {
  1283. hba->clk_scaling.enable_attr.show = ufshcd_clkscale_enable_show;
  1284. hba->clk_scaling.enable_attr.store = ufshcd_clkscale_enable_store;
  1285. sysfs_attr_init(&hba->clk_scaling.enable_attr.attr);
  1286. hba->clk_scaling.enable_attr.attr.name = "clkscale_enable";
  1287. hba->clk_scaling.enable_attr.attr.mode = 0644;
  1288. if (device_create_file(hba->dev, &hba->clk_scaling.enable_attr))
  1289. dev_err(hba->dev, "Failed to create sysfs for clkscale_enable\n");
  1290. }
  1291. static void ufshcd_ungate_work(struct work_struct *work)
  1292. {
  1293. int ret;
  1294. unsigned long flags;
  1295. struct ufs_hba *hba = container_of(work, struct ufs_hba,
  1296. clk_gating.ungate_work);
  1297. cancel_delayed_work_sync(&hba->clk_gating.gate_work);
  1298. spin_lock_irqsave(hba->host->host_lock, flags);
  1299. if (hba->clk_gating.state == CLKS_ON) {
  1300. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1301. goto unblock_reqs;
  1302. }
  1303. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1304. ufshcd_setup_clocks(hba, true);
  1305. /* Exit from hibern8 */
  1306. if (ufshcd_can_hibern8_during_gating(hba)) {
  1307. /* Prevent gating in this path */
  1308. hba->clk_gating.is_suspended = true;
  1309. if (ufshcd_is_link_hibern8(hba)) {
  1310. ret = ufshcd_uic_hibern8_exit(hba);
  1311. if (ret)
  1312. dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
  1313. __func__, ret);
  1314. else
  1315. ufshcd_set_link_active(hba);
  1316. }
  1317. hba->clk_gating.is_suspended = false;
  1318. }
  1319. unblock_reqs:
  1320. ufshcd_scsi_unblock_requests(hba);
  1321. }
  1322. /**
  1323. * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release.
  1324. * Also, exit from hibern8 mode and set the link as active.
  1325. * @hba: per adapter instance
  1326. * @async: This indicates whether caller should ungate clocks asynchronously.
  1327. */
  1328. int ufshcd_hold(struct ufs_hba *hba, bool async)
  1329. {
  1330. int rc = 0;
  1331. unsigned long flags;
  1332. if (!ufshcd_is_clkgating_allowed(hba))
  1333. goto out;
  1334. spin_lock_irqsave(hba->host->host_lock, flags);
  1335. hba->clk_gating.active_reqs++;
  1336. if (ufshcd_eh_in_progress(hba)) {
  1337. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1338. return 0;
  1339. }
  1340. start:
  1341. switch (hba->clk_gating.state) {
  1342. case CLKS_ON:
  1343. /*
  1344. * Wait for the ungate work to complete if in progress.
  1345. * Though the clocks may be in ON state, the link could
  1346. * still be in hibner8 state if hibern8 is allowed
  1347. * during clock gating.
  1348. * Make sure we exit hibern8 state also in addition to
  1349. * clocks being ON.
  1350. */
  1351. if (ufshcd_can_hibern8_during_gating(hba) &&
  1352. ufshcd_is_link_hibern8(hba)) {
  1353. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1354. flush_work(&hba->clk_gating.ungate_work);
  1355. spin_lock_irqsave(hba->host->host_lock, flags);
  1356. goto start;
  1357. }
  1358. break;
  1359. case REQ_CLKS_OFF:
  1360. if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
  1361. hba->clk_gating.state = CLKS_ON;
  1362. trace_ufshcd_clk_gating(dev_name(hba->dev),
  1363. hba->clk_gating.state);
  1364. break;
  1365. }
  1366. /*
  1367. * If we are here, it means gating work is either done or
  1368. * currently running. Hence, fall through to cancel gating
  1369. * work and to enable clocks.
  1370. */
  1371. case CLKS_OFF:
  1372. ufshcd_scsi_block_requests(hba);
  1373. hba->clk_gating.state = REQ_CLKS_ON;
  1374. trace_ufshcd_clk_gating(dev_name(hba->dev),
  1375. hba->clk_gating.state);
  1376. queue_work(hba->clk_gating.clk_gating_workq,
  1377. &hba->clk_gating.ungate_work);
  1378. /*
  1379. * fall through to check if we should wait for this
  1380. * work to be done or not.
  1381. */
  1382. case REQ_CLKS_ON:
  1383. if (async) {
  1384. rc = -EAGAIN;
  1385. hba->clk_gating.active_reqs--;
  1386. break;
  1387. }
  1388. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1389. flush_work(&hba->clk_gating.ungate_work);
  1390. /* Make sure state is CLKS_ON before returning */
  1391. spin_lock_irqsave(hba->host->host_lock, flags);
  1392. goto start;
  1393. default:
  1394. dev_err(hba->dev, "%s: clk gating is in invalid state %d\n",
  1395. __func__, hba->clk_gating.state);
  1396. break;
  1397. }
  1398. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1399. out:
  1400. return rc;
  1401. }
  1402. EXPORT_SYMBOL_GPL(ufshcd_hold);
  1403. static void ufshcd_gate_work(struct work_struct *work)
  1404. {
  1405. struct ufs_hba *hba = container_of(work, struct ufs_hba,
  1406. clk_gating.gate_work.work);
  1407. unsigned long flags;
  1408. spin_lock_irqsave(hba->host->host_lock, flags);
  1409. /*
  1410. * In case you are here to cancel this work the gating state
  1411. * would be marked as REQ_CLKS_ON. In this case save time by
  1412. * skipping the gating work and exit after changing the clock
  1413. * state to CLKS_ON.
  1414. */
  1415. if (hba->clk_gating.is_suspended ||
  1416. (hba->clk_gating.state == REQ_CLKS_ON)) {
  1417. hba->clk_gating.state = CLKS_ON;
  1418. trace_ufshcd_clk_gating(dev_name(hba->dev),
  1419. hba->clk_gating.state);
  1420. goto rel_lock;
  1421. }
  1422. if (hba->clk_gating.active_reqs
  1423. || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
  1424. || hba->lrb_in_use || hba->outstanding_tasks
  1425. || hba->active_uic_cmd || hba->uic_async_done)
  1426. goto rel_lock;
  1427. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1428. /* put the link into hibern8 mode before turning off clocks */
  1429. if (ufshcd_can_hibern8_during_gating(hba)) {
  1430. if (ufshcd_uic_hibern8_enter(hba)) {
  1431. hba->clk_gating.state = CLKS_ON;
  1432. trace_ufshcd_clk_gating(dev_name(hba->dev),
  1433. hba->clk_gating.state);
  1434. goto out;
  1435. }
  1436. ufshcd_set_link_hibern8(hba);
  1437. }
  1438. if (!ufshcd_is_link_active(hba))
  1439. ufshcd_setup_clocks(hba, false);
  1440. else
  1441. /* If link is active, device ref_clk can't be switched off */
  1442. __ufshcd_setup_clocks(hba, false, true);
  1443. /*
  1444. * In case you are here to cancel this work the gating state
  1445. * would be marked as REQ_CLKS_ON. In this case keep the state
  1446. * as REQ_CLKS_ON which would anyway imply that clocks are off
  1447. * and a request to turn them on is pending. By doing this way,
  1448. * we keep the state machine in tact and this would ultimately
  1449. * prevent from doing cancel work multiple times when there are
  1450. * new requests arriving before the current cancel work is done.
  1451. */
  1452. spin_lock_irqsave(hba->host->host_lock, flags);
  1453. if (hba->clk_gating.state == REQ_CLKS_OFF) {
  1454. hba->clk_gating.state = CLKS_OFF;
  1455. trace_ufshcd_clk_gating(dev_name(hba->dev),
  1456. hba->clk_gating.state);
  1457. }
  1458. rel_lock:
  1459. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1460. out:
  1461. return;
  1462. }
  1463. /* host lock must be held before calling this variant */
  1464. static void __ufshcd_release(struct ufs_hba *hba)
  1465. {
  1466. if (!ufshcd_is_clkgating_allowed(hba))
  1467. return;
  1468. hba->clk_gating.active_reqs--;
  1469. if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended
  1470. || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
  1471. || hba->lrb_in_use || hba->outstanding_tasks
  1472. || hba->active_uic_cmd || hba->uic_async_done
  1473. || ufshcd_eh_in_progress(hba))
  1474. return;
  1475. hba->clk_gating.state = REQ_CLKS_OFF;
  1476. trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
  1477. queue_delayed_work(hba->clk_gating.clk_gating_workq,
  1478. &hba->clk_gating.gate_work,
  1479. msecs_to_jiffies(hba->clk_gating.delay_ms));
  1480. }
  1481. void ufshcd_release(struct ufs_hba *hba)
  1482. {
  1483. unsigned long flags;
  1484. spin_lock_irqsave(hba->host->host_lock, flags);
  1485. __ufshcd_release(hba);
  1486. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1487. }
  1488. EXPORT_SYMBOL_GPL(ufshcd_release);
  1489. static ssize_t ufshcd_clkgate_delay_show(struct device *dev,
  1490. struct device_attribute *attr, char *buf)
  1491. {
  1492. struct ufs_hba *hba = dev_get_drvdata(dev);
  1493. return snprintf(buf, PAGE_SIZE, "%lu\n", hba->clk_gating.delay_ms);
  1494. }
  1495. static ssize_t ufshcd_clkgate_delay_store(struct device *dev,
  1496. struct device_attribute *attr, const char *buf, size_t count)
  1497. {
  1498. struct ufs_hba *hba = dev_get_drvdata(dev);
  1499. unsigned long flags, value;
  1500. if (kstrtoul(buf, 0, &value))
  1501. return -EINVAL;
  1502. spin_lock_irqsave(hba->host->host_lock, flags);
  1503. hba->clk_gating.delay_ms = value;
  1504. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1505. return count;
  1506. }
  1507. static ssize_t ufshcd_clkgate_enable_show(struct device *dev,
  1508. struct device_attribute *attr, char *buf)
  1509. {
  1510. struct ufs_hba *hba = dev_get_drvdata(dev);
  1511. return snprintf(buf, PAGE_SIZE, "%d\n", hba->clk_gating.is_enabled);
  1512. }
  1513. static ssize_t ufshcd_clkgate_enable_store(struct device *dev,
  1514. struct device_attribute *attr, const char *buf, size_t count)
  1515. {
  1516. struct ufs_hba *hba = dev_get_drvdata(dev);
  1517. unsigned long flags;
  1518. u32 value;
  1519. if (kstrtou32(buf, 0, &value))
  1520. return -EINVAL;
  1521. value = !!value;
  1522. if (value == hba->clk_gating.is_enabled)
  1523. goto out;
  1524. if (value) {
  1525. ufshcd_release(hba);
  1526. } else {
  1527. spin_lock_irqsave(hba->host->host_lock, flags);
  1528. hba->clk_gating.active_reqs++;
  1529. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1530. }
  1531. hba->clk_gating.is_enabled = value;
  1532. out:
  1533. return count;
  1534. }
  1535. static void ufshcd_init_clk_scaling(struct ufs_hba *hba)
  1536. {
  1537. char wq_name[sizeof("ufs_clkscaling_00")];
  1538. if (!ufshcd_is_clkscaling_supported(hba))
  1539. return;
  1540. INIT_WORK(&hba->clk_scaling.suspend_work,
  1541. ufshcd_clk_scaling_suspend_work);
  1542. INIT_WORK(&hba->clk_scaling.resume_work,
  1543. ufshcd_clk_scaling_resume_work);
  1544. snprintf(wq_name, sizeof(wq_name), "ufs_clkscaling_%d",
  1545. hba->host->host_no);
  1546. hba->clk_scaling.workq = create_singlethread_workqueue(wq_name);
  1547. ufshcd_clkscaling_init_sysfs(hba);
  1548. }
  1549. static void ufshcd_exit_clk_scaling(struct ufs_hba *hba)
  1550. {
  1551. if (!ufshcd_is_clkscaling_supported(hba))
  1552. return;
  1553. destroy_workqueue(hba->clk_scaling.workq);
  1554. ufshcd_devfreq_remove(hba);
  1555. }
  1556. static void ufshcd_init_clk_gating(struct ufs_hba *hba)
  1557. {
  1558. char wq_name[sizeof("ufs_clk_gating_00")];
  1559. if (!ufshcd_is_clkgating_allowed(hba))
  1560. return;
  1561. hba->clk_gating.delay_ms = 150;
  1562. INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work);
  1563. INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work);
  1564. snprintf(wq_name, ARRAY_SIZE(wq_name), "ufs_clk_gating_%d",
  1565. hba->host->host_no);
  1566. hba->clk_gating.clk_gating_workq = alloc_ordered_workqueue(wq_name,
  1567. WQ_MEM_RECLAIM);
  1568. hba->clk_gating.is_enabled = true;
  1569. hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show;
  1570. hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store;
  1571. sysfs_attr_init(&hba->clk_gating.delay_attr.attr);
  1572. hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms";
  1573. hba->clk_gating.delay_attr.attr.mode = 0644;
  1574. if (device_create_file(hba->dev, &hba->clk_gating.delay_attr))
  1575. dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n");
  1576. hba->clk_gating.enable_attr.show = ufshcd_clkgate_enable_show;
  1577. hba->clk_gating.enable_attr.store = ufshcd_clkgate_enable_store;
  1578. sysfs_attr_init(&hba->clk_gating.enable_attr.attr);
  1579. hba->clk_gating.enable_attr.attr.name = "clkgate_enable";
  1580. hba->clk_gating.enable_attr.attr.mode = 0644;
  1581. if (device_create_file(hba->dev, &hba->clk_gating.enable_attr))
  1582. dev_err(hba->dev, "Failed to create sysfs for clkgate_enable\n");
  1583. }
  1584. static void ufshcd_exit_clk_gating(struct ufs_hba *hba)
  1585. {
  1586. if (!ufshcd_is_clkgating_allowed(hba))
  1587. return;
  1588. device_remove_file(hba->dev, &hba->clk_gating.delay_attr);
  1589. device_remove_file(hba->dev, &hba->clk_gating.enable_attr);
  1590. cancel_work_sync(&hba->clk_gating.ungate_work);
  1591. cancel_delayed_work_sync(&hba->clk_gating.gate_work);
  1592. destroy_workqueue(hba->clk_gating.clk_gating_workq);
  1593. }
  1594. /* Must be called with host lock acquired */
  1595. static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba)
  1596. {
  1597. bool queue_resume_work = false;
  1598. if (!ufshcd_is_clkscaling_supported(hba))
  1599. return;
  1600. if (!hba->clk_scaling.active_reqs++)
  1601. queue_resume_work = true;
  1602. if (!hba->clk_scaling.is_allowed || hba->pm_op_in_progress)
  1603. return;
  1604. if (queue_resume_work)
  1605. queue_work(hba->clk_scaling.workq,
  1606. &hba->clk_scaling.resume_work);
  1607. if (!hba->clk_scaling.window_start_t) {
  1608. hba->clk_scaling.window_start_t = jiffies;
  1609. hba->clk_scaling.tot_busy_t = 0;
  1610. hba->clk_scaling.is_busy_started = false;
  1611. }
  1612. if (!hba->clk_scaling.is_busy_started) {
  1613. hba->clk_scaling.busy_start_t = ktime_get();
  1614. hba->clk_scaling.is_busy_started = true;
  1615. }
  1616. }
  1617. static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba)
  1618. {
  1619. struct ufs_clk_scaling *scaling = &hba->clk_scaling;
  1620. if (!ufshcd_is_clkscaling_supported(hba))
  1621. return;
  1622. if (!hba->outstanding_reqs && scaling->is_busy_started) {
  1623. scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
  1624. scaling->busy_start_t));
  1625. scaling->busy_start_t = 0;
  1626. scaling->is_busy_started = false;
  1627. }
  1628. }
  1629. /**
  1630. * ufshcd_send_command - Send SCSI or device management commands
  1631. * @hba: per adapter instance
  1632. * @task_tag: Task tag of the command
  1633. */
  1634. static inline
  1635. void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
  1636. {
  1637. hba->lrb[task_tag].issue_time_stamp = ktime_get();
  1638. hba->lrb[task_tag].compl_time_stamp = ktime_set(0, 0);
  1639. ufshcd_clk_scaling_start_busy(hba);
  1640. __set_bit(task_tag, &hba->outstanding_reqs);
  1641. ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
  1642. /* Make sure that doorbell is committed immediately */
  1643. wmb();
  1644. ufshcd_add_command_trace(hba, task_tag, "send");
  1645. }
  1646. /**
  1647. * ufshcd_copy_sense_data - Copy sense data in case of check condition
  1648. * @lrbp: pointer to local reference block
  1649. */
  1650. static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
  1651. {
  1652. int len;
  1653. if (lrbp->sense_buffer &&
  1654. ufshcd_get_rsp_upiu_data_seg_len(lrbp->ucd_rsp_ptr)) {
  1655. int len_to_copy;
  1656. len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
  1657. len_to_copy = min_t(int, RESPONSE_UPIU_SENSE_DATA_LENGTH, len);
  1658. memcpy(lrbp->sense_buffer,
  1659. lrbp->ucd_rsp_ptr->sr.sense_data,
  1660. min_t(int, len_to_copy, UFSHCD_REQ_SENSE_SIZE));
  1661. }
  1662. }
  1663. /**
  1664. * ufshcd_copy_query_response() - Copy the Query Response and the data
  1665. * descriptor
  1666. * @hba: per adapter instance
  1667. * @lrbp: pointer to local reference block
  1668. */
  1669. static
  1670. int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
  1671. {
  1672. struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
  1673. memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
  1674. /* Get the descriptor */
  1675. if (hba->dev_cmd.query.descriptor &&
  1676. lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
  1677. u8 *descp = (u8 *)lrbp->ucd_rsp_ptr +
  1678. GENERAL_UPIU_REQUEST_SIZE;
  1679. u16 resp_len;
  1680. u16 buf_len;
  1681. /* data segment length */
  1682. resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
  1683. MASK_QUERY_DATA_SEG_LEN;
  1684. buf_len = be16_to_cpu(
  1685. hba->dev_cmd.query.request.upiu_req.length);
  1686. if (likely(buf_len >= resp_len)) {
  1687. memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
  1688. } else {
  1689. dev_warn(hba->dev,
  1690. "%s: Response size is bigger than buffer",
  1691. __func__);
  1692. return -EINVAL;
  1693. }
  1694. }
  1695. return 0;
  1696. }
  1697. /**
  1698. * ufshcd_hba_capabilities - Read controller capabilities
  1699. * @hba: per adapter instance
  1700. */
  1701. static inline void ufshcd_hba_capabilities(struct ufs_hba *hba)
  1702. {
  1703. hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
  1704. /* nutrs and nutmrs are 0 based values */
  1705. hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
  1706. hba->nutmrs =
  1707. ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
  1708. }
  1709. /**
  1710. * ufshcd_ready_for_uic_cmd - Check if controller is ready
  1711. * to accept UIC commands
  1712. * @hba: per adapter instance
  1713. * Return true on success, else false
  1714. */
  1715. static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
  1716. {
  1717. if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY)
  1718. return true;
  1719. else
  1720. return false;
  1721. }
  1722. /**
  1723. * ufshcd_get_upmcrs - Get the power mode change request status
  1724. * @hba: Pointer to adapter instance
  1725. *
  1726. * This function gets the UPMCRS field of HCS register
  1727. * Returns value of UPMCRS field
  1728. */
  1729. static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
  1730. {
  1731. return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
  1732. }
  1733. /**
  1734. * ufshcd_dispatch_uic_cmd - Dispatch UIC commands to unipro layers
  1735. * @hba: per adapter instance
  1736. * @uic_cmd: UIC command
  1737. *
  1738. * Mutex must be held.
  1739. */
  1740. static inline void
  1741. ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
  1742. {
  1743. WARN_ON(hba->active_uic_cmd);
  1744. hba->active_uic_cmd = uic_cmd;
  1745. /* Write Args */
  1746. ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
  1747. ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
  1748. ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
  1749. /* Write UIC Cmd */
  1750. ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
  1751. REG_UIC_COMMAND);
  1752. }
  1753. /**
  1754. * ufshcd_wait_for_uic_cmd - Wait complectioin of UIC command
  1755. * @hba: per adapter instance
  1756. * @uic_cmd: UIC command
  1757. *
  1758. * Must be called with mutex held.
  1759. * Returns 0 only if success.
  1760. */
  1761. static int
  1762. ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
  1763. {
  1764. int ret;
  1765. unsigned long flags;
  1766. if (wait_for_completion_timeout(&uic_cmd->done,
  1767. msecs_to_jiffies(UIC_CMD_TIMEOUT)))
  1768. ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
  1769. else
  1770. ret = -ETIMEDOUT;
  1771. spin_lock_irqsave(hba->host->host_lock, flags);
  1772. hba->active_uic_cmd = NULL;
  1773. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1774. return ret;
  1775. }
  1776. /**
  1777. * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
  1778. * @hba: per adapter instance
  1779. * @uic_cmd: UIC command
  1780. * @completion: initialize the completion only if this is set to true
  1781. *
  1782. * Identical to ufshcd_send_uic_cmd() expect mutex. Must be called
  1783. * with mutex held and host_lock locked.
  1784. * Returns 0 only if success.
  1785. */
  1786. static int
  1787. __ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd,
  1788. bool completion)
  1789. {
  1790. if (!ufshcd_ready_for_uic_cmd(hba)) {
  1791. dev_err(hba->dev,
  1792. "Controller not ready to accept UIC commands\n");
  1793. return -EIO;
  1794. }
  1795. if (completion)
  1796. init_completion(&uic_cmd->done);
  1797. ufshcd_dispatch_uic_cmd(hba, uic_cmd);
  1798. return 0;
  1799. }
  1800. /**
  1801. * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
  1802. * @hba: per adapter instance
  1803. * @uic_cmd: UIC command
  1804. *
  1805. * Returns 0 only if success.
  1806. */
  1807. static int
  1808. ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
  1809. {
  1810. int ret;
  1811. unsigned long flags;
  1812. ufshcd_hold(hba, false);
  1813. mutex_lock(&hba->uic_cmd_mutex);
  1814. ufshcd_add_delay_before_dme_cmd(hba);
  1815. spin_lock_irqsave(hba->host->host_lock, flags);
  1816. ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true);
  1817. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1818. if (!ret)
  1819. ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
  1820. mutex_unlock(&hba->uic_cmd_mutex);
  1821. ufshcd_release(hba);
  1822. return ret;
  1823. }
  1824. /**
  1825. * ufshcd_map_sg - Map scatter-gather list to prdt
  1826. * @hba: per adapter instance
  1827. * @lrbp: pointer to local reference block
  1828. *
  1829. * Returns 0 in case of success, non-zero value in case of failure
  1830. */
  1831. static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
  1832. {
  1833. struct ufshcd_sg_entry *prd_table;
  1834. struct scatterlist *sg;
  1835. struct scsi_cmnd *cmd;
  1836. int sg_segments;
  1837. int i;
  1838. cmd = lrbp->cmd;
  1839. sg_segments = scsi_dma_map(cmd);
  1840. if (sg_segments < 0)
  1841. return sg_segments;
  1842. if (sg_segments) {
  1843. if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
  1844. lrbp->utr_descriptor_ptr->prd_table_length =
  1845. cpu_to_le16((u16)(sg_segments *
  1846. sizeof(struct ufshcd_sg_entry)));
  1847. else
  1848. lrbp->utr_descriptor_ptr->prd_table_length =
  1849. cpu_to_le16((u16) (sg_segments));
  1850. prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
  1851. scsi_for_each_sg(cmd, sg, sg_segments, i) {
  1852. prd_table[i].size =
  1853. cpu_to_le32(((u32) sg_dma_len(sg))-1);
  1854. prd_table[i].base_addr =
  1855. cpu_to_le32(lower_32_bits(sg->dma_address));
  1856. prd_table[i].upper_addr =
  1857. cpu_to_le32(upper_32_bits(sg->dma_address));
  1858. prd_table[i].reserved = 0;
  1859. }
  1860. } else {
  1861. lrbp->utr_descriptor_ptr->prd_table_length = 0;
  1862. }
  1863. return 0;
  1864. }
  1865. /**
  1866. * ufshcd_enable_intr - enable interrupts
  1867. * @hba: per adapter instance
  1868. * @intrs: interrupt bits
  1869. */
  1870. static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
  1871. {
  1872. u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
  1873. if (hba->ufs_version == UFSHCI_VERSION_10) {
  1874. u32 rw;
  1875. rw = set & INTERRUPT_MASK_RW_VER_10;
  1876. set = rw | ((set ^ intrs) & intrs);
  1877. } else {
  1878. set |= intrs;
  1879. }
  1880. ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
  1881. }
  1882. /**
  1883. * ufshcd_disable_intr - disable interrupts
  1884. * @hba: per adapter instance
  1885. * @intrs: interrupt bits
  1886. */
  1887. static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
  1888. {
  1889. u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
  1890. if (hba->ufs_version == UFSHCI_VERSION_10) {
  1891. u32 rw;
  1892. rw = (set & INTERRUPT_MASK_RW_VER_10) &
  1893. ~(intrs & INTERRUPT_MASK_RW_VER_10);
  1894. set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10);
  1895. } else {
  1896. set &= ~intrs;
  1897. }
  1898. ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
  1899. }
  1900. /**
  1901. * ufshcd_prepare_req_desc_hdr() - Fills the requests header
  1902. * descriptor according to request
  1903. * @lrbp: pointer to local reference block
  1904. * @upiu_flags: flags required in the header
  1905. * @cmd_dir: requests data direction
  1906. */
  1907. static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp,
  1908. u32 *upiu_flags, enum dma_data_direction cmd_dir)
  1909. {
  1910. struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
  1911. u32 data_direction;
  1912. u32 dword_0;
  1913. if (cmd_dir == DMA_FROM_DEVICE) {
  1914. data_direction = UTP_DEVICE_TO_HOST;
  1915. *upiu_flags = UPIU_CMD_FLAGS_READ;
  1916. } else if (cmd_dir == DMA_TO_DEVICE) {
  1917. data_direction = UTP_HOST_TO_DEVICE;
  1918. *upiu_flags = UPIU_CMD_FLAGS_WRITE;
  1919. } else {
  1920. data_direction = UTP_NO_DATA_TRANSFER;
  1921. *upiu_flags = UPIU_CMD_FLAGS_NONE;
  1922. }
  1923. dword_0 = data_direction | (lrbp->command_type
  1924. << UPIU_COMMAND_TYPE_OFFSET);
  1925. if (lrbp->intr_cmd)
  1926. dword_0 |= UTP_REQ_DESC_INT_CMD;
  1927. /* Transfer request descriptor header fields */
  1928. req_desc->header.dword_0 = cpu_to_le32(dword_0);
  1929. /* dword_1 is reserved, hence it is set to 0 */
  1930. req_desc->header.dword_1 = 0;
  1931. /*
  1932. * assigning invalid value for command status. Controller
  1933. * updates OCS on command completion, with the command
  1934. * status
  1935. */
  1936. req_desc->header.dword_2 =
  1937. cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
  1938. /* dword_3 is reserved, hence it is set to 0 */
  1939. req_desc->header.dword_3 = 0;
  1940. req_desc->prd_table_length = 0;
  1941. }
  1942. /**
  1943. * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc,
  1944. * for scsi commands
  1945. * @lrbp: local reference block pointer
  1946. * @upiu_flags: flags
  1947. */
  1948. static
  1949. void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u32 upiu_flags)
  1950. {
  1951. struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
  1952. unsigned short cdb_len;
  1953. /* command descriptor fields */
  1954. ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
  1955. UPIU_TRANSACTION_COMMAND, upiu_flags,
  1956. lrbp->lun, lrbp->task_tag);
  1957. ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
  1958. UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
  1959. /* Total EHS length and Data segment length will be zero */
  1960. ucd_req_ptr->header.dword_2 = 0;
  1961. ucd_req_ptr->sc.exp_data_transfer_len =
  1962. cpu_to_be32(lrbp->cmd->sdb.length);
  1963. cdb_len = min_t(unsigned short, lrbp->cmd->cmd_len, MAX_CDB_SIZE);
  1964. memset(ucd_req_ptr->sc.cdb, 0, MAX_CDB_SIZE);
  1965. memcpy(ucd_req_ptr->sc.cdb, lrbp->cmd->cmnd, cdb_len);
  1966. memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
  1967. }
  1968. /**
  1969. * ufshcd_prepare_utp_query_req_upiu() - fills the utp_transfer_req_desc,
  1970. * for query requsts
  1971. * @hba: UFS hba
  1972. * @lrbp: local reference block pointer
  1973. * @upiu_flags: flags
  1974. */
  1975. static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
  1976. struct ufshcd_lrb *lrbp, u32 upiu_flags)
  1977. {
  1978. struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
  1979. struct ufs_query *query = &hba->dev_cmd.query;
  1980. u16 len = be16_to_cpu(query->request.upiu_req.length);
  1981. u8 *descp = (u8 *)lrbp->ucd_req_ptr + GENERAL_UPIU_REQUEST_SIZE;
  1982. /* Query request header */
  1983. ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
  1984. UPIU_TRANSACTION_QUERY_REQ, upiu_flags,
  1985. lrbp->lun, lrbp->task_tag);
  1986. ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
  1987. 0, query->request.query_func, 0, 0);
  1988. /* Data segment length only need for WRITE_DESC */
  1989. if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
  1990. ucd_req_ptr->header.dword_2 =
  1991. UPIU_HEADER_DWORD(0, 0, (len >> 8), (u8)len);
  1992. else
  1993. ucd_req_ptr->header.dword_2 = 0;
  1994. /* Copy the Query Request buffer as is */
  1995. memcpy(&ucd_req_ptr->qr, &query->request.upiu_req,
  1996. QUERY_OSF_SIZE);
  1997. /* Copy the Descriptor */
  1998. if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
  1999. memcpy(descp, query->descriptor, len);
  2000. memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
  2001. }
  2002. static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
  2003. {
  2004. struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
  2005. memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
  2006. /* command descriptor fields */
  2007. ucd_req_ptr->header.dword_0 =
  2008. UPIU_HEADER_DWORD(
  2009. UPIU_TRANSACTION_NOP_OUT, 0, 0, lrbp->task_tag);
  2010. /* clear rest of the fields of basic header */
  2011. ucd_req_ptr->header.dword_1 = 0;
  2012. ucd_req_ptr->header.dword_2 = 0;
  2013. memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
  2014. }
  2015. /**
  2016. * ufshcd_comp_devman_upiu - UFS Protocol Information Unit(UPIU)
  2017. * for Device Management Purposes
  2018. * @hba: per adapter instance
  2019. * @lrbp: pointer to local reference block
  2020. */
  2021. static int ufshcd_comp_devman_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
  2022. {
  2023. u32 upiu_flags;
  2024. int ret = 0;
  2025. if ((hba->ufs_version == UFSHCI_VERSION_10) ||
  2026. (hba->ufs_version == UFSHCI_VERSION_11))
  2027. lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
  2028. else
  2029. lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
  2030. ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
  2031. if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY)
  2032. ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags);
  2033. else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
  2034. ufshcd_prepare_utp_nop_upiu(lrbp);
  2035. else
  2036. ret = -EINVAL;
  2037. return ret;
  2038. }
  2039. /**
  2040. * ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU)
  2041. * for SCSI Purposes
  2042. * @hba: per adapter instance
  2043. * @lrbp: pointer to local reference block
  2044. */
  2045. static int ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
  2046. {
  2047. u32 upiu_flags;
  2048. int ret = 0;
  2049. if ((hba->ufs_version == UFSHCI_VERSION_10) ||
  2050. (hba->ufs_version == UFSHCI_VERSION_11))
  2051. lrbp->command_type = UTP_CMD_TYPE_SCSI;
  2052. else
  2053. lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
  2054. if (likely(lrbp->cmd)) {
  2055. ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags,
  2056. lrbp->cmd->sc_data_direction);
  2057. ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags);
  2058. } else {
  2059. ret = -EINVAL;
  2060. }
  2061. return ret;
  2062. }
  2063. /**
  2064. * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID
  2065. * @upiu_wlun_id: UPIU W-LUN id
  2066. *
  2067. * Returns SCSI W-LUN id
  2068. */
  2069. static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)
  2070. {
  2071. return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE;
  2072. }
  2073. /**
  2074. * ufshcd_queuecommand - main entry point for SCSI requests
  2075. * @host: SCSI host pointer
  2076. * @cmd: command from SCSI Midlayer
  2077. *
  2078. * Returns 0 for success, non-zero in case of failure
  2079. */
  2080. static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
  2081. {
  2082. struct ufshcd_lrb *lrbp;
  2083. struct ufs_hba *hba;
  2084. unsigned long flags;
  2085. int tag;
  2086. int err = 0;
  2087. hba = shost_priv(host);
  2088. tag = cmd->request->tag;
  2089. if (!ufshcd_valid_tag(hba, tag)) {
  2090. dev_err(hba->dev,
  2091. "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
  2092. __func__, tag, cmd, cmd->request);
  2093. BUG();
  2094. }
  2095. if (!down_read_trylock(&hba->clk_scaling_lock))
  2096. return SCSI_MLQUEUE_HOST_BUSY;
  2097. spin_lock_irqsave(hba->host->host_lock, flags);
  2098. switch (hba->ufshcd_state) {
  2099. case UFSHCD_STATE_OPERATIONAL:
  2100. break;
  2101. case UFSHCD_STATE_EH_SCHEDULED:
  2102. case UFSHCD_STATE_RESET:
  2103. err = SCSI_MLQUEUE_HOST_BUSY;
  2104. goto out_unlock;
  2105. case UFSHCD_STATE_ERROR:
  2106. set_host_byte(cmd, DID_ERROR);
  2107. cmd->scsi_done(cmd);
  2108. goto out_unlock;
  2109. default:
  2110. dev_WARN_ONCE(hba->dev, 1, "%s: invalid state %d\n",
  2111. __func__, hba->ufshcd_state);
  2112. set_host_byte(cmd, DID_BAD_TARGET);
  2113. cmd->scsi_done(cmd);
  2114. goto out_unlock;
  2115. }
  2116. /* if error handling is in progress, don't issue commands */
  2117. if (ufshcd_eh_in_progress(hba)) {
  2118. set_host_byte(cmd, DID_ERROR);
  2119. cmd->scsi_done(cmd);
  2120. goto out_unlock;
  2121. }
  2122. spin_unlock_irqrestore(hba->host->host_lock, flags);
  2123. hba->req_abort_count = 0;
  2124. /* acquire the tag to make sure device cmds don't use it */
  2125. if (test_and_set_bit_lock(tag, &hba->lrb_in_use)) {
  2126. /*
  2127. * Dev manage command in progress, requeue the command.
  2128. * Requeuing the command helps in cases where the request *may*
  2129. * find different tag instead of waiting for dev manage command
  2130. * completion.
  2131. */
  2132. err = SCSI_MLQUEUE_HOST_BUSY;
  2133. goto out;
  2134. }
  2135. err = ufshcd_hold(hba, true);
  2136. if (err) {
  2137. err = SCSI_MLQUEUE_HOST_BUSY;
  2138. clear_bit_unlock(tag, &hba->lrb_in_use);
  2139. goto out;
  2140. }
  2141. WARN_ON(hba->clk_gating.state != CLKS_ON);
  2142. lrbp = &hba->lrb[tag];
  2143. WARN_ON(lrbp->cmd);
  2144. lrbp->cmd = cmd;
  2145. lrbp->sense_bufflen = UFSHCD_REQ_SENSE_SIZE;
  2146. lrbp->sense_buffer = cmd->sense_buffer;
  2147. lrbp->task_tag = tag;
  2148. lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
  2149. lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba) ? true : false;
  2150. lrbp->req_abort_skip = false;
  2151. ufshcd_comp_scsi_upiu(hba, lrbp);
  2152. err = ufshcd_map_sg(hba, lrbp);
  2153. if (err) {
  2154. lrbp->cmd = NULL;
  2155. clear_bit_unlock(tag, &hba->lrb_in_use);
  2156. goto out;
  2157. }
  2158. /* Make sure descriptors are ready before ringing the doorbell */
  2159. wmb();
  2160. /* issue command to the controller */
  2161. spin_lock_irqsave(hba->host->host_lock, flags);
  2162. ufshcd_vops_setup_xfer_req(hba, tag, (lrbp->cmd ? true : false));
  2163. ufshcd_send_command(hba, tag);
  2164. out_unlock:
  2165. spin_unlock_irqrestore(hba->host->host_lock, flags);
  2166. out:
  2167. up_read(&hba->clk_scaling_lock);
  2168. return err;
  2169. }
  2170. static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
  2171. struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag)
  2172. {
  2173. lrbp->cmd = NULL;
  2174. lrbp->sense_bufflen = 0;
  2175. lrbp->sense_buffer = NULL;
  2176. lrbp->task_tag = tag;
  2177. lrbp->lun = 0; /* device management cmd is not specific to any LUN */
  2178. lrbp->intr_cmd = true; /* No interrupt aggregation */
  2179. hba->dev_cmd.type = cmd_type;
  2180. return ufshcd_comp_devman_upiu(hba, lrbp);
  2181. }
  2182. static int
  2183. ufshcd_clear_cmd(struct ufs_hba *hba, int tag)
  2184. {
  2185. int err = 0;
  2186. unsigned long flags;
  2187. u32 mask = 1 << tag;
  2188. /* clear outstanding transaction before retry */
  2189. spin_lock_irqsave(hba->host->host_lock, flags);
  2190. ufshcd_utrl_clear(hba, tag);
  2191. spin_unlock_irqrestore(hba->host->host_lock, flags);
  2192. /*
  2193. * wait for for h/w to clear corresponding bit in door-bell.
  2194. * max. wait is 1 sec.
  2195. */
  2196. err = ufshcd_wait_for_register(hba,
  2197. REG_UTP_TRANSFER_REQ_DOOR_BELL,
  2198. mask, ~mask, 1000, 1000, true);
  2199. return err;
  2200. }
  2201. static int
  2202. ufshcd_check_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
  2203. {
  2204. struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
  2205. /* Get the UPIU response */
  2206. query_res->response = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr) >>
  2207. UPIU_RSP_CODE_OFFSET;
  2208. return query_res->response;
  2209. }
  2210. /**
  2211. * ufshcd_dev_cmd_completion() - handles device management command responses
  2212. * @hba: per adapter instance
  2213. * @lrbp: pointer to local reference block
  2214. */
  2215. static int
  2216. ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
  2217. {
  2218. int resp;
  2219. int err = 0;
  2220. hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
  2221. resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
  2222. switch (resp) {
  2223. case UPIU_TRANSACTION_NOP_IN:
  2224. if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
  2225. err = -EINVAL;
  2226. dev_err(hba->dev, "%s: unexpected response %x\n",
  2227. __func__, resp);
  2228. }
  2229. break;
  2230. case UPIU_TRANSACTION_QUERY_RSP:
  2231. err = ufshcd_check_query_response(hba, lrbp);
  2232. if (!err)
  2233. err = ufshcd_copy_query_response(hba, lrbp);
  2234. break;
  2235. case UPIU_TRANSACTION_REJECT_UPIU:
  2236. /* TODO: handle Reject UPIU Response */
  2237. err = -EPERM;
  2238. dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
  2239. __func__);
  2240. break;
  2241. default:
  2242. err = -EINVAL;
  2243. dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
  2244. __func__, resp);
  2245. break;
  2246. }
  2247. return err;
  2248. }
  2249. static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
  2250. struct ufshcd_lrb *lrbp, int max_timeout)
  2251. {
  2252. int err = 0;
  2253. unsigned long time_left;
  2254. unsigned long flags;
  2255. time_left = wait_for_completion_timeout(hba->dev_cmd.complete,
  2256. msecs_to_jiffies(max_timeout));
  2257. /* Make sure descriptors are ready before ringing the doorbell */
  2258. wmb();
  2259. spin_lock_irqsave(hba->host->host_lock, flags);
  2260. hba->dev_cmd.complete = NULL;
  2261. if (likely(time_left)) {
  2262. err = ufshcd_get_tr_ocs(lrbp);
  2263. if (!err)
  2264. err = ufshcd_dev_cmd_completion(hba, lrbp);
  2265. }
  2266. spin_unlock_irqrestore(hba->host->host_lock, flags);
  2267. if (!time_left) {
  2268. err = -ETIMEDOUT;
  2269. dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n",
  2270. __func__, lrbp->task_tag);
  2271. if (!ufshcd_clear_cmd(hba, lrbp->task_tag))
  2272. /* successfully cleared the command, retry if needed */
  2273. err = -EAGAIN;
  2274. /*
  2275. * in case of an error, after clearing the doorbell,
  2276. * we also need to clear the outstanding_request
  2277. * field in hba
  2278. */
  2279. ufshcd_outstanding_req_clear(hba, lrbp->task_tag);
  2280. }
  2281. return err;
  2282. }
  2283. /**
  2284. * ufshcd_get_dev_cmd_tag - Get device management command tag
  2285. * @hba: per-adapter instance
  2286. * @tag_out: pointer to variable with available slot value
  2287. *
  2288. * Get a free slot and lock it until device management command
  2289. * completes.
  2290. *
  2291. * Returns false if free slot is unavailable for locking, else
  2292. * return true with tag value in @tag.
  2293. */
  2294. static bool ufshcd_get_dev_cmd_tag(struct ufs_hba *hba, int *tag_out)
  2295. {
  2296. int tag;
  2297. bool ret = false;
  2298. unsigned long tmp;
  2299. if (!tag_out)
  2300. goto out;
  2301. do {
  2302. tmp = ~hba->lrb_in_use;
  2303. tag = find_last_bit(&tmp, hba->nutrs);
  2304. if (tag >= hba->nutrs)
  2305. goto out;
  2306. } while (test_and_set_bit_lock(tag, &hba->lrb_in_use));
  2307. *tag_out = tag;
  2308. ret = true;
  2309. out:
  2310. return ret;
  2311. }
  2312. static inline void ufshcd_put_dev_cmd_tag(struct ufs_hba *hba, int tag)
  2313. {
  2314. clear_bit_unlock(tag, &hba->lrb_in_use);
  2315. }
  2316. /**
  2317. * ufshcd_exec_dev_cmd - API for sending device management requests
  2318. * @hba: UFS hba
  2319. * @cmd_type: specifies the type (NOP, Query...)
  2320. * @timeout: time in seconds
  2321. *
  2322. * NOTE: Since there is only one available tag for device management commands,
  2323. * it is expected you hold the hba->dev_cmd.lock mutex.
  2324. */
  2325. static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
  2326. enum dev_cmd_type cmd_type, int timeout)
  2327. {
  2328. struct ufshcd_lrb *lrbp;
  2329. int err;
  2330. int tag;
  2331. struct completion wait;
  2332. unsigned long flags;
  2333. down_read(&hba->clk_scaling_lock);
  2334. /*
  2335. * Get free slot, sleep if slots are unavailable.
  2336. * Even though we use wait_event() which sleeps indefinitely,
  2337. * the maximum wait time is bounded by SCSI request timeout.
  2338. */
  2339. wait_event(hba->dev_cmd.tag_wq, ufshcd_get_dev_cmd_tag(hba, &tag));
  2340. init_completion(&wait);
  2341. lrbp = &hba->lrb[tag];
  2342. WARN_ON(lrbp->cmd);
  2343. err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag);
  2344. if (unlikely(err))
  2345. goto out_put_tag;
  2346. hba->dev_cmd.complete = &wait;
  2347. ufshcd_add_query_upiu_trace(hba, tag, "query_send");
  2348. /* Make sure descriptors are ready before ringing the doorbell */
  2349. wmb();
  2350. spin_lock_irqsave(hba->host->host_lock, flags);
  2351. ufshcd_vops_setup_xfer_req(hba, tag, (lrbp->cmd ? true : false));
  2352. ufshcd_send_command(hba, tag);
  2353. spin_unlock_irqrestore(hba->host->host_lock, flags);
  2354. err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout);
  2355. ufshcd_add_query_upiu_trace(hba, tag,
  2356. err ? "query_complete_err" : "query_complete");
  2357. out_put_tag:
  2358. ufshcd_put_dev_cmd_tag(hba, tag);
  2359. wake_up(&hba->dev_cmd.tag_wq);
  2360. up_read(&hba->clk_scaling_lock);
  2361. return err;
  2362. }
  2363. /**
  2364. * ufshcd_init_query() - init the query response and request parameters
  2365. * @hba: per-adapter instance
  2366. * @request: address of the request pointer to be initialized
  2367. * @response: address of the response pointer to be initialized
  2368. * @opcode: operation to perform
  2369. * @idn: flag idn to access
  2370. * @index: LU number to access
  2371. * @selector: query/flag/descriptor further identification
  2372. */
  2373. static inline void ufshcd_init_query(struct ufs_hba *hba,
  2374. struct ufs_query_req **request, struct ufs_query_res **response,
  2375. enum query_opcode opcode, u8 idn, u8 index, u8 selector)
  2376. {
  2377. *request = &hba->dev_cmd.query.request;
  2378. *response = &hba->dev_cmd.query.response;
  2379. memset(*request, 0, sizeof(struct ufs_query_req));
  2380. memset(*response, 0, sizeof(struct ufs_query_res));
  2381. (*request)->upiu_req.opcode = opcode;
  2382. (*request)->upiu_req.idn = idn;
  2383. (*request)->upiu_req.index = index;
  2384. (*request)->upiu_req.selector = selector;
  2385. }
  2386. static int ufshcd_query_flag_retry(struct ufs_hba *hba,
  2387. enum query_opcode opcode, enum flag_idn idn, bool *flag_res)
  2388. {
  2389. int ret;
  2390. int retries;
  2391. for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) {
  2392. ret = ufshcd_query_flag(hba, opcode, idn, flag_res);
  2393. if (ret)
  2394. dev_dbg(hba->dev,
  2395. "%s: failed with error %d, retries %d\n",
  2396. __func__, ret, retries);
  2397. else
  2398. break;
  2399. }
  2400. if (ret)
  2401. dev_err(hba->dev,
  2402. "%s: query attribute, opcode %d, idn %d, failed with error %d after %d retires\n",
  2403. __func__, opcode, idn, ret, retries);
  2404. return ret;
  2405. }
  2406. /**
  2407. * ufshcd_query_flag() - API function for sending flag query requests
  2408. * @hba: per-adapter instance
  2409. * @opcode: flag query to perform
  2410. * @idn: flag idn to access
  2411. * @flag_res: the flag value after the query request completes
  2412. *
  2413. * Returns 0 for success, non-zero in case of failure
  2414. */
  2415. int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
  2416. enum flag_idn idn, bool *flag_res)
  2417. {
  2418. struct ufs_query_req *request = NULL;
  2419. struct ufs_query_res *response = NULL;
  2420. int err, index = 0, selector = 0;
  2421. int timeout = QUERY_REQ_TIMEOUT;
  2422. BUG_ON(!hba);
  2423. ufshcd_hold(hba, false);
  2424. mutex_lock(&hba->dev_cmd.lock);
  2425. ufshcd_init_query(hba, &request, &response, opcode, idn, index,
  2426. selector);
  2427. switch (opcode) {
  2428. case UPIU_QUERY_OPCODE_SET_FLAG:
  2429. case UPIU_QUERY_OPCODE_CLEAR_FLAG:
  2430. case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
  2431. request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
  2432. break;
  2433. case UPIU_QUERY_OPCODE_READ_FLAG:
  2434. request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
  2435. if (!flag_res) {
  2436. /* No dummy reads */
  2437. dev_err(hba->dev, "%s: Invalid argument for read request\n",
  2438. __func__);
  2439. err = -EINVAL;
  2440. goto out_unlock;
  2441. }
  2442. break;
  2443. default:
  2444. dev_err(hba->dev,
  2445. "%s: Expected query flag opcode but got = %d\n",
  2446. __func__, opcode);
  2447. err = -EINVAL;
  2448. goto out_unlock;
  2449. }
  2450. err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout);
  2451. if (err) {
  2452. dev_err(hba->dev,
  2453. "%s: Sending flag query for idn %d failed, err = %d\n",
  2454. __func__, idn, err);
  2455. goto out_unlock;
  2456. }
  2457. if (flag_res)
  2458. *flag_res = (be32_to_cpu(response->upiu_res.value) &
  2459. MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
  2460. out_unlock:
  2461. mutex_unlock(&hba->dev_cmd.lock);
  2462. ufshcd_release(hba);
  2463. return err;
  2464. }
  2465. /**
  2466. * ufshcd_query_attr - API function for sending attribute requests
  2467. * @hba: per-adapter instance
  2468. * @opcode: attribute opcode
  2469. * @idn: attribute idn to access
  2470. * @index: index field
  2471. * @selector: selector field
  2472. * @attr_val: the attribute value after the query request completes
  2473. *
  2474. * Returns 0 for success, non-zero in case of failure
  2475. */
  2476. int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
  2477. enum attr_idn idn, u8 index, u8 selector, u32 *attr_val)
  2478. {
  2479. struct ufs_query_req *request = NULL;
  2480. struct ufs_query_res *response = NULL;
  2481. int err;
  2482. BUG_ON(!hba);
  2483. ufshcd_hold(hba, false);
  2484. if (!attr_val) {
  2485. dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n",
  2486. __func__, opcode);
  2487. err = -EINVAL;
  2488. goto out;
  2489. }
  2490. mutex_lock(&hba->dev_cmd.lock);
  2491. ufshcd_init_query(hba, &request, &response, opcode, idn, index,
  2492. selector);
  2493. switch (opcode) {
  2494. case UPIU_QUERY_OPCODE_WRITE_ATTR:
  2495. request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
  2496. request->upiu_req.value = cpu_to_be32(*attr_val);
  2497. break;
  2498. case UPIU_QUERY_OPCODE_READ_ATTR:
  2499. request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
  2500. break;
  2501. default:
  2502. dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n",
  2503. __func__, opcode);
  2504. err = -EINVAL;
  2505. goto out_unlock;
  2506. }
  2507. err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
  2508. if (err) {
  2509. dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
  2510. __func__, opcode, idn, index, err);
  2511. goto out_unlock;
  2512. }
  2513. *attr_val = be32_to_cpu(response->upiu_res.value);
  2514. out_unlock:
  2515. mutex_unlock(&hba->dev_cmd.lock);
  2516. out:
  2517. ufshcd_release(hba);
  2518. return err;
  2519. }
  2520. /**
  2521. * ufshcd_query_attr_retry() - API function for sending query
  2522. * attribute with retries
  2523. * @hba: per-adapter instance
  2524. * @opcode: attribute opcode
  2525. * @idn: attribute idn to access
  2526. * @index: index field
  2527. * @selector: selector field
  2528. * @attr_val: the attribute value after the query request
  2529. * completes
  2530. *
  2531. * Returns 0 for success, non-zero in case of failure
  2532. */
  2533. static int ufshcd_query_attr_retry(struct ufs_hba *hba,
  2534. enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector,
  2535. u32 *attr_val)
  2536. {
  2537. int ret = 0;
  2538. u32 retries;
  2539. for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
  2540. ret = ufshcd_query_attr(hba, opcode, idn, index,
  2541. selector, attr_val);
  2542. if (ret)
  2543. dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n",
  2544. __func__, ret, retries);
  2545. else
  2546. break;
  2547. }
  2548. if (ret)
  2549. dev_err(hba->dev,
  2550. "%s: query attribute, idn %d, failed with error %d after %d retires\n",
  2551. __func__, idn, ret, QUERY_REQ_RETRIES);
  2552. return ret;
  2553. }
  2554. static int __ufshcd_query_descriptor(struct ufs_hba *hba,
  2555. enum query_opcode opcode, enum desc_idn idn, u8 index,
  2556. u8 selector, u8 *desc_buf, int *buf_len)
  2557. {
  2558. struct ufs_query_req *request = NULL;
  2559. struct ufs_query_res *response = NULL;
  2560. int err;
  2561. BUG_ON(!hba);
  2562. ufshcd_hold(hba, false);
  2563. if (!desc_buf) {
  2564. dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
  2565. __func__, opcode);
  2566. err = -EINVAL;
  2567. goto out;
  2568. }
  2569. if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
  2570. dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
  2571. __func__, *buf_len);
  2572. err = -EINVAL;
  2573. goto out;
  2574. }
  2575. mutex_lock(&hba->dev_cmd.lock);
  2576. ufshcd_init_query(hba, &request, &response, opcode, idn, index,
  2577. selector);
  2578. hba->dev_cmd.query.descriptor = desc_buf;
  2579. request->upiu_req.length = cpu_to_be16(*buf_len);
  2580. switch (opcode) {
  2581. case UPIU_QUERY_OPCODE_WRITE_DESC:
  2582. request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
  2583. break;
  2584. case UPIU_QUERY_OPCODE_READ_DESC:
  2585. request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
  2586. break;
  2587. default:
  2588. dev_err(hba->dev,
  2589. "%s: Expected query descriptor opcode but got = 0x%.2x\n",
  2590. __func__, opcode);
  2591. err = -EINVAL;
  2592. goto out_unlock;
  2593. }
  2594. err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
  2595. if (err) {
  2596. dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
  2597. __func__, opcode, idn, index, err);
  2598. goto out_unlock;
  2599. }
  2600. *buf_len = be16_to_cpu(response->upiu_res.length);
  2601. out_unlock:
  2602. hba->dev_cmd.query.descriptor = NULL;
  2603. mutex_unlock(&hba->dev_cmd.lock);
  2604. out:
  2605. ufshcd_release(hba);
  2606. return err;
  2607. }
  2608. /**
  2609. * ufshcd_query_descriptor_retry - API function for sending descriptor requests
  2610. * @hba: per-adapter instance
  2611. * @opcode: attribute opcode
  2612. * @idn: attribute idn to access
  2613. * @index: index field
  2614. * @selector: selector field
  2615. * @desc_buf: the buffer that contains the descriptor
  2616. * @buf_len: length parameter passed to the device
  2617. *
  2618. * Returns 0 for success, non-zero in case of failure.
  2619. * The buf_len parameter will contain, on return, the length parameter
  2620. * received on the response.
  2621. */
  2622. int ufshcd_query_descriptor_retry(struct ufs_hba *hba,
  2623. enum query_opcode opcode,
  2624. enum desc_idn idn, u8 index,
  2625. u8 selector,
  2626. u8 *desc_buf, int *buf_len)
  2627. {
  2628. int err;
  2629. int retries;
  2630. for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
  2631. err = __ufshcd_query_descriptor(hba, opcode, idn, index,
  2632. selector, desc_buf, buf_len);
  2633. if (!err || err == -EINVAL)
  2634. break;
  2635. }
  2636. return err;
  2637. }
  2638. /**
  2639. * ufshcd_read_desc_length - read the specified descriptor length from header
  2640. * @hba: Pointer to adapter instance
  2641. * @desc_id: descriptor idn value
  2642. * @desc_index: descriptor index
  2643. * @desc_length: pointer to variable to read the length of descriptor
  2644. *
  2645. * Return 0 in case of success, non-zero otherwise
  2646. */
  2647. static int ufshcd_read_desc_length(struct ufs_hba *hba,
  2648. enum desc_idn desc_id,
  2649. int desc_index,
  2650. int *desc_length)
  2651. {
  2652. int ret;
  2653. u8 header[QUERY_DESC_HDR_SIZE];
  2654. int header_len = QUERY_DESC_HDR_SIZE;
  2655. if (desc_id >= QUERY_DESC_IDN_MAX)
  2656. return -EINVAL;
  2657. ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
  2658. desc_id, desc_index, 0, header,
  2659. &header_len);
  2660. if (ret) {
  2661. dev_err(hba->dev, "%s: Failed to get descriptor header id %d",
  2662. __func__, desc_id);
  2663. return ret;
  2664. } else if (desc_id != header[QUERY_DESC_DESC_TYPE_OFFSET]) {
  2665. dev_warn(hba->dev, "%s: descriptor header id %d and desc_id %d mismatch",
  2666. __func__, header[QUERY_DESC_DESC_TYPE_OFFSET],
  2667. desc_id);
  2668. ret = -EINVAL;
  2669. }
  2670. *desc_length = header[QUERY_DESC_LENGTH_OFFSET];
  2671. return ret;
  2672. }
  2673. /**
  2674. * ufshcd_map_desc_id_to_length - map descriptor IDN to its length
  2675. * @hba: Pointer to adapter instance
  2676. * @desc_id: descriptor idn value
  2677. * @desc_len: mapped desc length (out)
  2678. *
  2679. * Return 0 in case of success, non-zero otherwise
  2680. */
  2681. int ufshcd_map_desc_id_to_length(struct ufs_hba *hba,
  2682. enum desc_idn desc_id, int *desc_len)
  2683. {
  2684. switch (desc_id) {
  2685. case QUERY_DESC_IDN_DEVICE:
  2686. *desc_len = hba->desc_size.dev_desc;
  2687. break;
  2688. case QUERY_DESC_IDN_POWER:
  2689. *desc_len = hba->desc_size.pwr_desc;
  2690. break;
  2691. case QUERY_DESC_IDN_GEOMETRY:
  2692. *desc_len = hba->desc_size.geom_desc;
  2693. break;
  2694. case QUERY_DESC_IDN_CONFIGURATION:
  2695. *desc_len = hba->desc_size.conf_desc;
  2696. break;
  2697. case QUERY_DESC_IDN_UNIT:
  2698. *desc_len = hba->desc_size.unit_desc;
  2699. break;
  2700. case QUERY_DESC_IDN_INTERCONNECT:
  2701. *desc_len = hba->desc_size.interc_desc;
  2702. break;
  2703. case QUERY_DESC_IDN_STRING:
  2704. *desc_len = QUERY_DESC_MAX_SIZE;
  2705. break;
  2706. case QUERY_DESC_IDN_HEALTH:
  2707. *desc_len = hba->desc_size.hlth_desc;
  2708. break;
  2709. case QUERY_DESC_IDN_RFU_0:
  2710. case QUERY_DESC_IDN_RFU_1:
  2711. *desc_len = 0;
  2712. break;
  2713. default:
  2714. *desc_len = 0;
  2715. return -EINVAL;
  2716. }
  2717. return 0;
  2718. }
  2719. EXPORT_SYMBOL(ufshcd_map_desc_id_to_length);
  2720. /**
  2721. * ufshcd_read_desc_param - read the specified descriptor parameter
  2722. * @hba: Pointer to adapter instance
  2723. * @desc_id: descriptor idn value
  2724. * @desc_index: descriptor index
  2725. * @param_offset: offset of the parameter to read
  2726. * @param_read_buf: pointer to buffer where parameter would be read
  2727. * @param_size: sizeof(param_read_buf)
  2728. *
  2729. * Return 0 in case of success, non-zero otherwise
  2730. */
  2731. int ufshcd_read_desc_param(struct ufs_hba *hba,
  2732. enum desc_idn desc_id,
  2733. int desc_index,
  2734. u8 param_offset,
  2735. u8 *param_read_buf,
  2736. u8 param_size)
  2737. {
  2738. int ret;
  2739. u8 *desc_buf;
  2740. int buff_len;
  2741. bool is_kmalloc = true;
  2742. /* Safety check */
  2743. if (desc_id >= QUERY_DESC_IDN_MAX || !param_size)
  2744. return -EINVAL;
  2745. /* Get the max length of descriptor from structure filled up at probe
  2746. * time.
  2747. */
  2748. ret = ufshcd_map_desc_id_to_length(hba, desc_id, &buff_len);
  2749. /* Sanity checks */
  2750. if (ret || !buff_len) {
  2751. dev_err(hba->dev, "%s: Failed to get full descriptor length",
  2752. __func__);
  2753. return ret;
  2754. }
  2755. /* Check whether we need temp memory */
  2756. if (param_offset != 0 || param_size < buff_len) {
  2757. desc_buf = kmalloc(buff_len, GFP_KERNEL);
  2758. if (!desc_buf)
  2759. return -ENOMEM;
  2760. } else {
  2761. desc_buf = param_read_buf;
  2762. is_kmalloc = false;
  2763. }
  2764. /* Request for full descriptor */
  2765. ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
  2766. desc_id, desc_index, 0,
  2767. desc_buf, &buff_len);
  2768. if (ret) {
  2769. dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d",
  2770. __func__, desc_id, desc_index, param_offset, ret);
  2771. goto out;
  2772. }
  2773. /* Sanity check */
  2774. if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) {
  2775. dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header",
  2776. __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]);
  2777. ret = -EINVAL;
  2778. goto out;
  2779. }
  2780. /* Check wherher we will not copy more data, than available */
  2781. if (is_kmalloc && param_size > buff_len)
  2782. param_size = buff_len;
  2783. if (is_kmalloc)
  2784. memcpy(param_read_buf, &desc_buf[param_offset], param_size);
  2785. out:
  2786. if (is_kmalloc)
  2787. kfree(desc_buf);
  2788. return ret;
  2789. }
  2790. static inline int ufshcd_read_desc(struct ufs_hba *hba,
  2791. enum desc_idn desc_id,
  2792. int desc_index,
  2793. u8 *buf,
  2794. u32 size)
  2795. {
  2796. return ufshcd_read_desc_param(hba, desc_id, desc_index, 0, buf, size);
  2797. }
  2798. static inline int ufshcd_read_power_desc(struct ufs_hba *hba,
  2799. u8 *buf,
  2800. u32 size)
  2801. {
  2802. return ufshcd_read_desc(hba, QUERY_DESC_IDN_POWER, 0, buf, size);
  2803. }
  2804. static int ufshcd_read_device_desc(struct ufs_hba *hba, u8 *buf, u32 size)
  2805. {
  2806. return ufshcd_read_desc(hba, QUERY_DESC_IDN_DEVICE, 0, buf, size);
  2807. }
  2808. /**
  2809. * ufshcd_read_string_desc - read string descriptor
  2810. * @hba: pointer to adapter instance
  2811. * @desc_index: descriptor index
  2812. * @buf: pointer to buffer where descriptor would be read
  2813. * @size: size of buf
  2814. * @ascii: if true convert from unicode to ascii characters
  2815. *
  2816. * Return 0 in case of success, non-zero otherwise
  2817. */
  2818. int ufshcd_read_string_desc(struct ufs_hba *hba, int desc_index,
  2819. u8 *buf, u32 size, bool ascii)
  2820. {
  2821. int err = 0;
  2822. err = ufshcd_read_desc(hba,
  2823. QUERY_DESC_IDN_STRING, desc_index, buf, size);
  2824. if (err) {
  2825. dev_err(hba->dev, "%s: reading String Desc failed after %d retries. err = %d\n",
  2826. __func__, QUERY_REQ_RETRIES, err);
  2827. goto out;
  2828. }
  2829. if (ascii) {
  2830. int desc_len;
  2831. int ascii_len;
  2832. int i;
  2833. char *buff_ascii;
  2834. desc_len = buf[0];
  2835. /* remove header and divide by 2 to move from UTF16 to UTF8 */
  2836. ascii_len = (desc_len - QUERY_DESC_HDR_SIZE) / 2 + 1;
  2837. if (size < ascii_len + QUERY_DESC_HDR_SIZE) {
  2838. dev_err(hba->dev, "%s: buffer allocated size is too small\n",
  2839. __func__);
  2840. err = -ENOMEM;
  2841. goto out;
  2842. }
  2843. buff_ascii = kmalloc(ascii_len, GFP_KERNEL);
  2844. if (!buff_ascii) {
  2845. err = -ENOMEM;
  2846. goto out;
  2847. }
  2848. /*
  2849. * the descriptor contains string in UTF16 format
  2850. * we need to convert to utf-8 so it can be displayed
  2851. */
  2852. utf16s_to_utf8s((wchar_t *)&buf[QUERY_DESC_HDR_SIZE],
  2853. desc_len - QUERY_DESC_HDR_SIZE,
  2854. UTF16_BIG_ENDIAN, buff_ascii, ascii_len);
  2855. /* replace non-printable or non-ASCII characters with spaces */
  2856. for (i = 0; i < ascii_len; i++)
  2857. ufshcd_remove_non_printable(&buff_ascii[i]);
  2858. memset(buf + QUERY_DESC_HDR_SIZE, 0,
  2859. size - QUERY_DESC_HDR_SIZE);
  2860. memcpy(buf + QUERY_DESC_HDR_SIZE, buff_ascii, ascii_len);
  2861. buf[QUERY_DESC_LENGTH_OFFSET] = ascii_len + QUERY_DESC_HDR_SIZE;
  2862. kfree(buff_ascii);
  2863. }
  2864. out:
  2865. return err;
  2866. }
  2867. /**
  2868. * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter
  2869. * @hba: Pointer to adapter instance
  2870. * @lun: lun id
  2871. * @param_offset: offset of the parameter to read
  2872. * @param_read_buf: pointer to buffer where parameter would be read
  2873. * @param_size: sizeof(param_read_buf)
  2874. *
  2875. * Return 0 in case of success, non-zero otherwise
  2876. */
  2877. static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba,
  2878. int lun,
  2879. enum unit_desc_param param_offset,
  2880. u8 *param_read_buf,
  2881. u32 param_size)
  2882. {
  2883. /*
  2884. * Unit descriptors are only available for general purpose LUs (LUN id
  2885. * from 0 to 7) and RPMB Well known LU.
  2886. */
  2887. if (!ufs_is_valid_unit_desc_lun(lun))
  2888. return -EOPNOTSUPP;
  2889. return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun,
  2890. param_offset, param_read_buf, param_size);
  2891. }
  2892. /**
  2893. * ufshcd_memory_alloc - allocate memory for host memory space data structures
  2894. * @hba: per adapter instance
  2895. *
  2896. * 1. Allocate DMA memory for Command Descriptor array
  2897. * Each command descriptor consist of Command UPIU, Response UPIU and PRDT
  2898. * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL).
  2899. * 3. Allocate DMA memory for UTP Task Management Request Descriptor List
  2900. * (UTMRDL)
  2901. * 4. Allocate memory for local reference block(lrb).
  2902. *
  2903. * Returns 0 for success, non-zero in case of failure
  2904. */
  2905. static int ufshcd_memory_alloc(struct ufs_hba *hba)
  2906. {
  2907. size_t utmrdl_size, utrdl_size, ucdl_size;
  2908. /* Allocate memory for UTP command descriptors */
  2909. ucdl_size = (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs);
  2910. hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev,
  2911. ucdl_size,
  2912. &hba->ucdl_dma_addr,
  2913. GFP_KERNEL);
  2914. /*
  2915. * UFSHCI requires UTP command descriptor to be 128 byte aligned.
  2916. * make sure hba->ucdl_dma_addr is aligned to PAGE_SIZE
  2917. * if hba->ucdl_dma_addr is aligned to PAGE_SIZE, then it will
  2918. * be aligned to 128 bytes as well
  2919. */
  2920. if (!hba->ucdl_base_addr ||
  2921. WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) {
  2922. dev_err(hba->dev,
  2923. "Command Descriptor Memory allocation failed\n");
  2924. goto out;
  2925. }
  2926. /*
  2927. * Allocate memory for UTP Transfer descriptors
  2928. * UFSHCI requires 1024 byte alignment of UTRD
  2929. */
  2930. utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
  2931. hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev,
  2932. utrdl_size,
  2933. &hba->utrdl_dma_addr,
  2934. GFP_KERNEL);
  2935. if (!hba->utrdl_base_addr ||
  2936. WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) {
  2937. dev_err(hba->dev,
  2938. "Transfer Descriptor Memory allocation failed\n");
  2939. goto out;
  2940. }
  2941. /*
  2942. * Allocate memory for UTP Task Management descriptors
  2943. * UFSHCI requires 1024 byte alignment of UTMRD
  2944. */
  2945. utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
  2946. hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev,
  2947. utmrdl_size,
  2948. &hba->utmrdl_dma_addr,
  2949. GFP_KERNEL);
  2950. if (!hba->utmrdl_base_addr ||
  2951. WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) {
  2952. dev_err(hba->dev,
  2953. "Task Management Descriptor Memory allocation failed\n");
  2954. goto out;
  2955. }
  2956. /* Allocate memory for local reference block */
  2957. hba->lrb = devm_kcalloc(hba->dev,
  2958. hba->nutrs, sizeof(struct ufshcd_lrb),
  2959. GFP_KERNEL);
  2960. if (!hba->lrb) {
  2961. dev_err(hba->dev, "LRB Memory allocation failed\n");
  2962. goto out;
  2963. }
  2964. return 0;
  2965. out:
  2966. return -ENOMEM;
  2967. }
  2968. /**
  2969. * ufshcd_host_memory_configure - configure local reference block with
  2970. * memory offsets
  2971. * @hba: per adapter instance
  2972. *
  2973. * Configure Host memory space
  2974. * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA
  2975. * address.
  2976. * 2. Update each UTRD with Response UPIU offset, Response UPIU length
  2977. * and PRDT offset.
  2978. * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT
  2979. * into local reference block.
  2980. */
  2981. static void ufshcd_host_memory_configure(struct ufs_hba *hba)
  2982. {
  2983. struct utp_transfer_cmd_desc *cmd_descp;
  2984. struct utp_transfer_req_desc *utrdlp;
  2985. dma_addr_t cmd_desc_dma_addr;
  2986. dma_addr_t cmd_desc_element_addr;
  2987. u16 response_offset;
  2988. u16 prdt_offset;
  2989. int cmd_desc_size;
  2990. int i;
  2991. utrdlp = hba->utrdl_base_addr;
  2992. cmd_descp = hba->ucdl_base_addr;
  2993. response_offset =
  2994. offsetof(struct utp_transfer_cmd_desc, response_upiu);
  2995. prdt_offset =
  2996. offsetof(struct utp_transfer_cmd_desc, prd_table);
  2997. cmd_desc_size = sizeof(struct utp_transfer_cmd_desc);
  2998. cmd_desc_dma_addr = hba->ucdl_dma_addr;
  2999. for (i = 0; i < hba->nutrs; i++) {
  3000. /* Configure UTRD with command descriptor base address */
  3001. cmd_desc_element_addr =
  3002. (cmd_desc_dma_addr + (cmd_desc_size * i));
  3003. utrdlp[i].command_desc_base_addr_lo =
  3004. cpu_to_le32(lower_32_bits(cmd_desc_element_addr));
  3005. utrdlp[i].command_desc_base_addr_hi =
  3006. cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
  3007. /* Response upiu and prdt offset should be in double words */
  3008. if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) {
  3009. utrdlp[i].response_upiu_offset =
  3010. cpu_to_le16(response_offset);
  3011. utrdlp[i].prd_table_offset =
  3012. cpu_to_le16(prdt_offset);
  3013. utrdlp[i].response_upiu_length =
  3014. cpu_to_le16(ALIGNED_UPIU_SIZE);
  3015. } else {
  3016. utrdlp[i].response_upiu_offset =
  3017. cpu_to_le16((response_offset >> 2));
  3018. utrdlp[i].prd_table_offset =
  3019. cpu_to_le16((prdt_offset >> 2));
  3020. utrdlp[i].response_upiu_length =
  3021. cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
  3022. }
  3023. hba->lrb[i].utr_descriptor_ptr = (utrdlp + i);
  3024. hba->lrb[i].utrd_dma_addr = hba->utrdl_dma_addr +
  3025. (i * sizeof(struct utp_transfer_req_desc));
  3026. hba->lrb[i].ucd_req_ptr =
  3027. (struct utp_upiu_req *)(cmd_descp + i);
  3028. hba->lrb[i].ucd_req_dma_addr = cmd_desc_element_addr;
  3029. hba->lrb[i].ucd_rsp_ptr =
  3030. (struct utp_upiu_rsp *)cmd_descp[i].response_upiu;
  3031. hba->lrb[i].ucd_rsp_dma_addr = cmd_desc_element_addr +
  3032. response_offset;
  3033. hba->lrb[i].ucd_prdt_ptr =
  3034. (struct ufshcd_sg_entry *)cmd_descp[i].prd_table;
  3035. hba->lrb[i].ucd_prdt_dma_addr = cmd_desc_element_addr +
  3036. prdt_offset;
  3037. }
  3038. }
  3039. /**
  3040. * ufshcd_dme_link_startup - Notify Unipro to perform link startup
  3041. * @hba: per adapter instance
  3042. *
  3043. * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer,
  3044. * in order to initialize the Unipro link startup procedure.
  3045. * Once the Unipro links are up, the device connected to the controller
  3046. * is detected.
  3047. *
  3048. * Returns 0 on success, non-zero value on failure
  3049. */
  3050. static int ufshcd_dme_link_startup(struct ufs_hba *hba)
  3051. {
  3052. struct uic_command uic_cmd = {0};
  3053. int ret;
  3054. uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
  3055. ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
  3056. if (ret)
  3057. dev_dbg(hba->dev,
  3058. "dme-link-startup: error code %d\n", ret);
  3059. return ret;
  3060. }
  3061. /**
  3062. * ufshcd_dme_reset - UIC command for DME_RESET
  3063. * @hba: per adapter instance
  3064. *
  3065. * DME_RESET command is issued in order to reset UniPro stack.
  3066. * This function now deal with cold reset.
  3067. *
  3068. * Returns 0 on success, non-zero value on failure
  3069. */
  3070. static int ufshcd_dme_reset(struct ufs_hba *hba)
  3071. {
  3072. struct uic_command uic_cmd = {0};
  3073. int ret;
  3074. uic_cmd.command = UIC_CMD_DME_RESET;
  3075. ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
  3076. if (ret)
  3077. dev_err(hba->dev,
  3078. "dme-reset: error code %d\n", ret);
  3079. return ret;
  3080. }
  3081. /**
  3082. * ufshcd_dme_enable - UIC command for DME_ENABLE
  3083. * @hba: per adapter instance
  3084. *
  3085. * DME_ENABLE command is issued in order to enable UniPro stack.
  3086. *
  3087. * Returns 0 on success, non-zero value on failure
  3088. */
  3089. static int ufshcd_dme_enable(struct ufs_hba *hba)
  3090. {
  3091. struct uic_command uic_cmd = {0};
  3092. int ret;
  3093. uic_cmd.command = UIC_CMD_DME_ENABLE;
  3094. ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
  3095. if (ret)
  3096. dev_err(hba->dev,
  3097. "dme-reset: error code %d\n", ret);
  3098. return ret;
  3099. }
  3100. static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
  3101. {
  3102. #define MIN_DELAY_BEFORE_DME_CMDS_US 1000
  3103. unsigned long min_sleep_time_us;
  3104. if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS))
  3105. return;
  3106. /*
  3107. * last_dme_cmd_tstamp will be 0 only for 1st call to
  3108. * this function
  3109. */
  3110. if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) {
  3111. min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US;
  3112. } else {
  3113. unsigned long delta =
  3114. (unsigned long) ktime_to_us(
  3115. ktime_sub(ktime_get(),
  3116. hba->last_dme_cmd_tstamp));
  3117. if (delta < MIN_DELAY_BEFORE_DME_CMDS_US)
  3118. min_sleep_time_us =
  3119. MIN_DELAY_BEFORE_DME_CMDS_US - delta;
  3120. else
  3121. return; /* no more delay required */
  3122. }
  3123. /* allow sleep for extra 50us if needed */
  3124. usleep_range(min_sleep_time_us, min_sleep_time_us + 50);
  3125. }
  3126. /**
  3127. * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
  3128. * @hba: per adapter instance
  3129. * @attr_sel: uic command argument1
  3130. * @attr_set: attribute set type as uic command argument2
  3131. * @mib_val: setting value as uic command argument3
  3132. * @peer: indicate whether peer or local
  3133. *
  3134. * Returns 0 on success, non-zero value on failure
  3135. */
  3136. int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
  3137. u8 attr_set, u32 mib_val, u8 peer)
  3138. {
  3139. struct uic_command uic_cmd = {0};
  3140. static const char *const action[] = {
  3141. "dme-set",
  3142. "dme-peer-set"
  3143. };
  3144. const char *set = action[!!peer];
  3145. int ret;
  3146. int retries = UFS_UIC_COMMAND_RETRIES;
  3147. uic_cmd.command = peer ?
  3148. UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
  3149. uic_cmd.argument1 = attr_sel;
  3150. uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
  3151. uic_cmd.argument3 = mib_val;
  3152. do {
  3153. /* for peer attributes we retry upon failure */
  3154. ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
  3155. if (ret)
  3156. dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
  3157. set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
  3158. } while (ret && peer && --retries);
  3159. if (ret)
  3160. dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n",
  3161. set, UIC_GET_ATTR_ID(attr_sel), mib_val,
  3162. UFS_UIC_COMMAND_RETRIES - retries);
  3163. return ret;
  3164. }
  3165. EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr);
  3166. /**
  3167. * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
  3168. * @hba: per adapter instance
  3169. * @attr_sel: uic command argument1
  3170. * @mib_val: the value of the attribute as returned by the UIC command
  3171. * @peer: indicate whether peer or local
  3172. *
  3173. * Returns 0 on success, non-zero value on failure
  3174. */
  3175. int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
  3176. u32 *mib_val, u8 peer)
  3177. {
  3178. struct uic_command uic_cmd = {0};
  3179. static const char *const action[] = {
  3180. "dme-get",
  3181. "dme-peer-get"
  3182. };
  3183. const char *get = action[!!peer];
  3184. int ret;
  3185. int retries = UFS_UIC_COMMAND_RETRIES;
  3186. struct ufs_pa_layer_attr orig_pwr_info;
  3187. struct ufs_pa_layer_attr temp_pwr_info;
  3188. bool pwr_mode_change = false;
  3189. if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) {
  3190. orig_pwr_info = hba->pwr_info;
  3191. temp_pwr_info = orig_pwr_info;
  3192. if (orig_pwr_info.pwr_tx == FAST_MODE ||
  3193. orig_pwr_info.pwr_rx == FAST_MODE) {
  3194. temp_pwr_info.pwr_tx = FASTAUTO_MODE;
  3195. temp_pwr_info.pwr_rx = FASTAUTO_MODE;
  3196. pwr_mode_change = true;
  3197. } else if (orig_pwr_info.pwr_tx == SLOW_MODE ||
  3198. orig_pwr_info.pwr_rx == SLOW_MODE) {
  3199. temp_pwr_info.pwr_tx = SLOWAUTO_MODE;
  3200. temp_pwr_info.pwr_rx = SLOWAUTO_MODE;
  3201. pwr_mode_change = true;
  3202. }
  3203. if (pwr_mode_change) {
  3204. ret = ufshcd_change_power_mode(hba, &temp_pwr_info);
  3205. if (ret)
  3206. goto out;
  3207. }
  3208. }
  3209. uic_cmd.command = peer ?
  3210. UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
  3211. uic_cmd.argument1 = attr_sel;
  3212. do {
  3213. /* for peer attributes we retry upon failure */
  3214. ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
  3215. if (ret)
  3216. dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n",
  3217. get, UIC_GET_ATTR_ID(attr_sel), ret);
  3218. } while (ret && peer && --retries);
  3219. if (ret)
  3220. dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n",
  3221. get, UIC_GET_ATTR_ID(attr_sel),
  3222. UFS_UIC_COMMAND_RETRIES - retries);
  3223. if (mib_val && !ret)
  3224. *mib_val = uic_cmd.argument3;
  3225. if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)
  3226. && pwr_mode_change)
  3227. ufshcd_change_power_mode(hba, &orig_pwr_info);
  3228. out:
  3229. return ret;
  3230. }
  3231. EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
  3232. /**
  3233. * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
  3234. * state) and waits for it to take effect.
  3235. *
  3236. * @hba: per adapter instance
  3237. * @cmd: UIC command to execute
  3238. *
  3239. * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER &
  3240. * DME_HIBERNATE_EXIT commands take some time to take its effect on both host
  3241. * and device UniPro link and hence it's final completion would be indicated by
  3242. * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in
  3243. * addition to normal UIC command completion Status (UCCS). This function only
  3244. * returns after the relevant status bits indicate the completion.
  3245. *
  3246. * Returns 0 on success, non-zero value on failure
  3247. */
  3248. static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
  3249. {
  3250. struct completion uic_async_done;
  3251. unsigned long flags;
  3252. u8 status;
  3253. int ret;
  3254. bool reenable_intr = false;
  3255. mutex_lock(&hba->uic_cmd_mutex);
  3256. init_completion(&uic_async_done);
  3257. ufshcd_add_delay_before_dme_cmd(hba);
  3258. spin_lock_irqsave(hba->host->host_lock, flags);
  3259. hba->uic_async_done = &uic_async_done;
  3260. if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) {
  3261. ufshcd_disable_intr(hba, UIC_COMMAND_COMPL);
  3262. /*
  3263. * Make sure UIC command completion interrupt is disabled before
  3264. * issuing UIC command.
  3265. */
  3266. wmb();
  3267. reenable_intr = true;
  3268. }
  3269. ret = __ufshcd_send_uic_cmd(hba, cmd, false);
  3270. spin_unlock_irqrestore(hba->host->host_lock, flags);
  3271. if (ret) {
  3272. dev_err(hba->dev,
  3273. "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
  3274. cmd->command, cmd->argument3, ret);
  3275. goto out;
  3276. }
  3277. if (!wait_for_completion_timeout(hba->uic_async_done,
  3278. msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
  3279. dev_err(hba->dev,
  3280. "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n",
  3281. cmd->command, cmd->argument3);
  3282. ret = -ETIMEDOUT;
  3283. goto out;
  3284. }
  3285. status = ufshcd_get_upmcrs(hba);
  3286. if (status != PWR_LOCAL) {
  3287. dev_err(hba->dev,
  3288. "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n",
  3289. cmd->command, status);
  3290. ret = (status != PWR_OK) ? status : -1;
  3291. }
  3292. out:
  3293. if (ret) {
  3294. ufshcd_print_host_state(hba);
  3295. ufshcd_print_pwr_info(hba);
  3296. ufshcd_print_host_regs(hba);
  3297. }
  3298. spin_lock_irqsave(hba->host->host_lock, flags);
  3299. hba->active_uic_cmd = NULL;
  3300. hba->uic_async_done = NULL;
  3301. if (reenable_intr)
  3302. ufshcd_enable_intr(hba, UIC_COMMAND_COMPL);
  3303. spin_unlock_irqrestore(hba->host->host_lock, flags);
  3304. mutex_unlock(&hba->uic_cmd_mutex);
  3305. return ret;
  3306. }
  3307. /**
  3308. * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage
  3309. * using DME_SET primitives.
  3310. * @hba: per adapter instance
  3311. * @mode: powr mode value
  3312. *
  3313. * Returns 0 on success, non-zero value on failure
  3314. */
  3315. static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
  3316. {
  3317. struct uic_command uic_cmd = {0};
  3318. int ret;
  3319. if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) {
  3320. ret = ufshcd_dme_set(hba,
  3321. UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1);
  3322. if (ret) {
  3323. dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n",
  3324. __func__, ret);
  3325. goto out;
  3326. }
  3327. }
  3328. uic_cmd.command = UIC_CMD_DME_SET;
  3329. uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
  3330. uic_cmd.argument3 = mode;
  3331. ufshcd_hold(hba, false);
  3332. ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
  3333. ufshcd_release(hba);
  3334. out:
  3335. return ret;
  3336. }
  3337. static int ufshcd_link_recovery(struct ufs_hba *hba)
  3338. {
  3339. int ret;
  3340. unsigned long flags;
  3341. spin_lock_irqsave(hba->host->host_lock, flags);
  3342. hba->ufshcd_state = UFSHCD_STATE_RESET;
  3343. ufshcd_set_eh_in_progress(hba);
  3344. spin_unlock_irqrestore(hba->host->host_lock, flags);
  3345. ret = ufshcd_host_reset_and_restore(hba);
  3346. spin_lock_irqsave(hba->host->host_lock, flags);
  3347. if (ret)
  3348. hba->ufshcd_state = UFSHCD_STATE_ERROR;
  3349. ufshcd_clear_eh_in_progress(hba);
  3350. spin_unlock_irqrestore(hba->host->host_lock, flags);
  3351. if (ret)
  3352. dev_err(hba->dev, "%s: link recovery failed, err %d",
  3353. __func__, ret);
  3354. return ret;
  3355. }
  3356. static int __ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
  3357. {
  3358. int ret;
  3359. struct uic_command uic_cmd = {0};
  3360. ktime_t start = ktime_get();
  3361. ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, PRE_CHANGE);
  3362. uic_cmd.command = UIC_CMD_DME_HIBER_ENTER;
  3363. ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
  3364. trace_ufshcd_profile_hibern8(dev_name(hba->dev), "enter",
  3365. ktime_to_us(ktime_sub(ktime_get(), start)), ret);
  3366. if (ret) {
  3367. int err;
  3368. dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n",
  3369. __func__, ret);
  3370. /*
  3371. * If link recovery fails then return error code returned from
  3372. * ufshcd_link_recovery().
  3373. * If link recovery succeeds then return -EAGAIN to attempt
  3374. * hibern8 enter retry again.
  3375. */
  3376. err = ufshcd_link_recovery(hba);
  3377. if (err) {
  3378. dev_err(hba->dev, "%s: link recovery failed", __func__);
  3379. ret = err;
  3380. } else {
  3381. ret = -EAGAIN;
  3382. }
  3383. } else
  3384. ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER,
  3385. POST_CHANGE);
  3386. return ret;
  3387. }
  3388. static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
  3389. {
  3390. int ret = 0, retries;
  3391. for (retries = UIC_HIBERN8_ENTER_RETRIES; retries > 0; retries--) {
  3392. ret = __ufshcd_uic_hibern8_enter(hba);
  3393. if (!ret)
  3394. goto out;
  3395. }
  3396. out:
  3397. return ret;
  3398. }
  3399. static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
  3400. {
  3401. struct uic_command uic_cmd = {0};
  3402. int ret;
  3403. ktime_t start = ktime_get();
  3404. ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE);
  3405. uic_cmd.command = UIC_CMD_DME_HIBER_EXIT;
  3406. ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
  3407. trace_ufshcd_profile_hibern8(dev_name(hba->dev), "exit",
  3408. ktime_to_us(ktime_sub(ktime_get(), start)), ret);
  3409. if (ret) {
  3410. dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n",
  3411. __func__, ret);
  3412. ret = ufshcd_link_recovery(hba);
  3413. } else {
  3414. ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT,
  3415. POST_CHANGE);
  3416. hba->ufs_stats.last_hibern8_exit_tstamp = ktime_get();
  3417. hba->ufs_stats.hibern8_exit_cnt++;
  3418. }
  3419. return ret;
  3420. }
  3421. static void ufshcd_auto_hibern8_enable(struct ufs_hba *hba)
  3422. {
  3423. unsigned long flags;
  3424. if (!(hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT) || !hba->ahit)
  3425. return;
  3426. spin_lock_irqsave(hba->host->host_lock, flags);
  3427. ufshcd_writel(hba, hba->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER);
  3428. spin_unlock_irqrestore(hba->host->host_lock, flags);
  3429. }
  3430. /**
  3431. * ufshcd_init_pwr_info - setting the POR (power on reset)
  3432. * values in hba power info
  3433. * @hba: per-adapter instance
  3434. */
  3435. static void ufshcd_init_pwr_info(struct ufs_hba *hba)
  3436. {
  3437. hba->pwr_info.gear_rx = UFS_PWM_G1;
  3438. hba->pwr_info.gear_tx = UFS_PWM_G1;
  3439. hba->pwr_info.lane_rx = 1;
  3440. hba->pwr_info.lane_tx = 1;
  3441. hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
  3442. hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
  3443. hba->pwr_info.hs_rate = 0;
  3444. }
  3445. /**
  3446. * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
  3447. * @hba: per-adapter instance
  3448. */
  3449. static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
  3450. {
  3451. struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
  3452. if (hba->max_pwr_info.is_valid)
  3453. return 0;
  3454. pwr_info->pwr_tx = FAST_MODE;
  3455. pwr_info->pwr_rx = FAST_MODE;
  3456. pwr_info->hs_rate = PA_HS_MODE_B;
  3457. /* Get the connected lane count */
  3458. ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
  3459. &pwr_info->lane_rx);
  3460. ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
  3461. &pwr_info->lane_tx);
  3462. if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
  3463. dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
  3464. __func__,
  3465. pwr_info->lane_rx,
  3466. pwr_info->lane_tx);
  3467. return -EINVAL;
  3468. }
  3469. /*
  3470. * First, get the maximum gears of HS speed.
  3471. * If a zero value, it means there is no HSGEAR capability.
  3472. * Then, get the maximum gears of PWM speed.
  3473. */
  3474. ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
  3475. if (!pwr_info->gear_rx) {
  3476. ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
  3477. &pwr_info->gear_rx);
  3478. if (!pwr_info->gear_rx) {
  3479. dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
  3480. __func__, pwr_info->gear_rx);
  3481. return -EINVAL;
  3482. }
  3483. pwr_info->pwr_rx = SLOW_MODE;
  3484. }
  3485. ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
  3486. &pwr_info->gear_tx);
  3487. if (!pwr_info->gear_tx) {
  3488. ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
  3489. &pwr_info->gear_tx);
  3490. if (!pwr_info->gear_tx) {
  3491. dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
  3492. __func__, pwr_info->gear_tx);
  3493. return -EINVAL;
  3494. }
  3495. pwr_info->pwr_tx = SLOW_MODE;
  3496. }
  3497. hba->max_pwr_info.is_valid = true;
  3498. return 0;
  3499. }
  3500. static int ufshcd_change_power_mode(struct ufs_hba *hba,
  3501. struct ufs_pa_layer_attr *pwr_mode)
  3502. {
  3503. int ret;
  3504. /* if already configured to the requested pwr_mode */
  3505. if (pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
  3506. pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
  3507. pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
  3508. pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
  3509. pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
  3510. pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
  3511. pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
  3512. dev_dbg(hba->dev, "%s: power already configured\n", __func__);
  3513. return 0;
  3514. }
  3515. /*
  3516. * Configure attributes for power mode change with below.
  3517. * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
  3518. * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
  3519. * - PA_HSSERIES
  3520. */
  3521. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
  3522. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
  3523. pwr_mode->lane_rx);
  3524. if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
  3525. pwr_mode->pwr_rx == FAST_MODE)
  3526. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE);
  3527. else
  3528. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE);
  3529. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
  3530. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
  3531. pwr_mode->lane_tx);
  3532. if (pwr_mode->pwr_tx == FASTAUTO_MODE ||
  3533. pwr_mode->pwr_tx == FAST_MODE)
  3534. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE);
  3535. else
  3536. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE);
  3537. if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
  3538. pwr_mode->pwr_tx == FASTAUTO_MODE ||
  3539. pwr_mode->pwr_rx == FAST_MODE ||
  3540. pwr_mode->pwr_tx == FAST_MODE)
  3541. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
  3542. pwr_mode->hs_rate);
  3543. ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
  3544. | pwr_mode->pwr_tx);
  3545. if (ret) {
  3546. dev_err(hba->dev,
  3547. "%s: power mode change failed %d\n", __func__, ret);
  3548. } else {
  3549. ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL,
  3550. pwr_mode);
  3551. memcpy(&hba->pwr_info, pwr_mode,
  3552. sizeof(struct ufs_pa_layer_attr));
  3553. }
  3554. return ret;
  3555. }
  3556. /**
  3557. * ufshcd_config_pwr_mode - configure a new power mode
  3558. * @hba: per-adapter instance
  3559. * @desired_pwr_mode: desired power configuration
  3560. */
  3561. int ufshcd_config_pwr_mode(struct ufs_hba *hba,
  3562. struct ufs_pa_layer_attr *desired_pwr_mode)
  3563. {
  3564. struct ufs_pa_layer_attr final_params = { 0 };
  3565. int ret;
  3566. ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE,
  3567. desired_pwr_mode, &final_params);
  3568. if (ret)
  3569. memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
  3570. ret = ufshcd_change_power_mode(hba, &final_params);
  3571. if (!ret)
  3572. ufshcd_print_pwr_info(hba);
  3573. return ret;
  3574. }
  3575. EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode);
  3576. /**
  3577. * ufshcd_complete_dev_init() - checks device readiness
  3578. * @hba: per-adapter instance
  3579. *
  3580. * Set fDeviceInit flag and poll until device toggles it.
  3581. */
  3582. static int ufshcd_complete_dev_init(struct ufs_hba *hba)
  3583. {
  3584. int i;
  3585. int err;
  3586. bool flag_res = 1;
  3587. err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
  3588. QUERY_FLAG_IDN_FDEVICEINIT, NULL);
  3589. if (err) {
  3590. dev_err(hba->dev,
  3591. "%s setting fDeviceInit flag failed with error %d\n",
  3592. __func__, err);
  3593. goto out;
  3594. }
  3595. /* poll for max. 1000 iterations for fDeviceInit flag to clear */
  3596. for (i = 0; i < 1000 && !err && flag_res; i++)
  3597. err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
  3598. QUERY_FLAG_IDN_FDEVICEINIT, &flag_res);
  3599. if (err)
  3600. dev_err(hba->dev,
  3601. "%s reading fDeviceInit flag failed with error %d\n",
  3602. __func__, err);
  3603. else if (flag_res)
  3604. dev_err(hba->dev,
  3605. "%s fDeviceInit was not cleared by the device\n",
  3606. __func__);
  3607. out:
  3608. return err;
  3609. }
  3610. /**
  3611. * ufshcd_make_hba_operational - Make UFS controller operational
  3612. * @hba: per adapter instance
  3613. *
  3614. * To bring UFS host controller to operational state,
  3615. * 1. Enable required interrupts
  3616. * 2. Configure interrupt aggregation
  3617. * 3. Program UTRL and UTMRL base address
  3618. * 4. Configure run-stop-registers
  3619. *
  3620. * Returns 0 on success, non-zero value on failure
  3621. */
  3622. static int ufshcd_make_hba_operational(struct ufs_hba *hba)
  3623. {
  3624. int err = 0;
  3625. u32 reg;
  3626. /* Enable required interrupts */
  3627. ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
  3628. /* Configure interrupt aggregation */
  3629. if (ufshcd_is_intr_aggr_allowed(hba))
  3630. ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO);
  3631. else
  3632. ufshcd_disable_intr_aggr(hba);
  3633. /* Configure UTRL and UTMRL base address registers */
  3634. ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
  3635. REG_UTP_TRANSFER_REQ_LIST_BASE_L);
  3636. ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
  3637. REG_UTP_TRANSFER_REQ_LIST_BASE_H);
  3638. ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
  3639. REG_UTP_TASK_REQ_LIST_BASE_L);
  3640. ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
  3641. REG_UTP_TASK_REQ_LIST_BASE_H);
  3642. /*
  3643. * Make sure base address and interrupt setup are updated before
  3644. * enabling the run/stop registers below.
  3645. */
  3646. wmb();
  3647. /*
  3648. * UCRDY, UTMRLDY and UTRLRDY bits must be 1
  3649. */
  3650. reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
  3651. if (!(ufshcd_get_lists_status(reg))) {
  3652. ufshcd_enable_run_stop_reg(hba);
  3653. } else {
  3654. dev_err(hba->dev,
  3655. "Host controller not ready to process requests");
  3656. err = -EIO;
  3657. goto out;
  3658. }
  3659. out:
  3660. return err;
  3661. }
  3662. /**
  3663. * ufshcd_hba_stop - Send controller to reset state
  3664. * @hba: per adapter instance
  3665. * @can_sleep: perform sleep or just spin
  3666. */
  3667. static inline void ufshcd_hba_stop(struct ufs_hba *hba, bool can_sleep)
  3668. {
  3669. int err;
  3670. ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE);
  3671. err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE,
  3672. CONTROLLER_ENABLE, CONTROLLER_DISABLE,
  3673. 10, 1, can_sleep);
  3674. if (err)
  3675. dev_err(hba->dev, "%s: Controller disable failed\n", __func__);
  3676. }
  3677. /**
  3678. * ufshcd_hba_execute_hce - initialize the controller
  3679. * @hba: per adapter instance
  3680. *
  3681. * The controller resets itself and controller firmware initialization
  3682. * sequence kicks off. When controller is ready it will set
  3683. * the Host Controller Enable bit to 1.
  3684. *
  3685. * Returns 0 on success, non-zero value on failure
  3686. */
  3687. static int ufshcd_hba_execute_hce(struct ufs_hba *hba)
  3688. {
  3689. int retry;
  3690. /*
  3691. * msleep of 1 and 5 used in this function might result in msleep(20),
  3692. * but it was necessary to send the UFS FPGA to reset mode during
  3693. * development and testing of this driver. msleep can be changed to
  3694. * mdelay and retry count can be reduced based on the controller.
  3695. */
  3696. if (!ufshcd_is_hba_active(hba))
  3697. /* change controller state to "reset state" */
  3698. ufshcd_hba_stop(hba, true);
  3699. /* UniPro link is disabled at this point */
  3700. ufshcd_set_link_off(hba);
  3701. ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
  3702. /* start controller initialization sequence */
  3703. ufshcd_hba_start(hba);
  3704. /*
  3705. * To initialize a UFS host controller HCE bit must be set to 1.
  3706. * During initialization the HCE bit value changes from 1->0->1.
  3707. * When the host controller completes initialization sequence
  3708. * it sets the value of HCE bit to 1. The same HCE bit is read back
  3709. * to check if the controller has completed initialization sequence.
  3710. * So without this delay the value HCE = 1, set in the previous
  3711. * instruction might be read back.
  3712. * This delay can be changed based on the controller.
  3713. */
  3714. msleep(1);
  3715. /* wait for the host controller to complete initialization */
  3716. retry = 10;
  3717. while (ufshcd_is_hba_active(hba)) {
  3718. if (retry) {
  3719. retry--;
  3720. } else {
  3721. dev_err(hba->dev,
  3722. "Controller enable failed\n");
  3723. return -EIO;
  3724. }
  3725. msleep(5);
  3726. }
  3727. /* enable UIC related interrupts */
  3728. ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
  3729. ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
  3730. return 0;
  3731. }
  3732. static int ufshcd_hba_enable(struct ufs_hba *hba)
  3733. {
  3734. int ret;
  3735. if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) {
  3736. ufshcd_set_link_off(hba);
  3737. ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
  3738. /* enable UIC related interrupts */
  3739. ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
  3740. ret = ufshcd_dme_reset(hba);
  3741. if (!ret) {
  3742. ret = ufshcd_dme_enable(hba);
  3743. if (!ret)
  3744. ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
  3745. if (ret)
  3746. dev_err(hba->dev,
  3747. "Host controller enable failed with non-hce\n");
  3748. }
  3749. } else {
  3750. ret = ufshcd_hba_execute_hce(hba);
  3751. }
  3752. return ret;
  3753. }
  3754. static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
  3755. {
  3756. int tx_lanes, i, err = 0;
  3757. if (!peer)
  3758. ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
  3759. &tx_lanes);
  3760. else
  3761. ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
  3762. &tx_lanes);
  3763. for (i = 0; i < tx_lanes; i++) {
  3764. if (!peer)
  3765. err = ufshcd_dme_set(hba,
  3766. UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
  3767. UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
  3768. 0);
  3769. else
  3770. err = ufshcd_dme_peer_set(hba,
  3771. UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
  3772. UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
  3773. 0);
  3774. if (err) {
  3775. dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
  3776. __func__, peer, i, err);
  3777. break;
  3778. }
  3779. }
  3780. return err;
  3781. }
  3782. static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba)
  3783. {
  3784. return ufshcd_disable_tx_lcc(hba, true);
  3785. }
  3786. /**
  3787. * ufshcd_link_startup - Initialize unipro link startup
  3788. * @hba: per adapter instance
  3789. *
  3790. * Returns 0 for success, non-zero in case of failure
  3791. */
  3792. static int ufshcd_link_startup(struct ufs_hba *hba)
  3793. {
  3794. int ret;
  3795. int retries = DME_LINKSTARTUP_RETRIES;
  3796. bool link_startup_again = false;
  3797. /*
  3798. * If UFS device isn't active then we will have to issue link startup
  3799. * 2 times to make sure the device state move to active.
  3800. */
  3801. if (!ufshcd_is_ufs_dev_active(hba))
  3802. link_startup_again = true;
  3803. link_startup:
  3804. do {
  3805. ufshcd_vops_link_startup_notify(hba, PRE_CHANGE);
  3806. ret = ufshcd_dme_link_startup(hba);
  3807. /* check if device is detected by inter-connect layer */
  3808. if (!ret && !ufshcd_is_device_present(hba)) {
  3809. dev_err(hba->dev, "%s: Device not present\n", __func__);
  3810. ret = -ENXIO;
  3811. goto out;
  3812. }
  3813. /*
  3814. * DME link lost indication is only received when link is up,
  3815. * but we can't be sure if the link is up until link startup
  3816. * succeeds. So reset the local Uni-Pro and try again.
  3817. */
  3818. if (ret && ufshcd_hba_enable(hba))
  3819. goto out;
  3820. } while (ret && retries--);
  3821. if (ret)
  3822. /* failed to get the link up... retire */
  3823. goto out;
  3824. if (link_startup_again) {
  3825. link_startup_again = false;
  3826. retries = DME_LINKSTARTUP_RETRIES;
  3827. goto link_startup;
  3828. }
  3829. /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */
  3830. ufshcd_init_pwr_info(hba);
  3831. ufshcd_print_pwr_info(hba);
  3832. if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) {
  3833. ret = ufshcd_disable_device_tx_lcc(hba);
  3834. if (ret)
  3835. goto out;
  3836. }
  3837. /* Include any host controller configuration via UIC commands */
  3838. ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE);
  3839. if (ret)
  3840. goto out;
  3841. ret = ufshcd_make_hba_operational(hba);
  3842. out:
  3843. if (ret) {
  3844. dev_err(hba->dev, "link startup failed %d\n", ret);
  3845. ufshcd_print_host_state(hba);
  3846. ufshcd_print_pwr_info(hba);
  3847. ufshcd_print_host_regs(hba);
  3848. }
  3849. return ret;
  3850. }
  3851. /**
  3852. * ufshcd_verify_dev_init() - Verify device initialization
  3853. * @hba: per-adapter instance
  3854. *
  3855. * Send NOP OUT UPIU and wait for NOP IN response to check whether the
  3856. * device Transport Protocol (UTP) layer is ready after a reset.
  3857. * If the UTP layer at the device side is not initialized, it may
  3858. * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT
  3859. * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations.
  3860. */
  3861. static int ufshcd_verify_dev_init(struct ufs_hba *hba)
  3862. {
  3863. int err = 0;
  3864. int retries;
  3865. ufshcd_hold(hba, false);
  3866. mutex_lock(&hba->dev_cmd.lock);
  3867. for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
  3868. err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
  3869. NOP_OUT_TIMEOUT);
  3870. if (!err || err == -ETIMEDOUT)
  3871. break;
  3872. dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
  3873. }
  3874. mutex_unlock(&hba->dev_cmd.lock);
  3875. ufshcd_release(hba);
  3876. if (err)
  3877. dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
  3878. return err;
  3879. }
  3880. /**
  3881. * ufshcd_set_queue_depth - set lun queue depth
  3882. * @sdev: pointer to SCSI device
  3883. *
  3884. * Read bLUQueueDepth value and activate scsi tagged command
  3885. * queueing. For WLUN, queue depth is set to 1. For best-effort
  3886. * cases (bLUQueueDepth = 0) the queue depth is set to a maximum
  3887. * value that host can queue.
  3888. */
  3889. static void ufshcd_set_queue_depth(struct scsi_device *sdev)
  3890. {
  3891. int ret = 0;
  3892. u8 lun_qdepth;
  3893. struct ufs_hba *hba;
  3894. hba = shost_priv(sdev->host);
  3895. lun_qdepth = hba->nutrs;
  3896. ret = ufshcd_read_unit_desc_param(hba,
  3897. ufshcd_scsi_to_upiu_lun(sdev->lun),
  3898. UNIT_DESC_PARAM_LU_Q_DEPTH,
  3899. &lun_qdepth,
  3900. sizeof(lun_qdepth));
  3901. /* Some WLUN doesn't support unit descriptor */
  3902. if (ret == -EOPNOTSUPP)
  3903. lun_qdepth = 1;
  3904. else if (!lun_qdepth)
  3905. /* eventually, we can figure out the real queue depth */
  3906. lun_qdepth = hba->nutrs;
  3907. else
  3908. lun_qdepth = min_t(int, lun_qdepth, hba->nutrs);
  3909. dev_dbg(hba->dev, "%s: activate tcq with queue depth %d\n",
  3910. __func__, lun_qdepth);
  3911. scsi_change_queue_depth(sdev, lun_qdepth);
  3912. }
  3913. /*
  3914. * ufshcd_get_lu_wp - returns the "b_lu_write_protect" from UNIT DESCRIPTOR
  3915. * @hba: per-adapter instance
  3916. * @lun: UFS device lun id
  3917. * @b_lu_write_protect: pointer to buffer to hold the LU's write protect info
  3918. *
  3919. * Returns 0 in case of success and b_lu_write_protect status would be returned
  3920. * @b_lu_write_protect parameter.
  3921. * Returns -ENOTSUPP if reading b_lu_write_protect is not supported.
  3922. * Returns -EINVAL in case of invalid parameters passed to this function.
  3923. */
  3924. static int ufshcd_get_lu_wp(struct ufs_hba *hba,
  3925. u8 lun,
  3926. u8 *b_lu_write_protect)
  3927. {
  3928. int ret;
  3929. if (!b_lu_write_protect)
  3930. ret = -EINVAL;
  3931. /*
  3932. * According to UFS device spec, RPMB LU can't be write
  3933. * protected so skip reading bLUWriteProtect parameter for
  3934. * it. For other W-LUs, UNIT DESCRIPTOR is not available.
  3935. */
  3936. else if (lun >= UFS_UPIU_MAX_GENERAL_LUN)
  3937. ret = -ENOTSUPP;
  3938. else
  3939. ret = ufshcd_read_unit_desc_param(hba,
  3940. lun,
  3941. UNIT_DESC_PARAM_LU_WR_PROTECT,
  3942. b_lu_write_protect,
  3943. sizeof(*b_lu_write_protect));
  3944. return ret;
  3945. }
  3946. /**
  3947. * ufshcd_get_lu_power_on_wp_status - get LU's power on write protect
  3948. * status
  3949. * @hba: per-adapter instance
  3950. * @sdev: pointer to SCSI device
  3951. *
  3952. */
  3953. static inline void ufshcd_get_lu_power_on_wp_status(struct ufs_hba *hba,
  3954. struct scsi_device *sdev)
  3955. {
  3956. if (hba->dev_info.f_power_on_wp_en &&
  3957. !hba->dev_info.is_lu_power_on_wp) {
  3958. u8 b_lu_write_protect;
  3959. if (!ufshcd_get_lu_wp(hba, ufshcd_scsi_to_upiu_lun(sdev->lun),
  3960. &b_lu_write_protect) &&
  3961. (b_lu_write_protect == UFS_LU_POWER_ON_WP))
  3962. hba->dev_info.is_lu_power_on_wp = true;
  3963. }
  3964. }
  3965. /**
  3966. * ufshcd_slave_alloc - handle initial SCSI device configurations
  3967. * @sdev: pointer to SCSI device
  3968. *
  3969. * Returns success
  3970. */
  3971. static int ufshcd_slave_alloc(struct scsi_device *sdev)
  3972. {
  3973. struct ufs_hba *hba;
  3974. hba = shost_priv(sdev->host);
  3975. /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */
  3976. sdev->use_10_for_ms = 1;
  3977. /* allow SCSI layer to restart the device in case of errors */
  3978. sdev->allow_restart = 1;
  3979. /* REPORT SUPPORTED OPERATION CODES is not supported */
  3980. sdev->no_report_opcodes = 1;
  3981. /* WRITE_SAME command is not supported */
  3982. sdev->no_write_same = 1;
  3983. ufshcd_set_queue_depth(sdev);
  3984. ufshcd_get_lu_power_on_wp_status(hba, sdev);
  3985. return 0;
  3986. }
  3987. /**
  3988. * ufshcd_change_queue_depth - change queue depth
  3989. * @sdev: pointer to SCSI device
  3990. * @depth: required depth to set
  3991. *
  3992. * Change queue depth and make sure the max. limits are not crossed.
  3993. */
  3994. static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth)
  3995. {
  3996. struct ufs_hba *hba = shost_priv(sdev->host);
  3997. if (depth > hba->nutrs)
  3998. depth = hba->nutrs;
  3999. return scsi_change_queue_depth(sdev, depth);
  4000. }
  4001. /**
  4002. * ufshcd_slave_configure - adjust SCSI device configurations
  4003. * @sdev: pointer to SCSI device
  4004. */
  4005. static int ufshcd_slave_configure(struct scsi_device *sdev)
  4006. {
  4007. struct request_queue *q = sdev->request_queue;
  4008. blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1);
  4009. blk_queue_max_segment_size(q, PRDT_DATA_BYTE_COUNT_MAX);
  4010. return 0;
  4011. }
  4012. /**
  4013. * ufshcd_slave_destroy - remove SCSI device configurations
  4014. * @sdev: pointer to SCSI device
  4015. */
  4016. static void ufshcd_slave_destroy(struct scsi_device *sdev)
  4017. {
  4018. struct ufs_hba *hba;
  4019. hba = shost_priv(sdev->host);
  4020. /* Drop the reference as it won't be needed anymore */
  4021. if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) {
  4022. unsigned long flags;
  4023. spin_lock_irqsave(hba->host->host_lock, flags);
  4024. hba->sdev_ufs_device = NULL;
  4025. spin_unlock_irqrestore(hba->host->host_lock, flags);
  4026. }
  4027. }
  4028. /**
  4029. * ufshcd_task_req_compl - handle task management request completion
  4030. * @hba: per adapter instance
  4031. * @index: index of the completed request
  4032. * @resp: task management service response
  4033. *
  4034. * Returns non-zero value on error, zero on success
  4035. */
  4036. static int ufshcd_task_req_compl(struct ufs_hba *hba, u32 index, u8 *resp)
  4037. {
  4038. struct utp_task_req_desc *task_req_descp;
  4039. struct utp_upiu_task_rsp *task_rsp_upiup;
  4040. unsigned long flags;
  4041. int ocs_value;
  4042. int task_result;
  4043. spin_lock_irqsave(hba->host->host_lock, flags);
  4044. /* Clear completed tasks from outstanding_tasks */
  4045. __clear_bit(index, &hba->outstanding_tasks);
  4046. task_req_descp = hba->utmrdl_base_addr;
  4047. ocs_value = ufshcd_get_tmr_ocs(&task_req_descp[index]);
  4048. if (ocs_value == OCS_SUCCESS) {
  4049. task_rsp_upiup = (struct utp_upiu_task_rsp *)
  4050. task_req_descp[index].task_rsp_upiu;
  4051. task_result = be32_to_cpu(task_rsp_upiup->output_param1);
  4052. task_result = task_result & MASK_TM_SERVICE_RESP;
  4053. if (resp)
  4054. *resp = (u8)task_result;
  4055. } else {
  4056. dev_err(hba->dev, "%s: failed, ocs = 0x%x\n",
  4057. __func__, ocs_value);
  4058. }
  4059. spin_unlock_irqrestore(hba->host->host_lock, flags);
  4060. return ocs_value;
  4061. }
  4062. /**
  4063. * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status
  4064. * @lrbp: pointer to local reference block of completed command
  4065. * @scsi_status: SCSI command status
  4066. *
  4067. * Returns value base on SCSI command status
  4068. */
  4069. static inline int
  4070. ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
  4071. {
  4072. int result = 0;
  4073. switch (scsi_status) {
  4074. case SAM_STAT_CHECK_CONDITION:
  4075. ufshcd_copy_sense_data(lrbp);
  4076. case SAM_STAT_GOOD:
  4077. result |= DID_OK << 16 |
  4078. COMMAND_COMPLETE << 8 |
  4079. scsi_status;
  4080. break;
  4081. case SAM_STAT_TASK_SET_FULL:
  4082. case SAM_STAT_BUSY:
  4083. case SAM_STAT_TASK_ABORTED:
  4084. ufshcd_copy_sense_data(lrbp);
  4085. result |= scsi_status;
  4086. break;
  4087. default:
  4088. result |= DID_ERROR << 16;
  4089. break;
  4090. } /* end of switch */
  4091. return result;
  4092. }
  4093. /**
  4094. * ufshcd_transfer_rsp_status - Get overall status of the response
  4095. * @hba: per adapter instance
  4096. * @lrbp: pointer to local reference block of completed command
  4097. *
  4098. * Returns result of the command to notify SCSI midlayer
  4099. */
  4100. static inline int
  4101. ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
  4102. {
  4103. int result = 0;
  4104. int scsi_status;
  4105. int ocs;
  4106. /* overall command status of utrd */
  4107. ocs = ufshcd_get_tr_ocs(lrbp);
  4108. switch (ocs) {
  4109. case OCS_SUCCESS:
  4110. result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
  4111. hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
  4112. switch (result) {
  4113. case UPIU_TRANSACTION_RESPONSE:
  4114. /*
  4115. * get the response UPIU result to extract
  4116. * the SCSI command status
  4117. */
  4118. result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
  4119. /*
  4120. * get the result based on SCSI status response
  4121. * to notify the SCSI midlayer of the command status
  4122. */
  4123. scsi_status = result & MASK_SCSI_STATUS;
  4124. result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
  4125. /*
  4126. * Currently we are only supporting BKOPs exception
  4127. * events hence we can ignore BKOPs exception event
  4128. * during power management callbacks. BKOPs exception
  4129. * event is not expected to be raised in runtime suspend
  4130. * callback as it allows the urgent bkops.
  4131. * During system suspend, we are anyway forcefully
  4132. * disabling the bkops and if urgent bkops is needed
  4133. * it will be enabled on system resume. Long term
  4134. * solution could be to abort the system suspend if
  4135. * UFS device needs urgent BKOPs.
  4136. */
  4137. if (!hba->pm_op_in_progress &&
  4138. ufshcd_is_exception_event(lrbp->ucd_rsp_ptr))
  4139. schedule_work(&hba->eeh_work);
  4140. break;
  4141. case UPIU_TRANSACTION_REJECT_UPIU:
  4142. /* TODO: handle Reject UPIU Response */
  4143. result = DID_ERROR << 16;
  4144. dev_err(hba->dev,
  4145. "Reject UPIU not fully implemented\n");
  4146. break;
  4147. default:
  4148. result = DID_ERROR << 16;
  4149. dev_err(hba->dev,
  4150. "Unexpected request response code = %x\n",
  4151. result);
  4152. break;
  4153. }
  4154. break;
  4155. case OCS_ABORTED:
  4156. result |= DID_ABORT << 16;
  4157. break;
  4158. case OCS_INVALID_COMMAND_STATUS:
  4159. result |= DID_REQUEUE << 16;
  4160. break;
  4161. case OCS_INVALID_CMD_TABLE_ATTR:
  4162. case OCS_INVALID_PRDT_ATTR:
  4163. case OCS_MISMATCH_DATA_BUF_SIZE:
  4164. case OCS_MISMATCH_RESP_UPIU_SIZE:
  4165. case OCS_PEER_COMM_FAILURE:
  4166. case OCS_FATAL_ERROR:
  4167. default:
  4168. result |= DID_ERROR << 16;
  4169. dev_err(hba->dev,
  4170. "OCS error from controller = %x for tag %d\n",
  4171. ocs, lrbp->task_tag);
  4172. ufshcd_print_host_regs(hba);
  4173. ufshcd_print_host_state(hba);
  4174. break;
  4175. } /* end of switch */
  4176. if ((host_byte(result) != DID_OK) && !hba->silence_err_logs)
  4177. ufshcd_print_trs(hba, 1 << lrbp->task_tag, true);
  4178. return result;
  4179. }
  4180. /**
  4181. * ufshcd_uic_cmd_compl - handle completion of uic command
  4182. * @hba: per adapter instance
  4183. * @intr_status: interrupt status generated by the controller
  4184. */
  4185. static void ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
  4186. {
  4187. if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) {
  4188. hba->active_uic_cmd->argument2 |=
  4189. ufshcd_get_uic_cmd_result(hba);
  4190. hba->active_uic_cmd->argument3 =
  4191. ufshcd_get_dme_attr_val(hba);
  4192. complete(&hba->active_uic_cmd->done);
  4193. }
  4194. if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done)
  4195. complete(hba->uic_async_done);
  4196. }
  4197. /**
  4198. * __ufshcd_transfer_req_compl - handle SCSI and query command completion
  4199. * @hba: per adapter instance
  4200. * @completed_reqs: requests to complete
  4201. */
  4202. static void __ufshcd_transfer_req_compl(struct ufs_hba *hba,
  4203. unsigned long completed_reqs)
  4204. {
  4205. struct ufshcd_lrb *lrbp;
  4206. struct scsi_cmnd *cmd;
  4207. int result;
  4208. int index;
  4209. for_each_set_bit(index, &completed_reqs, hba->nutrs) {
  4210. lrbp = &hba->lrb[index];
  4211. cmd = lrbp->cmd;
  4212. if (cmd) {
  4213. ufshcd_add_command_trace(hba, index, "complete");
  4214. result = ufshcd_transfer_rsp_status(hba, lrbp);
  4215. scsi_dma_unmap(cmd);
  4216. cmd->result = result;
  4217. /* Mark completed command as NULL in LRB */
  4218. lrbp->cmd = NULL;
  4219. clear_bit_unlock(index, &hba->lrb_in_use);
  4220. /* Do not touch lrbp after scsi done */
  4221. cmd->scsi_done(cmd);
  4222. __ufshcd_release(hba);
  4223. } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE ||
  4224. lrbp->command_type == UTP_CMD_TYPE_UFS_STORAGE) {
  4225. if (hba->dev_cmd.complete) {
  4226. ufshcd_add_command_trace(hba, index,
  4227. "dev_complete");
  4228. complete(hba->dev_cmd.complete);
  4229. }
  4230. }
  4231. if (ufshcd_is_clkscaling_supported(hba))
  4232. hba->clk_scaling.active_reqs--;
  4233. lrbp->compl_time_stamp = ktime_get();
  4234. }
  4235. /* clear corresponding bits of completed commands */
  4236. hba->outstanding_reqs ^= completed_reqs;
  4237. ufshcd_clk_scaling_update_busy(hba);
  4238. /* we might have free'd some tags above */
  4239. wake_up(&hba->dev_cmd.tag_wq);
  4240. }
  4241. /**
  4242. * ufshcd_transfer_req_compl - handle SCSI and query command completion
  4243. * @hba: per adapter instance
  4244. */
  4245. static void ufshcd_transfer_req_compl(struct ufs_hba *hba)
  4246. {
  4247. unsigned long completed_reqs;
  4248. u32 tr_doorbell;
  4249. /* Resetting interrupt aggregation counters first and reading the
  4250. * DOOR_BELL afterward allows us to handle all the completed requests.
  4251. * In order to prevent other interrupts starvation the DB is read once
  4252. * after reset. The down side of this solution is the possibility of
  4253. * false interrupt if device completes another request after resetting
  4254. * aggregation and before reading the DB.
  4255. */
  4256. if (ufshcd_is_intr_aggr_allowed(hba) &&
  4257. !(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR))
  4258. ufshcd_reset_intr_aggr(hba);
  4259. tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
  4260. completed_reqs = tr_doorbell ^ hba->outstanding_reqs;
  4261. __ufshcd_transfer_req_compl(hba, completed_reqs);
  4262. }
  4263. /**
  4264. * ufshcd_disable_ee - disable exception event
  4265. * @hba: per-adapter instance
  4266. * @mask: exception event to disable
  4267. *
  4268. * Disables exception event in the device so that the EVENT_ALERT
  4269. * bit is not set.
  4270. *
  4271. * Returns zero on success, non-zero error value on failure.
  4272. */
  4273. static int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask)
  4274. {
  4275. int err = 0;
  4276. u32 val;
  4277. if (!(hba->ee_ctrl_mask & mask))
  4278. goto out;
  4279. val = hba->ee_ctrl_mask & ~mask;
  4280. val &= MASK_EE_STATUS;
  4281. err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
  4282. QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
  4283. if (!err)
  4284. hba->ee_ctrl_mask &= ~mask;
  4285. out:
  4286. return err;
  4287. }
  4288. /**
  4289. * ufshcd_enable_ee - enable exception event
  4290. * @hba: per-adapter instance
  4291. * @mask: exception event to enable
  4292. *
  4293. * Enable corresponding exception event in the device to allow
  4294. * device to alert host in critical scenarios.
  4295. *
  4296. * Returns zero on success, non-zero error value on failure.
  4297. */
  4298. static int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask)
  4299. {
  4300. int err = 0;
  4301. u32 val;
  4302. if (hba->ee_ctrl_mask & mask)
  4303. goto out;
  4304. val = hba->ee_ctrl_mask | mask;
  4305. val &= MASK_EE_STATUS;
  4306. err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
  4307. QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
  4308. if (!err)
  4309. hba->ee_ctrl_mask |= mask;
  4310. out:
  4311. return err;
  4312. }
  4313. /**
  4314. * ufshcd_enable_auto_bkops - Allow device managed BKOPS
  4315. * @hba: per-adapter instance
  4316. *
  4317. * Allow device to manage background operations on its own. Enabling
  4318. * this might lead to inconsistent latencies during normal data transfers
  4319. * as the device is allowed to manage its own way of handling background
  4320. * operations.
  4321. *
  4322. * Returns zero on success, non-zero on failure.
  4323. */
  4324. static int ufshcd_enable_auto_bkops(struct ufs_hba *hba)
  4325. {
  4326. int err = 0;
  4327. if (hba->auto_bkops_enabled)
  4328. goto out;
  4329. err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
  4330. QUERY_FLAG_IDN_BKOPS_EN, NULL);
  4331. if (err) {
  4332. dev_err(hba->dev, "%s: failed to enable bkops %d\n",
  4333. __func__, err);
  4334. goto out;
  4335. }
  4336. hba->auto_bkops_enabled = true;
  4337. trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Enabled");
  4338. /* No need of URGENT_BKOPS exception from the device */
  4339. err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
  4340. if (err)
  4341. dev_err(hba->dev, "%s: failed to disable exception event %d\n",
  4342. __func__, err);
  4343. out:
  4344. return err;
  4345. }
  4346. /**
  4347. * ufshcd_disable_auto_bkops - block device in doing background operations
  4348. * @hba: per-adapter instance
  4349. *
  4350. * Disabling background operations improves command response latency but
  4351. * has drawback of device moving into critical state where the device is
  4352. * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the
  4353. * host is idle so that BKOPS are managed effectively without any negative
  4354. * impacts.
  4355. *
  4356. * Returns zero on success, non-zero on failure.
  4357. */
  4358. static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
  4359. {
  4360. int err = 0;
  4361. if (!hba->auto_bkops_enabled)
  4362. goto out;
  4363. /*
  4364. * If host assisted BKOPs is to be enabled, make sure
  4365. * urgent bkops exception is allowed.
  4366. */
  4367. err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS);
  4368. if (err) {
  4369. dev_err(hba->dev, "%s: failed to enable exception event %d\n",
  4370. __func__, err);
  4371. goto out;
  4372. }
  4373. err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
  4374. QUERY_FLAG_IDN_BKOPS_EN, NULL);
  4375. if (err) {
  4376. dev_err(hba->dev, "%s: failed to disable bkops %d\n",
  4377. __func__, err);
  4378. ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
  4379. goto out;
  4380. }
  4381. hba->auto_bkops_enabled = false;
  4382. trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Disabled");
  4383. hba->is_urgent_bkops_lvl_checked = false;
  4384. out:
  4385. return err;
  4386. }
  4387. /**
  4388. * ufshcd_force_reset_auto_bkops - force reset auto bkops state
  4389. * @hba: per adapter instance
  4390. *
  4391. * After a device reset the device may toggle the BKOPS_EN flag
  4392. * to default value. The s/w tracking variables should be updated
  4393. * as well. This function would change the auto-bkops state based on
  4394. * UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND.
  4395. */
  4396. static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
  4397. {
  4398. if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) {
  4399. hba->auto_bkops_enabled = false;
  4400. hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS;
  4401. ufshcd_enable_auto_bkops(hba);
  4402. } else {
  4403. hba->auto_bkops_enabled = true;
  4404. hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS;
  4405. ufshcd_disable_auto_bkops(hba);
  4406. }
  4407. hba->is_urgent_bkops_lvl_checked = false;
  4408. }
  4409. static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
  4410. {
  4411. return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
  4412. QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status);
  4413. }
  4414. /**
  4415. * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status
  4416. * @hba: per-adapter instance
  4417. * @status: bkops_status value
  4418. *
  4419. * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn
  4420. * flag in the device to permit background operations if the device
  4421. * bkops_status is greater than or equal to "status" argument passed to
  4422. * this function, disable otherwise.
  4423. *
  4424. * Returns 0 for success, non-zero in case of failure.
  4425. *
  4426. * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag
  4427. * to know whether auto bkops is enabled or disabled after this function
  4428. * returns control to it.
  4429. */
  4430. static int ufshcd_bkops_ctrl(struct ufs_hba *hba,
  4431. enum bkops_status status)
  4432. {
  4433. int err;
  4434. u32 curr_status = 0;
  4435. err = ufshcd_get_bkops_status(hba, &curr_status);
  4436. if (err) {
  4437. dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
  4438. __func__, err);
  4439. goto out;
  4440. } else if (curr_status > BKOPS_STATUS_MAX) {
  4441. dev_err(hba->dev, "%s: invalid BKOPS status %d\n",
  4442. __func__, curr_status);
  4443. err = -EINVAL;
  4444. goto out;
  4445. }
  4446. if (curr_status >= status)
  4447. err = ufshcd_enable_auto_bkops(hba);
  4448. else
  4449. err = ufshcd_disable_auto_bkops(hba);
  4450. hba->urgent_bkops_lvl = curr_status;
  4451. out:
  4452. return err;
  4453. }
  4454. /**
  4455. * ufshcd_urgent_bkops - handle urgent bkops exception event
  4456. * @hba: per-adapter instance
  4457. *
  4458. * Enable fBackgroundOpsEn flag in the device to permit background
  4459. * operations.
  4460. *
  4461. * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled
  4462. * and negative error value for any other failure.
  4463. */
  4464. static int ufshcd_urgent_bkops(struct ufs_hba *hba)
  4465. {
  4466. return ufshcd_bkops_ctrl(hba, hba->urgent_bkops_lvl);
  4467. }
  4468. static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status)
  4469. {
  4470. return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
  4471. QUERY_ATTR_IDN_EE_STATUS, 0, 0, status);
  4472. }
  4473. static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba)
  4474. {
  4475. int err;
  4476. u32 curr_status = 0;
  4477. if (hba->is_urgent_bkops_lvl_checked)
  4478. goto enable_auto_bkops;
  4479. err = ufshcd_get_bkops_status(hba, &curr_status);
  4480. if (err) {
  4481. dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
  4482. __func__, err);
  4483. goto out;
  4484. }
  4485. /*
  4486. * We are seeing that some devices are raising the urgent bkops
  4487. * exception events even when BKOPS status doesn't indicate performace
  4488. * impacted or critical. Handle these device by determining their urgent
  4489. * bkops status at runtime.
  4490. */
  4491. if (curr_status < BKOPS_STATUS_PERF_IMPACT) {
  4492. dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n",
  4493. __func__, curr_status);
  4494. /* update the current status as the urgent bkops level */
  4495. hba->urgent_bkops_lvl = curr_status;
  4496. hba->is_urgent_bkops_lvl_checked = true;
  4497. }
  4498. enable_auto_bkops:
  4499. err = ufshcd_enable_auto_bkops(hba);
  4500. out:
  4501. if (err < 0)
  4502. dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n",
  4503. __func__, err);
  4504. }
  4505. /**
  4506. * ufshcd_exception_event_handler - handle exceptions raised by device
  4507. * @work: pointer to work data
  4508. *
  4509. * Read bExceptionEventStatus attribute from the device and handle the
  4510. * exception event accordingly.
  4511. */
  4512. static void ufshcd_exception_event_handler(struct work_struct *work)
  4513. {
  4514. struct ufs_hba *hba;
  4515. int err;
  4516. u32 status = 0;
  4517. hba = container_of(work, struct ufs_hba, eeh_work);
  4518. pm_runtime_get_sync(hba->dev);
  4519. scsi_block_requests(hba->host);
  4520. err = ufshcd_get_ee_status(hba, &status);
  4521. if (err) {
  4522. dev_err(hba->dev, "%s: failed to get exception status %d\n",
  4523. __func__, err);
  4524. goto out;
  4525. }
  4526. status &= hba->ee_ctrl_mask;
  4527. if (status & MASK_EE_URGENT_BKOPS)
  4528. ufshcd_bkops_exception_event_handler(hba);
  4529. out:
  4530. scsi_unblock_requests(hba->host);
  4531. pm_runtime_put_sync(hba->dev);
  4532. return;
  4533. }
  4534. /* Complete requests that have door-bell cleared */
  4535. static void ufshcd_complete_requests(struct ufs_hba *hba)
  4536. {
  4537. ufshcd_transfer_req_compl(hba);
  4538. ufshcd_tmc_handler(hba);
  4539. }
  4540. /**
  4541. * ufshcd_quirk_dl_nac_errors - This function checks if error handling is
  4542. * to recover from the DL NAC errors or not.
  4543. * @hba: per-adapter instance
  4544. *
  4545. * Returns true if error handling is required, false otherwise
  4546. */
  4547. static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba)
  4548. {
  4549. unsigned long flags;
  4550. bool err_handling = true;
  4551. spin_lock_irqsave(hba->host->host_lock, flags);
  4552. /*
  4553. * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the
  4554. * device fatal error and/or DL NAC & REPLAY timeout errors.
  4555. */
  4556. if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR))
  4557. goto out;
  4558. if ((hba->saved_err & DEVICE_FATAL_ERROR) ||
  4559. ((hba->saved_err & UIC_ERROR) &&
  4560. (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))
  4561. goto out;
  4562. if ((hba->saved_err & UIC_ERROR) &&
  4563. (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) {
  4564. int err;
  4565. /*
  4566. * wait for 50ms to see if we can get any other errors or not.
  4567. */
  4568. spin_unlock_irqrestore(hba->host->host_lock, flags);
  4569. msleep(50);
  4570. spin_lock_irqsave(hba->host->host_lock, flags);
  4571. /*
  4572. * now check if we have got any other severe errors other than
  4573. * DL NAC error?
  4574. */
  4575. if ((hba->saved_err & INT_FATAL_ERRORS) ||
  4576. ((hba->saved_err & UIC_ERROR) &&
  4577. (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)))
  4578. goto out;
  4579. /*
  4580. * As DL NAC is the only error received so far, send out NOP
  4581. * command to confirm if link is still active or not.
  4582. * - If we don't get any response then do error recovery.
  4583. * - If we get response then clear the DL NAC error bit.
  4584. */
  4585. spin_unlock_irqrestore(hba->host->host_lock, flags);
  4586. err = ufshcd_verify_dev_init(hba);
  4587. spin_lock_irqsave(hba->host->host_lock, flags);
  4588. if (err)
  4589. goto out;
  4590. /* Link seems to be alive hence ignore the DL NAC errors */
  4591. if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)
  4592. hba->saved_err &= ~UIC_ERROR;
  4593. /* clear NAC error */
  4594. hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
  4595. if (!hba->saved_uic_err) {
  4596. err_handling = false;
  4597. goto out;
  4598. }
  4599. }
  4600. out:
  4601. spin_unlock_irqrestore(hba->host->host_lock, flags);
  4602. return err_handling;
  4603. }
  4604. /**
  4605. * ufshcd_err_handler - handle UFS errors that require s/w attention
  4606. * @work: pointer to work structure
  4607. */
  4608. static void ufshcd_err_handler(struct work_struct *work)
  4609. {
  4610. struct ufs_hba *hba;
  4611. unsigned long flags;
  4612. u32 err_xfer = 0;
  4613. u32 err_tm = 0;
  4614. int err = 0;
  4615. int tag;
  4616. bool needs_reset = false;
  4617. hba = container_of(work, struct ufs_hba, eh_work);
  4618. pm_runtime_get_sync(hba->dev);
  4619. ufshcd_hold(hba, false);
  4620. spin_lock_irqsave(hba->host->host_lock, flags);
  4621. if (hba->ufshcd_state == UFSHCD_STATE_RESET)
  4622. goto out;
  4623. hba->ufshcd_state = UFSHCD_STATE_RESET;
  4624. ufshcd_set_eh_in_progress(hba);
  4625. /* Complete requests that have door-bell cleared by h/w */
  4626. ufshcd_complete_requests(hba);
  4627. if (hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
  4628. bool ret;
  4629. spin_unlock_irqrestore(hba->host->host_lock, flags);
  4630. /* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */
  4631. ret = ufshcd_quirk_dl_nac_errors(hba);
  4632. spin_lock_irqsave(hba->host->host_lock, flags);
  4633. if (!ret)
  4634. goto skip_err_handling;
  4635. }
  4636. if ((hba->saved_err & INT_FATAL_ERRORS) ||
  4637. ((hba->saved_err & UIC_ERROR) &&
  4638. (hba->saved_uic_err & (UFSHCD_UIC_DL_PA_INIT_ERROR |
  4639. UFSHCD_UIC_DL_NAC_RECEIVED_ERROR |
  4640. UFSHCD_UIC_DL_TCx_REPLAY_ERROR))))
  4641. needs_reset = true;
  4642. /*
  4643. * if host reset is required then skip clearing the pending
  4644. * transfers forcefully because they will get cleared during
  4645. * host reset and restore
  4646. */
  4647. if (needs_reset)
  4648. goto skip_pending_xfer_clear;
  4649. /* release lock as clear command might sleep */
  4650. spin_unlock_irqrestore(hba->host->host_lock, flags);
  4651. /* Clear pending transfer requests */
  4652. for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs) {
  4653. if (ufshcd_clear_cmd(hba, tag)) {
  4654. err_xfer = true;
  4655. goto lock_skip_pending_xfer_clear;
  4656. }
  4657. }
  4658. /* Clear pending task management requests */
  4659. for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) {
  4660. if (ufshcd_clear_tm_cmd(hba, tag)) {
  4661. err_tm = true;
  4662. goto lock_skip_pending_xfer_clear;
  4663. }
  4664. }
  4665. lock_skip_pending_xfer_clear:
  4666. spin_lock_irqsave(hba->host->host_lock, flags);
  4667. /* Complete the requests that are cleared by s/w */
  4668. ufshcd_complete_requests(hba);
  4669. if (err_xfer || err_tm)
  4670. needs_reset = true;
  4671. skip_pending_xfer_clear:
  4672. /* Fatal errors need reset */
  4673. if (needs_reset) {
  4674. unsigned long max_doorbells = (1UL << hba->nutrs) - 1;
  4675. /*
  4676. * ufshcd_reset_and_restore() does the link reinitialization
  4677. * which will need atleast one empty doorbell slot to send the
  4678. * device management commands (NOP and query commands).
  4679. * If there is no slot empty at this moment then free up last
  4680. * slot forcefully.
  4681. */
  4682. if (hba->outstanding_reqs == max_doorbells)
  4683. __ufshcd_transfer_req_compl(hba,
  4684. (1UL << (hba->nutrs - 1)));
  4685. spin_unlock_irqrestore(hba->host->host_lock, flags);
  4686. err = ufshcd_reset_and_restore(hba);
  4687. spin_lock_irqsave(hba->host->host_lock, flags);
  4688. if (err) {
  4689. dev_err(hba->dev, "%s: reset and restore failed\n",
  4690. __func__);
  4691. hba->ufshcd_state = UFSHCD_STATE_ERROR;
  4692. }
  4693. /*
  4694. * Inform scsi mid-layer that we did reset and allow to handle
  4695. * Unit Attention properly.
  4696. */
  4697. scsi_report_bus_reset(hba->host, 0);
  4698. hba->saved_err = 0;
  4699. hba->saved_uic_err = 0;
  4700. }
  4701. skip_err_handling:
  4702. if (!needs_reset) {
  4703. hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
  4704. if (hba->saved_err || hba->saved_uic_err)
  4705. dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x",
  4706. __func__, hba->saved_err, hba->saved_uic_err);
  4707. }
  4708. ufshcd_clear_eh_in_progress(hba);
  4709. out:
  4710. spin_unlock_irqrestore(hba->host->host_lock, flags);
  4711. ufshcd_scsi_unblock_requests(hba);
  4712. ufshcd_release(hba);
  4713. pm_runtime_put_sync(hba->dev);
  4714. }
  4715. static void ufshcd_update_uic_reg_hist(struct ufs_uic_err_reg_hist *reg_hist,
  4716. u32 reg)
  4717. {
  4718. reg_hist->reg[reg_hist->pos] = reg;
  4719. reg_hist->tstamp[reg_hist->pos] = ktime_get();
  4720. reg_hist->pos = (reg_hist->pos + 1) % UIC_ERR_REG_HIST_LENGTH;
  4721. }
  4722. /**
  4723. * ufshcd_update_uic_error - check and set fatal UIC error flags.
  4724. * @hba: per-adapter instance
  4725. */
  4726. static void ufshcd_update_uic_error(struct ufs_hba *hba)
  4727. {
  4728. u32 reg;
  4729. /* PHY layer lane error */
  4730. reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
  4731. /* Ignore LINERESET indication, as this is not an error */
  4732. if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) &&
  4733. (reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK)) {
  4734. /*
  4735. * To know whether this error is fatal or not, DB timeout
  4736. * must be checked but this error is handled separately.
  4737. */
  4738. dev_dbg(hba->dev, "%s: UIC Lane error reported\n", __func__);
  4739. ufshcd_update_uic_reg_hist(&hba->ufs_stats.pa_err, reg);
  4740. }
  4741. /* PA_INIT_ERROR is fatal and needs UIC reset */
  4742. reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
  4743. if (reg)
  4744. ufshcd_update_uic_reg_hist(&hba->ufs_stats.dl_err, reg);
  4745. if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
  4746. hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
  4747. else if (hba->dev_quirks &
  4748. UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
  4749. if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED)
  4750. hba->uic_error |=
  4751. UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
  4752. else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT)
  4753. hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR;
  4754. }
  4755. /* UIC NL/TL/DME errors needs software retry */
  4756. reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
  4757. if (reg) {
  4758. ufshcd_update_uic_reg_hist(&hba->ufs_stats.nl_err, reg);
  4759. hba->uic_error |= UFSHCD_UIC_NL_ERROR;
  4760. }
  4761. reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
  4762. if (reg) {
  4763. ufshcd_update_uic_reg_hist(&hba->ufs_stats.tl_err, reg);
  4764. hba->uic_error |= UFSHCD_UIC_TL_ERROR;
  4765. }
  4766. reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
  4767. if (reg) {
  4768. ufshcd_update_uic_reg_hist(&hba->ufs_stats.dme_err, reg);
  4769. hba->uic_error |= UFSHCD_UIC_DME_ERROR;
  4770. }
  4771. dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
  4772. __func__, hba->uic_error);
  4773. }
  4774. /**
  4775. * ufshcd_check_errors - Check for errors that need s/w attention
  4776. * @hba: per-adapter instance
  4777. */
  4778. static void ufshcd_check_errors(struct ufs_hba *hba)
  4779. {
  4780. bool queue_eh_work = false;
  4781. if (hba->errors & INT_FATAL_ERRORS)
  4782. queue_eh_work = true;
  4783. if (hba->errors & UIC_ERROR) {
  4784. hba->uic_error = 0;
  4785. ufshcd_update_uic_error(hba);
  4786. if (hba->uic_error)
  4787. queue_eh_work = true;
  4788. }
  4789. if (queue_eh_work) {
  4790. /*
  4791. * update the transfer error masks to sticky bits, let's do this
  4792. * irrespective of current ufshcd_state.
  4793. */
  4794. hba->saved_err |= hba->errors;
  4795. hba->saved_uic_err |= hba->uic_error;
  4796. /* handle fatal errors only when link is functional */
  4797. if (hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL) {
  4798. /* block commands from scsi mid-layer */
  4799. ufshcd_scsi_block_requests(hba);
  4800. hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED;
  4801. /* dump controller state before resetting */
  4802. if (hba->saved_err & (INT_FATAL_ERRORS | UIC_ERROR)) {
  4803. bool pr_prdt = !!(hba->saved_err &
  4804. SYSTEM_BUS_FATAL_ERROR);
  4805. dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x\n",
  4806. __func__, hba->saved_err,
  4807. hba->saved_uic_err);
  4808. ufshcd_print_host_regs(hba);
  4809. ufshcd_print_pwr_info(hba);
  4810. ufshcd_print_tmrs(hba, hba->outstanding_tasks);
  4811. ufshcd_print_trs(hba, hba->outstanding_reqs,
  4812. pr_prdt);
  4813. }
  4814. schedule_work(&hba->eh_work);
  4815. }
  4816. }
  4817. /*
  4818. * if (!queue_eh_work) -
  4819. * Other errors are either non-fatal where host recovers
  4820. * itself without s/w intervention or errors that will be
  4821. * handled by the SCSI core layer.
  4822. */
  4823. }
  4824. /**
  4825. * ufshcd_tmc_handler - handle task management function completion
  4826. * @hba: per adapter instance
  4827. */
  4828. static void ufshcd_tmc_handler(struct ufs_hba *hba)
  4829. {
  4830. u32 tm_doorbell;
  4831. tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
  4832. hba->tm_condition = tm_doorbell ^ hba->outstanding_tasks;
  4833. wake_up(&hba->tm_wq);
  4834. }
  4835. /**
  4836. * ufshcd_sl_intr - Interrupt service routine
  4837. * @hba: per adapter instance
  4838. * @intr_status: contains interrupts generated by the controller
  4839. */
  4840. static void ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
  4841. {
  4842. hba->errors = UFSHCD_ERROR_MASK & intr_status;
  4843. if (hba->errors)
  4844. ufshcd_check_errors(hba);
  4845. if (intr_status & UFSHCD_UIC_MASK)
  4846. ufshcd_uic_cmd_compl(hba, intr_status);
  4847. if (intr_status & UTP_TASK_REQ_COMPL)
  4848. ufshcd_tmc_handler(hba);
  4849. if (intr_status & UTP_TRANSFER_REQ_COMPL)
  4850. ufshcd_transfer_req_compl(hba);
  4851. }
  4852. /**
  4853. * ufshcd_intr - Main interrupt service routine
  4854. * @irq: irq number
  4855. * @__hba: pointer to adapter instance
  4856. *
  4857. * Returns IRQ_HANDLED - If interrupt is valid
  4858. * IRQ_NONE - If invalid interrupt
  4859. */
  4860. static irqreturn_t ufshcd_intr(int irq, void *__hba)
  4861. {
  4862. u32 intr_status, enabled_intr_status;
  4863. irqreturn_t retval = IRQ_NONE;
  4864. struct ufs_hba *hba = __hba;
  4865. int retries = hba->nutrs;
  4866. spin_lock(hba->host->host_lock);
  4867. intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
  4868. /*
  4869. * There could be max of hba->nutrs reqs in flight and in worst case
  4870. * if the reqs get finished 1 by 1 after the interrupt status is
  4871. * read, make sure we handle them by checking the interrupt status
  4872. * again in a loop until we process all of the reqs before returning.
  4873. */
  4874. do {
  4875. enabled_intr_status =
  4876. intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
  4877. if (intr_status)
  4878. ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
  4879. if (enabled_intr_status) {
  4880. ufshcd_sl_intr(hba, enabled_intr_status);
  4881. retval = IRQ_HANDLED;
  4882. }
  4883. intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
  4884. } while (intr_status && --retries);
  4885. spin_unlock(hba->host->host_lock);
  4886. return retval;
  4887. }
  4888. static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
  4889. {
  4890. int err = 0;
  4891. u32 mask = 1 << tag;
  4892. unsigned long flags;
  4893. if (!test_bit(tag, &hba->outstanding_tasks))
  4894. goto out;
  4895. spin_lock_irqsave(hba->host->host_lock, flags);
  4896. ufshcd_utmrl_clear(hba, tag);
  4897. spin_unlock_irqrestore(hba->host->host_lock, flags);
  4898. /* poll for max. 1 sec to clear door bell register by h/w */
  4899. err = ufshcd_wait_for_register(hba,
  4900. REG_UTP_TASK_REQ_DOOR_BELL,
  4901. mask, 0, 1000, 1000, true);
  4902. out:
  4903. return err;
  4904. }
  4905. /**
  4906. * ufshcd_issue_tm_cmd - issues task management commands to controller
  4907. * @hba: per adapter instance
  4908. * @lun_id: LUN ID to which TM command is sent
  4909. * @task_id: task ID to which the TM command is applicable
  4910. * @tm_function: task management function opcode
  4911. * @tm_response: task management service response return value
  4912. *
  4913. * Returns non-zero value on error, zero on success.
  4914. */
  4915. static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
  4916. u8 tm_function, u8 *tm_response)
  4917. {
  4918. struct utp_task_req_desc *task_req_descp;
  4919. struct utp_upiu_task_req *task_req_upiup;
  4920. struct Scsi_Host *host;
  4921. unsigned long flags;
  4922. int free_slot;
  4923. int err;
  4924. int task_tag;
  4925. host = hba->host;
  4926. /*
  4927. * Get free slot, sleep if slots are unavailable.
  4928. * Even though we use wait_event() which sleeps indefinitely,
  4929. * the maximum wait time is bounded by %TM_CMD_TIMEOUT.
  4930. */
  4931. wait_event(hba->tm_tag_wq, ufshcd_get_tm_free_slot(hba, &free_slot));
  4932. ufshcd_hold(hba, false);
  4933. spin_lock_irqsave(host->host_lock, flags);
  4934. task_req_descp = hba->utmrdl_base_addr;
  4935. task_req_descp += free_slot;
  4936. /* Configure task request descriptor */
  4937. task_req_descp->header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
  4938. task_req_descp->header.dword_2 =
  4939. cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
  4940. /* Configure task request UPIU */
  4941. task_req_upiup =
  4942. (struct utp_upiu_task_req *) task_req_descp->task_req_upiu;
  4943. task_tag = hba->nutrs + free_slot;
  4944. task_req_upiup->header.dword_0 =
  4945. UPIU_HEADER_DWORD(UPIU_TRANSACTION_TASK_REQ, 0,
  4946. lun_id, task_tag);
  4947. task_req_upiup->header.dword_1 =
  4948. UPIU_HEADER_DWORD(0, tm_function, 0, 0);
  4949. /*
  4950. * The host shall provide the same value for LUN field in the basic
  4951. * header and for Input Parameter.
  4952. */
  4953. task_req_upiup->input_param1 = cpu_to_be32(lun_id);
  4954. task_req_upiup->input_param2 = cpu_to_be32(task_id);
  4955. ufshcd_vops_setup_task_mgmt(hba, free_slot, tm_function);
  4956. /* send command to the controller */
  4957. __set_bit(free_slot, &hba->outstanding_tasks);
  4958. /* Make sure descriptors are ready before ringing the task doorbell */
  4959. wmb();
  4960. ufshcd_writel(hba, 1 << free_slot, REG_UTP_TASK_REQ_DOOR_BELL);
  4961. /* Make sure that doorbell is committed immediately */
  4962. wmb();
  4963. spin_unlock_irqrestore(host->host_lock, flags);
  4964. ufshcd_add_tm_upiu_trace(hba, task_tag, "tm_send");
  4965. /* wait until the task management command is completed */
  4966. err = wait_event_timeout(hba->tm_wq,
  4967. test_bit(free_slot, &hba->tm_condition),
  4968. msecs_to_jiffies(TM_CMD_TIMEOUT));
  4969. if (!err) {
  4970. ufshcd_add_tm_upiu_trace(hba, task_tag, "tm_complete_err");
  4971. dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n",
  4972. __func__, tm_function);
  4973. if (ufshcd_clear_tm_cmd(hba, free_slot))
  4974. dev_WARN(hba->dev, "%s: unable clear tm cmd (slot %d) after timeout\n",
  4975. __func__, free_slot);
  4976. err = -ETIMEDOUT;
  4977. } else {
  4978. err = ufshcd_task_req_compl(hba, free_slot, tm_response);
  4979. ufshcd_add_tm_upiu_trace(hba, task_tag, "tm_complete");
  4980. }
  4981. clear_bit(free_slot, &hba->tm_condition);
  4982. ufshcd_put_tm_slot(hba, free_slot);
  4983. wake_up(&hba->tm_tag_wq);
  4984. ufshcd_release(hba);
  4985. return err;
  4986. }
  4987. /**
  4988. * ufshcd_eh_device_reset_handler - device reset handler registered to
  4989. * scsi layer.
  4990. * @cmd: SCSI command pointer
  4991. *
  4992. * Returns SUCCESS/FAILED
  4993. */
  4994. static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
  4995. {
  4996. struct Scsi_Host *host;
  4997. struct ufs_hba *hba;
  4998. unsigned int tag;
  4999. u32 pos;
  5000. int err;
  5001. u8 resp = 0xF;
  5002. struct ufshcd_lrb *lrbp;
  5003. unsigned long flags;
  5004. host = cmd->device->host;
  5005. hba = shost_priv(host);
  5006. tag = cmd->request->tag;
  5007. lrbp = &hba->lrb[tag];
  5008. err = ufshcd_issue_tm_cmd(hba, lrbp->lun, 0, UFS_LOGICAL_RESET, &resp);
  5009. if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
  5010. if (!err)
  5011. err = resp;
  5012. goto out;
  5013. }
  5014. /* clear the commands that were pending for corresponding LUN */
  5015. for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) {
  5016. if (hba->lrb[pos].lun == lrbp->lun) {
  5017. err = ufshcd_clear_cmd(hba, pos);
  5018. if (err)
  5019. break;
  5020. }
  5021. }
  5022. spin_lock_irqsave(host->host_lock, flags);
  5023. ufshcd_transfer_req_compl(hba);
  5024. spin_unlock_irqrestore(host->host_lock, flags);
  5025. out:
  5026. hba->req_abort_count = 0;
  5027. if (!err) {
  5028. err = SUCCESS;
  5029. } else {
  5030. dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
  5031. err = FAILED;
  5032. }
  5033. return err;
  5034. }
  5035. static void ufshcd_set_req_abort_skip(struct ufs_hba *hba, unsigned long bitmap)
  5036. {
  5037. struct ufshcd_lrb *lrbp;
  5038. int tag;
  5039. for_each_set_bit(tag, &bitmap, hba->nutrs) {
  5040. lrbp = &hba->lrb[tag];
  5041. lrbp->req_abort_skip = true;
  5042. }
  5043. }
  5044. /**
  5045. * ufshcd_abort - abort a specific command
  5046. * @cmd: SCSI command pointer
  5047. *
  5048. * Abort the pending command in device by sending UFS_ABORT_TASK task management
  5049. * command, and in host controller by clearing the door-bell register. There can
  5050. * be race between controller sending the command to the device while abort is
  5051. * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is
  5052. * really issued and then try to abort it.
  5053. *
  5054. * Returns SUCCESS/FAILED
  5055. */
  5056. static int ufshcd_abort(struct scsi_cmnd *cmd)
  5057. {
  5058. struct Scsi_Host *host;
  5059. struct ufs_hba *hba;
  5060. unsigned long flags;
  5061. unsigned int tag;
  5062. int err = 0;
  5063. int poll_cnt;
  5064. u8 resp = 0xF;
  5065. struct ufshcd_lrb *lrbp;
  5066. u32 reg;
  5067. host = cmd->device->host;
  5068. hba = shost_priv(host);
  5069. tag = cmd->request->tag;
  5070. lrbp = &hba->lrb[tag];
  5071. if (!ufshcd_valid_tag(hba, tag)) {
  5072. dev_err(hba->dev,
  5073. "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
  5074. __func__, tag, cmd, cmd->request);
  5075. BUG();
  5076. }
  5077. /*
  5078. * Task abort to the device W-LUN is illegal. When this command
  5079. * will fail, due to spec violation, scsi err handling next step
  5080. * will be to send LU reset which, again, is a spec violation.
  5081. * To avoid these unnecessary/illegal step we skip to the last error
  5082. * handling stage: reset and restore.
  5083. */
  5084. if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN)
  5085. return ufshcd_eh_host_reset_handler(cmd);
  5086. ufshcd_hold(hba, false);
  5087. reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
  5088. /* If command is already aborted/completed, return SUCCESS */
  5089. if (!(test_bit(tag, &hba->outstanding_reqs))) {
  5090. dev_err(hba->dev,
  5091. "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n",
  5092. __func__, tag, hba->outstanding_reqs, reg);
  5093. goto out;
  5094. }
  5095. if (!(reg & (1 << tag))) {
  5096. dev_err(hba->dev,
  5097. "%s: cmd was completed, but without a notifying intr, tag = %d",
  5098. __func__, tag);
  5099. }
  5100. /* Print Transfer Request of aborted task */
  5101. dev_err(hba->dev, "%s: Device abort task at tag %d\n", __func__, tag);
  5102. /*
  5103. * Print detailed info about aborted request.
  5104. * As more than one request might get aborted at the same time,
  5105. * print full information only for the first aborted request in order
  5106. * to reduce repeated printouts. For other aborted requests only print
  5107. * basic details.
  5108. */
  5109. scsi_print_command(hba->lrb[tag].cmd);
  5110. if (!hba->req_abort_count) {
  5111. ufshcd_print_host_regs(hba);
  5112. ufshcd_print_host_state(hba);
  5113. ufshcd_print_pwr_info(hba);
  5114. ufshcd_print_trs(hba, 1 << tag, true);
  5115. } else {
  5116. ufshcd_print_trs(hba, 1 << tag, false);
  5117. }
  5118. hba->req_abort_count++;
  5119. /* Skip task abort in case previous aborts failed and report failure */
  5120. if (lrbp->req_abort_skip) {
  5121. err = -EIO;
  5122. goto out;
  5123. }
  5124. for (poll_cnt = 100; poll_cnt; poll_cnt--) {
  5125. err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
  5126. UFS_QUERY_TASK, &resp);
  5127. if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) {
  5128. /* cmd pending in the device */
  5129. dev_err(hba->dev, "%s: cmd pending in the device. tag = %d\n",
  5130. __func__, tag);
  5131. break;
  5132. } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
  5133. /*
  5134. * cmd not pending in the device, check if it is
  5135. * in transition.
  5136. */
  5137. dev_err(hba->dev, "%s: cmd at tag %d not pending in the device.\n",
  5138. __func__, tag);
  5139. reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
  5140. if (reg & (1 << tag)) {
  5141. /* sleep for max. 200us to stabilize */
  5142. usleep_range(100, 200);
  5143. continue;
  5144. }
  5145. /* command completed already */
  5146. dev_err(hba->dev, "%s: cmd at tag %d successfully cleared from DB.\n",
  5147. __func__, tag);
  5148. goto out;
  5149. } else {
  5150. dev_err(hba->dev,
  5151. "%s: no response from device. tag = %d, err %d\n",
  5152. __func__, tag, err);
  5153. if (!err)
  5154. err = resp; /* service response error */
  5155. goto out;
  5156. }
  5157. }
  5158. if (!poll_cnt) {
  5159. err = -EBUSY;
  5160. goto out;
  5161. }
  5162. err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
  5163. UFS_ABORT_TASK, &resp);
  5164. if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
  5165. if (!err) {
  5166. err = resp; /* service response error */
  5167. dev_err(hba->dev, "%s: issued. tag = %d, err %d\n",
  5168. __func__, tag, err);
  5169. }
  5170. goto out;
  5171. }
  5172. err = ufshcd_clear_cmd(hba, tag);
  5173. if (err) {
  5174. dev_err(hba->dev, "%s: Failed clearing cmd at tag %d, err %d\n",
  5175. __func__, tag, err);
  5176. goto out;
  5177. }
  5178. scsi_dma_unmap(cmd);
  5179. spin_lock_irqsave(host->host_lock, flags);
  5180. ufshcd_outstanding_req_clear(hba, tag);
  5181. hba->lrb[tag].cmd = NULL;
  5182. spin_unlock_irqrestore(host->host_lock, flags);
  5183. clear_bit_unlock(tag, &hba->lrb_in_use);
  5184. wake_up(&hba->dev_cmd.tag_wq);
  5185. out:
  5186. if (!err) {
  5187. err = SUCCESS;
  5188. } else {
  5189. dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
  5190. ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs);
  5191. err = FAILED;
  5192. }
  5193. /*
  5194. * This ufshcd_release() corresponds to the original scsi cmd that got
  5195. * aborted here (as we won't get any IRQ for it).
  5196. */
  5197. ufshcd_release(hba);
  5198. return err;
  5199. }
  5200. /**
  5201. * ufshcd_host_reset_and_restore - reset and restore host controller
  5202. * @hba: per-adapter instance
  5203. *
  5204. * Note that host controller reset may issue DME_RESET to
  5205. * local and remote (device) Uni-Pro stack and the attributes
  5206. * are reset to default state.
  5207. *
  5208. * Returns zero on success, non-zero on failure
  5209. */
  5210. static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
  5211. {
  5212. int err;
  5213. unsigned long flags;
  5214. /*
  5215. * Stop the host controller and complete the requests
  5216. * cleared by h/w
  5217. */
  5218. spin_lock_irqsave(hba->host->host_lock, flags);
  5219. ufshcd_hba_stop(hba, false);
  5220. hba->silence_err_logs = true;
  5221. ufshcd_complete_requests(hba);
  5222. hba->silence_err_logs = false;
  5223. spin_unlock_irqrestore(hba->host->host_lock, flags);
  5224. /* scale up clocks to max frequency before full reinitialization */
  5225. ufshcd_scale_clks(hba, true);
  5226. err = ufshcd_hba_enable(hba);
  5227. if (err)
  5228. goto out;
  5229. /* Establish the link again and restore the device */
  5230. err = ufshcd_probe_hba(hba);
  5231. if (!err && (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL))
  5232. err = -EIO;
  5233. out:
  5234. if (err)
  5235. dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err);
  5236. return err;
  5237. }
  5238. /**
  5239. * ufshcd_reset_and_restore - reset and re-initialize host/device
  5240. * @hba: per-adapter instance
  5241. *
  5242. * Reset and recover device, host and re-establish link. This
  5243. * is helpful to recover the communication in fatal error conditions.
  5244. *
  5245. * Returns zero on success, non-zero on failure
  5246. */
  5247. static int ufshcd_reset_and_restore(struct ufs_hba *hba)
  5248. {
  5249. int err = 0;
  5250. int retries = MAX_HOST_RESET_RETRIES;
  5251. do {
  5252. err = ufshcd_host_reset_and_restore(hba);
  5253. } while (err && --retries);
  5254. return err;
  5255. }
  5256. /**
  5257. * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer
  5258. * @cmd: SCSI command pointer
  5259. *
  5260. * Returns SUCCESS/FAILED
  5261. */
  5262. static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd)
  5263. {
  5264. int err;
  5265. unsigned long flags;
  5266. struct ufs_hba *hba;
  5267. hba = shost_priv(cmd->device->host);
  5268. ufshcd_hold(hba, false);
  5269. /*
  5270. * Check if there is any race with fatal error handling.
  5271. * If so, wait for it to complete. Even though fatal error
  5272. * handling does reset and restore in some cases, don't assume
  5273. * anything out of it. We are just avoiding race here.
  5274. */
  5275. do {
  5276. spin_lock_irqsave(hba->host->host_lock, flags);
  5277. if (!(work_pending(&hba->eh_work) ||
  5278. hba->ufshcd_state == UFSHCD_STATE_RESET ||
  5279. hba->ufshcd_state == UFSHCD_STATE_EH_SCHEDULED))
  5280. break;
  5281. spin_unlock_irqrestore(hba->host->host_lock, flags);
  5282. dev_dbg(hba->dev, "%s: reset in progress\n", __func__);
  5283. flush_work(&hba->eh_work);
  5284. } while (1);
  5285. hba->ufshcd_state = UFSHCD_STATE_RESET;
  5286. ufshcd_set_eh_in_progress(hba);
  5287. spin_unlock_irqrestore(hba->host->host_lock, flags);
  5288. err = ufshcd_reset_and_restore(hba);
  5289. spin_lock_irqsave(hba->host->host_lock, flags);
  5290. if (!err) {
  5291. err = SUCCESS;
  5292. hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
  5293. } else {
  5294. err = FAILED;
  5295. hba->ufshcd_state = UFSHCD_STATE_ERROR;
  5296. }
  5297. ufshcd_clear_eh_in_progress(hba);
  5298. spin_unlock_irqrestore(hba->host->host_lock, flags);
  5299. ufshcd_release(hba);
  5300. return err;
  5301. }
  5302. /**
  5303. * ufshcd_get_max_icc_level - calculate the ICC level
  5304. * @sup_curr_uA: max. current supported by the regulator
  5305. * @start_scan: row at the desc table to start scan from
  5306. * @buff: power descriptor buffer
  5307. *
  5308. * Returns calculated max ICC level for specific regulator
  5309. */
  5310. static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, char *buff)
  5311. {
  5312. int i;
  5313. int curr_uA;
  5314. u16 data;
  5315. u16 unit;
  5316. for (i = start_scan; i >= 0; i--) {
  5317. data = be16_to_cpup((__be16 *)&buff[2 * i]);
  5318. unit = (data & ATTR_ICC_LVL_UNIT_MASK) >>
  5319. ATTR_ICC_LVL_UNIT_OFFSET;
  5320. curr_uA = data & ATTR_ICC_LVL_VALUE_MASK;
  5321. switch (unit) {
  5322. case UFSHCD_NANO_AMP:
  5323. curr_uA = curr_uA / 1000;
  5324. break;
  5325. case UFSHCD_MILI_AMP:
  5326. curr_uA = curr_uA * 1000;
  5327. break;
  5328. case UFSHCD_AMP:
  5329. curr_uA = curr_uA * 1000 * 1000;
  5330. break;
  5331. case UFSHCD_MICRO_AMP:
  5332. default:
  5333. break;
  5334. }
  5335. if (sup_curr_uA >= curr_uA)
  5336. break;
  5337. }
  5338. if (i < 0) {
  5339. i = 0;
  5340. pr_err("%s: Couldn't find valid icc_level = %d", __func__, i);
  5341. }
  5342. return (u32)i;
  5343. }
  5344. /**
  5345. * ufshcd_calc_icc_level - calculate the max ICC level
  5346. * In case regulators are not initialized we'll return 0
  5347. * @hba: per-adapter instance
  5348. * @desc_buf: power descriptor buffer to extract ICC levels from.
  5349. * @len: length of desc_buff
  5350. *
  5351. * Returns calculated ICC level
  5352. */
  5353. static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba,
  5354. u8 *desc_buf, int len)
  5355. {
  5356. u32 icc_level = 0;
  5357. if (!hba->vreg_info.vcc || !hba->vreg_info.vccq ||
  5358. !hba->vreg_info.vccq2) {
  5359. dev_err(hba->dev,
  5360. "%s: Regulator capability was not set, actvIccLevel=%d",
  5361. __func__, icc_level);
  5362. goto out;
  5363. }
  5364. if (hba->vreg_info.vcc && hba->vreg_info.vcc->max_uA)
  5365. icc_level = ufshcd_get_max_icc_level(
  5366. hba->vreg_info.vcc->max_uA,
  5367. POWER_DESC_MAX_ACTV_ICC_LVLS - 1,
  5368. &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]);
  5369. if (hba->vreg_info.vccq && hba->vreg_info.vccq->max_uA)
  5370. icc_level = ufshcd_get_max_icc_level(
  5371. hba->vreg_info.vccq->max_uA,
  5372. icc_level,
  5373. &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]);
  5374. if (hba->vreg_info.vccq2 && hba->vreg_info.vccq2->max_uA)
  5375. icc_level = ufshcd_get_max_icc_level(
  5376. hba->vreg_info.vccq2->max_uA,
  5377. icc_level,
  5378. &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]);
  5379. out:
  5380. return icc_level;
  5381. }
  5382. static void ufshcd_init_icc_levels(struct ufs_hba *hba)
  5383. {
  5384. int ret;
  5385. int buff_len = hba->desc_size.pwr_desc;
  5386. u8 *desc_buf;
  5387. desc_buf = kmalloc(buff_len, GFP_KERNEL);
  5388. if (!desc_buf)
  5389. return;
  5390. ret = ufshcd_read_power_desc(hba, desc_buf, buff_len);
  5391. if (ret) {
  5392. dev_err(hba->dev,
  5393. "%s: Failed reading power descriptor.len = %d ret = %d",
  5394. __func__, buff_len, ret);
  5395. goto out;
  5396. }
  5397. hba->init_prefetch_data.icc_level =
  5398. ufshcd_find_max_sup_active_icc_level(hba,
  5399. desc_buf, buff_len);
  5400. dev_dbg(hba->dev, "%s: setting icc_level 0x%x",
  5401. __func__, hba->init_prefetch_data.icc_level);
  5402. ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
  5403. QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0,
  5404. &hba->init_prefetch_data.icc_level);
  5405. if (ret)
  5406. dev_err(hba->dev,
  5407. "%s: Failed configuring bActiveICCLevel = %d ret = %d",
  5408. __func__, hba->init_prefetch_data.icc_level , ret);
  5409. out:
  5410. kfree(desc_buf);
  5411. }
  5412. /**
  5413. * ufshcd_scsi_add_wlus - Adds required W-LUs
  5414. * @hba: per-adapter instance
  5415. *
  5416. * UFS device specification requires the UFS devices to support 4 well known
  5417. * logical units:
  5418. * "REPORT_LUNS" (address: 01h)
  5419. * "UFS Device" (address: 50h)
  5420. * "RPMB" (address: 44h)
  5421. * "BOOT" (address: 30h)
  5422. * UFS device's power management needs to be controlled by "POWER CONDITION"
  5423. * field of SSU (START STOP UNIT) command. But this "power condition" field
  5424. * will take effect only when its sent to "UFS device" well known logical unit
  5425. * hence we require the scsi_device instance to represent this logical unit in
  5426. * order for the UFS host driver to send the SSU command for power management.
  5427. *
  5428. * We also require the scsi_device instance for "RPMB" (Replay Protected Memory
  5429. * Block) LU so user space process can control this LU. User space may also
  5430. * want to have access to BOOT LU.
  5431. *
  5432. * This function adds scsi device instances for each of all well known LUs
  5433. * (except "REPORT LUNS" LU).
  5434. *
  5435. * Returns zero on success (all required W-LUs are added successfully),
  5436. * non-zero error value on failure (if failed to add any of the required W-LU).
  5437. */
  5438. static int ufshcd_scsi_add_wlus(struct ufs_hba *hba)
  5439. {
  5440. int ret = 0;
  5441. struct scsi_device *sdev_rpmb;
  5442. struct scsi_device *sdev_boot;
  5443. hba->sdev_ufs_device = __scsi_add_device(hba->host, 0, 0,
  5444. ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL);
  5445. if (IS_ERR(hba->sdev_ufs_device)) {
  5446. ret = PTR_ERR(hba->sdev_ufs_device);
  5447. hba->sdev_ufs_device = NULL;
  5448. goto out;
  5449. }
  5450. scsi_device_put(hba->sdev_ufs_device);
  5451. sdev_rpmb = __scsi_add_device(hba->host, 0, 0,
  5452. ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL);
  5453. if (IS_ERR(sdev_rpmb)) {
  5454. ret = PTR_ERR(sdev_rpmb);
  5455. goto remove_sdev_ufs_device;
  5456. }
  5457. scsi_device_put(sdev_rpmb);
  5458. sdev_boot = __scsi_add_device(hba->host, 0, 0,
  5459. ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL);
  5460. if (IS_ERR(sdev_boot))
  5461. dev_err(hba->dev, "%s: BOOT WLUN not found\n", __func__);
  5462. else
  5463. scsi_device_put(sdev_boot);
  5464. goto out;
  5465. remove_sdev_ufs_device:
  5466. scsi_remove_device(hba->sdev_ufs_device);
  5467. out:
  5468. return ret;
  5469. }
  5470. static int ufs_get_device_desc(struct ufs_hba *hba,
  5471. struct ufs_dev_desc *dev_desc)
  5472. {
  5473. int err;
  5474. size_t buff_len;
  5475. u8 model_index;
  5476. u8 *desc_buf;
  5477. buff_len = max_t(size_t, hba->desc_size.dev_desc,
  5478. QUERY_DESC_MAX_SIZE + 1);
  5479. desc_buf = kmalloc(buff_len, GFP_KERNEL);
  5480. if (!desc_buf) {
  5481. err = -ENOMEM;
  5482. goto out;
  5483. }
  5484. err = ufshcd_read_device_desc(hba, desc_buf, hba->desc_size.dev_desc);
  5485. if (err) {
  5486. dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n",
  5487. __func__, err);
  5488. goto out;
  5489. }
  5490. /*
  5491. * getting vendor (manufacturerID) and Bank Index in big endian
  5492. * format
  5493. */
  5494. dev_desc->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 |
  5495. desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1];
  5496. model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
  5497. /* Zero-pad entire buffer for string termination. */
  5498. memset(desc_buf, 0, buff_len);
  5499. err = ufshcd_read_string_desc(hba, model_index, desc_buf,
  5500. QUERY_DESC_MAX_SIZE, true/*ASCII*/);
  5501. if (err) {
  5502. dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n",
  5503. __func__, err);
  5504. goto out;
  5505. }
  5506. desc_buf[QUERY_DESC_MAX_SIZE] = '\0';
  5507. strlcpy(dev_desc->model, (desc_buf + QUERY_DESC_HDR_SIZE),
  5508. min_t(u8, desc_buf[QUERY_DESC_LENGTH_OFFSET],
  5509. MAX_MODEL_LEN));
  5510. /* Null terminate the model string */
  5511. dev_desc->model[MAX_MODEL_LEN] = '\0';
  5512. out:
  5513. kfree(desc_buf);
  5514. return err;
  5515. }
  5516. static void ufs_fixup_device_setup(struct ufs_hba *hba,
  5517. struct ufs_dev_desc *dev_desc)
  5518. {
  5519. struct ufs_dev_fix *f;
  5520. for (f = ufs_fixups; f->quirk; f++) {
  5521. if ((f->card.wmanufacturerid == dev_desc->wmanufacturerid ||
  5522. f->card.wmanufacturerid == UFS_ANY_VENDOR) &&
  5523. (STR_PRFX_EQUAL(f->card.model, dev_desc->model) ||
  5524. !strcmp(f->card.model, UFS_ANY_MODEL)))
  5525. hba->dev_quirks |= f->quirk;
  5526. }
  5527. }
  5528. /**
  5529. * ufshcd_tune_pa_tactivate - Tunes PA_TActivate of local UniPro
  5530. * @hba: per-adapter instance
  5531. *
  5532. * PA_TActivate parameter can be tuned manually if UniPro version is less than
  5533. * 1.61. PA_TActivate needs to be greater than or equal to peerM-PHY's
  5534. * RX_MIN_ACTIVATETIME_CAPABILITY attribute. This optimal value can help reduce
  5535. * the hibern8 exit latency.
  5536. *
  5537. * Returns zero on success, non-zero error value on failure.
  5538. */
  5539. static int ufshcd_tune_pa_tactivate(struct ufs_hba *hba)
  5540. {
  5541. int ret = 0;
  5542. u32 peer_rx_min_activatetime = 0, tuned_pa_tactivate;
  5543. ret = ufshcd_dme_peer_get(hba,
  5544. UIC_ARG_MIB_SEL(
  5545. RX_MIN_ACTIVATETIME_CAPABILITY,
  5546. UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
  5547. &peer_rx_min_activatetime);
  5548. if (ret)
  5549. goto out;
  5550. /* make sure proper unit conversion is applied */
  5551. tuned_pa_tactivate =
  5552. ((peer_rx_min_activatetime * RX_MIN_ACTIVATETIME_UNIT_US)
  5553. / PA_TACTIVATE_TIME_UNIT_US);
  5554. ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
  5555. tuned_pa_tactivate);
  5556. out:
  5557. return ret;
  5558. }
  5559. /**
  5560. * ufshcd_tune_pa_hibern8time - Tunes PA_Hibern8Time of local UniPro
  5561. * @hba: per-adapter instance
  5562. *
  5563. * PA_Hibern8Time parameter can be tuned manually if UniPro version is less than
  5564. * 1.61. PA_Hibern8Time needs to be maximum of local M-PHY's
  5565. * TX_HIBERN8TIME_CAPABILITY & peer M-PHY's RX_HIBERN8TIME_CAPABILITY.
  5566. * This optimal value can help reduce the hibern8 exit latency.
  5567. *
  5568. * Returns zero on success, non-zero error value on failure.
  5569. */
  5570. static int ufshcd_tune_pa_hibern8time(struct ufs_hba *hba)
  5571. {
  5572. int ret = 0;
  5573. u32 local_tx_hibern8_time_cap = 0, peer_rx_hibern8_time_cap = 0;
  5574. u32 max_hibern8_time, tuned_pa_hibern8time;
  5575. ret = ufshcd_dme_get(hba,
  5576. UIC_ARG_MIB_SEL(TX_HIBERN8TIME_CAPABILITY,
  5577. UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
  5578. &local_tx_hibern8_time_cap);
  5579. if (ret)
  5580. goto out;
  5581. ret = ufshcd_dme_peer_get(hba,
  5582. UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAPABILITY,
  5583. UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
  5584. &peer_rx_hibern8_time_cap);
  5585. if (ret)
  5586. goto out;
  5587. max_hibern8_time = max(local_tx_hibern8_time_cap,
  5588. peer_rx_hibern8_time_cap);
  5589. /* make sure proper unit conversion is applied */
  5590. tuned_pa_hibern8time = ((max_hibern8_time * HIBERN8TIME_UNIT_US)
  5591. / PA_HIBERN8_TIME_UNIT_US);
  5592. ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
  5593. tuned_pa_hibern8time);
  5594. out:
  5595. return ret;
  5596. }
  5597. /**
  5598. * ufshcd_quirk_tune_host_pa_tactivate - Ensures that host PA_TACTIVATE is
  5599. * less than device PA_TACTIVATE time.
  5600. * @hba: per-adapter instance
  5601. *
  5602. * Some UFS devices require host PA_TACTIVATE to be lower than device
  5603. * PA_TACTIVATE, we need to enable UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE quirk
  5604. * for such devices.
  5605. *
  5606. * Returns zero on success, non-zero error value on failure.
  5607. */
  5608. static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba)
  5609. {
  5610. int ret = 0;
  5611. u32 granularity, peer_granularity;
  5612. u32 pa_tactivate, peer_pa_tactivate;
  5613. u32 pa_tactivate_us, peer_pa_tactivate_us;
  5614. u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100};
  5615. ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
  5616. &granularity);
  5617. if (ret)
  5618. goto out;
  5619. ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
  5620. &peer_granularity);
  5621. if (ret)
  5622. goto out;
  5623. if ((granularity < PA_GRANULARITY_MIN_VAL) ||
  5624. (granularity > PA_GRANULARITY_MAX_VAL)) {
  5625. dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d",
  5626. __func__, granularity);
  5627. return -EINVAL;
  5628. }
  5629. if ((peer_granularity < PA_GRANULARITY_MIN_VAL) ||
  5630. (peer_granularity > PA_GRANULARITY_MAX_VAL)) {
  5631. dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d",
  5632. __func__, peer_granularity);
  5633. return -EINVAL;
  5634. }
  5635. ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate);
  5636. if (ret)
  5637. goto out;
  5638. ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE),
  5639. &peer_pa_tactivate);
  5640. if (ret)
  5641. goto out;
  5642. pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1];
  5643. peer_pa_tactivate_us = peer_pa_tactivate *
  5644. gran_to_us_table[peer_granularity - 1];
  5645. if (pa_tactivate_us > peer_pa_tactivate_us) {
  5646. u32 new_peer_pa_tactivate;
  5647. new_peer_pa_tactivate = pa_tactivate_us /
  5648. gran_to_us_table[peer_granularity - 1];
  5649. new_peer_pa_tactivate++;
  5650. ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
  5651. new_peer_pa_tactivate);
  5652. }
  5653. out:
  5654. return ret;
  5655. }
  5656. static void ufshcd_tune_unipro_params(struct ufs_hba *hba)
  5657. {
  5658. if (ufshcd_is_unipro_pa_params_tuning_req(hba)) {
  5659. ufshcd_tune_pa_tactivate(hba);
  5660. ufshcd_tune_pa_hibern8time(hba);
  5661. }
  5662. if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE)
  5663. /* set 1ms timeout for PA_TACTIVATE */
  5664. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10);
  5665. if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE)
  5666. ufshcd_quirk_tune_host_pa_tactivate(hba);
  5667. ufshcd_vops_apply_dev_quirks(hba);
  5668. }
  5669. static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba)
  5670. {
  5671. int err_reg_hist_size = sizeof(struct ufs_uic_err_reg_hist);
  5672. hba->ufs_stats.hibern8_exit_cnt = 0;
  5673. hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
  5674. memset(&hba->ufs_stats.pa_err, 0, err_reg_hist_size);
  5675. memset(&hba->ufs_stats.dl_err, 0, err_reg_hist_size);
  5676. memset(&hba->ufs_stats.nl_err, 0, err_reg_hist_size);
  5677. memset(&hba->ufs_stats.tl_err, 0, err_reg_hist_size);
  5678. memset(&hba->ufs_stats.dme_err, 0, err_reg_hist_size);
  5679. hba->req_abort_count = 0;
  5680. }
  5681. static void ufshcd_init_desc_sizes(struct ufs_hba *hba)
  5682. {
  5683. int err;
  5684. err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_DEVICE, 0,
  5685. &hba->desc_size.dev_desc);
  5686. if (err)
  5687. hba->desc_size.dev_desc = QUERY_DESC_DEVICE_DEF_SIZE;
  5688. err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_POWER, 0,
  5689. &hba->desc_size.pwr_desc);
  5690. if (err)
  5691. hba->desc_size.pwr_desc = QUERY_DESC_POWER_DEF_SIZE;
  5692. err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_INTERCONNECT, 0,
  5693. &hba->desc_size.interc_desc);
  5694. if (err)
  5695. hba->desc_size.interc_desc = QUERY_DESC_INTERCONNECT_DEF_SIZE;
  5696. err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_CONFIGURATION, 0,
  5697. &hba->desc_size.conf_desc);
  5698. if (err)
  5699. hba->desc_size.conf_desc = QUERY_DESC_CONFIGURATION_DEF_SIZE;
  5700. err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_UNIT, 0,
  5701. &hba->desc_size.unit_desc);
  5702. if (err)
  5703. hba->desc_size.unit_desc = QUERY_DESC_UNIT_DEF_SIZE;
  5704. err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_GEOMETRY, 0,
  5705. &hba->desc_size.geom_desc);
  5706. if (err)
  5707. hba->desc_size.geom_desc = QUERY_DESC_GEOMETRY_DEF_SIZE;
  5708. err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_HEALTH, 0,
  5709. &hba->desc_size.hlth_desc);
  5710. if (err)
  5711. hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE;
  5712. }
  5713. static void ufshcd_def_desc_sizes(struct ufs_hba *hba)
  5714. {
  5715. hba->desc_size.dev_desc = QUERY_DESC_DEVICE_DEF_SIZE;
  5716. hba->desc_size.pwr_desc = QUERY_DESC_POWER_DEF_SIZE;
  5717. hba->desc_size.interc_desc = QUERY_DESC_INTERCONNECT_DEF_SIZE;
  5718. hba->desc_size.conf_desc = QUERY_DESC_CONFIGURATION_DEF_SIZE;
  5719. hba->desc_size.unit_desc = QUERY_DESC_UNIT_DEF_SIZE;
  5720. hba->desc_size.geom_desc = QUERY_DESC_GEOMETRY_DEF_SIZE;
  5721. hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE;
  5722. }
  5723. /**
  5724. * ufshcd_probe_hba - probe hba to detect device and initialize
  5725. * @hba: per-adapter instance
  5726. *
  5727. * Execute link-startup and verify device initialization
  5728. */
  5729. static int ufshcd_probe_hba(struct ufs_hba *hba)
  5730. {
  5731. struct ufs_dev_desc card = {0};
  5732. int ret;
  5733. ktime_t start = ktime_get();
  5734. ret = ufshcd_link_startup(hba);
  5735. if (ret)
  5736. goto out;
  5737. /* set the default level for urgent bkops */
  5738. hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT;
  5739. hba->is_urgent_bkops_lvl_checked = false;
  5740. /* Debug counters initialization */
  5741. ufshcd_clear_dbg_ufs_stats(hba);
  5742. /* UniPro link is active now */
  5743. ufshcd_set_link_active(hba);
  5744. /* Enable Auto-Hibernate if configured */
  5745. ufshcd_auto_hibern8_enable(hba);
  5746. ret = ufshcd_verify_dev_init(hba);
  5747. if (ret)
  5748. goto out;
  5749. ret = ufshcd_complete_dev_init(hba);
  5750. if (ret)
  5751. goto out;
  5752. /* Init check for device descriptor sizes */
  5753. ufshcd_init_desc_sizes(hba);
  5754. ret = ufs_get_device_desc(hba, &card);
  5755. if (ret) {
  5756. dev_err(hba->dev, "%s: Failed getting device info. err = %d\n",
  5757. __func__, ret);
  5758. goto out;
  5759. }
  5760. ufs_fixup_device_setup(hba, &card);
  5761. ufshcd_tune_unipro_params(hba);
  5762. ret = ufshcd_set_vccq_rail_unused(hba,
  5763. (hba->dev_quirks & UFS_DEVICE_NO_VCCQ) ? true : false);
  5764. if (ret)
  5765. goto out;
  5766. /* UFS device is also active now */
  5767. ufshcd_set_ufs_dev_active(hba);
  5768. ufshcd_force_reset_auto_bkops(hba);
  5769. hba->wlun_dev_clr_ua = true;
  5770. if (ufshcd_get_max_pwr_mode(hba)) {
  5771. dev_err(hba->dev,
  5772. "%s: Failed getting max supported power mode\n",
  5773. __func__);
  5774. } else {
  5775. ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
  5776. if (ret) {
  5777. dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
  5778. __func__, ret);
  5779. goto out;
  5780. }
  5781. }
  5782. /* set the state as operational after switching to desired gear */
  5783. hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
  5784. /*
  5785. * If we are in error handling context or in power management callbacks
  5786. * context, no need to scan the host
  5787. */
  5788. if (!ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
  5789. bool flag;
  5790. /* clear any previous UFS device information */
  5791. memset(&hba->dev_info, 0, sizeof(hba->dev_info));
  5792. if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
  5793. QUERY_FLAG_IDN_PWR_ON_WPE, &flag))
  5794. hba->dev_info.f_power_on_wp_en = flag;
  5795. if (!hba->is_init_prefetch)
  5796. ufshcd_init_icc_levels(hba);
  5797. /* Add required well known logical units to scsi mid layer */
  5798. ret = ufshcd_scsi_add_wlus(hba);
  5799. if (ret)
  5800. goto out;
  5801. /* Initialize devfreq after UFS device is detected */
  5802. if (ufshcd_is_clkscaling_supported(hba)) {
  5803. memcpy(&hba->clk_scaling.saved_pwr_info.info,
  5804. &hba->pwr_info,
  5805. sizeof(struct ufs_pa_layer_attr));
  5806. hba->clk_scaling.saved_pwr_info.is_valid = true;
  5807. if (!hba->devfreq) {
  5808. ret = ufshcd_devfreq_init(hba);
  5809. if (ret)
  5810. goto out;
  5811. }
  5812. hba->clk_scaling.is_allowed = true;
  5813. }
  5814. scsi_scan_host(hba->host);
  5815. pm_runtime_put_sync(hba->dev);
  5816. }
  5817. if (!hba->is_init_prefetch)
  5818. hba->is_init_prefetch = true;
  5819. out:
  5820. /*
  5821. * If we failed to initialize the device or the device is not
  5822. * present, turn off the power/clocks etc.
  5823. */
  5824. if (ret && !ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
  5825. pm_runtime_put_sync(hba->dev);
  5826. ufshcd_exit_clk_scaling(hba);
  5827. ufshcd_hba_exit(hba);
  5828. }
  5829. trace_ufshcd_init(dev_name(hba->dev), ret,
  5830. ktime_to_us(ktime_sub(ktime_get(), start)),
  5831. hba->curr_dev_pwr_mode, hba->uic_link_state);
  5832. return ret;
  5833. }
  5834. /**
  5835. * ufshcd_async_scan - asynchronous execution for probing hba
  5836. * @data: data pointer to pass to this function
  5837. * @cookie: cookie data
  5838. */
  5839. static void ufshcd_async_scan(void *data, async_cookie_t cookie)
  5840. {
  5841. struct ufs_hba *hba = (struct ufs_hba *)data;
  5842. ufshcd_probe_hba(hba);
  5843. }
  5844. static enum blk_eh_timer_return ufshcd_eh_timed_out(struct scsi_cmnd *scmd)
  5845. {
  5846. unsigned long flags;
  5847. struct Scsi_Host *host;
  5848. struct ufs_hba *hba;
  5849. int index;
  5850. bool found = false;
  5851. if (!scmd || !scmd->device || !scmd->device->host)
  5852. return BLK_EH_DONE;
  5853. host = scmd->device->host;
  5854. hba = shost_priv(host);
  5855. if (!hba)
  5856. return BLK_EH_DONE;
  5857. spin_lock_irqsave(host->host_lock, flags);
  5858. for_each_set_bit(index, &hba->outstanding_reqs, hba->nutrs) {
  5859. if (hba->lrb[index].cmd == scmd) {
  5860. found = true;
  5861. break;
  5862. }
  5863. }
  5864. spin_unlock_irqrestore(host->host_lock, flags);
  5865. /*
  5866. * Bypass SCSI error handling and reset the block layer timer if this
  5867. * SCSI command was not actually dispatched to UFS driver, otherwise
  5868. * let SCSI layer handle the error as usual.
  5869. */
  5870. return found ? BLK_EH_DONE : BLK_EH_RESET_TIMER;
  5871. }
  5872. static const struct attribute_group *ufshcd_driver_groups[] = {
  5873. &ufs_sysfs_unit_descriptor_group,
  5874. &ufs_sysfs_lun_attributes_group,
  5875. NULL,
  5876. };
  5877. static struct scsi_host_template ufshcd_driver_template = {
  5878. .module = THIS_MODULE,
  5879. .name = UFSHCD,
  5880. .proc_name = UFSHCD,
  5881. .queuecommand = ufshcd_queuecommand,
  5882. .slave_alloc = ufshcd_slave_alloc,
  5883. .slave_configure = ufshcd_slave_configure,
  5884. .slave_destroy = ufshcd_slave_destroy,
  5885. .change_queue_depth = ufshcd_change_queue_depth,
  5886. .eh_abort_handler = ufshcd_abort,
  5887. .eh_device_reset_handler = ufshcd_eh_device_reset_handler,
  5888. .eh_host_reset_handler = ufshcd_eh_host_reset_handler,
  5889. .eh_timed_out = ufshcd_eh_timed_out,
  5890. .this_id = -1,
  5891. .sg_tablesize = SG_ALL,
  5892. .cmd_per_lun = UFSHCD_CMD_PER_LUN,
  5893. .can_queue = UFSHCD_CAN_QUEUE,
  5894. .max_host_blocked = 1,
  5895. .track_queue_depth = 1,
  5896. .sdev_groups = ufshcd_driver_groups,
  5897. };
  5898. static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg,
  5899. int ua)
  5900. {
  5901. int ret;
  5902. if (!vreg)
  5903. return 0;
  5904. /*
  5905. * "set_load" operation shall be required on those regulators
  5906. * which specifically configured current limitation. Otherwise
  5907. * zero max_uA may cause unexpected behavior when regulator is
  5908. * enabled or set as high power mode.
  5909. */
  5910. if (!vreg->max_uA)
  5911. return 0;
  5912. ret = regulator_set_load(vreg->reg, ua);
  5913. if (ret < 0) {
  5914. dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n",
  5915. __func__, vreg->name, ua, ret);
  5916. }
  5917. return ret;
  5918. }
  5919. static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba,
  5920. struct ufs_vreg *vreg)
  5921. {
  5922. if (!vreg)
  5923. return 0;
  5924. else if (vreg->unused)
  5925. return 0;
  5926. else
  5927. return ufshcd_config_vreg_load(hba->dev, vreg,
  5928. UFS_VREG_LPM_LOAD_UA);
  5929. }
  5930. static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
  5931. struct ufs_vreg *vreg)
  5932. {
  5933. if (!vreg)
  5934. return 0;
  5935. else if (vreg->unused)
  5936. return 0;
  5937. else
  5938. return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA);
  5939. }
  5940. static int ufshcd_config_vreg(struct device *dev,
  5941. struct ufs_vreg *vreg, bool on)
  5942. {
  5943. int ret = 0;
  5944. struct regulator *reg;
  5945. const char *name;
  5946. int min_uV, uA_load;
  5947. BUG_ON(!vreg);
  5948. reg = vreg->reg;
  5949. name = vreg->name;
  5950. if (regulator_count_voltages(reg) > 0) {
  5951. if (vreg->min_uV && vreg->max_uV) {
  5952. min_uV = on ? vreg->min_uV : 0;
  5953. ret = regulator_set_voltage(reg, min_uV, vreg->max_uV);
  5954. if (ret) {
  5955. dev_err(dev,
  5956. "%s: %s set voltage failed, err=%d\n",
  5957. __func__, name, ret);
  5958. goto out;
  5959. }
  5960. }
  5961. uA_load = on ? vreg->max_uA : 0;
  5962. ret = ufshcd_config_vreg_load(dev, vreg, uA_load);
  5963. if (ret)
  5964. goto out;
  5965. }
  5966. out:
  5967. return ret;
  5968. }
  5969. static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg)
  5970. {
  5971. int ret = 0;
  5972. if (!vreg)
  5973. goto out;
  5974. else if (vreg->enabled || vreg->unused)
  5975. goto out;
  5976. ret = ufshcd_config_vreg(dev, vreg, true);
  5977. if (!ret)
  5978. ret = regulator_enable(vreg->reg);
  5979. if (!ret)
  5980. vreg->enabled = true;
  5981. else
  5982. dev_err(dev, "%s: %s enable failed, err=%d\n",
  5983. __func__, vreg->name, ret);
  5984. out:
  5985. return ret;
  5986. }
  5987. static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg)
  5988. {
  5989. int ret = 0;
  5990. if (!vreg)
  5991. goto out;
  5992. else if (!vreg->enabled || vreg->unused)
  5993. goto out;
  5994. ret = regulator_disable(vreg->reg);
  5995. if (!ret) {
  5996. /* ignore errors on applying disable config */
  5997. ufshcd_config_vreg(dev, vreg, false);
  5998. vreg->enabled = false;
  5999. } else {
  6000. dev_err(dev, "%s: %s disable failed, err=%d\n",
  6001. __func__, vreg->name, ret);
  6002. }
  6003. out:
  6004. return ret;
  6005. }
  6006. static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on)
  6007. {
  6008. int ret = 0;
  6009. struct device *dev = hba->dev;
  6010. struct ufs_vreg_info *info = &hba->vreg_info;
  6011. if (!info)
  6012. goto out;
  6013. ret = ufshcd_toggle_vreg(dev, info->vcc, on);
  6014. if (ret)
  6015. goto out;
  6016. ret = ufshcd_toggle_vreg(dev, info->vccq, on);
  6017. if (ret)
  6018. goto out;
  6019. ret = ufshcd_toggle_vreg(dev, info->vccq2, on);
  6020. if (ret)
  6021. goto out;
  6022. out:
  6023. if (ret) {
  6024. ufshcd_toggle_vreg(dev, info->vccq2, false);
  6025. ufshcd_toggle_vreg(dev, info->vccq, false);
  6026. ufshcd_toggle_vreg(dev, info->vcc, false);
  6027. }
  6028. return ret;
  6029. }
  6030. static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on)
  6031. {
  6032. struct ufs_vreg_info *info = &hba->vreg_info;
  6033. if (info)
  6034. return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on);
  6035. return 0;
  6036. }
  6037. static int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg)
  6038. {
  6039. int ret = 0;
  6040. if (!vreg)
  6041. goto out;
  6042. vreg->reg = devm_regulator_get(dev, vreg->name);
  6043. if (IS_ERR(vreg->reg)) {
  6044. ret = PTR_ERR(vreg->reg);
  6045. dev_err(dev, "%s: %s get failed, err=%d\n",
  6046. __func__, vreg->name, ret);
  6047. }
  6048. out:
  6049. return ret;
  6050. }
  6051. static int ufshcd_init_vreg(struct ufs_hba *hba)
  6052. {
  6053. int ret = 0;
  6054. struct device *dev = hba->dev;
  6055. struct ufs_vreg_info *info = &hba->vreg_info;
  6056. if (!info)
  6057. goto out;
  6058. ret = ufshcd_get_vreg(dev, info->vcc);
  6059. if (ret)
  6060. goto out;
  6061. ret = ufshcd_get_vreg(dev, info->vccq);
  6062. if (ret)
  6063. goto out;
  6064. ret = ufshcd_get_vreg(dev, info->vccq2);
  6065. out:
  6066. return ret;
  6067. }
  6068. static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
  6069. {
  6070. struct ufs_vreg_info *info = &hba->vreg_info;
  6071. if (info)
  6072. return ufshcd_get_vreg(hba->dev, info->vdd_hba);
  6073. return 0;
  6074. }
  6075. static int ufshcd_set_vccq_rail_unused(struct ufs_hba *hba, bool unused)
  6076. {
  6077. int ret = 0;
  6078. struct ufs_vreg_info *info = &hba->vreg_info;
  6079. if (!info)
  6080. goto out;
  6081. else if (!info->vccq)
  6082. goto out;
  6083. if (unused) {
  6084. /* shut off the rail here */
  6085. ret = ufshcd_toggle_vreg(hba->dev, info->vccq, false);
  6086. /*
  6087. * Mark this rail as no longer used, so it doesn't get enabled
  6088. * later by mistake
  6089. */
  6090. if (!ret)
  6091. info->vccq->unused = true;
  6092. } else {
  6093. /*
  6094. * rail should have been already enabled hence just make sure
  6095. * that unused flag is cleared.
  6096. */
  6097. info->vccq->unused = false;
  6098. }
  6099. out:
  6100. return ret;
  6101. }
  6102. static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
  6103. bool skip_ref_clk)
  6104. {
  6105. int ret = 0;
  6106. struct ufs_clk_info *clki;
  6107. struct list_head *head = &hba->clk_list_head;
  6108. unsigned long flags;
  6109. ktime_t start = ktime_get();
  6110. bool clk_state_changed = false;
  6111. if (list_empty(head))
  6112. goto out;
  6113. /*
  6114. * vendor specific setup_clocks ops may depend on clocks managed by
  6115. * this standard driver hence call the vendor specific setup_clocks
  6116. * before disabling the clocks managed here.
  6117. */
  6118. if (!on) {
  6119. ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE);
  6120. if (ret)
  6121. return ret;
  6122. }
  6123. list_for_each_entry(clki, head, list) {
  6124. if (!IS_ERR_OR_NULL(clki->clk)) {
  6125. if (skip_ref_clk && !strcmp(clki->name, "ref_clk"))
  6126. continue;
  6127. clk_state_changed = on ^ clki->enabled;
  6128. if (on && !clki->enabled) {
  6129. ret = clk_prepare_enable(clki->clk);
  6130. if (ret) {
  6131. dev_err(hba->dev, "%s: %s prepare enable failed, %d\n",
  6132. __func__, clki->name, ret);
  6133. goto out;
  6134. }
  6135. } else if (!on && clki->enabled) {
  6136. clk_disable_unprepare(clki->clk);
  6137. }
  6138. clki->enabled = on;
  6139. dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__,
  6140. clki->name, on ? "en" : "dis");
  6141. }
  6142. }
  6143. /*
  6144. * vendor specific setup_clocks ops may depend on clocks managed by
  6145. * this standard driver hence call the vendor specific setup_clocks
  6146. * after enabling the clocks managed here.
  6147. */
  6148. if (on) {
  6149. ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE);
  6150. if (ret)
  6151. return ret;
  6152. }
  6153. out:
  6154. if (ret) {
  6155. list_for_each_entry(clki, head, list) {
  6156. if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled)
  6157. clk_disable_unprepare(clki->clk);
  6158. }
  6159. } else if (!ret && on) {
  6160. spin_lock_irqsave(hba->host->host_lock, flags);
  6161. hba->clk_gating.state = CLKS_ON;
  6162. trace_ufshcd_clk_gating(dev_name(hba->dev),
  6163. hba->clk_gating.state);
  6164. spin_unlock_irqrestore(hba->host->host_lock, flags);
  6165. }
  6166. if (clk_state_changed)
  6167. trace_ufshcd_profile_clk_gating(dev_name(hba->dev),
  6168. (on ? "on" : "off"),
  6169. ktime_to_us(ktime_sub(ktime_get(), start)), ret);
  6170. return ret;
  6171. }
  6172. static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on)
  6173. {
  6174. return __ufshcd_setup_clocks(hba, on, false);
  6175. }
  6176. static int ufshcd_init_clocks(struct ufs_hba *hba)
  6177. {
  6178. int ret = 0;
  6179. struct ufs_clk_info *clki;
  6180. struct device *dev = hba->dev;
  6181. struct list_head *head = &hba->clk_list_head;
  6182. if (list_empty(head))
  6183. goto out;
  6184. list_for_each_entry(clki, head, list) {
  6185. if (!clki->name)
  6186. continue;
  6187. clki->clk = devm_clk_get(dev, clki->name);
  6188. if (IS_ERR(clki->clk)) {
  6189. ret = PTR_ERR(clki->clk);
  6190. dev_err(dev, "%s: %s clk get failed, %d\n",
  6191. __func__, clki->name, ret);
  6192. goto out;
  6193. }
  6194. if (clki->max_freq) {
  6195. ret = clk_set_rate(clki->clk, clki->max_freq);
  6196. if (ret) {
  6197. dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
  6198. __func__, clki->name,
  6199. clki->max_freq, ret);
  6200. goto out;
  6201. }
  6202. clki->curr_freq = clki->max_freq;
  6203. }
  6204. dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__,
  6205. clki->name, clk_get_rate(clki->clk));
  6206. }
  6207. out:
  6208. return ret;
  6209. }
  6210. static int ufshcd_variant_hba_init(struct ufs_hba *hba)
  6211. {
  6212. int err = 0;
  6213. if (!hba->vops)
  6214. goto out;
  6215. err = ufshcd_vops_init(hba);
  6216. if (err)
  6217. goto out;
  6218. err = ufshcd_vops_setup_regulators(hba, true);
  6219. if (err)
  6220. goto out_exit;
  6221. goto out;
  6222. out_exit:
  6223. ufshcd_vops_exit(hba);
  6224. out:
  6225. if (err)
  6226. dev_err(hba->dev, "%s: variant %s init failed err %d\n",
  6227. __func__, ufshcd_get_var_name(hba), err);
  6228. return err;
  6229. }
  6230. static void ufshcd_variant_hba_exit(struct ufs_hba *hba)
  6231. {
  6232. if (!hba->vops)
  6233. return;
  6234. ufshcd_vops_setup_regulators(hba, false);
  6235. ufshcd_vops_exit(hba);
  6236. }
  6237. static int ufshcd_hba_init(struct ufs_hba *hba)
  6238. {
  6239. int err;
  6240. /*
  6241. * Handle host controller power separately from the UFS device power
  6242. * rails as it will help controlling the UFS host controller power
  6243. * collapse easily which is different than UFS device power collapse.
  6244. * Also, enable the host controller power before we go ahead with rest
  6245. * of the initialization here.
  6246. */
  6247. err = ufshcd_init_hba_vreg(hba);
  6248. if (err)
  6249. goto out;
  6250. err = ufshcd_setup_hba_vreg(hba, true);
  6251. if (err)
  6252. goto out;
  6253. err = ufshcd_init_clocks(hba);
  6254. if (err)
  6255. goto out_disable_hba_vreg;
  6256. err = ufshcd_setup_clocks(hba, true);
  6257. if (err)
  6258. goto out_disable_hba_vreg;
  6259. err = ufshcd_init_vreg(hba);
  6260. if (err)
  6261. goto out_disable_clks;
  6262. err = ufshcd_setup_vreg(hba, true);
  6263. if (err)
  6264. goto out_disable_clks;
  6265. err = ufshcd_variant_hba_init(hba);
  6266. if (err)
  6267. goto out_disable_vreg;
  6268. hba->is_powered = true;
  6269. goto out;
  6270. out_disable_vreg:
  6271. ufshcd_setup_vreg(hba, false);
  6272. out_disable_clks:
  6273. ufshcd_setup_clocks(hba, false);
  6274. out_disable_hba_vreg:
  6275. ufshcd_setup_hba_vreg(hba, false);
  6276. out:
  6277. return err;
  6278. }
  6279. static void ufshcd_hba_exit(struct ufs_hba *hba)
  6280. {
  6281. if (hba->is_powered) {
  6282. ufshcd_variant_hba_exit(hba);
  6283. ufshcd_setup_vreg(hba, false);
  6284. ufshcd_suspend_clkscaling(hba);
  6285. if (ufshcd_is_clkscaling_supported(hba))
  6286. if (hba->devfreq)
  6287. ufshcd_suspend_clkscaling(hba);
  6288. ufshcd_setup_clocks(hba, false);
  6289. ufshcd_setup_hba_vreg(hba, false);
  6290. hba->is_powered = false;
  6291. }
  6292. }
  6293. static int
  6294. ufshcd_send_request_sense(struct ufs_hba *hba, struct scsi_device *sdp)
  6295. {
  6296. unsigned char cmd[6] = {REQUEST_SENSE,
  6297. 0,
  6298. 0,
  6299. 0,
  6300. UFSHCD_REQ_SENSE_SIZE,
  6301. 0};
  6302. char *buffer;
  6303. int ret;
  6304. buffer = kzalloc(UFSHCD_REQ_SENSE_SIZE, GFP_KERNEL);
  6305. if (!buffer) {
  6306. ret = -ENOMEM;
  6307. goto out;
  6308. }
  6309. ret = scsi_execute(sdp, cmd, DMA_FROM_DEVICE, buffer,
  6310. UFSHCD_REQ_SENSE_SIZE, NULL, NULL,
  6311. msecs_to_jiffies(1000), 3, 0, RQF_PM, NULL);
  6312. if (ret)
  6313. pr_err("%s: failed with err %d\n", __func__, ret);
  6314. kfree(buffer);
  6315. out:
  6316. return ret;
  6317. }
  6318. /**
  6319. * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device
  6320. * power mode
  6321. * @hba: per adapter instance
  6322. * @pwr_mode: device power mode to set
  6323. *
  6324. * Returns 0 if requested power mode is set successfully
  6325. * Returns non-zero if failed to set the requested power mode
  6326. */
  6327. static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba,
  6328. enum ufs_dev_pwr_mode pwr_mode)
  6329. {
  6330. unsigned char cmd[6] = { START_STOP };
  6331. struct scsi_sense_hdr sshdr;
  6332. struct scsi_device *sdp;
  6333. unsigned long flags;
  6334. int ret;
  6335. spin_lock_irqsave(hba->host->host_lock, flags);
  6336. sdp = hba->sdev_ufs_device;
  6337. if (sdp) {
  6338. ret = scsi_device_get(sdp);
  6339. if (!ret && !scsi_device_online(sdp)) {
  6340. ret = -ENODEV;
  6341. scsi_device_put(sdp);
  6342. }
  6343. } else {
  6344. ret = -ENODEV;
  6345. }
  6346. spin_unlock_irqrestore(hba->host->host_lock, flags);
  6347. if (ret)
  6348. return ret;
  6349. /*
  6350. * If scsi commands fail, the scsi mid-layer schedules scsi error-
  6351. * handling, which would wait for host to be resumed. Since we know
  6352. * we are functional while we are here, skip host resume in error
  6353. * handling context.
  6354. */
  6355. hba->host->eh_noresume = 1;
  6356. if (hba->wlun_dev_clr_ua) {
  6357. ret = ufshcd_send_request_sense(hba, sdp);
  6358. if (ret)
  6359. goto out;
  6360. /* Unit attention condition is cleared now */
  6361. hba->wlun_dev_clr_ua = false;
  6362. }
  6363. cmd[4] = pwr_mode << 4;
  6364. /*
  6365. * Current function would be generally called from the power management
  6366. * callbacks hence set the RQF_PM flag so that it doesn't resume the
  6367. * already suspended childs.
  6368. */
  6369. ret = scsi_execute(sdp, cmd, DMA_NONE, NULL, 0, NULL, &sshdr,
  6370. START_STOP_TIMEOUT, 0, 0, RQF_PM, NULL);
  6371. if (ret) {
  6372. sdev_printk(KERN_WARNING, sdp,
  6373. "START_STOP failed for power mode: %d, result %x\n",
  6374. pwr_mode, ret);
  6375. if (driver_byte(ret) == DRIVER_SENSE)
  6376. scsi_print_sense_hdr(sdp, NULL, &sshdr);
  6377. }
  6378. if (!ret)
  6379. hba->curr_dev_pwr_mode = pwr_mode;
  6380. out:
  6381. scsi_device_put(sdp);
  6382. hba->host->eh_noresume = 0;
  6383. return ret;
  6384. }
  6385. static int ufshcd_link_state_transition(struct ufs_hba *hba,
  6386. enum uic_link_state req_link_state,
  6387. int check_for_bkops)
  6388. {
  6389. int ret = 0;
  6390. if (req_link_state == hba->uic_link_state)
  6391. return 0;
  6392. if (req_link_state == UIC_LINK_HIBERN8_STATE) {
  6393. ret = ufshcd_uic_hibern8_enter(hba);
  6394. if (!ret)
  6395. ufshcd_set_link_hibern8(hba);
  6396. else
  6397. goto out;
  6398. }
  6399. /*
  6400. * If autobkops is enabled, link can't be turned off because
  6401. * turning off the link would also turn off the device.
  6402. */
  6403. else if ((req_link_state == UIC_LINK_OFF_STATE) &&
  6404. (!check_for_bkops || (check_for_bkops &&
  6405. !hba->auto_bkops_enabled))) {
  6406. /*
  6407. * Let's make sure that link is in low power mode, we are doing
  6408. * this currently by putting the link in Hibern8. Otherway to
  6409. * put the link in low power mode is to send the DME end point
  6410. * to device and then send the DME reset command to local
  6411. * unipro. But putting the link in hibern8 is much faster.
  6412. */
  6413. ret = ufshcd_uic_hibern8_enter(hba);
  6414. if (ret)
  6415. goto out;
  6416. /*
  6417. * Change controller state to "reset state" which
  6418. * should also put the link in off/reset state
  6419. */
  6420. ufshcd_hba_stop(hba, true);
  6421. /*
  6422. * TODO: Check if we need any delay to make sure that
  6423. * controller is reset
  6424. */
  6425. ufshcd_set_link_off(hba);
  6426. }
  6427. out:
  6428. return ret;
  6429. }
  6430. static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
  6431. {
  6432. /*
  6433. * It seems some UFS devices may keep drawing more than sleep current
  6434. * (atleast for 500us) from UFS rails (especially from VCCQ rail).
  6435. * To avoid this situation, add 2ms delay before putting these UFS
  6436. * rails in LPM mode.
  6437. */
  6438. if (!ufshcd_is_link_active(hba) &&
  6439. hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM)
  6440. usleep_range(2000, 2100);
  6441. /*
  6442. * If UFS device is either in UFS_Sleep turn off VCC rail to save some
  6443. * power.
  6444. *
  6445. * If UFS device and link is in OFF state, all power supplies (VCC,
  6446. * VCCQ, VCCQ2) can be turned off if power on write protect is not
  6447. * required. If UFS link is inactive (Hibern8 or OFF state) and device
  6448. * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode.
  6449. *
  6450. * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway
  6451. * in low power state which would save some power.
  6452. */
  6453. if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
  6454. !hba->dev_info.is_lu_power_on_wp) {
  6455. ufshcd_setup_vreg(hba, false);
  6456. } else if (!ufshcd_is_ufs_dev_active(hba)) {
  6457. ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
  6458. if (!ufshcd_is_link_active(hba)) {
  6459. ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
  6460. ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2);
  6461. }
  6462. }
  6463. }
  6464. static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
  6465. {
  6466. int ret = 0;
  6467. if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
  6468. !hba->dev_info.is_lu_power_on_wp) {
  6469. ret = ufshcd_setup_vreg(hba, true);
  6470. } else if (!ufshcd_is_ufs_dev_active(hba)) {
  6471. if (!ret && !ufshcd_is_link_active(hba)) {
  6472. ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
  6473. if (ret)
  6474. goto vcc_disable;
  6475. ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
  6476. if (ret)
  6477. goto vccq_lpm;
  6478. }
  6479. ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
  6480. }
  6481. goto out;
  6482. vccq_lpm:
  6483. ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
  6484. vcc_disable:
  6485. ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
  6486. out:
  6487. return ret;
  6488. }
  6489. static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba)
  6490. {
  6491. if (ufshcd_is_link_off(hba))
  6492. ufshcd_setup_hba_vreg(hba, false);
  6493. }
  6494. static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba)
  6495. {
  6496. if (ufshcd_is_link_off(hba))
  6497. ufshcd_setup_hba_vreg(hba, true);
  6498. }
  6499. /**
  6500. * ufshcd_suspend - helper function for suspend operations
  6501. * @hba: per adapter instance
  6502. * @pm_op: desired low power operation type
  6503. *
  6504. * This function will try to put the UFS device and link into low power
  6505. * mode based on the "rpm_lvl" (Runtime PM level) or "spm_lvl"
  6506. * (System PM level).
  6507. *
  6508. * If this function is called during shutdown, it will make sure that
  6509. * both UFS device and UFS link is powered off.
  6510. *
  6511. * NOTE: UFS device & link must be active before we enter in this function.
  6512. *
  6513. * Returns 0 for success and non-zero for failure
  6514. */
  6515. static int ufshcd_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
  6516. {
  6517. int ret = 0;
  6518. enum ufs_pm_level pm_lvl;
  6519. enum ufs_dev_pwr_mode req_dev_pwr_mode;
  6520. enum uic_link_state req_link_state;
  6521. hba->pm_op_in_progress = 1;
  6522. if (!ufshcd_is_shutdown_pm(pm_op)) {
  6523. pm_lvl = ufshcd_is_runtime_pm(pm_op) ?
  6524. hba->rpm_lvl : hba->spm_lvl;
  6525. req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl);
  6526. req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl);
  6527. } else {
  6528. req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE;
  6529. req_link_state = UIC_LINK_OFF_STATE;
  6530. }
  6531. /*
  6532. * If we can't transition into any of the low power modes
  6533. * just gate the clocks.
  6534. */
  6535. ufshcd_hold(hba, false);
  6536. hba->clk_gating.is_suspended = true;
  6537. if (hba->clk_scaling.is_allowed) {
  6538. cancel_work_sync(&hba->clk_scaling.suspend_work);
  6539. cancel_work_sync(&hba->clk_scaling.resume_work);
  6540. ufshcd_suspend_clkscaling(hba);
  6541. }
  6542. if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE &&
  6543. req_link_state == UIC_LINK_ACTIVE_STATE) {
  6544. goto disable_clks;
  6545. }
  6546. if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) &&
  6547. (req_link_state == hba->uic_link_state))
  6548. goto enable_gating;
  6549. /* UFS device & link must be active before we enter in this function */
  6550. if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) {
  6551. ret = -EINVAL;
  6552. goto enable_gating;
  6553. }
  6554. if (ufshcd_is_runtime_pm(pm_op)) {
  6555. if (ufshcd_can_autobkops_during_suspend(hba)) {
  6556. /*
  6557. * The device is idle with no requests in the queue,
  6558. * allow background operations if bkops status shows
  6559. * that performance might be impacted.
  6560. */
  6561. ret = ufshcd_urgent_bkops(hba);
  6562. if (ret)
  6563. goto enable_gating;
  6564. } else {
  6565. /* make sure that auto bkops is disabled */
  6566. ufshcd_disable_auto_bkops(hba);
  6567. }
  6568. }
  6569. if ((req_dev_pwr_mode != hba->curr_dev_pwr_mode) &&
  6570. ((ufshcd_is_runtime_pm(pm_op) && !hba->auto_bkops_enabled) ||
  6571. !ufshcd_is_runtime_pm(pm_op))) {
  6572. /* ensure that bkops is disabled */
  6573. ufshcd_disable_auto_bkops(hba);
  6574. ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode);
  6575. if (ret)
  6576. goto enable_gating;
  6577. }
  6578. ret = ufshcd_link_state_transition(hba, req_link_state, 1);
  6579. if (ret)
  6580. goto set_dev_active;
  6581. ufshcd_vreg_set_lpm(hba);
  6582. disable_clks:
  6583. /*
  6584. * Call vendor specific suspend callback. As these callbacks may access
  6585. * vendor specific host controller register space call them before the
  6586. * host clocks are ON.
  6587. */
  6588. ret = ufshcd_vops_suspend(hba, pm_op);
  6589. if (ret)
  6590. goto set_link_active;
  6591. if (!ufshcd_is_link_active(hba))
  6592. ufshcd_setup_clocks(hba, false);
  6593. else
  6594. /* If link is active, device ref_clk can't be switched off */
  6595. __ufshcd_setup_clocks(hba, false, true);
  6596. hba->clk_gating.state = CLKS_OFF;
  6597. trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
  6598. /*
  6599. * Disable the host irq as host controller as there won't be any
  6600. * host controller transaction expected till resume.
  6601. */
  6602. ufshcd_disable_irq(hba);
  6603. /* Put the host controller in low power mode if possible */
  6604. ufshcd_hba_vreg_set_lpm(hba);
  6605. goto out;
  6606. set_link_active:
  6607. if (hba->clk_scaling.is_allowed)
  6608. ufshcd_resume_clkscaling(hba);
  6609. ufshcd_vreg_set_hpm(hba);
  6610. if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba))
  6611. ufshcd_set_link_active(hba);
  6612. else if (ufshcd_is_link_off(hba))
  6613. ufshcd_host_reset_and_restore(hba);
  6614. set_dev_active:
  6615. if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE))
  6616. ufshcd_disable_auto_bkops(hba);
  6617. enable_gating:
  6618. if (hba->clk_scaling.is_allowed)
  6619. ufshcd_resume_clkscaling(hba);
  6620. hba->clk_gating.is_suspended = false;
  6621. ufshcd_release(hba);
  6622. out:
  6623. hba->pm_op_in_progress = 0;
  6624. return ret;
  6625. }
  6626. /**
  6627. * ufshcd_resume - helper function for resume operations
  6628. * @hba: per adapter instance
  6629. * @pm_op: runtime PM or system PM
  6630. *
  6631. * This function basically brings the UFS device, UniPro link and controller
  6632. * to active state.
  6633. *
  6634. * Returns 0 for success and non-zero for failure
  6635. */
  6636. static int ufshcd_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
  6637. {
  6638. int ret;
  6639. enum uic_link_state old_link_state;
  6640. hba->pm_op_in_progress = 1;
  6641. old_link_state = hba->uic_link_state;
  6642. ufshcd_hba_vreg_set_hpm(hba);
  6643. /* Make sure clocks are enabled before accessing controller */
  6644. ret = ufshcd_setup_clocks(hba, true);
  6645. if (ret)
  6646. goto out;
  6647. /* enable the host irq as host controller would be active soon */
  6648. ret = ufshcd_enable_irq(hba);
  6649. if (ret)
  6650. goto disable_irq_and_vops_clks;
  6651. ret = ufshcd_vreg_set_hpm(hba);
  6652. if (ret)
  6653. goto disable_irq_and_vops_clks;
  6654. /*
  6655. * Call vendor specific resume callback. As these callbacks may access
  6656. * vendor specific host controller register space call them when the
  6657. * host clocks are ON.
  6658. */
  6659. ret = ufshcd_vops_resume(hba, pm_op);
  6660. if (ret)
  6661. goto disable_vreg;
  6662. if (ufshcd_is_link_hibern8(hba)) {
  6663. ret = ufshcd_uic_hibern8_exit(hba);
  6664. if (!ret)
  6665. ufshcd_set_link_active(hba);
  6666. else
  6667. goto vendor_suspend;
  6668. } else if (ufshcd_is_link_off(hba)) {
  6669. ret = ufshcd_host_reset_and_restore(hba);
  6670. /*
  6671. * ufshcd_host_reset_and_restore() should have already
  6672. * set the link state as active
  6673. */
  6674. if (ret || !ufshcd_is_link_active(hba))
  6675. goto vendor_suspend;
  6676. }
  6677. if (!ufshcd_is_ufs_dev_active(hba)) {
  6678. ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE);
  6679. if (ret)
  6680. goto set_old_link_state;
  6681. }
  6682. if (ufshcd_keep_autobkops_enabled_except_suspend(hba))
  6683. ufshcd_enable_auto_bkops(hba);
  6684. else
  6685. /*
  6686. * If BKOPs operations are urgently needed at this moment then
  6687. * keep auto-bkops enabled or else disable it.
  6688. */
  6689. ufshcd_urgent_bkops(hba);
  6690. hba->clk_gating.is_suspended = false;
  6691. if (hba->clk_scaling.is_allowed)
  6692. ufshcd_resume_clkscaling(hba);
  6693. /* Schedule clock gating in case of no access to UFS device yet */
  6694. ufshcd_release(hba);
  6695. /* Enable Auto-Hibernate if configured */
  6696. ufshcd_auto_hibern8_enable(hba);
  6697. goto out;
  6698. set_old_link_state:
  6699. ufshcd_link_state_transition(hba, old_link_state, 0);
  6700. vendor_suspend:
  6701. ufshcd_vops_suspend(hba, pm_op);
  6702. disable_vreg:
  6703. ufshcd_vreg_set_lpm(hba);
  6704. disable_irq_and_vops_clks:
  6705. ufshcd_disable_irq(hba);
  6706. if (hba->clk_scaling.is_allowed)
  6707. ufshcd_suspend_clkscaling(hba);
  6708. ufshcd_setup_clocks(hba, false);
  6709. out:
  6710. hba->pm_op_in_progress = 0;
  6711. return ret;
  6712. }
  6713. /**
  6714. * ufshcd_system_suspend - system suspend routine
  6715. * @hba: per adapter instance
  6716. *
  6717. * Check the description of ufshcd_suspend() function for more details.
  6718. *
  6719. * Returns 0 for success and non-zero for failure
  6720. */
  6721. int ufshcd_system_suspend(struct ufs_hba *hba)
  6722. {
  6723. int ret = 0;
  6724. ktime_t start = ktime_get();
  6725. if (!hba || !hba->is_powered)
  6726. return 0;
  6727. if ((ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl) ==
  6728. hba->curr_dev_pwr_mode) &&
  6729. (ufs_get_pm_lvl_to_link_pwr_state(hba->spm_lvl) ==
  6730. hba->uic_link_state))
  6731. goto out;
  6732. if (pm_runtime_suspended(hba->dev)) {
  6733. /*
  6734. * UFS device and/or UFS link low power states during runtime
  6735. * suspend seems to be different than what is expected during
  6736. * system suspend. Hence runtime resume the devic & link and
  6737. * let the system suspend low power states to take effect.
  6738. * TODO: If resume takes longer time, we might have optimize
  6739. * it in future by not resuming everything if possible.
  6740. */
  6741. ret = ufshcd_runtime_resume(hba);
  6742. if (ret)
  6743. goto out;
  6744. }
  6745. ret = ufshcd_suspend(hba, UFS_SYSTEM_PM);
  6746. out:
  6747. trace_ufshcd_system_suspend(dev_name(hba->dev), ret,
  6748. ktime_to_us(ktime_sub(ktime_get(), start)),
  6749. hba->curr_dev_pwr_mode, hba->uic_link_state);
  6750. if (!ret)
  6751. hba->is_sys_suspended = true;
  6752. return ret;
  6753. }
  6754. EXPORT_SYMBOL(ufshcd_system_suspend);
  6755. /**
  6756. * ufshcd_system_resume - system resume routine
  6757. * @hba: per adapter instance
  6758. *
  6759. * Returns 0 for success and non-zero for failure
  6760. */
  6761. int ufshcd_system_resume(struct ufs_hba *hba)
  6762. {
  6763. int ret = 0;
  6764. ktime_t start = ktime_get();
  6765. if (!hba)
  6766. return -EINVAL;
  6767. if (!hba->is_powered || pm_runtime_suspended(hba->dev))
  6768. /*
  6769. * Let the runtime resume take care of resuming
  6770. * if runtime suspended.
  6771. */
  6772. goto out;
  6773. else
  6774. ret = ufshcd_resume(hba, UFS_SYSTEM_PM);
  6775. out:
  6776. trace_ufshcd_system_resume(dev_name(hba->dev), ret,
  6777. ktime_to_us(ktime_sub(ktime_get(), start)),
  6778. hba->curr_dev_pwr_mode, hba->uic_link_state);
  6779. if (!ret)
  6780. hba->is_sys_suspended = false;
  6781. return ret;
  6782. }
  6783. EXPORT_SYMBOL(ufshcd_system_resume);
  6784. /**
  6785. * ufshcd_runtime_suspend - runtime suspend routine
  6786. * @hba: per adapter instance
  6787. *
  6788. * Check the description of ufshcd_suspend() function for more details.
  6789. *
  6790. * Returns 0 for success and non-zero for failure
  6791. */
  6792. int ufshcd_runtime_suspend(struct ufs_hba *hba)
  6793. {
  6794. int ret = 0;
  6795. ktime_t start = ktime_get();
  6796. if (!hba)
  6797. return -EINVAL;
  6798. if (!hba->is_powered)
  6799. goto out;
  6800. else
  6801. ret = ufshcd_suspend(hba, UFS_RUNTIME_PM);
  6802. out:
  6803. trace_ufshcd_runtime_suspend(dev_name(hba->dev), ret,
  6804. ktime_to_us(ktime_sub(ktime_get(), start)),
  6805. hba->curr_dev_pwr_mode, hba->uic_link_state);
  6806. return ret;
  6807. }
  6808. EXPORT_SYMBOL(ufshcd_runtime_suspend);
  6809. /**
  6810. * ufshcd_runtime_resume - runtime resume routine
  6811. * @hba: per adapter instance
  6812. *
  6813. * This function basically brings the UFS device, UniPro link and controller
  6814. * to active state. Following operations are done in this function:
  6815. *
  6816. * 1. Turn on all the controller related clocks
  6817. * 2. Bring the UniPro link out of Hibernate state
  6818. * 3. If UFS device is in sleep state, turn ON VCC rail and bring the UFS device
  6819. * to active state.
  6820. * 4. If auto-bkops is enabled on the device, disable it.
  6821. *
  6822. * So following would be the possible power state after this function return
  6823. * successfully:
  6824. * S1: UFS device in Active state with VCC rail ON
  6825. * UniPro link in Active state
  6826. * All the UFS/UniPro controller clocks are ON
  6827. *
  6828. * Returns 0 for success and non-zero for failure
  6829. */
  6830. int ufshcd_runtime_resume(struct ufs_hba *hba)
  6831. {
  6832. int ret = 0;
  6833. ktime_t start = ktime_get();
  6834. if (!hba)
  6835. return -EINVAL;
  6836. if (!hba->is_powered)
  6837. goto out;
  6838. else
  6839. ret = ufshcd_resume(hba, UFS_RUNTIME_PM);
  6840. out:
  6841. trace_ufshcd_runtime_resume(dev_name(hba->dev), ret,
  6842. ktime_to_us(ktime_sub(ktime_get(), start)),
  6843. hba->curr_dev_pwr_mode, hba->uic_link_state);
  6844. return ret;
  6845. }
  6846. EXPORT_SYMBOL(ufshcd_runtime_resume);
  6847. int ufshcd_runtime_idle(struct ufs_hba *hba)
  6848. {
  6849. return 0;
  6850. }
  6851. EXPORT_SYMBOL(ufshcd_runtime_idle);
  6852. /**
  6853. * ufshcd_shutdown - shutdown routine
  6854. * @hba: per adapter instance
  6855. *
  6856. * This function would power off both UFS device and UFS link.
  6857. *
  6858. * Returns 0 always to allow force shutdown even in case of errors.
  6859. */
  6860. int ufshcd_shutdown(struct ufs_hba *hba)
  6861. {
  6862. int ret = 0;
  6863. if (!hba->is_powered)
  6864. goto out;
  6865. if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba))
  6866. goto out;
  6867. if (pm_runtime_suspended(hba->dev)) {
  6868. ret = ufshcd_runtime_resume(hba);
  6869. if (ret)
  6870. goto out;
  6871. }
  6872. ret = ufshcd_suspend(hba, UFS_SHUTDOWN_PM);
  6873. out:
  6874. if (ret)
  6875. dev_err(hba->dev, "%s failed, err %d\n", __func__, ret);
  6876. /* allow force shutdown even in case of errors */
  6877. return 0;
  6878. }
  6879. EXPORT_SYMBOL(ufshcd_shutdown);
  6880. /**
  6881. * ufshcd_remove - de-allocate SCSI host and host memory space
  6882. * data structure memory
  6883. * @hba: per adapter instance
  6884. */
  6885. void ufshcd_remove(struct ufs_hba *hba)
  6886. {
  6887. ufs_sysfs_remove_nodes(hba->dev);
  6888. scsi_remove_host(hba->host);
  6889. /* disable interrupts */
  6890. ufshcd_disable_intr(hba, hba->intr_mask);
  6891. ufshcd_hba_stop(hba, true);
  6892. ufshcd_exit_clk_scaling(hba);
  6893. ufshcd_exit_clk_gating(hba);
  6894. if (ufshcd_is_clkscaling_supported(hba))
  6895. device_remove_file(hba->dev, &hba->clk_scaling.enable_attr);
  6896. ufshcd_hba_exit(hba);
  6897. }
  6898. EXPORT_SYMBOL_GPL(ufshcd_remove);
  6899. /**
  6900. * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA)
  6901. * @hba: pointer to Host Bus Adapter (HBA)
  6902. */
  6903. void ufshcd_dealloc_host(struct ufs_hba *hba)
  6904. {
  6905. scsi_host_put(hba->host);
  6906. }
  6907. EXPORT_SYMBOL_GPL(ufshcd_dealloc_host);
  6908. /**
  6909. * ufshcd_set_dma_mask - Set dma mask based on the controller
  6910. * addressing capability
  6911. * @hba: per adapter instance
  6912. *
  6913. * Returns 0 for success, non-zero for failure
  6914. */
  6915. static int ufshcd_set_dma_mask(struct ufs_hba *hba)
  6916. {
  6917. if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
  6918. if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64)))
  6919. return 0;
  6920. }
  6921. return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
  6922. }
  6923. /**
  6924. * ufshcd_alloc_host - allocate Host Bus Adapter (HBA)
  6925. * @dev: pointer to device handle
  6926. * @hba_handle: driver private handle
  6927. * Returns 0 on success, non-zero value on failure
  6928. */
  6929. int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle)
  6930. {
  6931. struct Scsi_Host *host;
  6932. struct ufs_hba *hba;
  6933. int err = 0;
  6934. if (!dev) {
  6935. dev_err(dev,
  6936. "Invalid memory reference for dev is NULL\n");
  6937. err = -ENODEV;
  6938. goto out_error;
  6939. }
  6940. host = scsi_host_alloc(&ufshcd_driver_template,
  6941. sizeof(struct ufs_hba));
  6942. if (!host) {
  6943. dev_err(dev, "scsi_host_alloc failed\n");
  6944. err = -ENOMEM;
  6945. goto out_error;
  6946. }
  6947. /*
  6948. * Do not use blk-mq at this time because blk-mq does not support
  6949. * runtime pm.
  6950. */
  6951. host->use_blk_mq = false;
  6952. hba = shost_priv(host);
  6953. hba->host = host;
  6954. hba->dev = dev;
  6955. *hba_handle = hba;
  6956. INIT_LIST_HEAD(&hba->clk_list_head);
  6957. out_error:
  6958. return err;
  6959. }
  6960. EXPORT_SYMBOL(ufshcd_alloc_host);
  6961. /**
  6962. * ufshcd_init - Driver initialization routine
  6963. * @hba: per-adapter instance
  6964. * @mmio_base: base register address
  6965. * @irq: Interrupt line of device
  6966. * Returns 0 on success, non-zero value on failure
  6967. */
  6968. int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
  6969. {
  6970. int err;
  6971. struct Scsi_Host *host = hba->host;
  6972. struct device *dev = hba->dev;
  6973. if (!mmio_base) {
  6974. dev_err(hba->dev,
  6975. "Invalid memory reference for mmio_base is NULL\n");
  6976. err = -ENODEV;
  6977. goto out_error;
  6978. }
  6979. hba->mmio_base = mmio_base;
  6980. hba->irq = irq;
  6981. /* Set descriptor lengths to specification defaults */
  6982. ufshcd_def_desc_sizes(hba);
  6983. err = ufshcd_hba_init(hba);
  6984. if (err)
  6985. goto out_error;
  6986. /* Read capabilities registers */
  6987. ufshcd_hba_capabilities(hba);
  6988. /* Get UFS version supported by the controller */
  6989. hba->ufs_version = ufshcd_get_ufs_version(hba);
  6990. if ((hba->ufs_version != UFSHCI_VERSION_10) &&
  6991. (hba->ufs_version != UFSHCI_VERSION_11) &&
  6992. (hba->ufs_version != UFSHCI_VERSION_20) &&
  6993. (hba->ufs_version != UFSHCI_VERSION_21))
  6994. dev_err(hba->dev, "invalid UFS version 0x%x\n",
  6995. hba->ufs_version);
  6996. /* Get Interrupt bit mask per version */
  6997. hba->intr_mask = ufshcd_get_intr_mask(hba);
  6998. err = ufshcd_set_dma_mask(hba);
  6999. if (err) {
  7000. dev_err(hba->dev, "set dma mask failed\n");
  7001. goto out_disable;
  7002. }
  7003. /* Allocate memory for host memory space */
  7004. err = ufshcd_memory_alloc(hba);
  7005. if (err) {
  7006. dev_err(hba->dev, "Memory allocation failed\n");
  7007. goto out_disable;
  7008. }
  7009. /* Configure LRB */
  7010. ufshcd_host_memory_configure(hba);
  7011. host->can_queue = hba->nutrs;
  7012. host->cmd_per_lun = hba->nutrs;
  7013. host->max_id = UFSHCD_MAX_ID;
  7014. host->max_lun = UFS_MAX_LUNS;
  7015. host->max_channel = UFSHCD_MAX_CHANNEL;
  7016. host->unique_id = host->host_no;
  7017. host->max_cmd_len = MAX_CDB_SIZE;
  7018. hba->max_pwr_info.is_valid = false;
  7019. /* Initailize wait queue for task management */
  7020. init_waitqueue_head(&hba->tm_wq);
  7021. init_waitqueue_head(&hba->tm_tag_wq);
  7022. /* Initialize work queues */
  7023. INIT_WORK(&hba->eh_work, ufshcd_err_handler);
  7024. INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
  7025. /* Initialize UIC command mutex */
  7026. mutex_init(&hba->uic_cmd_mutex);
  7027. /* Initialize mutex for device management commands */
  7028. mutex_init(&hba->dev_cmd.lock);
  7029. init_rwsem(&hba->clk_scaling_lock);
  7030. /* Initialize device management tag acquire wait queue */
  7031. init_waitqueue_head(&hba->dev_cmd.tag_wq);
  7032. ufshcd_init_clk_gating(hba);
  7033. ufshcd_init_clk_scaling(hba);
  7034. /*
  7035. * In order to avoid any spurious interrupt immediately after
  7036. * registering UFS controller interrupt handler, clear any pending UFS
  7037. * interrupt status and disable all the UFS interrupts.
  7038. */
  7039. ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),
  7040. REG_INTERRUPT_STATUS);
  7041. ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
  7042. /*
  7043. * Make sure that UFS interrupts are disabled and any pending interrupt
  7044. * status is cleared before registering UFS interrupt handler.
  7045. */
  7046. mb();
  7047. /* IRQ registration */
  7048. err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
  7049. if (err) {
  7050. dev_err(hba->dev, "request irq failed\n");
  7051. goto exit_gating;
  7052. } else {
  7053. hba->is_irq_enabled = true;
  7054. }
  7055. err = scsi_add_host(host, hba->dev);
  7056. if (err) {
  7057. dev_err(hba->dev, "scsi_add_host failed\n");
  7058. goto exit_gating;
  7059. }
  7060. /* Host controller enable */
  7061. err = ufshcd_hba_enable(hba);
  7062. if (err) {
  7063. dev_err(hba->dev, "Host controller enable failed\n");
  7064. ufshcd_print_host_regs(hba);
  7065. ufshcd_print_host_state(hba);
  7066. goto out_remove_scsi_host;
  7067. }
  7068. /*
  7069. * Set the default power management level for runtime and system PM.
  7070. * Default power saving mode is to keep UFS link in Hibern8 state
  7071. * and UFS device in sleep state.
  7072. */
  7073. hba->rpm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
  7074. UFS_SLEEP_PWR_MODE,
  7075. UIC_LINK_HIBERN8_STATE);
  7076. hba->spm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
  7077. UFS_SLEEP_PWR_MODE,
  7078. UIC_LINK_HIBERN8_STATE);
  7079. /* Set the default auto-hiberate idle timer value to 150 ms */
  7080. if (hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT) {
  7081. hba->ahit = FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 150) |
  7082. FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3);
  7083. }
  7084. /* Hold auto suspend until async scan completes */
  7085. pm_runtime_get_sync(dev);
  7086. atomic_set(&hba->scsi_block_reqs_cnt, 0);
  7087. /*
  7088. * We are assuming that device wasn't put in sleep/power-down
  7089. * state exclusively during the boot stage before kernel.
  7090. * This assumption helps avoid doing link startup twice during
  7091. * ufshcd_probe_hba().
  7092. */
  7093. ufshcd_set_ufs_dev_active(hba);
  7094. async_schedule(ufshcd_async_scan, hba);
  7095. ufs_sysfs_add_nodes(hba->dev);
  7096. return 0;
  7097. out_remove_scsi_host:
  7098. scsi_remove_host(hba->host);
  7099. exit_gating:
  7100. ufshcd_exit_clk_scaling(hba);
  7101. ufshcd_exit_clk_gating(hba);
  7102. out_disable:
  7103. hba->is_irq_enabled = false;
  7104. ufshcd_hba_exit(hba);
  7105. out_error:
  7106. return err;
  7107. }
  7108. EXPORT_SYMBOL_GPL(ufshcd_init);
  7109. MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
  7110. MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
  7111. MODULE_DESCRIPTION("Generic UFS host controller driver Core");
  7112. MODULE_LICENSE("GPL");
  7113. MODULE_VERSION(UFSHCD_DRIVER_VERSION);