ql4_83xx.c 44 KB

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  1. /*
  2. * QLogic iSCSI HBA Driver
  3. * Copyright (c) 2003-2013 QLogic Corporation
  4. *
  5. * See LICENSE.qla4xxx for copyright and licensing details.
  6. */
  7. #include <linux/ratelimit.h>
  8. #include "ql4_def.h"
  9. #include "ql4_version.h"
  10. #include "ql4_glbl.h"
  11. #include "ql4_dbg.h"
  12. #include "ql4_inline.h"
  13. uint32_t qla4_83xx_rd_reg(struct scsi_qla_host *ha, ulong addr)
  14. {
  15. return readl((void __iomem *)(ha->nx_pcibase + addr));
  16. }
  17. void qla4_83xx_wr_reg(struct scsi_qla_host *ha, ulong addr, uint32_t val)
  18. {
  19. writel(val, (void __iomem *)(ha->nx_pcibase + addr));
  20. }
  21. static int qla4_83xx_set_win_base(struct scsi_qla_host *ha, uint32_t addr)
  22. {
  23. uint32_t val;
  24. int ret_val = QLA_SUCCESS;
  25. qla4_83xx_wr_reg(ha, QLA83XX_CRB_WIN_FUNC(ha->func_num), addr);
  26. val = qla4_83xx_rd_reg(ha, QLA83XX_CRB_WIN_FUNC(ha->func_num));
  27. if (val != addr) {
  28. ql4_printk(KERN_ERR, ha, "%s: Failed to set register window : addr written 0x%x, read 0x%x!\n",
  29. __func__, addr, val);
  30. ret_val = QLA_ERROR;
  31. }
  32. return ret_val;
  33. }
  34. int qla4_83xx_rd_reg_indirect(struct scsi_qla_host *ha, uint32_t addr,
  35. uint32_t *data)
  36. {
  37. int ret_val;
  38. ret_val = qla4_83xx_set_win_base(ha, addr);
  39. if (ret_val == QLA_SUCCESS) {
  40. *data = qla4_83xx_rd_reg(ha, QLA83XX_WILDCARD);
  41. } else {
  42. *data = 0xffffffff;
  43. ql4_printk(KERN_ERR, ha, "%s: failed read of addr 0x%x!\n",
  44. __func__, addr);
  45. }
  46. return ret_val;
  47. }
  48. int qla4_83xx_wr_reg_indirect(struct scsi_qla_host *ha, uint32_t addr,
  49. uint32_t data)
  50. {
  51. int ret_val;
  52. ret_val = qla4_83xx_set_win_base(ha, addr);
  53. if (ret_val == QLA_SUCCESS)
  54. qla4_83xx_wr_reg(ha, QLA83XX_WILDCARD, data);
  55. else
  56. ql4_printk(KERN_ERR, ha, "%s: failed wrt to addr 0x%x, data 0x%x\n",
  57. __func__, addr, data);
  58. return ret_val;
  59. }
  60. static int qla4_83xx_flash_lock(struct scsi_qla_host *ha)
  61. {
  62. int lock_owner;
  63. int timeout = 0;
  64. uint32_t lock_status = 0;
  65. int ret_val = QLA_SUCCESS;
  66. while (lock_status == 0) {
  67. lock_status = qla4_83xx_rd_reg(ha, QLA83XX_FLASH_LOCK);
  68. if (lock_status)
  69. break;
  70. if (++timeout >= QLA83XX_FLASH_LOCK_TIMEOUT / 20) {
  71. lock_owner = qla4_83xx_rd_reg(ha,
  72. QLA83XX_FLASH_LOCK_ID);
  73. ql4_printk(KERN_ERR, ha, "%s: flash lock by func %d failed, held by func %d\n",
  74. __func__, ha->func_num, lock_owner);
  75. ret_val = QLA_ERROR;
  76. break;
  77. }
  78. msleep(20);
  79. }
  80. qla4_83xx_wr_reg(ha, QLA83XX_FLASH_LOCK_ID, ha->func_num);
  81. return ret_val;
  82. }
  83. static void qla4_83xx_flash_unlock(struct scsi_qla_host *ha)
  84. {
  85. /* Reading FLASH_UNLOCK register unlocks the Flash */
  86. qla4_83xx_wr_reg(ha, QLA83XX_FLASH_LOCK_ID, 0xFF);
  87. qla4_83xx_rd_reg(ha, QLA83XX_FLASH_UNLOCK);
  88. }
  89. int qla4_83xx_flash_read_u32(struct scsi_qla_host *ha, uint32_t flash_addr,
  90. uint8_t *p_data, int u32_word_count)
  91. {
  92. int i;
  93. uint32_t u32_word;
  94. uint32_t addr = flash_addr;
  95. int ret_val = QLA_SUCCESS;
  96. ret_val = qla4_83xx_flash_lock(ha);
  97. if (ret_val == QLA_ERROR)
  98. goto exit_lock_error;
  99. if (addr & 0x03) {
  100. ql4_printk(KERN_ERR, ha, "%s: Illegal addr = 0x%x\n",
  101. __func__, addr);
  102. ret_val = QLA_ERROR;
  103. goto exit_flash_read;
  104. }
  105. for (i = 0; i < u32_word_count; i++) {
  106. ret_val = qla4_83xx_wr_reg_indirect(ha,
  107. QLA83XX_FLASH_DIRECT_WINDOW,
  108. (addr & 0xFFFF0000));
  109. if (ret_val == QLA_ERROR) {
  110. ql4_printk(KERN_ERR, ha, "%s: failed to write addr 0x%x to FLASH_DIRECT_WINDOW\n!",
  111. __func__, addr);
  112. goto exit_flash_read;
  113. }
  114. ret_val = qla4_83xx_rd_reg_indirect(ha,
  115. QLA83XX_FLASH_DIRECT_DATA(addr),
  116. &u32_word);
  117. if (ret_val == QLA_ERROR) {
  118. ql4_printk(KERN_ERR, ha, "%s: failed to read addr 0x%x!\n",
  119. __func__, addr);
  120. goto exit_flash_read;
  121. }
  122. *(__le32 *)p_data = le32_to_cpu(u32_word);
  123. p_data = p_data + 4;
  124. addr = addr + 4;
  125. }
  126. exit_flash_read:
  127. qla4_83xx_flash_unlock(ha);
  128. exit_lock_error:
  129. return ret_val;
  130. }
  131. int qla4_83xx_lockless_flash_read_u32(struct scsi_qla_host *ha,
  132. uint32_t flash_addr, uint8_t *p_data,
  133. int u32_word_count)
  134. {
  135. uint32_t i;
  136. uint32_t u32_word;
  137. uint32_t flash_offset;
  138. uint32_t addr = flash_addr;
  139. int ret_val = QLA_SUCCESS;
  140. flash_offset = addr & (QLA83XX_FLASH_SECTOR_SIZE - 1);
  141. if (addr & 0x3) {
  142. ql4_printk(KERN_ERR, ha, "%s: Illegal addr = 0x%x\n",
  143. __func__, addr);
  144. ret_val = QLA_ERROR;
  145. goto exit_lockless_read;
  146. }
  147. ret_val = qla4_83xx_wr_reg_indirect(ha, QLA83XX_FLASH_DIRECT_WINDOW,
  148. addr);
  149. if (ret_val == QLA_ERROR) {
  150. ql4_printk(KERN_ERR, ha, "%s: failed to write addr 0x%x to FLASH_DIRECT_WINDOW!\n",
  151. __func__, addr);
  152. goto exit_lockless_read;
  153. }
  154. /* Check if data is spread across multiple sectors */
  155. if ((flash_offset + (u32_word_count * sizeof(uint32_t))) >
  156. (QLA83XX_FLASH_SECTOR_SIZE - 1)) {
  157. /* Multi sector read */
  158. for (i = 0; i < u32_word_count; i++) {
  159. ret_val = qla4_83xx_rd_reg_indirect(ha,
  160. QLA83XX_FLASH_DIRECT_DATA(addr),
  161. &u32_word);
  162. if (ret_val == QLA_ERROR) {
  163. ql4_printk(KERN_ERR, ha, "%s: failed to read addr 0x%x!\n",
  164. __func__, addr);
  165. goto exit_lockless_read;
  166. }
  167. *(__le32 *)p_data = le32_to_cpu(u32_word);
  168. p_data = p_data + 4;
  169. addr = addr + 4;
  170. flash_offset = flash_offset + 4;
  171. if (flash_offset > (QLA83XX_FLASH_SECTOR_SIZE - 1)) {
  172. /* This write is needed once for each sector */
  173. ret_val = qla4_83xx_wr_reg_indirect(ha,
  174. QLA83XX_FLASH_DIRECT_WINDOW,
  175. addr);
  176. if (ret_val == QLA_ERROR) {
  177. ql4_printk(KERN_ERR, ha, "%s: failed to write addr 0x%x to FLASH_DIRECT_WINDOW!\n",
  178. __func__, addr);
  179. goto exit_lockless_read;
  180. }
  181. flash_offset = 0;
  182. }
  183. }
  184. } else {
  185. /* Single sector read */
  186. for (i = 0; i < u32_word_count; i++) {
  187. ret_val = qla4_83xx_rd_reg_indirect(ha,
  188. QLA83XX_FLASH_DIRECT_DATA(addr),
  189. &u32_word);
  190. if (ret_val == QLA_ERROR) {
  191. ql4_printk(KERN_ERR, ha, "%s: failed to read addr 0x%x!\n",
  192. __func__, addr);
  193. goto exit_lockless_read;
  194. }
  195. *(__le32 *)p_data = le32_to_cpu(u32_word);
  196. p_data = p_data + 4;
  197. addr = addr + 4;
  198. }
  199. }
  200. exit_lockless_read:
  201. return ret_val;
  202. }
  203. void qla4_83xx_rom_lock_recovery(struct scsi_qla_host *ha)
  204. {
  205. if (qla4_83xx_flash_lock(ha))
  206. ql4_printk(KERN_INFO, ha, "%s: Resetting rom lock\n", __func__);
  207. /*
  208. * We got the lock, or someone else is holding the lock
  209. * since we are restting, forcefully unlock
  210. */
  211. qla4_83xx_flash_unlock(ha);
  212. }
  213. #define INTENT_TO_RECOVER 0x01
  214. #define PROCEED_TO_RECOVER 0x02
  215. static int qla4_83xx_lock_recovery(struct scsi_qla_host *ha)
  216. {
  217. uint32_t lock = 0, lockid;
  218. int ret_val = QLA_ERROR;
  219. lockid = ha->isp_ops->rd_reg_direct(ha, QLA83XX_DRV_LOCKRECOVERY);
  220. /* Check for other Recovery in progress, go wait */
  221. if ((lockid & 0x3) != 0)
  222. goto exit_lock_recovery;
  223. /* Intent to Recover */
  224. ha->isp_ops->wr_reg_direct(ha, QLA83XX_DRV_LOCKRECOVERY,
  225. (ha->func_num << 2) | INTENT_TO_RECOVER);
  226. msleep(200);
  227. /* Check Intent to Recover is advertised */
  228. lockid = ha->isp_ops->rd_reg_direct(ha, QLA83XX_DRV_LOCKRECOVERY);
  229. if ((lockid & 0x3C) != (ha->func_num << 2))
  230. goto exit_lock_recovery;
  231. ql4_printk(KERN_INFO, ha, "%s: IDC Lock recovery initiated for func %d\n",
  232. __func__, ha->func_num);
  233. /* Proceed to Recover */
  234. ha->isp_ops->wr_reg_direct(ha, QLA83XX_DRV_LOCKRECOVERY,
  235. (ha->func_num << 2) | PROCEED_TO_RECOVER);
  236. /* Force Unlock */
  237. ha->isp_ops->wr_reg_direct(ha, QLA83XX_DRV_LOCK_ID, 0xFF);
  238. ha->isp_ops->rd_reg_direct(ha, QLA83XX_DRV_UNLOCK);
  239. /* Clear bits 0-5 in IDC_RECOVERY register*/
  240. ha->isp_ops->wr_reg_direct(ha, QLA83XX_DRV_LOCKRECOVERY, 0);
  241. /* Get lock */
  242. lock = ha->isp_ops->rd_reg_direct(ha, QLA83XX_DRV_LOCK);
  243. if (lock) {
  244. lockid = ha->isp_ops->rd_reg_direct(ha, QLA83XX_DRV_LOCK_ID);
  245. lockid = ((lockid + (1 << 8)) & ~0xFF) | ha->func_num;
  246. ha->isp_ops->wr_reg_direct(ha, QLA83XX_DRV_LOCK_ID, lockid);
  247. ret_val = QLA_SUCCESS;
  248. }
  249. exit_lock_recovery:
  250. return ret_val;
  251. }
  252. #define QLA83XX_DRV_LOCK_MSLEEP 200
  253. int qla4_83xx_drv_lock(struct scsi_qla_host *ha)
  254. {
  255. int timeout = 0;
  256. uint32_t status = 0;
  257. int ret_val = QLA_SUCCESS;
  258. uint32_t first_owner = 0;
  259. uint32_t tmo_owner = 0;
  260. uint32_t lock_id;
  261. uint32_t func_num;
  262. uint32_t lock_cnt;
  263. while (status == 0) {
  264. status = qla4_83xx_rd_reg(ha, QLA83XX_DRV_LOCK);
  265. if (status) {
  266. /* Increment Counter (8-31) and update func_num (0-7) on
  267. * getting a successful lock */
  268. lock_id = qla4_83xx_rd_reg(ha, QLA83XX_DRV_LOCK_ID);
  269. lock_id = ((lock_id + (1 << 8)) & ~0xFF) | ha->func_num;
  270. qla4_83xx_wr_reg(ha, QLA83XX_DRV_LOCK_ID, lock_id);
  271. break;
  272. }
  273. if (timeout == 0)
  274. /* Save counter + ID of function holding the lock for
  275. * first failure */
  276. first_owner = ha->isp_ops->rd_reg_direct(ha,
  277. QLA83XX_DRV_LOCK_ID);
  278. if (++timeout >=
  279. (QLA83XX_DRV_LOCK_TIMEOUT / QLA83XX_DRV_LOCK_MSLEEP)) {
  280. tmo_owner = qla4_83xx_rd_reg(ha, QLA83XX_DRV_LOCK_ID);
  281. func_num = tmo_owner & 0xFF;
  282. lock_cnt = tmo_owner >> 8;
  283. ql4_printk(KERN_INFO, ha, "%s: Lock by func %d failed after 2s, lock held by func %d, lock count %d, first_owner %d\n",
  284. __func__, ha->func_num, func_num, lock_cnt,
  285. (first_owner & 0xFF));
  286. if (first_owner != tmo_owner) {
  287. /* Some other driver got lock, OR same driver
  288. * got lock again (counter value changed), when
  289. * we were waiting for lock.
  290. * Retry for another 2 sec */
  291. ql4_printk(KERN_INFO, ha, "%s: IDC lock failed for func %d\n",
  292. __func__, ha->func_num);
  293. timeout = 0;
  294. } else {
  295. /* Same driver holding lock > 2sec.
  296. * Force Recovery */
  297. ret_val = qla4_83xx_lock_recovery(ha);
  298. if (ret_val == QLA_SUCCESS) {
  299. /* Recovered and got lock */
  300. ql4_printk(KERN_INFO, ha, "%s: IDC lock Recovery by %d successful\n",
  301. __func__, ha->func_num);
  302. break;
  303. }
  304. /* Recovery Failed, some other function
  305. * has the lock, wait for 2secs and retry */
  306. ql4_printk(KERN_INFO, ha, "%s: IDC lock Recovery by %d failed, Retrying timeout\n",
  307. __func__, ha->func_num);
  308. timeout = 0;
  309. }
  310. }
  311. msleep(QLA83XX_DRV_LOCK_MSLEEP);
  312. }
  313. return ret_val;
  314. }
  315. void qla4_83xx_drv_unlock(struct scsi_qla_host *ha)
  316. {
  317. int id;
  318. id = qla4_83xx_rd_reg(ha, QLA83XX_DRV_LOCK_ID);
  319. if ((id & 0xFF) != ha->func_num) {
  320. ql4_printk(KERN_ERR, ha, "%s: IDC Unlock by %d failed, lock owner is %d\n",
  321. __func__, ha->func_num, (id & 0xFF));
  322. return;
  323. }
  324. /* Keep lock counter value, update the ha->func_num to 0xFF */
  325. qla4_83xx_wr_reg(ha, QLA83XX_DRV_LOCK_ID, (id | 0xFF));
  326. qla4_83xx_rd_reg(ha, QLA83XX_DRV_UNLOCK);
  327. }
  328. void qla4_83xx_set_idc_dontreset(struct scsi_qla_host *ha)
  329. {
  330. uint32_t idc_ctrl;
  331. idc_ctrl = qla4_83xx_rd_reg(ha, QLA83XX_IDC_DRV_CTRL);
  332. idc_ctrl |= DONTRESET_BIT0;
  333. qla4_83xx_wr_reg(ha, QLA83XX_IDC_DRV_CTRL, idc_ctrl);
  334. DEBUG2(ql4_printk(KERN_INFO, ha, "%s: idc_ctrl = %d\n", __func__,
  335. idc_ctrl));
  336. }
  337. void qla4_83xx_clear_idc_dontreset(struct scsi_qla_host *ha)
  338. {
  339. uint32_t idc_ctrl;
  340. idc_ctrl = qla4_83xx_rd_reg(ha, QLA83XX_IDC_DRV_CTRL);
  341. idc_ctrl &= ~DONTRESET_BIT0;
  342. qla4_83xx_wr_reg(ha, QLA83XX_IDC_DRV_CTRL, idc_ctrl);
  343. DEBUG2(ql4_printk(KERN_INFO, ha, "%s: idc_ctrl = %d\n", __func__,
  344. idc_ctrl));
  345. }
  346. int qla4_83xx_idc_dontreset(struct scsi_qla_host *ha)
  347. {
  348. uint32_t idc_ctrl;
  349. idc_ctrl = qla4_83xx_rd_reg(ha, QLA83XX_IDC_DRV_CTRL);
  350. return idc_ctrl & DONTRESET_BIT0;
  351. }
  352. /*-------------------------IDC State Machine ---------------------*/
  353. enum {
  354. UNKNOWN_CLASS = 0,
  355. NIC_CLASS,
  356. FCOE_CLASS,
  357. ISCSI_CLASS
  358. };
  359. struct device_info {
  360. int func_num;
  361. int device_type;
  362. int port_num;
  363. };
  364. int qla4_83xx_can_perform_reset(struct scsi_qla_host *ha)
  365. {
  366. uint32_t drv_active;
  367. uint32_t dev_part, dev_part1, dev_part2;
  368. int i;
  369. struct device_info device_map[16];
  370. int func_nibble;
  371. int nibble;
  372. int nic_present = 0;
  373. int iscsi_present = 0;
  374. int iscsi_func_low = 0;
  375. /* Use the dev_partition register to determine the PCI function number
  376. * and then check drv_active register to see which driver is loaded */
  377. dev_part1 = qla4_83xx_rd_reg(ha,
  378. ha->reg_tbl[QLA8XXX_CRB_DEV_PART_INFO]);
  379. dev_part2 = qla4_83xx_rd_reg(ha, QLA83XX_CRB_DEV_PART_INFO2);
  380. drv_active = qla4_83xx_rd_reg(ha, ha->reg_tbl[QLA8XXX_CRB_DRV_ACTIVE]);
  381. /* Each function has 4 bits in dev_partition Info register,
  382. * Lower 2 bits - device type, Upper 2 bits - physical port number */
  383. dev_part = dev_part1;
  384. for (i = nibble = 0; i <= 15; i++, nibble++) {
  385. func_nibble = dev_part & (0xF << (nibble * 4));
  386. func_nibble >>= (nibble * 4);
  387. device_map[i].func_num = i;
  388. device_map[i].device_type = func_nibble & 0x3;
  389. device_map[i].port_num = func_nibble & 0xC;
  390. if (device_map[i].device_type == NIC_CLASS) {
  391. if (drv_active & (1 << device_map[i].func_num)) {
  392. nic_present++;
  393. break;
  394. }
  395. } else if (device_map[i].device_type == ISCSI_CLASS) {
  396. if (drv_active & (1 << device_map[i].func_num)) {
  397. if (!iscsi_present ||
  398. (iscsi_present &&
  399. (iscsi_func_low > device_map[i].func_num)))
  400. iscsi_func_low = device_map[i].func_num;
  401. iscsi_present++;
  402. }
  403. }
  404. /* For function_num[8..15] get info from dev_part2 register */
  405. if (nibble == 7) {
  406. nibble = 0;
  407. dev_part = dev_part2;
  408. }
  409. }
  410. /* NIC, iSCSI and FCOE are the Reset owners based on order, NIC gets
  411. * precedence over iSCSI and FCOE and iSCSI over FCOE, based on drivers
  412. * present. */
  413. if (!nic_present && (ha->func_num == iscsi_func_low)) {
  414. DEBUG2(ql4_printk(KERN_INFO, ha,
  415. "%s: can reset - NIC not present and lower iSCSI function is %d\n",
  416. __func__, ha->func_num));
  417. return 1;
  418. }
  419. return 0;
  420. }
  421. /**
  422. * qla4_83xx_need_reset_handler - Code to start reset sequence
  423. * @ha: pointer to adapter structure
  424. *
  425. * Note: IDC lock must be held upon entry
  426. **/
  427. void qla4_83xx_need_reset_handler(struct scsi_qla_host *ha)
  428. {
  429. uint32_t dev_state, drv_state, drv_active;
  430. unsigned long reset_timeout, dev_init_timeout;
  431. ql4_printk(KERN_INFO, ha, "%s: Performing ISP error recovery\n",
  432. __func__);
  433. if (!test_bit(AF_8XXX_RST_OWNER, &ha->flags)) {
  434. DEBUG2(ql4_printk(KERN_INFO, ha, "%s: reset acknowledged\n",
  435. __func__));
  436. qla4_8xxx_set_rst_ready(ha);
  437. /* Non-reset owners ACK Reset and wait for device INIT state
  438. * as part of Reset Recovery by Reset Owner */
  439. dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ);
  440. do {
  441. if (time_after_eq(jiffies, dev_init_timeout)) {
  442. ql4_printk(KERN_INFO, ha, "%s: Non Reset owner dev init timeout\n",
  443. __func__);
  444. break;
  445. }
  446. ha->isp_ops->idc_unlock(ha);
  447. msleep(1000);
  448. ha->isp_ops->idc_lock(ha);
  449. dev_state = qla4_8xxx_rd_direct(ha,
  450. QLA8XXX_CRB_DEV_STATE);
  451. } while (dev_state == QLA8XXX_DEV_NEED_RESET);
  452. } else {
  453. qla4_8xxx_set_rst_ready(ha);
  454. reset_timeout = jiffies + (ha->nx_reset_timeout * HZ);
  455. drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
  456. drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
  457. ql4_printk(KERN_INFO, ha, "%s: drv_state = 0x%x, drv_active = 0x%x\n",
  458. __func__, drv_state, drv_active);
  459. while (drv_state != drv_active) {
  460. if (time_after_eq(jiffies, reset_timeout)) {
  461. ql4_printk(KERN_INFO, ha, "%s: %s: RESET TIMEOUT! drv_state: 0x%08x, drv_active: 0x%08x\n",
  462. __func__, DRIVER_NAME, drv_state,
  463. drv_active);
  464. break;
  465. }
  466. ha->isp_ops->idc_unlock(ha);
  467. msleep(1000);
  468. ha->isp_ops->idc_lock(ha);
  469. drv_state = qla4_8xxx_rd_direct(ha,
  470. QLA8XXX_CRB_DRV_STATE);
  471. drv_active = qla4_8xxx_rd_direct(ha,
  472. QLA8XXX_CRB_DRV_ACTIVE);
  473. }
  474. if (drv_state != drv_active) {
  475. ql4_printk(KERN_INFO, ha, "%s: Reset_owner turning off drv_active of non-acking function 0x%x\n",
  476. __func__, (drv_active ^ drv_state));
  477. drv_active = drv_active & drv_state;
  478. qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_ACTIVE,
  479. drv_active);
  480. }
  481. clear_bit(AF_8XXX_RST_OWNER, &ha->flags);
  482. /* Start Reset Recovery */
  483. qla4_8xxx_device_bootstrap(ha);
  484. }
  485. }
  486. void qla4_83xx_get_idc_param(struct scsi_qla_host *ha)
  487. {
  488. uint32_t idc_params, ret_val;
  489. ret_val = qla4_83xx_flash_read_u32(ha, QLA83XX_IDC_PARAM_ADDR,
  490. (uint8_t *)&idc_params, 1);
  491. if (ret_val == QLA_SUCCESS) {
  492. ha->nx_dev_init_timeout = idc_params & 0xFFFF;
  493. ha->nx_reset_timeout = (idc_params >> 16) & 0xFFFF;
  494. } else {
  495. ha->nx_dev_init_timeout = ROM_DEV_INIT_TIMEOUT;
  496. ha->nx_reset_timeout = ROM_DRV_RESET_ACK_TIMEOUT;
  497. }
  498. DEBUG2(ql4_printk(KERN_DEBUG, ha,
  499. "%s: ha->nx_dev_init_timeout = %d, ha->nx_reset_timeout = %d\n",
  500. __func__, ha->nx_dev_init_timeout,
  501. ha->nx_reset_timeout));
  502. }
  503. /*-------------------------Reset Sequence Functions-----------------------*/
  504. static void qla4_83xx_dump_reset_seq_hdr(struct scsi_qla_host *ha)
  505. {
  506. uint8_t *phdr;
  507. if (!ha->reset_tmplt.buff) {
  508. ql4_printk(KERN_ERR, ha, "%s: Error: Invalid reset_seq_template\n",
  509. __func__);
  510. return;
  511. }
  512. phdr = ha->reset_tmplt.buff;
  513. DEBUG2(ql4_printk(KERN_INFO, ha,
  514. "Reset Template: 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X\n",
  515. *phdr, *(phdr+1), *(phdr+2), *(phdr+3), *(phdr+4),
  516. *(phdr+5), *(phdr+6), *(phdr+7), *(phdr + 8),
  517. *(phdr+9), *(phdr+10), *(phdr+11), *(phdr+12),
  518. *(phdr+13), *(phdr+14), *(phdr+15)));
  519. }
  520. static int qla4_83xx_copy_bootloader(struct scsi_qla_host *ha)
  521. {
  522. uint8_t *p_cache;
  523. uint32_t src, count, size;
  524. uint64_t dest;
  525. int ret_val = QLA_SUCCESS;
  526. src = QLA83XX_BOOTLOADER_FLASH_ADDR;
  527. dest = qla4_83xx_rd_reg(ha, QLA83XX_BOOTLOADER_ADDR);
  528. size = qla4_83xx_rd_reg(ha, QLA83XX_BOOTLOADER_SIZE);
  529. /* 128 bit alignment check */
  530. if (size & 0xF)
  531. size = (size + 16) & ~0xF;
  532. /* 16 byte count */
  533. count = size/16;
  534. p_cache = vmalloc(size);
  535. if (p_cache == NULL) {
  536. ql4_printk(KERN_ERR, ha, "%s: Failed to allocate memory for boot loader cache\n",
  537. __func__);
  538. ret_val = QLA_ERROR;
  539. goto exit_copy_bootloader;
  540. }
  541. ret_val = qla4_83xx_lockless_flash_read_u32(ha, src, p_cache,
  542. size / sizeof(uint32_t));
  543. if (ret_val == QLA_ERROR) {
  544. ql4_printk(KERN_ERR, ha, "%s: Error reading firmware from flash\n",
  545. __func__);
  546. goto exit_copy_error;
  547. }
  548. DEBUG2(ql4_printk(KERN_INFO, ha, "%s: Read firmware from flash\n",
  549. __func__));
  550. /* 128 bit/16 byte write to MS memory */
  551. ret_val = qla4_8xxx_ms_mem_write_128b(ha, dest, (uint32_t *)p_cache,
  552. count);
  553. if (ret_val == QLA_ERROR) {
  554. ql4_printk(KERN_ERR, ha, "%s: Error writing firmware to MS\n",
  555. __func__);
  556. goto exit_copy_error;
  557. }
  558. DEBUG2(ql4_printk(KERN_INFO, ha, "%s: Wrote firmware size %d to MS\n",
  559. __func__, size));
  560. exit_copy_error:
  561. vfree(p_cache);
  562. exit_copy_bootloader:
  563. return ret_val;
  564. }
  565. static int qla4_83xx_check_cmd_peg_status(struct scsi_qla_host *ha)
  566. {
  567. uint32_t val, ret_val = QLA_ERROR;
  568. int retries = CRB_CMDPEG_CHECK_RETRY_COUNT;
  569. do {
  570. val = qla4_83xx_rd_reg(ha, QLA83XX_CMDPEG_STATE);
  571. if (val == PHAN_INITIALIZE_COMPLETE) {
  572. DEBUG2(ql4_printk(KERN_INFO, ha,
  573. "%s: Command Peg initialization complete. State=0x%x\n",
  574. __func__, val));
  575. ret_val = QLA_SUCCESS;
  576. break;
  577. }
  578. msleep(CRB_CMDPEG_CHECK_DELAY);
  579. } while (--retries);
  580. return ret_val;
  581. }
  582. /**
  583. * qla4_83xx_poll_reg - Poll the given CRB addr for duration msecs till
  584. * value read ANDed with test_mask is equal to test_result.
  585. *
  586. * @ha : Pointer to adapter structure
  587. * @addr : CRB register address
  588. * @duration : Poll for total of "duration" msecs
  589. * @test_mask : Mask value read with "test_mask"
  590. * @test_result : Compare (value&test_mask) with test_result.
  591. **/
  592. static int qla4_83xx_poll_reg(struct scsi_qla_host *ha, uint32_t addr,
  593. int duration, uint32_t test_mask,
  594. uint32_t test_result)
  595. {
  596. uint32_t value;
  597. uint8_t retries;
  598. int ret_val = QLA_SUCCESS;
  599. ret_val = qla4_83xx_rd_reg_indirect(ha, addr, &value);
  600. if (ret_val == QLA_ERROR)
  601. goto exit_poll_reg;
  602. retries = duration / 10;
  603. do {
  604. if ((value & test_mask) != test_result) {
  605. msleep(duration / 10);
  606. ret_val = qla4_83xx_rd_reg_indirect(ha, addr, &value);
  607. if (ret_val == QLA_ERROR)
  608. goto exit_poll_reg;
  609. ret_val = QLA_ERROR;
  610. } else {
  611. ret_val = QLA_SUCCESS;
  612. break;
  613. }
  614. } while (retries--);
  615. exit_poll_reg:
  616. if (ret_val == QLA_ERROR) {
  617. ha->reset_tmplt.seq_error++;
  618. ql4_printk(KERN_ERR, ha, "%s: Poll Failed: 0x%08x 0x%08x 0x%08x\n",
  619. __func__, value, test_mask, test_result);
  620. }
  621. return ret_val;
  622. }
  623. static int qla4_83xx_reset_seq_checksum_test(struct scsi_qla_host *ha)
  624. {
  625. uint32_t sum = 0;
  626. uint16_t *buff = (uint16_t *)ha->reset_tmplt.buff;
  627. int u16_count = ha->reset_tmplt.hdr->size / sizeof(uint16_t);
  628. int ret_val;
  629. while (u16_count-- > 0)
  630. sum += *buff++;
  631. while (sum >> 16)
  632. sum = (sum & 0xFFFF) + (sum >> 16);
  633. /* checksum of 0 indicates a valid template */
  634. if (~sum) {
  635. ret_val = QLA_SUCCESS;
  636. } else {
  637. ql4_printk(KERN_ERR, ha, "%s: Reset seq checksum failed\n",
  638. __func__);
  639. ret_val = QLA_ERROR;
  640. }
  641. return ret_val;
  642. }
  643. /**
  644. * qla4_83xx_read_reset_template - Read Reset Template from Flash
  645. * @ha: Pointer to adapter structure
  646. **/
  647. void qla4_83xx_read_reset_template(struct scsi_qla_host *ha)
  648. {
  649. uint8_t *p_buff;
  650. uint32_t addr, tmplt_hdr_def_size, tmplt_hdr_size;
  651. uint32_t ret_val;
  652. ha->reset_tmplt.seq_error = 0;
  653. ha->reset_tmplt.buff = vmalloc(QLA83XX_RESTART_TEMPLATE_SIZE);
  654. if (ha->reset_tmplt.buff == NULL) {
  655. ql4_printk(KERN_ERR, ha, "%s: Failed to allocate reset template resources\n",
  656. __func__);
  657. goto exit_read_reset_template;
  658. }
  659. p_buff = ha->reset_tmplt.buff;
  660. addr = QLA83XX_RESET_TEMPLATE_ADDR;
  661. tmplt_hdr_def_size = sizeof(struct qla4_83xx_reset_template_hdr) /
  662. sizeof(uint32_t);
  663. DEBUG2(ql4_printk(KERN_INFO, ha,
  664. "%s: Read template hdr size %d from Flash\n",
  665. __func__, tmplt_hdr_def_size));
  666. /* Copy template header from flash */
  667. ret_val = qla4_83xx_flash_read_u32(ha, addr, p_buff,
  668. tmplt_hdr_def_size);
  669. if (ret_val != QLA_SUCCESS) {
  670. ql4_printk(KERN_ERR, ha, "%s: Failed to read reset template\n",
  671. __func__);
  672. goto exit_read_template_error;
  673. }
  674. ha->reset_tmplt.hdr =
  675. (struct qla4_83xx_reset_template_hdr *)ha->reset_tmplt.buff;
  676. /* Validate the template header size and signature */
  677. tmplt_hdr_size = ha->reset_tmplt.hdr->hdr_size/sizeof(uint32_t);
  678. if ((tmplt_hdr_size != tmplt_hdr_def_size) ||
  679. (ha->reset_tmplt.hdr->signature != RESET_TMPLT_HDR_SIGNATURE)) {
  680. ql4_printk(KERN_ERR, ha, "%s: Template Header size %d is invalid, tmplt_hdr_def_size %d\n",
  681. __func__, tmplt_hdr_size, tmplt_hdr_def_size);
  682. goto exit_read_template_error;
  683. }
  684. addr = QLA83XX_RESET_TEMPLATE_ADDR + ha->reset_tmplt.hdr->hdr_size;
  685. p_buff = ha->reset_tmplt.buff + ha->reset_tmplt.hdr->hdr_size;
  686. tmplt_hdr_def_size = (ha->reset_tmplt.hdr->size -
  687. ha->reset_tmplt.hdr->hdr_size) / sizeof(uint32_t);
  688. DEBUG2(ql4_printk(KERN_INFO, ha,
  689. "%s: Read rest of the template size %d\n",
  690. __func__, ha->reset_tmplt.hdr->size));
  691. /* Copy rest of the template */
  692. ret_val = qla4_83xx_flash_read_u32(ha, addr, p_buff,
  693. tmplt_hdr_def_size);
  694. if (ret_val != QLA_SUCCESS) {
  695. ql4_printk(KERN_ERR, ha, "%s: Failed to read reset template\n",
  696. __func__);
  697. goto exit_read_template_error;
  698. }
  699. /* Integrity check */
  700. if (qla4_83xx_reset_seq_checksum_test(ha)) {
  701. ql4_printk(KERN_ERR, ha, "%s: Reset Seq checksum failed!\n",
  702. __func__);
  703. goto exit_read_template_error;
  704. }
  705. DEBUG2(ql4_printk(KERN_INFO, ha,
  706. "%s: Reset Seq checksum passed, Get stop, start and init seq offsets\n",
  707. __func__));
  708. /* Get STOP, START, INIT sequence offsets */
  709. ha->reset_tmplt.init_offset = ha->reset_tmplt.buff +
  710. ha->reset_tmplt.hdr->init_seq_offset;
  711. ha->reset_tmplt.start_offset = ha->reset_tmplt.buff +
  712. ha->reset_tmplt.hdr->start_seq_offset;
  713. ha->reset_tmplt.stop_offset = ha->reset_tmplt.buff +
  714. ha->reset_tmplt.hdr->hdr_size;
  715. qla4_83xx_dump_reset_seq_hdr(ha);
  716. goto exit_read_reset_template;
  717. exit_read_template_error:
  718. vfree(ha->reset_tmplt.buff);
  719. exit_read_reset_template:
  720. return;
  721. }
  722. /**
  723. * qla4_83xx_read_write_crb_reg - Read from raddr and write value to waddr.
  724. *
  725. * @ha : Pointer to adapter structure
  726. * @raddr : CRB address to read from
  727. * @waddr : CRB address to write to
  728. **/
  729. static void qla4_83xx_read_write_crb_reg(struct scsi_qla_host *ha,
  730. uint32_t raddr, uint32_t waddr)
  731. {
  732. uint32_t value;
  733. qla4_83xx_rd_reg_indirect(ha, raddr, &value);
  734. qla4_83xx_wr_reg_indirect(ha, waddr, value);
  735. }
  736. /**
  737. * qla4_83xx_rmw_crb_reg - Read Modify Write crb register
  738. *
  739. * This function read value from raddr, AND with test_mask,
  740. * Shift Left,Right/OR/XOR with values RMW header and write value to waddr.
  741. *
  742. * @ha : Pointer to adapter structure
  743. * @raddr : CRB address to read from
  744. * @waddr : CRB address to write to
  745. * @p_rmw_hdr : header with shift/or/xor values.
  746. **/
  747. static void qla4_83xx_rmw_crb_reg(struct scsi_qla_host *ha, uint32_t raddr,
  748. uint32_t waddr,
  749. struct qla4_83xx_rmw *p_rmw_hdr)
  750. {
  751. uint32_t value;
  752. if (p_rmw_hdr->index_a)
  753. value = ha->reset_tmplt.array[p_rmw_hdr->index_a];
  754. else
  755. qla4_83xx_rd_reg_indirect(ha, raddr, &value);
  756. value &= p_rmw_hdr->test_mask;
  757. value <<= p_rmw_hdr->shl;
  758. value >>= p_rmw_hdr->shr;
  759. value |= p_rmw_hdr->or_value;
  760. value ^= p_rmw_hdr->xor_value;
  761. qla4_83xx_wr_reg_indirect(ha, waddr, value);
  762. return;
  763. }
  764. static void qla4_83xx_write_list(struct scsi_qla_host *ha,
  765. struct qla4_83xx_reset_entry_hdr *p_hdr)
  766. {
  767. struct qla4_83xx_entry *p_entry;
  768. uint32_t i;
  769. p_entry = (struct qla4_83xx_entry *)
  770. ((char *)p_hdr + sizeof(struct qla4_83xx_reset_entry_hdr));
  771. for (i = 0; i < p_hdr->count; i++, p_entry++) {
  772. qla4_83xx_wr_reg_indirect(ha, p_entry->arg1, p_entry->arg2);
  773. if (p_hdr->delay)
  774. udelay((uint32_t)(p_hdr->delay));
  775. }
  776. }
  777. static void qla4_83xx_read_write_list(struct scsi_qla_host *ha,
  778. struct qla4_83xx_reset_entry_hdr *p_hdr)
  779. {
  780. struct qla4_83xx_entry *p_entry;
  781. uint32_t i;
  782. p_entry = (struct qla4_83xx_entry *)
  783. ((char *)p_hdr + sizeof(struct qla4_83xx_reset_entry_hdr));
  784. for (i = 0; i < p_hdr->count; i++, p_entry++) {
  785. qla4_83xx_read_write_crb_reg(ha, p_entry->arg1, p_entry->arg2);
  786. if (p_hdr->delay)
  787. udelay((uint32_t)(p_hdr->delay));
  788. }
  789. }
  790. static void qla4_83xx_poll_list(struct scsi_qla_host *ha,
  791. struct qla4_83xx_reset_entry_hdr *p_hdr)
  792. {
  793. long delay;
  794. struct qla4_83xx_entry *p_entry;
  795. struct qla4_83xx_poll *p_poll;
  796. uint32_t i;
  797. uint32_t value;
  798. p_poll = (struct qla4_83xx_poll *)
  799. ((char *)p_hdr + sizeof(struct qla4_83xx_reset_entry_hdr));
  800. /* Entries start after 8 byte qla4_83xx_poll, poll header contains
  801. * the test_mask, test_value. */
  802. p_entry = (struct qla4_83xx_entry *)((char *)p_poll +
  803. sizeof(struct qla4_83xx_poll));
  804. delay = (long)p_hdr->delay;
  805. if (!delay) {
  806. for (i = 0; i < p_hdr->count; i++, p_entry++) {
  807. qla4_83xx_poll_reg(ha, p_entry->arg1, delay,
  808. p_poll->test_mask,
  809. p_poll->test_value);
  810. }
  811. } else {
  812. for (i = 0; i < p_hdr->count; i++, p_entry++) {
  813. if (qla4_83xx_poll_reg(ha, p_entry->arg1, delay,
  814. p_poll->test_mask,
  815. p_poll->test_value)) {
  816. qla4_83xx_rd_reg_indirect(ha, p_entry->arg1,
  817. &value);
  818. qla4_83xx_rd_reg_indirect(ha, p_entry->arg2,
  819. &value);
  820. }
  821. }
  822. }
  823. }
  824. static void qla4_83xx_poll_write_list(struct scsi_qla_host *ha,
  825. struct qla4_83xx_reset_entry_hdr *p_hdr)
  826. {
  827. long delay;
  828. struct qla4_83xx_quad_entry *p_entry;
  829. struct qla4_83xx_poll *p_poll;
  830. uint32_t i;
  831. p_poll = (struct qla4_83xx_poll *)
  832. ((char *)p_hdr + sizeof(struct qla4_83xx_reset_entry_hdr));
  833. p_entry = (struct qla4_83xx_quad_entry *)
  834. ((char *)p_poll + sizeof(struct qla4_83xx_poll));
  835. delay = (long)p_hdr->delay;
  836. for (i = 0; i < p_hdr->count; i++, p_entry++) {
  837. qla4_83xx_wr_reg_indirect(ha, p_entry->dr_addr,
  838. p_entry->dr_value);
  839. qla4_83xx_wr_reg_indirect(ha, p_entry->ar_addr,
  840. p_entry->ar_value);
  841. if (delay) {
  842. if (qla4_83xx_poll_reg(ha, p_entry->ar_addr, delay,
  843. p_poll->test_mask,
  844. p_poll->test_value)) {
  845. DEBUG2(ql4_printk(KERN_INFO, ha,
  846. "%s: Timeout Error: poll list, item_num %d, entry_num %d\n",
  847. __func__, i,
  848. ha->reset_tmplt.seq_index));
  849. }
  850. }
  851. }
  852. }
  853. static void qla4_83xx_read_modify_write(struct scsi_qla_host *ha,
  854. struct qla4_83xx_reset_entry_hdr *p_hdr)
  855. {
  856. struct qla4_83xx_entry *p_entry;
  857. struct qla4_83xx_rmw *p_rmw_hdr;
  858. uint32_t i;
  859. p_rmw_hdr = (struct qla4_83xx_rmw *)
  860. ((char *)p_hdr + sizeof(struct qla4_83xx_reset_entry_hdr));
  861. p_entry = (struct qla4_83xx_entry *)
  862. ((char *)p_rmw_hdr + sizeof(struct qla4_83xx_rmw));
  863. for (i = 0; i < p_hdr->count; i++, p_entry++) {
  864. qla4_83xx_rmw_crb_reg(ha, p_entry->arg1, p_entry->arg2,
  865. p_rmw_hdr);
  866. if (p_hdr->delay)
  867. udelay((uint32_t)(p_hdr->delay));
  868. }
  869. }
  870. static void qla4_83xx_pause(struct scsi_qla_host *ha,
  871. struct qla4_83xx_reset_entry_hdr *p_hdr)
  872. {
  873. if (p_hdr->delay)
  874. mdelay((uint32_t)((long)p_hdr->delay));
  875. }
  876. static void qla4_83xx_poll_read_list(struct scsi_qla_host *ha,
  877. struct qla4_83xx_reset_entry_hdr *p_hdr)
  878. {
  879. long delay;
  880. int index;
  881. struct qla4_83xx_quad_entry *p_entry;
  882. struct qla4_83xx_poll *p_poll;
  883. uint32_t i;
  884. uint32_t value;
  885. p_poll = (struct qla4_83xx_poll *)
  886. ((char *)p_hdr + sizeof(struct qla4_83xx_reset_entry_hdr));
  887. p_entry = (struct qla4_83xx_quad_entry *)
  888. ((char *)p_poll + sizeof(struct qla4_83xx_poll));
  889. delay = (long)p_hdr->delay;
  890. for (i = 0; i < p_hdr->count; i++, p_entry++) {
  891. qla4_83xx_wr_reg_indirect(ha, p_entry->ar_addr,
  892. p_entry->ar_value);
  893. if (delay) {
  894. if (qla4_83xx_poll_reg(ha, p_entry->ar_addr, delay,
  895. p_poll->test_mask,
  896. p_poll->test_value)) {
  897. DEBUG2(ql4_printk(KERN_INFO, ha,
  898. "%s: Timeout Error: poll list, Item_num %d, entry_num %d\n",
  899. __func__, i,
  900. ha->reset_tmplt.seq_index));
  901. } else {
  902. index = ha->reset_tmplt.array_index;
  903. qla4_83xx_rd_reg_indirect(ha, p_entry->dr_addr,
  904. &value);
  905. ha->reset_tmplt.array[index++] = value;
  906. if (index == QLA83XX_MAX_RESET_SEQ_ENTRIES)
  907. ha->reset_tmplt.array_index = 1;
  908. }
  909. }
  910. }
  911. }
  912. static void qla4_83xx_seq_end(struct scsi_qla_host *ha,
  913. struct qla4_83xx_reset_entry_hdr *p_hdr)
  914. {
  915. ha->reset_tmplt.seq_end = 1;
  916. }
  917. static void qla4_83xx_template_end(struct scsi_qla_host *ha,
  918. struct qla4_83xx_reset_entry_hdr *p_hdr)
  919. {
  920. ha->reset_tmplt.template_end = 1;
  921. if (ha->reset_tmplt.seq_error == 0) {
  922. DEBUG2(ql4_printk(KERN_INFO, ha,
  923. "%s: Reset sequence completed SUCCESSFULLY.\n",
  924. __func__));
  925. } else {
  926. ql4_printk(KERN_ERR, ha, "%s: Reset sequence completed with some timeout errors.\n",
  927. __func__);
  928. }
  929. }
  930. /**
  931. * qla4_83xx_process_reset_template - Process reset template.
  932. *
  933. * Process all entries in reset template till entry with SEQ_END opcode,
  934. * which indicates end of the reset template processing. Each entry has a
  935. * Reset Entry header, entry opcode/command, with size of the entry, number
  936. * of entries in sub-sequence and delay in microsecs or timeout in millisecs.
  937. *
  938. * @ha : Pointer to adapter structure
  939. * @p_buff : Common reset entry header.
  940. **/
  941. static void qla4_83xx_process_reset_template(struct scsi_qla_host *ha,
  942. char *p_buff)
  943. {
  944. int index, entries;
  945. struct qla4_83xx_reset_entry_hdr *p_hdr;
  946. char *p_entry = p_buff;
  947. ha->reset_tmplt.seq_end = 0;
  948. ha->reset_tmplt.template_end = 0;
  949. entries = ha->reset_tmplt.hdr->entries;
  950. index = ha->reset_tmplt.seq_index;
  951. for (; (!ha->reset_tmplt.seq_end) && (index < entries); index++) {
  952. p_hdr = (struct qla4_83xx_reset_entry_hdr *)p_entry;
  953. switch (p_hdr->cmd) {
  954. case OPCODE_NOP:
  955. break;
  956. case OPCODE_WRITE_LIST:
  957. qla4_83xx_write_list(ha, p_hdr);
  958. break;
  959. case OPCODE_READ_WRITE_LIST:
  960. qla4_83xx_read_write_list(ha, p_hdr);
  961. break;
  962. case OPCODE_POLL_LIST:
  963. qla4_83xx_poll_list(ha, p_hdr);
  964. break;
  965. case OPCODE_POLL_WRITE_LIST:
  966. qla4_83xx_poll_write_list(ha, p_hdr);
  967. break;
  968. case OPCODE_READ_MODIFY_WRITE:
  969. qla4_83xx_read_modify_write(ha, p_hdr);
  970. break;
  971. case OPCODE_SEQ_PAUSE:
  972. qla4_83xx_pause(ha, p_hdr);
  973. break;
  974. case OPCODE_SEQ_END:
  975. qla4_83xx_seq_end(ha, p_hdr);
  976. break;
  977. case OPCODE_TMPL_END:
  978. qla4_83xx_template_end(ha, p_hdr);
  979. break;
  980. case OPCODE_POLL_READ_LIST:
  981. qla4_83xx_poll_read_list(ha, p_hdr);
  982. break;
  983. default:
  984. ql4_printk(KERN_ERR, ha, "%s: Unknown command ==> 0x%04x on entry = %d\n",
  985. __func__, p_hdr->cmd, index);
  986. break;
  987. }
  988. /* Set pointer to next entry in the sequence. */
  989. p_entry += p_hdr->size;
  990. }
  991. ha->reset_tmplt.seq_index = index;
  992. }
  993. static void qla4_83xx_process_stop_seq(struct scsi_qla_host *ha)
  994. {
  995. ha->reset_tmplt.seq_index = 0;
  996. qla4_83xx_process_reset_template(ha, ha->reset_tmplt.stop_offset);
  997. if (ha->reset_tmplt.seq_end != 1)
  998. ql4_printk(KERN_ERR, ha, "%s: Abrupt STOP Sub-Sequence end.\n",
  999. __func__);
  1000. }
  1001. static void qla4_83xx_process_start_seq(struct scsi_qla_host *ha)
  1002. {
  1003. qla4_83xx_process_reset_template(ha, ha->reset_tmplt.start_offset);
  1004. if (ha->reset_tmplt.template_end != 1)
  1005. ql4_printk(KERN_ERR, ha, "%s: Abrupt START Sub-Sequence end.\n",
  1006. __func__);
  1007. }
  1008. static void qla4_83xx_process_init_seq(struct scsi_qla_host *ha)
  1009. {
  1010. qla4_83xx_process_reset_template(ha, ha->reset_tmplt.init_offset);
  1011. if (ha->reset_tmplt.seq_end != 1)
  1012. ql4_printk(KERN_ERR, ha, "%s: Abrupt INIT Sub-Sequence end.\n",
  1013. __func__);
  1014. }
  1015. static int qla4_83xx_restart(struct scsi_qla_host *ha)
  1016. {
  1017. int ret_val = QLA_SUCCESS;
  1018. uint32_t idc_ctrl;
  1019. qla4_83xx_process_stop_seq(ha);
  1020. /*
  1021. * Collect minidump.
  1022. * If IDC_CTRL BIT1 is set, clear it on going to INIT state and
  1023. * don't collect minidump
  1024. */
  1025. idc_ctrl = qla4_83xx_rd_reg(ha, QLA83XX_IDC_DRV_CTRL);
  1026. if (idc_ctrl & GRACEFUL_RESET_BIT1) {
  1027. qla4_83xx_wr_reg(ha, QLA83XX_IDC_DRV_CTRL,
  1028. (idc_ctrl & ~GRACEFUL_RESET_BIT1));
  1029. ql4_printk(KERN_INFO, ha, "%s: Graceful RESET: Not collecting minidump\n",
  1030. __func__);
  1031. } else {
  1032. qla4_8xxx_get_minidump(ha);
  1033. }
  1034. qla4_83xx_process_init_seq(ha);
  1035. if (qla4_83xx_copy_bootloader(ha)) {
  1036. ql4_printk(KERN_ERR, ha, "%s: Copy bootloader, firmware restart failed!\n",
  1037. __func__);
  1038. ret_val = QLA_ERROR;
  1039. goto exit_restart;
  1040. }
  1041. qla4_83xx_wr_reg(ha, QLA83XX_FW_IMAGE_VALID, QLA83XX_BOOT_FROM_FLASH);
  1042. qla4_83xx_process_start_seq(ha);
  1043. exit_restart:
  1044. return ret_val;
  1045. }
  1046. int qla4_83xx_start_firmware(struct scsi_qla_host *ha)
  1047. {
  1048. int ret_val = QLA_SUCCESS;
  1049. ret_val = qla4_83xx_restart(ha);
  1050. if (ret_val == QLA_ERROR) {
  1051. ql4_printk(KERN_ERR, ha, "%s: Restart error\n", __func__);
  1052. goto exit_start_fw;
  1053. } else {
  1054. DEBUG2(ql4_printk(KERN_INFO, ha, "%s: Restart done\n",
  1055. __func__));
  1056. }
  1057. ret_val = qla4_83xx_check_cmd_peg_status(ha);
  1058. if (ret_val == QLA_ERROR)
  1059. ql4_printk(KERN_ERR, ha, "%s: Peg not initialized\n",
  1060. __func__);
  1061. exit_start_fw:
  1062. return ret_val;
  1063. }
  1064. /*----------------------Interrupt Related functions ---------------------*/
  1065. static void qla4_83xx_disable_iocb_intrs(struct scsi_qla_host *ha)
  1066. {
  1067. if (test_and_clear_bit(AF_83XX_IOCB_INTR_ON, &ha->flags))
  1068. qla4_8xxx_intr_disable(ha);
  1069. }
  1070. static void qla4_83xx_disable_mbox_intrs(struct scsi_qla_host *ha)
  1071. {
  1072. uint32_t mb_int, ret;
  1073. if (test_and_clear_bit(AF_83XX_MBOX_INTR_ON, &ha->flags)) {
  1074. ret = readl(&ha->qla4_83xx_reg->mbox_int);
  1075. mb_int = ret & ~INT_ENABLE_FW_MB;
  1076. writel(mb_int, &ha->qla4_83xx_reg->mbox_int);
  1077. writel(1, &ha->qla4_83xx_reg->leg_int_mask);
  1078. }
  1079. }
  1080. void qla4_83xx_disable_intrs(struct scsi_qla_host *ha)
  1081. {
  1082. qla4_83xx_disable_mbox_intrs(ha);
  1083. qla4_83xx_disable_iocb_intrs(ha);
  1084. }
  1085. static void qla4_83xx_enable_iocb_intrs(struct scsi_qla_host *ha)
  1086. {
  1087. if (!test_bit(AF_83XX_IOCB_INTR_ON, &ha->flags)) {
  1088. qla4_8xxx_intr_enable(ha);
  1089. set_bit(AF_83XX_IOCB_INTR_ON, &ha->flags);
  1090. }
  1091. }
  1092. void qla4_83xx_enable_mbox_intrs(struct scsi_qla_host *ha)
  1093. {
  1094. uint32_t mb_int;
  1095. if (!test_bit(AF_83XX_MBOX_INTR_ON, &ha->flags)) {
  1096. mb_int = INT_ENABLE_FW_MB;
  1097. writel(mb_int, &ha->qla4_83xx_reg->mbox_int);
  1098. writel(0, &ha->qla4_83xx_reg->leg_int_mask);
  1099. set_bit(AF_83XX_MBOX_INTR_ON, &ha->flags);
  1100. }
  1101. }
  1102. void qla4_83xx_enable_intrs(struct scsi_qla_host *ha)
  1103. {
  1104. qla4_83xx_enable_mbox_intrs(ha);
  1105. qla4_83xx_enable_iocb_intrs(ha);
  1106. }
  1107. void qla4_83xx_queue_mbox_cmd(struct scsi_qla_host *ha, uint32_t *mbx_cmd,
  1108. int incount)
  1109. {
  1110. int i;
  1111. /* Load all mailbox registers, except mailbox 0. */
  1112. for (i = 1; i < incount; i++)
  1113. writel(mbx_cmd[i], &ha->qla4_83xx_reg->mailbox_in[i]);
  1114. writel(mbx_cmd[0], &ha->qla4_83xx_reg->mailbox_in[0]);
  1115. /* Set Host Interrupt register to 1, to tell the firmware that
  1116. * a mailbox command is pending. Firmware after reading the
  1117. * mailbox command, clears the host interrupt register */
  1118. writel(HINT_MBX_INT_PENDING, &ha->qla4_83xx_reg->host_intr);
  1119. }
  1120. void qla4_83xx_process_mbox_intr(struct scsi_qla_host *ha, int outcount)
  1121. {
  1122. int intr_status;
  1123. intr_status = readl(&ha->qla4_83xx_reg->risc_intr);
  1124. if (intr_status) {
  1125. ha->mbox_status_count = outcount;
  1126. ha->isp_ops->interrupt_service_routine(ha, intr_status);
  1127. }
  1128. }
  1129. /**
  1130. * qla4_83xx_isp_reset - Resets ISP and aborts all outstanding commands.
  1131. * @ha: pointer to host adapter structure.
  1132. **/
  1133. int qla4_83xx_isp_reset(struct scsi_qla_host *ha)
  1134. {
  1135. int rval;
  1136. uint32_t dev_state;
  1137. ha->isp_ops->idc_lock(ha);
  1138. dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE);
  1139. if (ql4xdontresethba)
  1140. qla4_83xx_set_idc_dontreset(ha);
  1141. if (dev_state == QLA8XXX_DEV_READY) {
  1142. /* If IDC_CTRL DONTRESETHBA_BIT0 is set dont do reset
  1143. * recovery */
  1144. if (qla4_83xx_idc_dontreset(ha) == DONTRESET_BIT0) {
  1145. ql4_printk(KERN_ERR, ha, "%s: Reset recovery disabled\n",
  1146. __func__);
  1147. rval = QLA_ERROR;
  1148. goto exit_isp_reset;
  1149. }
  1150. DEBUG2(ql4_printk(KERN_INFO, ha, "%s: HW State: NEED RESET\n",
  1151. __func__));
  1152. qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
  1153. QLA8XXX_DEV_NEED_RESET);
  1154. } else {
  1155. /* If device_state is NEED_RESET, go ahead with
  1156. * Reset,irrespective of ql4xdontresethba. This is to allow a
  1157. * non-reset-owner to force a reset. Non-reset-owner sets
  1158. * the IDC_CTRL BIT0 to prevent Reset-owner from doing a Reset
  1159. * and then forces a Reset by setting device_state to
  1160. * NEED_RESET. */
  1161. DEBUG2(ql4_printk(KERN_INFO, ha,
  1162. "%s: HW state already set to NEED_RESET\n",
  1163. __func__));
  1164. }
  1165. /* For ISP8324 and ISP8042, Reset owner is NIC, iSCSI or FCOE based on
  1166. * priority and which drivers are present. Unlike ISP8022, the function
  1167. * setting NEED_RESET, may not be the Reset owner. */
  1168. if (qla4_83xx_can_perform_reset(ha))
  1169. set_bit(AF_8XXX_RST_OWNER, &ha->flags);
  1170. ha->isp_ops->idc_unlock(ha);
  1171. rval = qla4_8xxx_device_state_handler(ha);
  1172. ha->isp_ops->idc_lock(ha);
  1173. qla4_8xxx_clear_rst_ready(ha);
  1174. exit_isp_reset:
  1175. ha->isp_ops->idc_unlock(ha);
  1176. if (rval == QLA_SUCCESS)
  1177. clear_bit(AF_FW_RECOVERY, &ha->flags);
  1178. return rval;
  1179. }
  1180. static void qla4_83xx_dump_pause_control_regs(struct scsi_qla_host *ha)
  1181. {
  1182. u32 val = 0, val1 = 0;
  1183. int i, status = QLA_SUCCESS;
  1184. status = qla4_83xx_rd_reg_indirect(ha, QLA83XX_SRE_SHIM_CONTROL, &val);
  1185. DEBUG2(ql4_printk(KERN_INFO, ha, "SRE-Shim Ctrl:0x%x\n", val));
  1186. /* Port 0 Rx Buffer Pause Threshold Registers. */
  1187. DEBUG2(ql4_printk(KERN_INFO, ha,
  1188. "Port 0 Rx Buffer Pause Threshold Registers[TC7..TC0]:"));
  1189. for (i = 0; i < 8; i++) {
  1190. status = qla4_83xx_rd_reg_indirect(ha,
  1191. QLA83XX_PORT0_RXB_PAUSE_THRS + (i * 0x4), &val);
  1192. DEBUG2(pr_info("0x%x ", val));
  1193. }
  1194. DEBUG2(pr_info("\n"));
  1195. /* Port 1 Rx Buffer Pause Threshold Registers. */
  1196. DEBUG2(ql4_printk(KERN_INFO, ha,
  1197. "Port 1 Rx Buffer Pause Threshold Registers[TC7..TC0]:"));
  1198. for (i = 0; i < 8; i++) {
  1199. status = qla4_83xx_rd_reg_indirect(ha,
  1200. QLA83XX_PORT1_RXB_PAUSE_THRS + (i * 0x4), &val);
  1201. DEBUG2(pr_info("0x%x ", val));
  1202. }
  1203. DEBUG2(pr_info("\n"));
  1204. /* Port 0 RxB Traffic Class Max Cell Registers. */
  1205. DEBUG2(ql4_printk(KERN_INFO, ha,
  1206. "Port 0 RxB Traffic Class Max Cell Registers[3..0]:"));
  1207. for (i = 0; i < 4; i++) {
  1208. status = qla4_83xx_rd_reg_indirect(ha,
  1209. QLA83XX_PORT0_RXB_TC_MAX_CELL + (i * 0x4), &val);
  1210. DEBUG2(pr_info("0x%x ", val));
  1211. }
  1212. DEBUG2(pr_info("\n"));
  1213. /* Port 1 RxB Traffic Class Max Cell Registers. */
  1214. DEBUG2(ql4_printk(KERN_INFO, ha,
  1215. "Port 1 RxB Traffic Class Max Cell Registers[3..0]:"));
  1216. for (i = 0; i < 4; i++) {
  1217. status = qla4_83xx_rd_reg_indirect(ha,
  1218. QLA83XX_PORT1_RXB_TC_MAX_CELL + (i * 0x4), &val);
  1219. DEBUG2(pr_info("0x%x ", val));
  1220. }
  1221. DEBUG2(pr_info("\n"));
  1222. /* Port 0 RxB Rx Traffic Class Stats. */
  1223. DEBUG2(ql4_printk(KERN_INFO, ha,
  1224. "Port 0 RxB Rx Traffic Class Stats [TC7..TC0]"));
  1225. for (i = 7; i >= 0; i--) {
  1226. status = qla4_83xx_rd_reg_indirect(ha,
  1227. QLA83XX_PORT0_RXB_TC_STATS,
  1228. &val);
  1229. val &= ~(0x7 << 29); /* Reset bits 29 to 31 */
  1230. qla4_83xx_wr_reg_indirect(ha, QLA83XX_PORT0_RXB_TC_STATS,
  1231. (val | (i << 29)));
  1232. status = qla4_83xx_rd_reg_indirect(ha,
  1233. QLA83XX_PORT0_RXB_TC_STATS,
  1234. &val);
  1235. DEBUG2(pr_info("0x%x ", val));
  1236. }
  1237. DEBUG2(pr_info("\n"));
  1238. /* Port 1 RxB Rx Traffic Class Stats. */
  1239. DEBUG2(ql4_printk(KERN_INFO, ha,
  1240. "Port 1 RxB Rx Traffic Class Stats [TC7..TC0]"));
  1241. for (i = 7; i >= 0; i--) {
  1242. status = qla4_83xx_rd_reg_indirect(ha,
  1243. QLA83XX_PORT1_RXB_TC_STATS,
  1244. &val);
  1245. val &= ~(0x7 << 29); /* Reset bits 29 to 31 */
  1246. qla4_83xx_wr_reg_indirect(ha, QLA83XX_PORT1_RXB_TC_STATS,
  1247. (val | (i << 29)));
  1248. status = qla4_83xx_rd_reg_indirect(ha,
  1249. QLA83XX_PORT1_RXB_TC_STATS,
  1250. &val);
  1251. DEBUG2(pr_info("0x%x ", val));
  1252. }
  1253. DEBUG2(pr_info("\n"));
  1254. status = qla4_83xx_rd_reg_indirect(ha, QLA83XX_PORT2_IFB_PAUSE_THRS,
  1255. &val);
  1256. status = qla4_83xx_rd_reg_indirect(ha, QLA83XX_PORT3_IFB_PAUSE_THRS,
  1257. &val1);
  1258. DEBUG2(ql4_printk(KERN_INFO, ha,
  1259. "IFB-Pause Thresholds: Port 2:0x%x, Port 3:0x%x\n",
  1260. val, val1));
  1261. }
  1262. static void __qla4_83xx_disable_pause(struct scsi_qla_host *ha)
  1263. {
  1264. int i;
  1265. /* set SRE-Shim Control Register */
  1266. qla4_83xx_wr_reg_indirect(ha, QLA83XX_SRE_SHIM_CONTROL,
  1267. QLA83XX_SET_PAUSE_VAL);
  1268. for (i = 0; i < 8; i++) {
  1269. /* Port 0 Rx Buffer Pause Threshold Registers. */
  1270. qla4_83xx_wr_reg_indirect(ha,
  1271. QLA83XX_PORT0_RXB_PAUSE_THRS + (i * 0x4),
  1272. QLA83XX_SET_PAUSE_VAL);
  1273. /* Port 1 Rx Buffer Pause Threshold Registers. */
  1274. qla4_83xx_wr_reg_indirect(ha,
  1275. QLA83XX_PORT1_RXB_PAUSE_THRS + (i * 0x4),
  1276. QLA83XX_SET_PAUSE_VAL);
  1277. }
  1278. for (i = 0; i < 4; i++) {
  1279. /* Port 0 RxB Traffic Class Max Cell Registers. */
  1280. qla4_83xx_wr_reg_indirect(ha,
  1281. QLA83XX_PORT0_RXB_TC_MAX_CELL + (i * 0x4),
  1282. QLA83XX_SET_TC_MAX_CELL_VAL);
  1283. /* Port 1 RxB Traffic Class Max Cell Registers. */
  1284. qla4_83xx_wr_reg_indirect(ha,
  1285. QLA83XX_PORT1_RXB_TC_MAX_CELL + (i * 0x4),
  1286. QLA83XX_SET_TC_MAX_CELL_VAL);
  1287. }
  1288. qla4_83xx_wr_reg_indirect(ha, QLA83XX_PORT2_IFB_PAUSE_THRS,
  1289. QLA83XX_SET_PAUSE_VAL);
  1290. qla4_83xx_wr_reg_indirect(ha, QLA83XX_PORT3_IFB_PAUSE_THRS,
  1291. QLA83XX_SET_PAUSE_VAL);
  1292. ql4_printk(KERN_INFO, ha, "Disabled pause frames successfully.\n");
  1293. }
  1294. /**
  1295. * qla4_83xx_eport_init - Initialize EPort.
  1296. * @ha: Pointer to host adapter structure.
  1297. *
  1298. * If EPort hardware is in reset state before disabling pause, there would be
  1299. * serious hardware wedging issues. To prevent this perform eport init everytime
  1300. * before disabling pause frames.
  1301. **/
  1302. static void qla4_83xx_eport_init(struct scsi_qla_host *ha)
  1303. {
  1304. /* Clear the 8 registers */
  1305. qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_REG, 0x0);
  1306. qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_PORT0, 0x0);
  1307. qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_PORT1, 0x0);
  1308. qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_PORT2, 0x0);
  1309. qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_PORT3, 0x0);
  1310. qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_SRE_SHIM, 0x0);
  1311. qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_EPG_SHIM, 0x0);
  1312. qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_ETHER_PCS, 0x0);
  1313. /* Write any value to Reset Control register */
  1314. qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_CONTROL, 0xFF);
  1315. ql4_printk(KERN_INFO, ha, "EPORT is out of reset.\n");
  1316. }
  1317. void qla4_83xx_disable_pause(struct scsi_qla_host *ha)
  1318. {
  1319. ha->isp_ops->idc_lock(ha);
  1320. /* Before disabling pause frames, ensure that eport is not in reset */
  1321. qla4_83xx_eport_init(ha);
  1322. qla4_83xx_dump_pause_control_regs(ha);
  1323. __qla4_83xx_disable_pause(ha);
  1324. ha->isp_ops->idc_unlock(ha);
  1325. }
  1326. /**
  1327. * qla4_83xx_is_detached - Check if we are marked invisible.
  1328. * @ha: Pointer to host adapter structure.
  1329. **/
  1330. int qla4_83xx_is_detached(struct scsi_qla_host *ha)
  1331. {
  1332. uint32_t drv_active;
  1333. drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
  1334. if (test_bit(AF_INIT_DONE, &ha->flags) &&
  1335. !(drv_active & (1 << ha->func_num))) {
  1336. DEBUG2(ql4_printk(KERN_INFO, ha, "%s: drv_active = 0x%X\n",
  1337. __func__, drv_active));
  1338. return QLA_SUCCESS;
  1339. }
  1340. return QLA_ERROR;
  1341. }