qla_mr.c 90 KB

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  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2014 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include <linux/delay.h>
  9. #include <linux/ktime.h>
  10. #include <linux/pci.h>
  11. #include <linux/ratelimit.h>
  12. #include <linux/vmalloc.h>
  13. #include <linux/bsg-lib.h>
  14. #include <scsi/scsi_tcq.h>
  15. #include <linux/utsname.h>
  16. /* QLAFX00 specific Mailbox implementation functions */
  17. /*
  18. * qlafx00_mailbox_command
  19. * Issue mailbox command and waits for completion.
  20. *
  21. * Input:
  22. * ha = adapter block pointer.
  23. * mcp = driver internal mbx struct pointer.
  24. *
  25. * Output:
  26. * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data.
  27. *
  28. * Returns:
  29. * 0 : QLA_SUCCESS = cmd performed success
  30. * 1 : QLA_FUNCTION_FAILED (error encountered)
  31. * 6 : QLA_FUNCTION_TIMEOUT (timeout condition encountered)
  32. *
  33. * Context:
  34. * Kernel context.
  35. */
  36. static int
  37. qlafx00_mailbox_command(scsi_qla_host_t *vha, struct mbx_cmd_32 *mcp)
  38. {
  39. int rval;
  40. unsigned long flags = 0;
  41. device_reg_t *reg;
  42. uint8_t abort_active;
  43. uint8_t io_lock_on;
  44. uint16_t command = 0;
  45. uint32_t *iptr;
  46. uint32_t __iomem *optr;
  47. uint32_t cnt;
  48. uint32_t mboxes;
  49. unsigned long wait_time;
  50. struct qla_hw_data *ha = vha->hw;
  51. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  52. if (ha->pdev->error_state > pci_channel_io_frozen) {
  53. ql_log(ql_log_warn, vha, 0x115c,
  54. "error_state is greater than pci_channel_io_frozen, "
  55. "exiting.\n");
  56. return QLA_FUNCTION_TIMEOUT;
  57. }
  58. if (vha->device_flags & DFLG_DEV_FAILED) {
  59. ql_log(ql_log_warn, vha, 0x115f,
  60. "Device in failed state, exiting.\n");
  61. return QLA_FUNCTION_TIMEOUT;
  62. }
  63. reg = ha->iobase;
  64. io_lock_on = base_vha->flags.init_done;
  65. rval = QLA_SUCCESS;
  66. abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  67. if (ha->flags.pci_channel_io_perm_failure) {
  68. ql_log(ql_log_warn, vha, 0x1175,
  69. "Perm failure on EEH timeout MBX, exiting.\n");
  70. return QLA_FUNCTION_TIMEOUT;
  71. }
  72. if (ha->flags.isp82xx_fw_hung) {
  73. /* Setting Link-Down error */
  74. mcp->mb[0] = MBS_LINK_DOWN_ERROR;
  75. ql_log(ql_log_warn, vha, 0x1176,
  76. "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
  77. rval = QLA_FUNCTION_FAILED;
  78. goto premature_exit;
  79. }
  80. /*
  81. * Wait for active mailbox commands to finish by waiting at most tov
  82. * seconds. This is to serialize actual issuing of mailbox cmds during
  83. * non ISP abort time.
  84. */
  85. if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) {
  86. /* Timeout occurred. Return error. */
  87. ql_log(ql_log_warn, vha, 0x1177,
  88. "Cmd access timeout, cmd=0x%x, Exiting.\n",
  89. mcp->mb[0]);
  90. return QLA_FUNCTION_TIMEOUT;
  91. }
  92. ha->flags.mbox_busy = 1;
  93. /* Save mailbox command for debug */
  94. ha->mcp32 = mcp;
  95. ql_dbg(ql_dbg_mbx, vha, 0x1178,
  96. "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]);
  97. spin_lock_irqsave(&ha->hardware_lock, flags);
  98. /* Load mailbox registers. */
  99. optr = (uint32_t __iomem *)&reg->ispfx00.mailbox0;
  100. iptr = mcp->mb;
  101. command = mcp->mb[0];
  102. mboxes = mcp->out_mb;
  103. for (cnt = 0; cnt < ha->mbx_count; cnt++) {
  104. if (mboxes & BIT_0)
  105. WRT_REG_DWORD(optr, *iptr);
  106. mboxes >>= 1;
  107. optr++;
  108. iptr++;
  109. }
  110. /* Issue set host interrupt command to send cmd out. */
  111. ha->flags.mbox_int = 0;
  112. clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  113. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1172,
  114. (uint8_t *)mcp->mb, 16);
  115. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1173,
  116. ((uint8_t *)mcp->mb + 0x10), 16);
  117. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1174,
  118. ((uint8_t *)mcp->mb + 0x20), 8);
  119. /* Unlock mbx registers and wait for interrupt */
  120. ql_dbg(ql_dbg_mbx, vha, 0x1179,
  121. "Going to unlock irq & waiting for interrupts. "
  122. "jiffies=%lx.\n", jiffies);
  123. /* Wait for mbx cmd completion until timeout */
  124. if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) {
  125. set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
  126. QLAFX00_SET_HST_INTR(ha, ha->mbx_intr_code);
  127. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  128. wait_for_completion_timeout(&ha->mbx_intr_comp, mcp->tov * HZ);
  129. } else {
  130. ql_dbg(ql_dbg_mbx, vha, 0x112c,
  131. "Cmd=%x Polling Mode.\n", command);
  132. QLAFX00_SET_HST_INTR(ha, ha->mbx_intr_code);
  133. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  134. wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */
  135. while (!ha->flags.mbox_int) {
  136. if (time_after(jiffies, wait_time))
  137. break;
  138. /* Check for pending interrupts. */
  139. qla2x00_poll(ha->rsp_q_map[0]);
  140. if (!ha->flags.mbox_int &&
  141. !(IS_QLA2200(ha) &&
  142. command == MBC_LOAD_RISC_RAM_EXTENDED))
  143. usleep_range(10000, 11000);
  144. } /* while */
  145. ql_dbg(ql_dbg_mbx, vha, 0x112d,
  146. "Waited %d sec.\n",
  147. (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ));
  148. }
  149. /* Check whether we timed out */
  150. if (ha->flags.mbox_int) {
  151. uint32_t *iptr2;
  152. ql_dbg(ql_dbg_mbx, vha, 0x112e,
  153. "Cmd=%x completed.\n", command);
  154. /* Got interrupt. Clear the flag. */
  155. ha->flags.mbox_int = 0;
  156. clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  157. if (ha->mailbox_out32[0] != MBS_COMMAND_COMPLETE)
  158. rval = QLA_FUNCTION_FAILED;
  159. /* Load return mailbox registers. */
  160. iptr2 = mcp->mb;
  161. iptr = (uint32_t *)&ha->mailbox_out32[0];
  162. mboxes = mcp->in_mb;
  163. for (cnt = 0; cnt < ha->mbx_count; cnt++) {
  164. if (mboxes & BIT_0)
  165. *iptr2 = *iptr;
  166. mboxes >>= 1;
  167. iptr2++;
  168. iptr++;
  169. }
  170. } else {
  171. rval = QLA_FUNCTION_TIMEOUT;
  172. }
  173. ha->flags.mbox_busy = 0;
  174. /* Clean up */
  175. ha->mcp32 = NULL;
  176. if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) {
  177. ql_dbg(ql_dbg_mbx, vha, 0x113a,
  178. "checking for additional resp interrupt.\n");
  179. /* polling mode for non isp_abort commands. */
  180. qla2x00_poll(ha->rsp_q_map[0]);
  181. }
  182. if (rval == QLA_FUNCTION_TIMEOUT &&
  183. mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) {
  184. if (!io_lock_on || (mcp->flags & IOCTL_CMD) ||
  185. ha->flags.eeh_busy) {
  186. /* not in dpc. schedule it for dpc to take over. */
  187. ql_dbg(ql_dbg_mbx, vha, 0x115d,
  188. "Timeout, schedule isp_abort_needed.\n");
  189. if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
  190. !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
  191. !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
  192. ql_log(ql_log_info, base_vha, 0x115e,
  193. "Mailbox cmd timeout occurred, cmd=0x%x, "
  194. "mb[0]=0x%x, eeh_busy=0x%x. Scheduling ISP "
  195. "abort.\n", command, mcp->mb[0],
  196. ha->flags.eeh_busy);
  197. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  198. qla2xxx_wake_dpc(vha);
  199. }
  200. } else if (!abort_active) {
  201. /* call abort directly since we are in the DPC thread */
  202. ql_dbg(ql_dbg_mbx, vha, 0x1160,
  203. "Timeout, calling abort_isp.\n");
  204. if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
  205. !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
  206. !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
  207. ql_log(ql_log_info, base_vha, 0x1161,
  208. "Mailbox cmd timeout occurred, cmd=0x%x, "
  209. "mb[0]=0x%x. Scheduling ISP abort ",
  210. command, mcp->mb[0]);
  211. set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
  212. clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  213. if (ha->isp_ops->abort_isp(vha)) {
  214. /* Failed. retry later. */
  215. set_bit(ISP_ABORT_NEEDED,
  216. &vha->dpc_flags);
  217. }
  218. clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
  219. ql_dbg(ql_dbg_mbx, vha, 0x1162,
  220. "Finished abort_isp.\n");
  221. }
  222. }
  223. }
  224. premature_exit:
  225. /* Allow next mbx cmd to come in. */
  226. complete(&ha->mbx_cmd_comp);
  227. if (rval) {
  228. ql_log(ql_log_warn, base_vha, 0x1163,
  229. "**** Failed mbx[0]=%x, mb[1]=%x, mb[2]=%x, "
  230. "mb[3]=%x, cmd=%x ****.\n",
  231. mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3], command);
  232. } else {
  233. ql_dbg(ql_dbg_mbx, base_vha, 0x1164, "Done %s.\n", __func__);
  234. }
  235. return rval;
  236. }
  237. /*
  238. * qlafx00_driver_shutdown
  239. * Indicate a driver shutdown to firmware.
  240. *
  241. * Input:
  242. * ha = adapter block pointer.
  243. *
  244. * Returns:
  245. * local function return status code.
  246. *
  247. * Context:
  248. * Kernel context.
  249. */
  250. int
  251. qlafx00_driver_shutdown(scsi_qla_host_t *vha, int tmo)
  252. {
  253. int rval;
  254. struct mbx_cmd_32 mc;
  255. struct mbx_cmd_32 *mcp = &mc;
  256. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1166,
  257. "Entered %s.\n", __func__);
  258. mcp->mb[0] = MBC_MR_DRV_SHUTDOWN;
  259. mcp->out_mb = MBX_0;
  260. mcp->in_mb = MBX_0;
  261. if (tmo)
  262. mcp->tov = tmo;
  263. else
  264. mcp->tov = MBX_TOV_SECONDS;
  265. mcp->flags = 0;
  266. rval = qlafx00_mailbox_command(vha, mcp);
  267. if (rval != QLA_SUCCESS) {
  268. ql_dbg(ql_dbg_mbx, vha, 0x1167,
  269. "Failed=%x.\n", rval);
  270. } else {
  271. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1168,
  272. "Done %s.\n", __func__);
  273. }
  274. return rval;
  275. }
  276. /*
  277. * qlafx00_get_firmware_state
  278. * Get adapter firmware state.
  279. *
  280. * Input:
  281. * ha = adapter block pointer.
  282. * TARGET_QUEUE_LOCK must be released.
  283. * ADAPTER_STATE_LOCK must be released.
  284. *
  285. * Returns:
  286. * qla7xxx local function return status code.
  287. *
  288. * Context:
  289. * Kernel context.
  290. */
  291. static int
  292. qlafx00_get_firmware_state(scsi_qla_host_t *vha, uint32_t *states)
  293. {
  294. int rval;
  295. struct mbx_cmd_32 mc;
  296. struct mbx_cmd_32 *mcp = &mc;
  297. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1169,
  298. "Entered %s.\n", __func__);
  299. mcp->mb[0] = MBC_GET_FIRMWARE_STATE;
  300. mcp->out_mb = MBX_0;
  301. mcp->in_mb = MBX_1|MBX_0;
  302. mcp->tov = MBX_TOV_SECONDS;
  303. mcp->flags = 0;
  304. rval = qlafx00_mailbox_command(vha, mcp);
  305. /* Return firmware states. */
  306. states[0] = mcp->mb[1];
  307. if (rval != QLA_SUCCESS) {
  308. ql_dbg(ql_dbg_mbx, vha, 0x116a,
  309. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  310. } else {
  311. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116b,
  312. "Done %s.\n", __func__);
  313. }
  314. return rval;
  315. }
  316. /*
  317. * qlafx00_init_firmware
  318. * Initialize adapter firmware.
  319. *
  320. * Input:
  321. * ha = adapter block pointer.
  322. * dptr = Initialization control block pointer.
  323. * size = size of initialization control block.
  324. * TARGET_QUEUE_LOCK must be released.
  325. * ADAPTER_STATE_LOCK must be released.
  326. *
  327. * Returns:
  328. * qlafx00 local function return status code.
  329. *
  330. * Context:
  331. * Kernel context.
  332. */
  333. int
  334. qlafx00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
  335. {
  336. int rval;
  337. struct mbx_cmd_32 mc;
  338. struct mbx_cmd_32 *mcp = &mc;
  339. struct qla_hw_data *ha = vha->hw;
  340. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116c,
  341. "Entered %s.\n", __func__);
  342. mcp->mb[0] = MBC_INITIALIZE_FIRMWARE;
  343. mcp->mb[1] = 0;
  344. mcp->mb[2] = MSD(ha->init_cb_dma);
  345. mcp->mb[3] = LSD(ha->init_cb_dma);
  346. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  347. mcp->in_mb = MBX_0;
  348. mcp->buf_size = size;
  349. mcp->flags = MBX_DMA_OUT;
  350. mcp->tov = MBX_TOV_SECONDS;
  351. rval = qlafx00_mailbox_command(vha, mcp);
  352. if (rval != QLA_SUCCESS) {
  353. ql_dbg(ql_dbg_mbx, vha, 0x116d,
  354. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  355. } else {
  356. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116e,
  357. "Done %s.\n", __func__);
  358. }
  359. return rval;
  360. }
  361. /*
  362. * qlafx00_mbx_reg_test
  363. */
  364. static int
  365. qlafx00_mbx_reg_test(scsi_qla_host_t *vha)
  366. {
  367. int rval;
  368. struct mbx_cmd_32 mc;
  369. struct mbx_cmd_32 *mcp = &mc;
  370. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116f,
  371. "Entered %s.\n", __func__);
  372. mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST;
  373. mcp->mb[1] = 0xAAAA;
  374. mcp->mb[2] = 0x5555;
  375. mcp->mb[3] = 0xAA55;
  376. mcp->mb[4] = 0x55AA;
  377. mcp->mb[5] = 0xA5A5;
  378. mcp->mb[6] = 0x5A5A;
  379. mcp->mb[7] = 0x2525;
  380. mcp->mb[8] = 0xBBBB;
  381. mcp->mb[9] = 0x6666;
  382. mcp->mb[10] = 0xBB66;
  383. mcp->mb[11] = 0x66BB;
  384. mcp->mb[12] = 0xB6B6;
  385. mcp->mb[13] = 0x6B6B;
  386. mcp->mb[14] = 0x3636;
  387. mcp->mb[15] = 0xCCCC;
  388. mcp->out_mb = MBX_15|MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
  389. MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  390. mcp->in_mb = MBX_15|MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
  391. MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  392. mcp->buf_size = 0;
  393. mcp->flags = MBX_DMA_OUT;
  394. mcp->tov = MBX_TOV_SECONDS;
  395. rval = qlafx00_mailbox_command(vha, mcp);
  396. if (rval == QLA_SUCCESS) {
  397. if (mcp->mb[17] != 0xAAAA || mcp->mb[18] != 0x5555 ||
  398. mcp->mb[19] != 0xAA55 || mcp->mb[20] != 0x55AA)
  399. rval = QLA_FUNCTION_FAILED;
  400. if (mcp->mb[21] != 0xA5A5 || mcp->mb[22] != 0x5A5A ||
  401. mcp->mb[23] != 0x2525 || mcp->mb[24] != 0xBBBB)
  402. rval = QLA_FUNCTION_FAILED;
  403. if (mcp->mb[25] != 0x6666 || mcp->mb[26] != 0xBB66 ||
  404. mcp->mb[27] != 0x66BB || mcp->mb[28] != 0xB6B6)
  405. rval = QLA_FUNCTION_FAILED;
  406. if (mcp->mb[29] != 0x6B6B || mcp->mb[30] != 0x3636 ||
  407. mcp->mb[31] != 0xCCCC)
  408. rval = QLA_FUNCTION_FAILED;
  409. }
  410. if (rval != QLA_SUCCESS) {
  411. ql_dbg(ql_dbg_mbx, vha, 0x1170,
  412. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  413. } else {
  414. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1171,
  415. "Done %s.\n", __func__);
  416. }
  417. return rval;
  418. }
  419. /**
  420. * qlafx00_pci_config() - Setup ISPFx00 PCI configuration registers.
  421. * @vha: HA context
  422. *
  423. * Returns 0 on success.
  424. */
  425. int
  426. qlafx00_pci_config(scsi_qla_host_t *vha)
  427. {
  428. uint16_t w;
  429. struct qla_hw_data *ha = vha->hw;
  430. pci_set_master(ha->pdev);
  431. pci_try_set_mwi(ha->pdev);
  432. pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
  433. w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
  434. w &= ~PCI_COMMAND_INTX_DISABLE;
  435. pci_write_config_word(ha->pdev, PCI_COMMAND, w);
  436. /* PCIe -- adjust Maximum Read Request Size (2048). */
  437. if (pci_is_pcie(ha->pdev))
  438. pcie_set_readrq(ha->pdev, 2048);
  439. ha->chip_revision = ha->pdev->revision;
  440. return QLA_SUCCESS;
  441. }
  442. /**
  443. * qlafx00_warm_reset() - Perform warm reset of iSA(CPUs being reset on SOC).
  444. * @vha: HA context
  445. *
  446. */
  447. static inline void
  448. qlafx00_soc_cpu_reset(scsi_qla_host_t *vha)
  449. {
  450. unsigned long flags = 0;
  451. struct qla_hw_data *ha = vha->hw;
  452. int i, core;
  453. uint32_t cnt;
  454. uint32_t reg_val;
  455. spin_lock_irqsave(&ha->hardware_lock, flags);
  456. QLAFX00_SET_HBA_SOC_REG(ha, 0x80004, 0);
  457. QLAFX00_SET_HBA_SOC_REG(ha, 0x82004, 0);
  458. /* stop the XOR DMA engines */
  459. QLAFX00_SET_HBA_SOC_REG(ha, 0x60920, 0x02);
  460. QLAFX00_SET_HBA_SOC_REG(ha, 0x60924, 0x02);
  461. QLAFX00_SET_HBA_SOC_REG(ha, 0xf0920, 0x02);
  462. QLAFX00_SET_HBA_SOC_REG(ha, 0xf0924, 0x02);
  463. /* stop the IDMA engines */
  464. reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x60840);
  465. reg_val &= ~(1<<12);
  466. QLAFX00_SET_HBA_SOC_REG(ha, 0x60840, reg_val);
  467. reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x60844);
  468. reg_val &= ~(1<<12);
  469. QLAFX00_SET_HBA_SOC_REG(ha, 0x60844, reg_val);
  470. reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x60848);
  471. reg_val &= ~(1<<12);
  472. QLAFX00_SET_HBA_SOC_REG(ha, 0x60848, reg_val);
  473. reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x6084C);
  474. reg_val &= ~(1<<12);
  475. QLAFX00_SET_HBA_SOC_REG(ha, 0x6084C, reg_val);
  476. for (i = 0; i < 100000; i++) {
  477. if ((QLAFX00_GET_HBA_SOC_REG(ha, 0xd0000) & 0x10000000) == 0 &&
  478. (QLAFX00_GET_HBA_SOC_REG(ha, 0x10600) & 0x1) == 0)
  479. break;
  480. udelay(100);
  481. }
  482. /* Set all 4 cores in reset */
  483. for (i = 0; i < 4; i++) {
  484. QLAFX00_SET_HBA_SOC_REG(ha,
  485. (SOC_SW_RST_CONTROL_REG_CORE0 + 8*i), (0xF01));
  486. QLAFX00_SET_HBA_SOC_REG(ha,
  487. (SOC_SW_RST_CONTROL_REG_CORE0 + 4 + 8*i), (0x01010101));
  488. }
  489. /* Reset all units in Fabric */
  490. QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_RST_CONTROL_REG, (0x011f0101));
  491. /* */
  492. QLAFX00_SET_HBA_SOC_REG(ha, 0x10610, 1);
  493. QLAFX00_SET_HBA_SOC_REG(ha, 0x10600, 0);
  494. /* Set all 4 core Memory Power Down Registers */
  495. for (i = 0; i < 5; i++) {
  496. QLAFX00_SET_HBA_SOC_REG(ha,
  497. (SOC_PWR_MANAGEMENT_PWR_DOWN_REG + 4*i), (0x0));
  498. }
  499. /* Reset all interrupt control registers */
  500. for (i = 0; i < 115; i++) {
  501. QLAFX00_SET_HBA_SOC_REG(ha,
  502. (SOC_INTERRUPT_SOURCE_I_CONTROL_REG + 4*i), (0x0));
  503. }
  504. /* Reset Timers control registers. per core */
  505. for (core = 0; core < 4; core++)
  506. for (i = 0; i < 8; i++)
  507. QLAFX00_SET_HBA_SOC_REG(ha,
  508. (SOC_CORE_TIMER_REG + 0x100*core + 4*i), (0x0));
  509. /* Reset per core IRQ ack register */
  510. for (core = 0; core < 4; core++)
  511. QLAFX00_SET_HBA_SOC_REG(ha,
  512. (SOC_IRQ_ACK_REG + 0x100*core), (0x3FF));
  513. /* Set Fabric control and config to defaults */
  514. QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_CONTROL_REG, (0x2));
  515. QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_CONFIG_REG, (0x3));
  516. /* Kick in Fabric units */
  517. QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_RST_CONTROL_REG, (0x0));
  518. /* Kick in Core0 to start boot process */
  519. QLAFX00_SET_HBA_SOC_REG(ha, SOC_SW_RST_CONTROL_REG_CORE0, (0xF00));
  520. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  521. /* Wait 10secs for soft-reset to complete. */
  522. for (cnt = 10; cnt; cnt--) {
  523. msleep(1000);
  524. barrier();
  525. }
  526. }
  527. /**
  528. * qlafx00_soft_reset() - Soft Reset ISPFx00.
  529. * @vha: HA context
  530. *
  531. * Returns 0 on success.
  532. */
  533. void
  534. qlafx00_soft_reset(scsi_qla_host_t *vha)
  535. {
  536. struct qla_hw_data *ha = vha->hw;
  537. if (unlikely(pci_channel_offline(ha->pdev) &&
  538. ha->flags.pci_channel_io_perm_failure))
  539. return;
  540. ha->isp_ops->disable_intrs(ha);
  541. qlafx00_soc_cpu_reset(vha);
  542. }
  543. /**
  544. * qlafx00_chip_diag() - Test ISPFx00 for proper operation.
  545. * @vha: HA context
  546. *
  547. * Returns 0 on success.
  548. */
  549. int
  550. qlafx00_chip_diag(scsi_qla_host_t *vha)
  551. {
  552. int rval = 0;
  553. struct qla_hw_data *ha = vha->hw;
  554. struct req_que *req = ha->req_q_map[0];
  555. ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
  556. rval = qlafx00_mbx_reg_test(vha);
  557. if (rval) {
  558. ql_log(ql_log_warn, vha, 0x1165,
  559. "Failed mailbox send register test\n");
  560. } else {
  561. /* Flag a successful rval */
  562. rval = QLA_SUCCESS;
  563. }
  564. return rval;
  565. }
  566. void
  567. qlafx00_config_rings(struct scsi_qla_host *vha)
  568. {
  569. struct qla_hw_data *ha = vha->hw;
  570. struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
  571. WRT_REG_DWORD(&reg->req_q_in, 0);
  572. WRT_REG_DWORD(&reg->req_q_out, 0);
  573. WRT_REG_DWORD(&reg->rsp_q_in, 0);
  574. WRT_REG_DWORD(&reg->rsp_q_out, 0);
  575. /* PCI posting */
  576. RD_REG_DWORD(&reg->rsp_q_out);
  577. }
  578. char *
  579. qlafx00_pci_info_str(struct scsi_qla_host *vha, char *str)
  580. {
  581. struct qla_hw_data *ha = vha->hw;
  582. if (pci_is_pcie(ha->pdev)) {
  583. strcpy(str, "PCIe iSA");
  584. return str;
  585. }
  586. return str;
  587. }
  588. char *
  589. qlafx00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
  590. {
  591. struct qla_hw_data *ha = vha->hw;
  592. snprintf(str, size, "%s", ha->mr.fw_version);
  593. return str;
  594. }
  595. void
  596. qlafx00_enable_intrs(struct qla_hw_data *ha)
  597. {
  598. unsigned long flags = 0;
  599. spin_lock_irqsave(&ha->hardware_lock, flags);
  600. ha->interrupts_on = 1;
  601. QLAFX00_ENABLE_ICNTRL_REG(ha);
  602. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  603. }
  604. void
  605. qlafx00_disable_intrs(struct qla_hw_data *ha)
  606. {
  607. unsigned long flags = 0;
  608. spin_lock_irqsave(&ha->hardware_lock, flags);
  609. ha->interrupts_on = 0;
  610. QLAFX00_DISABLE_ICNTRL_REG(ha);
  611. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  612. }
  613. int
  614. qlafx00_abort_target(fc_port_t *fcport, uint64_t l, int tag)
  615. {
  616. return qla2x00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag);
  617. }
  618. int
  619. qlafx00_lun_reset(fc_port_t *fcport, uint64_t l, int tag)
  620. {
  621. return qla2x00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag);
  622. }
  623. int
  624. qlafx00_loop_reset(scsi_qla_host_t *vha)
  625. {
  626. int ret;
  627. struct fc_port *fcport;
  628. struct qla_hw_data *ha = vha->hw;
  629. if (ql2xtargetreset) {
  630. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  631. if (fcport->port_type != FCT_TARGET)
  632. continue;
  633. ret = ha->isp_ops->target_reset(fcport, 0, 0);
  634. if (ret != QLA_SUCCESS) {
  635. ql_dbg(ql_dbg_taskm, vha, 0x803d,
  636. "Bus Reset failed: Reset=%d "
  637. "d_id=%x.\n", ret, fcport->d_id.b24);
  638. }
  639. }
  640. }
  641. return QLA_SUCCESS;
  642. }
  643. int
  644. qlafx00_iospace_config(struct qla_hw_data *ha)
  645. {
  646. if (pci_request_selected_regions(ha->pdev, ha->bars,
  647. QLA2XXX_DRIVER_NAME)) {
  648. ql_log_pci(ql_log_fatal, ha->pdev, 0x014e,
  649. "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
  650. pci_name(ha->pdev));
  651. goto iospace_error_exit;
  652. }
  653. /* Use MMIO operations for all accesses. */
  654. if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
  655. ql_log_pci(ql_log_warn, ha->pdev, 0x014f,
  656. "Invalid pci I/O region size (%s).\n",
  657. pci_name(ha->pdev));
  658. goto iospace_error_exit;
  659. }
  660. if (pci_resource_len(ha->pdev, 0) < BAR0_LEN_FX00) {
  661. ql_log_pci(ql_log_warn, ha->pdev, 0x0127,
  662. "Invalid PCI mem BAR0 region size (%s), aborting\n",
  663. pci_name(ha->pdev));
  664. goto iospace_error_exit;
  665. }
  666. ha->cregbase =
  667. ioremap_nocache(pci_resource_start(ha->pdev, 0), BAR0_LEN_FX00);
  668. if (!ha->cregbase) {
  669. ql_log_pci(ql_log_fatal, ha->pdev, 0x0128,
  670. "cannot remap MMIO (%s), aborting\n", pci_name(ha->pdev));
  671. goto iospace_error_exit;
  672. }
  673. if (!(pci_resource_flags(ha->pdev, 2) & IORESOURCE_MEM)) {
  674. ql_log_pci(ql_log_warn, ha->pdev, 0x0129,
  675. "region #2 not an MMIO resource (%s), aborting\n",
  676. pci_name(ha->pdev));
  677. goto iospace_error_exit;
  678. }
  679. if (pci_resource_len(ha->pdev, 2) < BAR2_LEN_FX00) {
  680. ql_log_pci(ql_log_warn, ha->pdev, 0x012a,
  681. "Invalid PCI mem BAR2 region size (%s), aborting\n",
  682. pci_name(ha->pdev));
  683. goto iospace_error_exit;
  684. }
  685. ha->iobase =
  686. ioremap_nocache(pci_resource_start(ha->pdev, 2), BAR2_LEN_FX00);
  687. if (!ha->iobase) {
  688. ql_log_pci(ql_log_fatal, ha->pdev, 0x012b,
  689. "cannot remap MMIO (%s), aborting\n", pci_name(ha->pdev));
  690. goto iospace_error_exit;
  691. }
  692. /* Determine queue resources */
  693. ha->max_req_queues = ha->max_rsp_queues = 1;
  694. ql_log_pci(ql_log_info, ha->pdev, 0x012c,
  695. "Bars 0x%x, iobase0 0x%p, iobase2 0x%p\n",
  696. ha->bars, ha->cregbase, ha->iobase);
  697. return 0;
  698. iospace_error_exit:
  699. return -ENOMEM;
  700. }
  701. static void
  702. qlafx00_save_queue_ptrs(struct scsi_qla_host *vha)
  703. {
  704. struct qla_hw_data *ha = vha->hw;
  705. struct req_que *req = ha->req_q_map[0];
  706. struct rsp_que *rsp = ha->rsp_q_map[0];
  707. req->length_fx00 = req->length;
  708. req->ring_fx00 = req->ring;
  709. req->dma_fx00 = req->dma;
  710. rsp->length_fx00 = rsp->length;
  711. rsp->ring_fx00 = rsp->ring;
  712. rsp->dma_fx00 = rsp->dma;
  713. ql_dbg(ql_dbg_init, vha, 0x012d,
  714. "req: %p, ring_fx00: %p, length_fx00: 0x%x,"
  715. "req->dma_fx00: 0x%llx\n", req, req->ring_fx00,
  716. req->length_fx00, (u64)req->dma_fx00);
  717. ql_dbg(ql_dbg_init, vha, 0x012e,
  718. "rsp: %p, ring_fx00: %p, length_fx00: 0x%x,"
  719. "rsp->dma_fx00: 0x%llx\n", rsp, rsp->ring_fx00,
  720. rsp->length_fx00, (u64)rsp->dma_fx00);
  721. }
  722. static int
  723. qlafx00_config_queues(struct scsi_qla_host *vha)
  724. {
  725. struct qla_hw_data *ha = vha->hw;
  726. struct req_que *req = ha->req_q_map[0];
  727. struct rsp_que *rsp = ha->rsp_q_map[0];
  728. dma_addr_t bar2_hdl = pci_resource_start(ha->pdev, 2);
  729. req->length = ha->req_que_len;
  730. req->ring = (void __force *)ha->iobase + ha->req_que_off;
  731. req->dma = bar2_hdl + ha->req_que_off;
  732. if ((!req->ring) || (req->length == 0)) {
  733. ql_log_pci(ql_log_info, ha->pdev, 0x012f,
  734. "Unable to allocate memory for req_ring\n");
  735. return QLA_FUNCTION_FAILED;
  736. }
  737. ql_dbg(ql_dbg_init, vha, 0x0130,
  738. "req: %p req_ring pointer %p req len 0x%x "
  739. "req off 0x%x\n, req->dma: 0x%llx",
  740. req, req->ring, req->length,
  741. ha->req_que_off, (u64)req->dma);
  742. rsp->length = ha->rsp_que_len;
  743. rsp->ring = (void __force *)ha->iobase + ha->rsp_que_off;
  744. rsp->dma = bar2_hdl + ha->rsp_que_off;
  745. if ((!rsp->ring) || (rsp->length == 0)) {
  746. ql_log_pci(ql_log_info, ha->pdev, 0x0131,
  747. "Unable to allocate memory for rsp_ring\n");
  748. return QLA_FUNCTION_FAILED;
  749. }
  750. ql_dbg(ql_dbg_init, vha, 0x0132,
  751. "rsp: %p rsp_ring pointer %p rsp len 0x%x "
  752. "rsp off 0x%x, rsp->dma: 0x%llx\n",
  753. rsp, rsp->ring, rsp->length,
  754. ha->rsp_que_off, (u64)rsp->dma);
  755. return QLA_SUCCESS;
  756. }
  757. static int
  758. qlafx00_init_fw_ready(scsi_qla_host_t *vha)
  759. {
  760. int rval = 0;
  761. unsigned long wtime;
  762. uint16_t wait_time; /* Wait time */
  763. struct qla_hw_data *ha = vha->hw;
  764. struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
  765. uint32_t aenmbx, aenmbx7 = 0;
  766. uint32_t pseudo_aen;
  767. uint32_t state[5];
  768. bool done = false;
  769. /* 30 seconds wait - Adjust if required */
  770. wait_time = 30;
  771. pseudo_aen = RD_REG_DWORD(&reg->pseudoaen);
  772. if (pseudo_aen == 1) {
  773. aenmbx7 = RD_REG_DWORD(&reg->initval7);
  774. ha->mbx_intr_code = MSW(aenmbx7);
  775. ha->rqstq_intr_code = LSW(aenmbx7);
  776. rval = qlafx00_driver_shutdown(vha, 10);
  777. if (rval != QLA_SUCCESS)
  778. qlafx00_soft_reset(vha);
  779. }
  780. /* wait time before firmware ready */
  781. wtime = jiffies + (wait_time * HZ);
  782. do {
  783. aenmbx = RD_REG_DWORD(&reg->aenmailbox0);
  784. barrier();
  785. ql_dbg(ql_dbg_mbx, vha, 0x0133,
  786. "aenmbx: 0x%x\n", aenmbx);
  787. switch (aenmbx) {
  788. case MBA_FW_NOT_STARTED:
  789. case MBA_FW_STARTING:
  790. break;
  791. case MBA_SYSTEM_ERR:
  792. case MBA_REQ_TRANSFER_ERR:
  793. case MBA_RSP_TRANSFER_ERR:
  794. case MBA_FW_INIT_FAILURE:
  795. qlafx00_soft_reset(vha);
  796. break;
  797. case MBA_FW_RESTART_CMPLT:
  798. /* Set the mbx and rqstq intr code */
  799. aenmbx7 = RD_REG_DWORD(&reg->aenmailbox7);
  800. ha->mbx_intr_code = MSW(aenmbx7);
  801. ha->rqstq_intr_code = LSW(aenmbx7);
  802. ha->req_que_off = RD_REG_DWORD(&reg->aenmailbox1);
  803. ha->rsp_que_off = RD_REG_DWORD(&reg->aenmailbox3);
  804. ha->req_que_len = RD_REG_DWORD(&reg->aenmailbox5);
  805. ha->rsp_que_len = RD_REG_DWORD(&reg->aenmailbox6);
  806. WRT_REG_DWORD(&reg->aenmailbox0, 0);
  807. RD_REG_DWORD_RELAXED(&reg->aenmailbox0);
  808. ql_dbg(ql_dbg_init, vha, 0x0134,
  809. "f/w returned mbx_intr_code: 0x%x, "
  810. "rqstq_intr_code: 0x%x\n",
  811. ha->mbx_intr_code, ha->rqstq_intr_code);
  812. QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
  813. rval = QLA_SUCCESS;
  814. done = true;
  815. break;
  816. default:
  817. if ((aenmbx & 0xFF00) == MBA_FW_INIT_INPROGRESS)
  818. break;
  819. /* If fw is apparently not ready. In order to continue,
  820. * we might need to issue Mbox cmd, but the problem is
  821. * that the DoorBell vector values that come with the
  822. * 8060 AEN are most likely gone by now (and thus no
  823. * bell would be rung on the fw side when mbox cmd is
  824. * issued). We have to therefore grab the 8060 AEN
  825. * shadow regs (filled in by FW when the last 8060
  826. * AEN was being posted).
  827. * Do the following to determine what is needed in
  828. * order to get the FW ready:
  829. * 1. reload the 8060 AEN values from the shadow regs
  830. * 2. clear int status to get rid of possible pending
  831. * interrupts
  832. * 3. issue Get FW State Mbox cmd to determine fw state
  833. * Set the mbx and rqstq intr code from Shadow Regs
  834. */
  835. aenmbx7 = RD_REG_DWORD(&reg->initval7);
  836. ha->mbx_intr_code = MSW(aenmbx7);
  837. ha->rqstq_intr_code = LSW(aenmbx7);
  838. ha->req_que_off = RD_REG_DWORD(&reg->initval1);
  839. ha->rsp_que_off = RD_REG_DWORD(&reg->initval3);
  840. ha->req_que_len = RD_REG_DWORD(&reg->initval5);
  841. ha->rsp_que_len = RD_REG_DWORD(&reg->initval6);
  842. ql_dbg(ql_dbg_init, vha, 0x0135,
  843. "f/w returned mbx_intr_code: 0x%x, "
  844. "rqstq_intr_code: 0x%x\n",
  845. ha->mbx_intr_code, ha->rqstq_intr_code);
  846. QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
  847. /* Get the FW state */
  848. rval = qlafx00_get_firmware_state(vha, state);
  849. if (rval != QLA_SUCCESS) {
  850. /* Retry if timer has not expired */
  851. break;
  852. }
  853. if (state[0] == FSTATE_FX00_CONFIG_WAIT) {
  854. /* Firmware is waiting to be
  855. * initialized by driver
  856. */
  857. rval = QLA_SUCCESS;
  858. done = true;
  859. break;
  860. }
  861. /* Issue driver shutdown and wait until f/w recovers.
  862. * Driver should continue to poll until 8060 AEN is
  863. * received indicating firmware recovery.
  864. */
  865. ql_dbg(ql_dbg_init, vha, 0x0136,
  866. "Sending Driver shutdown fw_state 0x%x\n",
  867. state[0]);
  868. rval = qlafx00_driver_shutdown(vha, 10);
  869. if (rval != QLA_SUCCESS) {
  870. rval = QLA_FUNCTION_FAILED;
  871. break;
  872. }
  873. msleep(500);
  874. wtime = jiffies + (wait_time * HZ);
  875. break;
  876. }
  877. if (!done) {
  878. if (time_after_eq(jiffies, wtime)) {
  879. ql_dbg(ql_dbg_init, vha, 0x0137,
  880. "Init f/w failed: aen[7]: 0x%x\n",
  881. RD_REG_DWORD(&reg->aenmailbox7));
  882. rval = QLA_FUNCTION_FAILED;
  883. done = true;
  884. break;
  885. }
  886. /* Delay for a while */
  887. msleep(500);
  888. }
  889. } while (!done);
  890. if (rval)
  891. ql_dbg(ql_dbg_init, vha, 0x0138,
  892. "%s **** FAILED ****.\n", __func__);
  893. else
  894. ql_dbg(ql_dbg_init, vha, 0x0139,
  895. "%s **** SUCCESS ****.\n", __func__);
  896. return rval;
  897. }
  898. /*
  899. * qlafx00_fw_ready() - Waits for firmware ready.
  900. * @ha: HA context
  901. *
  902. * Returns 0 on success.
  903. */
  904. int
  905. qlafx00_fw_ready(scsi_qla_host_t *vha)
  906. {
  907. int rval;
  908. unsigned long wtime;
  909. uint16_t wait_time; /* Wait time if loop is coming ready */
  910. uint32_t state[5];
  911. rval = QLA_SUCCESS;
  912. wait_time = 10;
  913. /* wait time before firmware ready */
  914. wtime = jiffies + (wait_time * HZ);
  915. /* Wait for ISP to finish init */
  916. if (!vha->flags.init_done)
  917. ql_dbg(ql_dbg_init, vha, 0x013a,
  918. "Waiting for init to complete...\n");
  919. do {
  920. rval = qlafx00_get_firmware_state(vha, state);
  921. if (rval == QLA_SUCCESS) {
  922. if (state[0] == FSTATE_FX00_INITIALIZED) {
  923. ql_dbg(ql_dbg_init, vha, 0x013b,
  924. "fw_state=%x\n", state[0]);
  925. rval = QLA_SUCCESS;
  926. break;
  927. }
  928. }
  929. rval = QLA_FUNCTION_FAILED;
  930. if (time_after_eq(jiffies, wtime))
  931. break;
  932. /* Delay for a while */
  933. msleep(500);
  934. ql_dbg(ql_dbg_init, vha, 0x013c,
  935. "fw_state=%x curr time=%lx.\n", state[0], jiffies);
  936. } while (1);
  937. if (rval)
  938. ql_dbg(ql_dbg_init, vha, 0x013d,
  939. "Firmware ready **** FAILED ****.\n");
  940. else
  941. ql_dbg(ql_dbg_init, vha, 0x013e,
  942. "Firmware ready **** SUCCESS ****.\n");
  943. return rval;
  944. }
  945. static int
  946. qlafx00_find_all_targets(scsi_qla_host_t *vha,
  947. struct list_head *new_fcports)
  948. {
  949. int rval;
  950. uint16_t tgt_id;
  951. fc_port_t *fcport, *new_fcport;
  952. int found;
  953. struct qla_hw_data *ha = vha->hw;
  954. rval = QLA_SUCCESS;
  955. if (!test_bit(LOOP_RESYNC_ACTIVE, &vha->dpc_flags))
  956. return QLA_FUNCTION_FAILED;
  957. if ((atomic_read(&vha->loop_down_timer) ||
  958. STATE_TRANSITION(vha))) {
  959. atomic_set(&vha->loop_down_timer, 0);
  960. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  961. return QLA_FUNCTION_FAILED;
  962. }
  963. ql_dbg(ql_dbg_disc + ql_dbg_init, vha, 0x2088,
  964. "Listing Target bit map...\n");
  965. ql_dump_buffer(ql_dbg_disc + ql_dbg_init, vha,
  966. 0x2089, (uint8_t *)ha->gid_list, 32);
  967. /* Allocate temporary rmtport for any new rmtports discovered. */
  968. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  969. if (new_fcport == NULL)
  970. return QLA_MEMORY_ALLOC_FAILED;
  971. for_each_set_bit(tgt_id, (void *)ha->gid_list,
  972. QLAFX00_TGT_NODE_LIST_SIZE) {
  973. /* Send get target node info */
  974. new_fcport->tgt_id = tgt_id;
  975. rval = qlafx00_fx_disc(vha, new_fcport,
  976. FXDISC_GET_TGT_NODE_INFO);
  977. if (rval != QLA_SUCCESS) {
  978. ql_log(ql_log_warn, vha, 0x208a,
  979. "Target info scan failed -- assuming zero-entry "
  980. "result...\n");
  981. continue;
  982. }
  983. /* Locate matching device in database. */
  984. found = 0;
  985. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  986. if (memcmp(new_fcport->port_name,
  987. fcport->port_name, WWN_SIZE))
  988. continue;
  989. found++;
  990. /*
  991. * If tgt_id is same and state FCS_ONLINE, nothing
  992. * changed.
  993. */
  994. if (fcport->tgt_id == new_fcport->tgt_id &&
  995. atomic_read(&fcport->state) == FCS_ONLINE)
  996. break;
  997. /*
  998. * Tgt ID changed or device was marked to be updated.
  999. */
  1000. ql_dbg(ql_dbg_disc + ql_dbg_init, vha, 0x208b,
  1001. "TGT-ID Change(%s): Present tgt id: "
  1002. "0x%x state: 0x%x "
  1003. "wwnn = %llx wwpn = %llx.\n",
  1004. __func__, fcport->tgt_id,
  1005. atomic_read(&fcport->state),
  1006. (unsigned long long)wwn_to_u64(fcport->node_name),
  1007. (unsigned long long)wwn_to_u64(fcport->port_name));
  1008. ql_log(ql_log_info, vha, 0x208c,
  1009. "TGT-ID Announce(%s): Discovered tgt "
  1010. "id 0x%x wwnn = %llx "
  1011. "wwpn = %llx.\n", __func__, new_fcport->tgt_id,
  1012. (unsigned long long)
  1013. wwn_to_u64(new_fcport->node_name),
  1014. (unsigned long long)
  1015. wwn_to_u64(new_fcport->port_name));
  1016. if (atomic_read(&fcport->state) != FCS_ONLINE) {
  1017. fcport->old_tgt_id = fcport->tgt_id;
  1018. fcport->tgt_id = new_fcport->tgt_id;
  1019. ql_log(ql_log_info, vha, 0x208d,
  1020. "TGT-ID: New fcport Added: %p\n", fcport);
  1021. qla2x00_update_fcport(vha, fcport);
  1022. } else {
  1023. ql_log(ql_log_info, vha, 0x208e,
  1024. " Existing TGT-ID %x did not get "
  1025. " offline event from firmware.\n",
  1026. fcport->old_tgt_id);
  1027. qla2x00_mark_device_lost(vha, fcport, 0, 0);
  1028. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1029. kfree(new_fcport);
  1030. return rval;
  1031. }
  1032. break;
  1033. }
  1034. if (found)
  1035. continue;
  1036. /* If device was not in our fcports list, then add it. */
  1037. list_add_tail(&new_fcport->list, new_fcports);
  1038. /* Allocate a new replacement fcport. */
  1039. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  1040. if (new_fcport == NULL)
  1041. return QLA_MEMORY_ALLOC_FAILED;
  1042. }
  1043. kfree(new_fcport);
  1044. return rval;
  1045. }
  1046. /*
  1047. * qlafx00_configure_all_targets
  1048. * Setup target devices with node ID's.
  1049. *
  1050. * Input:
  1051. * ha = adapter block pointer.
  1052. *
  1053. * Returns:
  1054. * 0 = success.
  1055. * BIT_0 = error
  1056. */
  1057. static int
  1058. qlafx00_configure_all_targets(scsi_qla_host_t *vha)
  1059. {
  1060. int rval;
  1061. fc_port_t *fcport, *rmptemp;
  1062. LIST_HEAD(new_fcports);
  1063. rval = qlafx00_fx_disc(vha, &vha->hw->mr.fcport,
  1064. FXDISC_GET_TGT_NODE_LIST);
  1065. if (rval != QLA_SUCCESS) {
  1066. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1067. return rval;
  1068. }
  1069. rval = qlafx00_find_all_targets(vha, &new_fcports);
  1070. if (rval != QLA_SUCCESS) {
  1071. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1072. return rval;
  1073. }
  1074. /*
  1075. * Delete all previous devices marked lost.
  1076. */
  1077. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  1078. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  1079. break;
  1080. if (atomic_read(&fcport->state) == FCS_DEVICE_LOST) {
  1081. if (fcport->port_type != FCT_INITIATOR)
  1082. qla2x00_mark_device_lost(vha, fcport, 0, 0);
  1083. }
  1084. }
  1085. /*
  1086. * Add the new devices to our devices list.
  1087. */
  1088. list_for_each_entry_safe(fcport, rmptemp, &new_fcports, list) {
  1089. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  1090. break;
  1091. qla2x00_update_fcport(vha, fcport);
  1092. list_move_tail(&fcport->list, &vha->vp_fcports);
  1093. ql_log(ql_log_info, vha, 0x208f,
  1094. "Attach new target id 0x%x wwnn = %llx "
  1095. "wwpn = %llx.\n",
  1096. fcport->tgt_id,
  1097. (unsigned long long)wwn_to_u64(fcport->node_name),
  1098. (unsigned long long)wwn_to_u64(fcport->port_name));
  1099. }
  1100. /* Free all new device structures not processed. */
  1101. list_for_each_entry_safe(fcport, rmptemp, &new_fcports, list) {
  1102. list_del(&fcport->list);
  1103. kfree(fcport);
  1104. }
  1105. return rval;
  1106. }
  1107. /*
  1108. * qlafx00_configure_devices
  1109. * Updates Fibre Channel Device Database with what is actually on loop.
  1110. *
  1111. * Input:
  1112. * ha = adapter block pointer.
  1113. *
  1114. * Returns:
  1115. * 0 = success.
  1116. * 1 = error.
  1117. * 2 = database was full and device was not configured.
  1118. */
  1119. int
  1120. qlafx00_configure_devices(scsi_qla_host_t *vha)
  1121. {
  1122. int rval;
  1123. unsigned long flags;
  1124. rval = QLA_SUCCESS;
  1125. flags = vha->dpc_flags;
  1126. ql_dbg(ql_dbg_disc, vha, 0x2090,
  1127. "Configure devices -- dpc flags =0x%lx\n", flags);
  1128. rval = qlafx00_configure_all_targets(vha);
  1129. if (rval == QLA_SUCCESS) {
  1130. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
  1131. rval = QLA_FUNCTION_FAILED;
  1132. } else {
  1133. atomic_set(&vha->loop_state, LOOP_READY);
  1134. ql_log(ql_log_info, vha, 0x2091,
  1135. "Device Ready\n");
  1136. }
  1137. }
  1138. if (rval) {
  1139. ql_dbg(ql_dbg_disc, vha, 0x2092,
  1140. "%s *** FAILED ***.\n", __func__);
  1141. } else {
  1142. ql_dbg(ql_dbg_disc, vha, 0x2093,
  1143. "%s: exiting normally.\n", __func__);
  1144. }
  1145. return rval;
  1146. }
  1147. static void
  1148. qlafx00_abort_isp_cleanup(scsi_qla_host_t *vha, bool critemp)
  1149. {
  1150. struct qla_hw_data *ha = vha->hw;
  1151. fc_port_t *fcport;
  1152. vha->flags.online = 0;
  1153. ha->mr.fw_hbt_en = 0;
  1154. if (!critemp) {
  1155. ha->flags.chip_reset_done = 0;
  1156. clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1157. vha->qla_stats.total_isp_aborts++;
  1158. ql_log(ql_log_info, vha, 0x013f,
  1159. "Performing ISP error recovery - ha = %p.\n", ha);
  1160. ha->isp_ops->reset_chip(vha);
  1161. }
  1162. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  1163. atomic_set(&vha->loop_state, LOOP_DOWN);
  1164. atomic_set(&vha->loop_down_timer,
  1165. QLAFX00_LOOP_DOWN_TIME);
  1166. } else {
  1167. if (!atomic_read(&vha->loop_down_timer))
  1168. atomic_set(&vha->loop_down_timer,
  1169. QLAFX00_LOOP_DOWN_TIME);
  1170. }
  1171. /* Clear all async request states across all VPs. */
  1172. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  1173. fcport->flags = 0;
  1174. if (atomic_read(&fcport->state) == FCS_ONLINE)
  1175. qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
  1176. }
  1177. if (!ha->flags.eeh_busy) {
  1178. if (critemp) {
  1179. qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
  1180. } else {
  1181. /* Requeue all commands in outstanding command list. */
  1182. qla2x00_abort_all_cmds(vha, DID_RESET << 16);
  1183. }
  1184. }
  1185. qla2x00_free_irqs(vha);
  1186. if (critemp)
  1187. set_bit(FX00_CRITEMP_RECOVERY, &vha->dpc_flags);
  1188. else
  1189. set_bit(FX00_RESET_RECOVERY, &vha->dpc_flags);
  1190. /* Clear the Interrupts */
  1191. QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
  1192. ql_log(ql_log_info, vha, 0x0140,
  1193. "%s Done done - ha=%p.\n", __func__, ha);
  1194. }
  1195. /**
  1196. * qlafx00_init_response_q_entries() - Initializes response queue entries.
  1197. * @rsp: response queue
  1198. *
  1199. * Beginning of request ring has initialization control block already built
  1200. * by nvram config routine.
  1201. *
  1202. * Returns 0 on success.
  1203. */
  1204. void
  1205. qlafx00_init_response_q_entries(struct rsp_que *rsp)
  1206. {
  1207. uint16_t cnt;
  1208. response_t *pkt;
  1209. rsp->ring_ptr = rsp->ring;
  1210. rsp->ring_index = 0;
  1211. rsp->status_srb = NULL;
  1212. pkt = rsp->ring_ptr;
  1213. for (cnt = 0; cnt < rsp->length; cnt++) {
  1214. pkt->signature = RESPONSE_PROCESSED;
  1215. WRT_REG_DWORD((void __force __iomem *)&pkt->signature,
  1216. RESPONSE_PROCESSED);
  1217. pkt++;
  1218. }
  1219. }
  1220. int
  1221. qlafx00_rescan_isp(scsi_qla_host_t *vha)
  1222. {
  1223. uint32_t status = QLA_FUNCTION_FAILED;
  1224. struct qla_hw_data *ha = vha->hw;
  1225. struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
  1226. uint32_t aenmbx7;
  1227. qla2x00_request_irqs(ha, ha->rsp_q_map[0]);
  1228. aenmbx7 = RD_REG_DWORD(&reg->aenmailbox7);
  1229. ha->mbx_intr_code = MSW(aenmbx7);
  1230. ha->rqstq_intr_code = LSW(aenmbx7);
  1231. ha->req_que_off = RD_REG_DWORD(&reg->aenmailbox1);
  1232. ha->rsp_que_off = RD_REG_DWORD(&reg->aenmailbox3);
  1233. ha->req_que_len = RD_REG_DWORD(&reg->aenmailbox5);
  1234. ha->rsp_que_len = RD_REG_DWORD(&reg->aenmailbox6);
  1235. ql_dbg(ql_dbg_disc, vha, 0x2094,
  1236. "fw returned mbx_intr_code: 0x%x, rqstq_intr_code: 0x%x "
  1237. " Req que offset 0x%x Rsp que offset 0x%x\n",
  1238. ha->mbx_intr_code, ha->rqstq_intr_code,
  1239. ha->req_que_off, ha->rsp_que_len);
  1240. /* Clear the Interrupts */
  1241. QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
  1242. status = qla2x00_init_rings(vha);
  1243. if (!status) {
  1244. vha->flags.online = 1;
  1245. /* if no cable then assume it's good */
  1246. if ((vha->device_flags & DFLG_NO_CABLE))
  1247. status = 0;
  1248. /* Register system information */
  1249. if (qlafx00_fx_disc(vha,
  1250. &vha->hw->mr.fcport, FXDISC_REG_HOST_INFO))
  1251. ql_dbg(ql_dbg_disc, vha, 0x2095,
  1252. "failed to register host info\n");
  1253. }
  1254. scsi_unblock_requests(vha->host);
  1255. return status;
  1256. }
  1257. void
  1258. qlafx00_timer_routine(scsi_qla_host_t *vha)
  1259. {
  1260. struct qla_hw_data *ha = vha->hw;
  1261. uint32_t fw_heart_beat;
  1262. uint32_t aenmbx0;
  1263. struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
  1264. uint32_t tempc;
  1265. /* Check firmware health */
  1266. if (ha->mr.fw_hbt_cnt)
  1267. ha->mr.fw_hbt_cnt--;
  1268. else {
  1269. if ((!ha->flags.mr_reset_hdlr_active) &&
  1270. (!test_bit(UNLOADING, &vha->dpc_flags)) &&
  1271. (!test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
  1272. (ha->mr.fw_hbt_en)) {
  1273. fw_heart_beat = RD_REG_DWORD(&reg->fwheartbeat);
  1274. if (fw_heart_beat != ha->mr.old_fw_hbt_cnt) {
  1275. ha->mr.old_fw_hbt_cnt = fw_heart_beat;
  1276. ha->mr.fw_hbt_miss_cnt = 0;
  1277. } else {
  1278. ha->mr.fw_hbt_miss_cnt++;
  1279. if (ha->mr.fw_hbt_miss_cnt ==
  1280. QLAFX00_HEARTBEAT_MISS_CNT) {
  1281. set_bit(ISP_ABORT_NEEDED,
  1282. &vha->dpc_flags);
  1283. qla2xxx_wake_dpc(vha);
  1284. ha->mr.fw_hbt_miss_cnt = 0;
  1285. }
  1286. }
  1287. }
  1288. ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
  1289. }
  1290. if (test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags)) {
  1291. /* Reset recovery to be performed in timer routine */
  1292. aenmbx0 = RD_REG_DWORD(&reg->aenmailbox0);
  1293. if (ha->mr.fw_reset_timer_exp) {
  1294. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1295. qla2xxx_wake_dpc(vha);
  1296. ha->mr.fw_reset_timer_exp = 0;
  1297. } else if (aenmbx0 == MBA_FW_RESTART_CMPLT) {
  1298. /* Wake up DPC to rescan the targets */
  1299. set_bit(FX00_TARGET_SCAN, &vha->dpc_flags);
  1300. clear_bit(FX00_RESET_RECOVERY, &vha->dpc_flags);
  1301. qla2xxx_wake_dpc(vha);
  1302. ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
  1303. } else if ((aenmbx0 == MBA_FW_STARTING) &&
  1304. (!ha->mr.fw_hbt_en)) {
  1305. ha->mr.fw_hbt_en = 1;
  1306. } else if (!ha->mr.fw_reset_timer_tick) {
  1307. if (aenmbx0 == ha->mr.old_aenmbx0_state)
  1308. ha->mr.fw_reset_timer_exp = 1;
  1309. ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
  1310. } else if (aenmbx0 == 0xFFFFFFFF) {
  1311. uint32_t data0, data1;
  1312. data0 = QLAFX00_RD_REG(ha,
  1313. QLAFX00_BAR1_BASE_ADDR_REG);
  1314. data1 = QLAFX00_RD_REG(ha,
  1315. QLAFX00_PEX0_WIN0_BASE_ADDR_REG);
  1316. data0 &= 0xffff0000;
  1317. data1 &= 0x0000ffff;
  1318. QLAFX00_WR_REG(ha,
  1319. QLAFX00_PEX0_WIN0_BASE_ADDR_REG,
  1320. (data0 | data1));
  1321. } else if ((aenmbx0 & 0xFF00) == MBA_FW_POLL_STATE) {
  1322. ha->mr.fw_reset_timer_tick =
  1323. QLAFX00_MAX_RESET_INTERVAL;
  1324. } else if (aenmbx0 == MBA_FW_RESET_FCT) {
  1325. ha->mr.fw_reset_timer_tick =
  1326. QLAFX00_MAX_RESET_INTERVAL;
  1327. }
  1328. if (ha->mr.old_aenmbx0_state != aenmbx0) {
  1329. ha->mr.old_aenmbx0_state = aenmbx0;
  1330. ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
  1331. }
  1332. ha->mr.fw_reset_timer_tick--;
  1333. }
  1334. if (test_bit(FX00_CRITEMP_RECOVERY, &vha->dpc_flags)) {
  1335. /*
  1336. * Critical temperature recovery to be
  1337. * performed in timer routine
  1338. */
  1339. if (ha->mr.fw_critemp_timer_tick == 0) {
  1340. tempc = QLAFX00_GET_TEMPERATURE(ha);
  1341. ql_dbg(ql_dbg_timer, vha, 0x6012,
  1342. "ISPFx00(%s): Critical temp timer, "
  1343. "current SOC temperature: %d\n",
  1344. __func__, tempc);
  1345. if (tempc < ha->mr.critical_temperature) {
  1346. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1347. clear_bit(FX00_CRITEMP_RECOVERY,
  1348. &vha->dpc_flags);
  1349. qla2xxx_wake_dpc(vha);
  1350. }
  1351. ha->mr.fw_critemp_timer_tick =
  1352. QLAFX00_CRITEMP_INTERVAL;
  1353. } else {
  1354. ha->mr.fw_critemp_timer_tick--;
  1355. }
  1356. }
  1357. if (ha->mr.host_info_resend) {
  1358. /*
  1359. * Incomplete host info might be sent to firmware
  1360. * durinng system boot - info should be resend
  1361. */
  1362. if (ha->mr.hinfo_resend_timer_tick == 0) {
  1363. ha->mr.host_info_resend = false;
  1364. set_bit(FX00_HOST_INFO_RESEND, &vha->dpc_flags);
  1365. ha->mr.hinfo_resend_timer_tick =
  1366. QLAFX00_HINFO_RESEND_INTERVAL;
  1367. qla2xxx_wake_dpc(vha);
  1368. } else {
  1369. ha->mr.hinfo_resend_timer_tick--;
  1370. }
  1371. }
  1372. }
  1373. /*
  1374. * qlfx00a_reset_initialize
  1375. * Re-initialize after a iSA device reset.
  1376. *
  1377. * Input:
  1378. * ha = adapter block pointer.
  1379. *
  1380. * Returns:
  1381. * 0 = success
  1382. */
  1383. int
  1384. qlafx00_reset_initialize(scsi_qla_host_t *vha)
  1385. {
  1386. struct qla_hw_data *ha = vha->hw;
  1387. if (vha->device_flags & DFLG_DEV_FAILED) {
  1388. ql_dbg(ql_dbg_init, vha, 0x0142,
  1389. "Device in failed state\n");
  1390. return QLA_SUCCESS;
  1391. }
  1392. ha->flags.mr_reset_hdlr_active = 1;
  1393. if (vha->flags.online) {
  1394. scsi_block_requests(vha->host);
  1395. qlafx00_abort_isp_cleanup(vha, false);
  1396. }
  1397. ql_log(ql_log_info, vha, 0x0143,
  1398. "(%s): succeeded.\n", __func__);
  1399. ha->flags.mr_reset_hdlr_active = 0;
  1400. return QLA_SUCCESS;
  1401. }
  1402. /*
  1403. * qlafx00_abort_isp
  1404. * Resets ISP and aborts all outstanding commands.
  1405. *
  1406. * Input:
  1407. * ha = adapter block pointer.
  1408. *
  1409. * Returns:
  1410. * 0 = success
  1411. */
  1412. int
  1413. qlafx00_abort_isp(scsi_qla_host_t *vha)
  1414. {
  1415. struct qla_hw_data *ha = vha->hw;
  1416. if (vha->flags.online) {
  1417. if (unlikely(pci_channel_offline(ha->pdev) &&
  1418. ha->flags.pci_channel_io_perm_failure)) {
  1419. clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  1420. return QLA_SUCCESS;
  1421. }
  1422. scsi_block_requests(vha->host);
  1423. qlafx00_abort_isp_cleanup(vha, false);
  1424. } else {
  1425. scsi_block_requests(vha->host);
  1426. clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1427. vha->qla_stats.total_isp_aborts++;
  1428. ha->isp_ops->reset_chip(vha);
  1429. set_bit(FX00_RESET_RECOVERY, &vha->dpc_flags);
  1430. /* Clear the Interrupts */
  1431. QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
  1432. }
  1433. ql_log(ql_log_info, vha, 0x0145,
  1434. "(%s): succeeded.\n", __func__);
  1435. return QLA_SUCCESS;
  1436. }
  1437. static inline fc_port_t*
  1438. qlafx00_get_fcport(struct scsi_qla_host *vha, int tgt_id)
  1439. {
  1440. fc_port_t *fcport;
  1441. /* Check for matching device in remote port list. */
  1442. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  1443. if (fcport->tgt_id == tgt_id) {
  1444. ql_dbg(ql_dbg_async, vha, 0x5072,
  1445. "Matching fcport(%p) found with TGT-ID: 0x%x "
  1446. "and Remote TGT_ID: 0x%x\n",
  1447. fcport, fcport->tgt_id, tgt_id);
  1448. return fcport;
  1449. }
  1450. }
  1451. return NULL;
  1452. }
  1453. static void
  1454. qlafx00_tgt_detach(struct scsi_qla_host *vha, int tgt_id)
  1455. {
  1456. fc_port_t *fcport;
  1457. ql_log(ql_log_info, vha, 0x5073,
  1458. "Detach TGT-ID: 0x%x\n", tgt_id);
  1459. fcport = qlafx00_get_fcport(vha, tgt_id);
  1460. if (!fcport)
  1461. return;
  1462. qla2x00_mark_device_lost(vha, fcport, 0, 0);
  1463. return;
  1464. }
  1465. int
  1466. qlafx00_process_aen(struct scsi_qla_host *vha, struct qla_work_evt *evt)
  1467. {
  1468. int rval = 0;
  1469. uint32_t aen_code, aen_data;
  1470. aen_code = FCH_EVT_VENDOR_UNIQUE;
  1471. aen_data = evt->u.aenfx.evtcode;
  1472. switch (evt->u.aenfx.evtcode) {
  1473. case QLAFX00_MBA_PORT_UPDATE: /* Port database update */
  1474. if (evt->u.aenfx.mbx[1] == 0) {
  1475. if (evt->u.aenfx.mbx[2] == 1) {
  1476. if (!vha->flags.fw_tgt_reported)
  1477. vha->flags.fw_tgt_reported = 1;
  1478. atomic_set(&vha->loop_down_timer, 0);
  1479. atomic_set(&vha->loop_state, LOOP_UP);
  1480. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1481. qla2xxx_wake_dpc(vha);
  1482. } else if (evt->u.aenfx.mbx[2] == 2) {
  1483. qlafx00_tgt_detach(vha, evt->u.aenfx.mbx[3]);
  1484. }
  1485. } else if (evt->u.aenfx.mbx[1] == 0xffff) {
  1486. if (evt->u.aenfx.mbx[2] == 1) {
  1487. if (!vha->flags.fw_tgt_reported)
  1488. vha->flags.fw_tgt_reported = 1;
  1489. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1490. } else if (evt->u.aenfx.mbx[2] == 2) {
  1491. vha->device_flags |= DFLG_NO_CABLE;
  1492. qla2x00_mark_all_devices_lost(vha, 1);
  1493. }
  1494. }
  1495. break;
  1496. case QLAFX00_MBA_LINK_UP:
  1497. aen_code = FCH_EVT_LINKUP;
  1498. aen_data = 0;
  1499. break;
  1500. case QLAFX00_MBA_LINK_DOWN:
  1501. aen_code = FCH_EVT_LINKDOWN;
  1502. aen_data = 0;
  1503. break;
  1504. case QLAFX00_MBA_TEMP_CRIT: /* Critical temperature event */
  1505. ql_log(ql_log_info, vha, 0x5082,
  1506. "Process critical temperature event "
  1507. "aenmb[0]: %x\n",
  1508. evt->u.aenfx.evtcode);
  1509. scsi_block_requests(vha->host);
  1510. qlafx00_abort_isp_cleanup(vha, true);
  1511. scsi_unblock_requests(vha->host);
  1512. break;
  1513. }
  1514. fc_host_post_event(vha->host, fc_get_event_number(),
  1515. aen_code, aen_data);
  1516. return rval;
  1517. }
  1518. static void
  1519. qlafx00_update_host_attr(scsi_qla_host_t *vha, struct port_info_data *pinfo)
  1520. {
  1521. u64 port_name = 0, node_name = 0;
  1522. port_name = (unsigned long long)wwn_to_u64(pinfo->port_name);
  1523. node_name = (unsigned long long)wwn_to_u64(pinfo->node_name);
  1524. fc_host_node_name(vha->host) = node_name;
  1525. fc_host_port_name(vha->host) = port_name;
  1526. if (!pinfo->port_type)
  1527. vha->hw->current_topology = ISP_CFG_F;
  1528. if (pinfo->link_status == QLAFX00_LINK_STATUS_UP)
  1529. atomic_set(&vha->loop_state, LOOP_READY);
  1530. else if (pinfo->link_status == QLAFX00_LINK_STATUS_DOWN)
  1531. atomic_set(&vha->loop_state, LOOP_DOWN);
  1532. vha->hw->link_data_rate = (uint16_t)pinfo->link_config;
  1533. }
  1534. static void
  1535. qla2x00_fxdisc_iocb_timeout(void *data)
  1536. {
  1537. srb_t *sp = data;
  1538. struct srb_iocb *lio = &sp->u.iocb_cmd;
  1539. complete(&lio->u.fxiocb.fxiocb_comp);
  1540. }
  1541. static void
  1542. qla2x00_fxdisc_sp_done(void *ptr, int res)
  1543. {
  1544. srb_t *sp = ptr;
  1545. struct srb_iocb *lio = &sp->u.iocb_cmd;
  1546. complete(&lio->u.fxiocb.fxiocb_comp);
  1547. }
  1548. int
  1549. qlafx00_fx_disc(scsi_qla_host_t *vha, fc_port_t *fcport, uint16_t fx_type)
  1550. {
  1551. srb_t *sp;
  1552. struct srb_iocb *fdisc;
  1553. int rval = QLA_FUNCTION_FAILED;
  1554. struct qla_hw_data *ha = vha->hw;
  1555. struct host_system_info *phost_info;
  1556. struct register_host_info *preg_hsi;
  1557. struct new_utsname *p_sysid = NULL;
  1558. sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
  1559. if (!sp)
  1560. goto done;
  1561. sp->type = SRB_FXIOCB_DCMD;
  1562. sp->name = "fxdisc";
  1563. fdisc = &sp->u.iocb_cmd;
  1564. fdisc->timeout = qla2x00_fxdisc_iocb_timeout;
  1565. qla2x00_init_timer(sp, FXDISC_TIMEOUT);
  1566. switch (fx_type) {
  1567. case FXDISC_GET_CONFIG_INFO:
  1568. fdisc->u.fxiocb.flags =
  1569. SRB_FXDISC_RESP_DMA_VALID;
  1570. fdisc->u.fxiocb.rsp_len = sizeof(struct config_info_data);
  1571. break;
  1572. case FXDISC_GET_PORT_INFO:
  1573. fdisc->u.fxiocb.flags =
  1574. SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID;
  1575. fdisc->u.fxiocb.rsp_len = QLAFX00_PORT_DATA_INFO;
  1576. fdisc->u.fxiocb.req_data = cpu_to_le32(fcport->port_id);
  1577. break;
  1578. case FXDISC_GET_TGT_NODE_INFO:
  1579. fdisc->u.fxiocb.flags =
  1580. SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID;
  1581. fdisc->u.fxiocb.rsp_len = QLAFX00_TGT_NODE_INFO;
  1582. fdisc->u.fxiocb.req_data = cpu_to_le32(fcport->tgt_id);
  1583. break;
  1584. case FXDISC_GET_TGT_NODE_LIST:
  1585. fdisc->u.fxiocb.flags =
  1586. SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID;
  1587. fdisc->u.fxiocb.rsp_len = QLAFX00_TGT_NODE_LIST_SIZE;
  1588. break;
  1589. case FXDISC_REG_HOST_INFO:
  1590. fdisc->u.fxiocb.flags = SRB_FXDISC_REQ_DMA_VALID;
  1591. fdisc->u.fxiocb.req_len = sizeof(struct register_host_info);
  1592. p_sysid = utsname();
  1593. if (!p_sysid) {
  1594. ql_log(ql_log_warn, vha, 0x303c,
  1595. "Not able to get the system information\n");
  1596. goto done_free_sp;
  1597. }
  1598. break;
  1599. case FXDISC_ABORT_IOCTL:
  1600. default:
  1601. break;
  1602. }
  1603. if (fdisc->u.fxiocb.flags & SRB_FXDISC_REQ_DMA_VALID) {
  1604. fdisc->u.fxiocb.req_addr = dma_alloc_coherent(&ha->pdev->dev,
  1605. fdisc->u.fxiocb.req_len,
  1606. &fdisc->u.fxiocb.req_dma_handle, GFP_KERNEL);
  1607. if (!fdisc->u.fxiocb.req_addr)
  1608. goto done_free_sp;
  1609. if (fx_type == FXDISC_REG_HOST_INFO) {
  1610. preg_hsi = (struct register_host_info *)
  1611. fdisc->u.fxiocb.req_addr;
  1612. phost_info = &preg_hsi->hsi;
  1613. memset(preg_hsi, 0, sizeof(struct register_host_info));
  1614. phost_info->os_type = OS_TYPE_LINUX;
  1615. strncpy(phost_info->sysname,
  1616. p_sysid->sysname, SYSNAME_LENGTH);
  1617. strncpy(phost_info->nodename,
  1618. p_sysid->nodename, NODENAME_LENGTH);
  1619. if (!strcmp(phost_info->nodename, "(none)"))
  1620. ha->mr.host_info_resend = true;
  1621. strncpy(phost_info->release,
  1622. p_sysid->release, RELEASE_LENGTH);
  1623. strncpy(phost_info->version,
  1624. p_sysid->version, VERSION_LENGTH);
  1625. strncpy(phost_info->machine,
  1626. p_sysid->machine, MACHINE_LENGTH);
  1627. strncpy(phost_info->domainname,
  1628. p_sysid->domainname, DOMNAME_LENGTH);
  1629. strncpy(phost_info->hostdriver,
  1630. QLA2XXX_VERSION, VERSION_LENGTH);
  1631. preg_hsi->utc = (uint64_t)ktime_get_real_seconds();
  1632. ql_dbg(ql_dbg_init, vha, 0x0149,
  1633. "ISP%04X: Host registration with firmware\n",
  1634. ha->pdev->device);
  1635. ql_dbg(ql_dbg_init, vha, 0x014a,
  1636. "os_type = '%d', sysname = '%s', nodname = '%s'\n",
  1637. phost_info->os_type,
  1638. phost_info->sysname,
  1639. phost_info->nodename);
  1640. ql_dbg(ql_dbg_init, vha, 0x014b,
  1641. "release = '%s', version = '%s'\n",
  1642. phost_info->release,
  1643. phost_info->version);
  1644. ql_dbg(ql_dbg_init, vha, 0x014c,
  1645. "machine = '%s' "
  1646. "domainname = '%s', hostdriver = '%s'\n",
  1647. phost_info->machine,
  1648. phost_info->domainname,
  1649. phost_info->hostdriver);
  1650. ql_dump_buffer(ql_dbg_init + ql_dbg_disc, vha, 0x014d,
  1651. (uint8_t *)phost_info,
  1652. sizeof(struct host_system_info));
  1653. }
  1654. }
  1655. if (fdisc->u.fxiocb.flags & SRB_FXDISC_RESP_DMA_VALID) {
  1656. fdisc->u.fxiocb.rsp_addr = dma_alloc_coherent(&ha->pdev->dev,
  1657. fdisc->u.fxiocb.rsp_len,
  1658. &fdisc->u.fxiocb.rsp_dma_handle, GFP_KERNEL);
  1659. if (!fdisc->u.fxiocb.rsp_addr)
  1660. goto done_unmap_req;
  1661. }
  1662. fdisc->u.fxiocb.req_func_type = cpu_to_le16(fx_type);
  1663. sp->done = qla2x00_fxdisc_sp_done;
  1664. rval = qla2x00_start_sp(sp);
  1665. if (rval != QLA_SUCCESS)
  1666. goto done_unmap_dma;
  1667. wait_for_completion(&fdisc->u.fxiocb.fxiocb_comp);
  1668. if (fx_type == FXDISC_GET_CONFIG_INFO) {
  1669. struct config_info_data *pinfo =
  1670. (struct config_info_data *) fdisc->u.fxiocb.rsp_addr;
  1671. strcpy(vha->hw->model_number, pinfo->model_num);
  1672. strcpy(vha->hw->model_desc, pinfo->model_description);
  1673. memcpy(&vha->hw->mr.symbolic_name, pinfo->symbolic_name,
  1674. sizeof(vha->hw->mr.symbolic_name));
  1675. memcpy(&vha->hw->mr.serial_num, pinfo->serial_num,
  1676. sizeof(vha->hw->mr.serial_num));
  1677. memcpy(&vha->hw->mr.hw_version, pinfo->hw_version,
  1678. sizeof(vha->hw->mr.hw_version));
  1679. memcpy(&vha->hw->mr.fw_version, pinfo->fw_version,
  1680. sizeof(vha->hw->mr.fw_version));
  1681. strim(vha->hw->mr.fw_version);
  1682. memcpy(&vha->hw->mr.uboot_version, pinfo->uboot_version,
  1683. sizeof(vha->hw->mr.uboot_version));
  1684. memcpy(&vha->hw->mr.fru_serial_num, pinfo->fru_serial_num,
  1685. sizeof(vha->hw->mr.fru_serial_num));
  1686. vha->hw->mr.critical_temperature =
  1687. (pinfo->nominal_temp_value) ?
  1688. pinfo->nominal_temp_value : QLAFX00_CRITEMP_THRSHLD;
  1689. ha->mr.extended_io_enabled = (pinfo->enabled_capabilities &
  1690. QLAFX00_EXTENDED_IO_EN_MASK) != 0;
  1691. } else if (fx_type == FXDISC_GET_PORT_INFO) {
  1692. struct port_info_data *pinfo =
  1693. (struct port_info_data *) fdisc->u.fxiocb.rsp_addr;
  1694. memcpy(vha->node_name, pinfo->node_name, WWN_SIZE);
  1695. memcpy(vha->port_name, pinfo->port_name, WWN_SIZE);
  1696. vha->d_id.b.domain = pinfo->port_id[0];
  1697. vha->d_id.b.area = pinfo->port_id[1];
  1698. vha->d_id.b.al_pa = pinfo->port_id[2];
  1699. qlafx00_update_host_attr(vha, pinfo);
  1700. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0141,
  1701. (uint8_t *)pinfo, 16);
  1702. } else if (fx_type == FXDISC_GET_TGT_NODE_INFO) {
  1703. struct qlafx00_tgt_node_info *pinfo =
  1704. (struct qlafx00_tgt_node_info *) fdisc->u.fxiocb.rsp_addr;
  1705. memcpy(fcport->node_name, pinfo->tgt_node_wwnn, WWN_SIZE);
  1706. memcpy(fcport->port_name, pinfo->tgt_node_wwpn, WWN_SIZE);
  1707. fcport->port_type = FCT_TARGET;
  1708. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0144,
  1709. (uint8_t *)pinfo, 16);
  1710. } else if (fx_type == FXDISC_GET_TGT_NODE_LIST) {
  1711. struct qlafx00_tgt_node_info *pinfo =
  1712. (struct qlafx00_tgt_node_info *) fdisc->u.fxiocb.rsp_addr;
  1713. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0146,
  1714. (uint8_t *)pinfo, 16);
  1715. memcpy(vha->hw->gid_list, pinfo, QLAFX00_TGT_NODE_LIST_SIZE);
  1716. } else if (fx_type == FXDISC_ABORT_IOCTL)
  1717. fdisc->u.fxiocb.result =
  1718. (fdisc->u.fxiocb.result ==
  1719. cpu_to_le32(QLAFX00_IOCTL_ICOB_ABORT_SUCCESS)) ?
  1720. cpu_to_le32(QLA_SUCCESS) : cpu_to_le32(QLA_FUNCTION_FAILED);
  1721. rval = le32_to_cpu(fdisc->u.fxiocb.result);
  1722. done_unmap_dma:
  1723. if (fdisc->u.fxiocb.rsp_addr)
  1724. dma_free_coherent(&ha->pdev->dev, fdisc->u.fxiocb.rsp_len,
  1725. fdisc->u.fxiocb.rsp_addr, fdisc->u.fxiocb.rsp_dma_handle);
  1726. done_unmap_req:
  1727. if (fdisc->u.fxiocb.req_addr)
  1728. dma_free_coherent(&ha->pdev->dev, fdisc->u.fxiocb.req_len,
  1729. fdisc->u.fxiocb.req_addr, fdisc->u.fxiocb.req_dma_handle);
  1730. done_free_sp:
  1731. sp->free(sp);
  1732. done:
  1733. return rval;
  1734. }
  1735. /*
  1736. * qlafx00_initialize_adapter
  1737. * Initialize board.
  1738. *
  1739. * Input:
  1740. * ha = adapter block pointer.
  1741. *
  1742. * Returns:
  1743. * 0 = success
  1744. */
  1745. int
  1746. qlafx00_initialize_adapter(scsi_qla_host_t *vha)
  1747. {
  1748. int rval;
  1749. struct qla_hw_data *ha = vha->hw;
  1750. uint32_t tempc;
  1751. /* Clear adapter flags. */
  1752. vha->flags.online = 0;
  1753. ha->flags.chip_reset_done = 0;
  1754. vha->flags.reset_active = 0;
  1755. ha->flags.pci_channel_io_perm_failure = 0;
  1756. ha->flags.eeh_busy = 0;
  1757. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  1758. atomic_set(&vha->loop_state, LOOP_DOWN);
  1759. vha->device_flags = DFLG_NO_CABLE;
  1760. vha->dpc_flags = 0;
  1761. vha->flags.management_server_logged_in = 0;
  1762. ha->isp_abort_cnt = 0;
  1763. ha->beacon_blink_led = 0;
  1764. set_bit(0, ha->req_qid_map);
  1765. set_bit(0, ha->rsp_qid_map);
  1766. ql_dbg(ql_dbg_init, vha, 0x0147,
  1767. "Configuring PCI space...\n");
  1768. rval = ha->isp_ops->pci_config(vha);
  1769. if (rval) {
  1770. ql_log(ql_log_warn, vha, 0x0148,
  1771. "Unable to configure PCI space.\n");
  1772. return rval;
  1773. }
  1774. rval = qlafx00_init_fw_ready(vha);
  1775. if (rval != QLA_SUCCESS)
  1776. return rval;
  1777. qlafx00_save_queue_ptrs(vha);
  1778. rval = qlafx00_config_queues(vha);
  1779. if (rval != QLA_SUCCESS)
  1780. return rval;
  1781. /*
  1782. * Allocate the array of outstanding commands
  1783. * now that we know the firmware resources.
  1784. */
  1785. rval = qla2x00_alloc_outstanding_cmds(ha, vha->req);
  1786. if (rval != QLA_SUCCESS)
  1787. return rval;
  1788. rval = qla2x00_init_rings(vha);
  1789. ha->flags.chip_reset_done = 1;
  1790. tempc = QLAFX00_GET_TEMPERATURE(ha);
  1791. ql_dbg(ql_dbg_init, vha, 0x0152,
  1792. "ISPFx00(%s): Critical temp timer, current SOC temperature: 0x%x\n",
  1793. __func__, tempc);
  1794. return rval;
  1795. }
  1796. uint32_t
  1797. qlafx00_fw_state_show(struct device *dev, struct device_attribute *attr,
  1798. char *buf)
  1799. {
  1800. scsi_qla_host_t *vha = shost_priv(class_to_shost(dev));
  1801. int rval = QLA_FUNCTION_FAILED;
  1802. uint32_t state[1];
  1803. if (qla2x00_reset_active(vha))
  1804. ql_log(ql_log_warn, vha, 0x70ce,
  1805. "ISP reset active.\n");
  1806. else if (!vha->hw->flags.eeh_busy) {
  1807. rval = qlafx00_get_firmware_state(vha, state);
  1808. }
  1809. if (rval != QLA_SUCCESS)
  1810. memset(state, -1, sizeof(state));
  1811. return state[0];
  1812. }
  1813. void
  1814. qlafx00_get_host_speed(struct Scsi_Host *shost)
  1815. {
  1816. struct qla_hw_data *ha = ((struct scsi_qla_host *)
  1817. (shost_priv(shost)))->hw;
  1818. u32 speed = FC_PORTSPEED_UNKNOWN;
  1819. switch (ha->link_data_rate) {
  1820. case QLAFX00_PORT_SPEED_2G:
  1821. speed = FC_PORTSPEED_2GBIT;
  1822. break;
  1823. case QLAFX00_PORT_SPEED_4G:
  1824. speed = FC_PORTSPEED_4GBIT;
  1825. break;
  1826. case QLAFX00_PORT_SPEED_8G:
  1827. speed = FC_PORTSPEED_8GBIT;
  1828. break;
  1829. case QLAFX00_PORT_SPEED_10G:
  1830. speed = FC_PORTSPEED_10GBIT;
  1831. break;
  1832. }
  1833. fc_host_speed(shost) = speed;
  1834. }
  1835. /** QLAFX00 specific ISR implementation functions */
  1836. static inline void
  1837. qlafx00_handle_sense(srb_t *sp, uint8_t *sense_data, uint32_t par_sense_len,
  1838. uint32_t sense_len, struct rsp_que *rsp, int res)
  1839. {
  1840. struct scsi_qla_host *vha = sp->vha;
  1841. struct scsi_cmnd *cp = GET_CMD_SP(sp);
  1842. uint32_t track_sense_len;
  1843. SET_FW_SENSE_LEN(sp, sense_len);
  1844. if (sense_len >= SCSI_SENSE_BUFFERSIZE)
  1845. sense_len = SCSI_SENSE_BUFFERSIZE;
  1846. SET_CMD_SENSE_LEN(sp, sense_len);
  1847. SET_CMD_SENSE_PTR(sp, cp->sense_buffer);
  1848. track_sense_len = sense_len;
  1849. if (sense_len > par_sense_len)
  1850. sense_len = par_sense_len;
  1851. memcpy(cp->sense_buffer, sense_data, sense_len);
  1852. SET_FW_SENSE_LEN(sp, GET_FW_SENSE_LEN(sp) - sense_len);
  1853. SET_CMD_SENSE_PTR(sp, cp->sense_buffer + sense_len);
  1854. track_sense_len -= sense_len;
  1855. SET_CMD_SENSE_LEN(sp, track_sense_len);
  1856. ql_dbg(ql_dbg_io, vha, 0x304d,
  1857. "sense_len=0x%x par_sense_len=0x%x track_sense_len=0x%x.\n",
  1858. sense_len, par_sense_len, track_sense_len);
  1859. if (GET_FW_SENSE_LEN(sp) > 0) {
  1860. rsp->status_srb = sp;
  1861. cp->result = res;
  1862. }
  1863. if (sense_len) {
  1864. ql_dbg(ql_dbg_io + ql_dbg_buffer, vha, 0x3039,
  1865. "Check condition Sense data, nexus%ld:%d:%llu cmd=%p.\n",
  1866. sp->vha->host_no, cp->device->id, cp->device->lun,
  1867. cp);
  1868. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x3049,
  1869. cp->sense_buffer, sense_len);
  1870. }
  1871. }
  1872. static void
  1873. qlafx00_tm_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
  1874. struct tsk_mgmt_entry_fx00 *pkt, srb_t *sp,
  1875. __le16 sstatus, __le16 cpstatus)
  1876. {
  1877. struct srb_iocb *tmf;
  1878. tmf = &sp->u.iocb_cmd;
  1879. if (cpstatus != cpu_to_le16((uint16_t)CS_COMPLETE) ||
  1880. (sstatus & cpu_to_le16((uint16_t)SS_RESPONSE_INFO_LEN_VALID)))
  1881. cpstatus = cpu_to_le16((uint16_t)CS_INCOMPLETE);
  1882. tmf->u.tmf.comp_status = cpstatus;
  1883. sp->done(sp, 0);
  1884. }
  1885. static void
  1886. qlafx00_abort_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
  1887. struct abort_iocb_entry_fx00 *pkt)
  1888. {
  1889. const char func[] = "ABT_IOCB";
  1890. srb_t *sp;
  1891. struct srb_iocb *abt;
  1892. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1893. if (!sp)
  1894. return;
  1895. abt = &sp->u.iocb_cmd;
  1896. abt->u.abt.comp_status = pkt->tgt_id_sts;
  1897. sp->done(sp, 0);
  1898. }
  1899. static void
  1900. qlafx00_ioctl_iosb_entry(scsi_qla_host_t *vha, struct req_que *req,
  1901. struct ioctl_iocb_entry_fx00 *pkt)
  1902. {
  1903. const char func[] = "IOSB_IOCB";
  1904. srb_t *sp;
  1905. struct bsg_job *bsg_job;
  1906. struct fc_bsg_reply *bsg_reply;
  1907. struct srb_iocb *iocb_job;
  1908. int res;
  1909. struct qla_mt_iocb_rsp_fx00 fstatus;
  1910. uint8_t *fw_sts_ptr;
  1911. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1912. if (!sp)
  1913. return;
  1914. if (sp->type == SRB_FXIOCB_DCMD) {
  1915. iocb_job = &sp->u.iocb_cmd;
  1916. iocb_job->u.fxiocb.seq_number = pkt->seq_no;
  1917. iocb_job->u.fxiocb.fw_flags = pkt->fw_iotcl_flags;
  1918. iocb_job->u.fxiocb.result = pkt->status;
  1919. if (iocb_job->u.fxiocb.flags & SRB_FXDISC_RSP_DWRD_VALID)
  1920. iocb_job->u.fxiocb.req_data =
  1921. pkt->dataword_r;
  1922. } else {
  1923. bsg_job = sp->u.bsg_job;
  1924. bsg_reply = bsg_job->reply;
  1925. memset(&fstatus, 0, sizeof(struct qla_mt_iocb_rsp_fx00));
  1926. fstatus.reserved_1 = pkt->reserved_0;
  1927. fstatus.func_type = pkt->comp_func_num;
  1928. fstatus.ioctl_flags = pkt->fw_iotcl_flags;
  1929. fstatus.ioctl_data = pkt->dataword_r;
  1930. fstatus.adapid = pkt->adapid;
  1931. fstatus.reserved_2 = pkt->dataword_r_extra;
  1932. fstatus.res_count = pkt->residuallen;
  1933. fstatus.status = pkt->status;
  1934. fstatus.seq_number = pkt->seq_no;
  1935. memcpy(fstatus.reserved_3,
  1936. pkt->reserved_2, 20 * sizeof(uint8_t));
  1937. fw_sts_ptr = bsg_job->reply + sizeof(struct fc_bsg_reply);
  1938. memcpy(fw_sts_ptr, (uint8_t *)&fstatus,
  1939. sizeof(struct qla_mt_iocb_rsp_fx00));
  1940. bsg_job->reply_len = sizeof(struct fc_bsg_reply) +
  1941. sizeof(struct qla_mt_iocb_rsp_fx00) + sizeof(uint8_t);
  1942. ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
  1943. sp->fcport->vha, 0x5080,
  1944. (uint8_t *)pkt, sizeof(struct ioctl_iocb_entry_fx00));
  1945. ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
  1946. sp->fcport->vha, 0x5074,
  1947. (uint8_t *)fw_sts_ptr, sizeof(struct qla_mt_iocb_rsp_fx00));
  1948. res = bsg_reply->result = DID_OK << 16;
  1949. bsg_reply->reply_payload_rcv_len =
  1950. bsg_job->reply_payload.payload_len;
  1951. }
  1952. sp->done(sp, res);
  1953. }
  1954. /**
  1955. * qlafx00_status_entry() - Process a Status IOCB entry.
  1956. * @vha: SCSI driver HA context
  1957. * @rsp: response queue
  1958. * @pkt: Entry pointer
  1959. */
  1960. static void
  1961. qlafx00_status_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, void *pkt)
  1962. {
  1963. srb_t *sp;
  1964. fc_port_t *fcport;
  1965. struct scsi_cmnd *cp;
  1966. struct sts_entry_fx00 *sts;
  1967. __le16 comp_status;
  1968. __le16 scsi_status;
  1969. __le16 lscsi_status;
  1970. int32_t resid;
  1971. uint32_t sense_len, par_sense_len, rsp_info_len, resid_len,
  1972. fw_resid_len;
  1973. uint8_t *rsp_info = NULL, *sense_data = NULL;
  1974. struct qla_hw_data *ha = vha->hw;
  1975. uint32_t hindex, handle;
  1976. uint16_t que;
  1977. struct req_que *req;
  1978. int logit = 1;
  1979. int res = 0;
  1980. sts = (struct sts_entry_fx00 *) pkt;
  1981. comp_status = sts->comp_status;
  1982. scsi_status = sts->scsi_status & cpu_to_le16((uint16_t)SS_MASK);
  1983. hindex = sts->handle;
  1984. handle = LSW(hindex);
  1985. que = MSW(hindex);
  1986. req = ha->req_q_map[que];
  1987. /* Validate handle. */
  1988. if (handle < req->num_outstanding_cmds)
  1989. sp = req->outstanding_cmds[handle];
  1990. else
  1991. sp = NULL;
  1992. if (sp == NULL) {
  1993. ql_dbg(ql_dbg_io, vha, 0x3034,
  1994. "Invalid status handle (0x%x).\n", handle);
  1995. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1996. qla2xxx_wake_dpc(vha);
  1997. return;
  1998. }
  1999. if (sp->type == SRB_TM_CMD) {
  2000. req->outstanding_cmds[handle] = NULL;
  2001. qlafx00_tm_iocb_entry(vha, req, pkt, sp,
  2002. scsi_status, comp_status);
  2003. return;
  2004. }
  2005. /* Fast path completion. */
  2006. if (comp_status == CS_COMPLETE && scsi_status == 0) {
  2007. qla2x00_process_completed_request(vha, req, handle);
  2008. return;
  2009. }
  2010. req->outstanding_cmds[handle] = NULL;
  2011. cp = GET_CMD_SP(sp);
  2012. if (cp == NULL) {
  2013. ql_dbg(ql_dbg_io, vha, 0x3048,
  2014. "Command already returned (0x%x/%p).\n",
  2015. handle, sp);
  2016. return;
  2017. }
  2018. lscsi_status = scsi_status & cpu_to_le16((uint16_t)STATUS_MASK);
  2019. fcport = sp->fcport;
  2020. sense_len = par_sense_len = rsp_info_len = resid_len =
  2021. fw_resid_len = 0;
  2022. if (scsi_status & cpu_to_le16((uint16_t)SS_SENSE_LEN_VALID))
  2023. sense_len = sts->sense_len;
  2024. if (scsi_status & cpu_to_le16(((uint16_t)SS_RESIDUAL_UNDER
  2025. | (uint16_t)SS_RESIDUAL_OVER)))
  2026. resid_len = le32_to_cpu(sts->residual_len);
  2027. if (comp_status == cpu_to_le16((uint16_t)CS_DATA_UNDERRUN))
  2028. fw_resid_len = le32_to_cpu(sts->residual_len);
  2029. rsp_info = sense_data = sts->data;
  2030. par_sense_len = sizeof(sts->data);
  2031. /* Check for overrun. */
  2032. if (comp_status == CS_COMPLETE &&
  2033. scsi_status & cpu_to_le16((uint16_t)SS_RESIDUAL_OVER))
  2034. comp_status = cpu_to_le16((uint16_t)CS_DATA_OVERRUN);
  2035. /*
  2036. * Based on Host and scsi status generate status code for Linux
  2037. */
  2038. switch (le16_to_cpu(comp_status)) {
  2039. case CS_COMPLETE:
  2040. case CS_QUEUE_FULL:
  2041. if (scsi_status == 0) {
  2042. res = DID_OK << 16;
  2043. break;
  2044. }
  2045. if (scsi_status & cpu_to_le16(((uint16_t)SS_RESIDUAL_UNDER
  2046. | (uint16_t)SS_RESIDUAL_OVER))) {
  2047. resid = resid_len;
  2048. scsi_set_resid(cp, resid);
  2049. if (!lscsi_status &&
  2050. ((unsigned)(scsi_bufflen(cp) - resid) <
  2051. cp->underflow)) {
  2052. ql_dbg(ql_dbg_io, fcport->vha, 0x3050,
  2053. "Mid-layer underflow "
  2054. "detected (0x%x of 0x%x bytes).\n",
  2055. resid, scsi_bufflen(cp));
  2056. res = DID_ERROR << 16;
  2057. break;
  2058. }
  2059. }
  2060. res = DID_OK << 16 | le16_to_cpu(lscsi_status);
  2061. if (lscsi_status ==
  2062. cpu_to_le16((uint16_t)SAM_STAT_TASK_SET_FULL)) {
  2063. ql_dbg(ql_dbg_io, fcport->vha, 0x3051,
  2064. "QUEUE FULL detected.\n");
  2065. break;
  2066. }
  2067. logit = 0;
  2068. if (lscsi_status != cpu_to_le16((uint16_t)SS_CHECK_CONDITION))
  2069. break;
  2070. memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
  2071. if (!(scsi_status & cpu_to_le16((uint16_t)SS_SENSE_LEN_VALID)))
  2072. break;
  2073. qlafx00_handle_sense(sp, sense_data, par_sense_len, sense_len,
  2074. rsp, res);
  2075. break;
  2076. case CS_DATA_UNDERRUN:
  2077. /* Use F/W calculated residual length. */
  2078. if (IS_FWI2_CAPABLE(ha) || IS_QLAFX00(ha))
  2079. resid = fw_resid_len;
  2080. else
  2081. resid = resid_len;
  2082. scsi_set_resid(cp, resid);
  2083. if (scsi_status & cpu_to_le16((uint16_t)SS_RESIDUAL_UNDER)) {
  2084. if ((IS_FWI2_CAPABLE(ha) || IS_QLAFX00(ha))
  2085. && fw_resid_len != resid_len) {
  2086. ql_dbg(ql_dbg_io, fcport->vha, 0x3052,
  2087. "Dropped frame(s) detected "
  2088. "(0x%x of 0x%x bytes).\n",
  2089. resid, scsi_bufflen(cp));
  2090. res = DID_ERROR << 16 |
  2091. le16_to_cpu(lscsi_status);
  2092. goto check_scsi_status;
  2093. }
  2094. if (!lscsi_status &&
  2095. ((unsigned)(scsi_bufflen(cp) - resid) <
  2096. cp->underflow)) {
  2097. ql_dbg(ql_dbg_io, fcport->vha, 0x3053,
  2098. "Mid-layer underflow "
  2099. "detected (0x%x of 0x%x bytes, "
  2100. "cp->underflow: 0x%x).\n",
  2101. resid, scsi_bufflen(cp), cp->underflow);
  2102. res = DID_ERROR << 16;
  2103. break;
  2104. }
  2105. } else if (lscsi_status !=
  2106. cpu_to_le16((uint16_t)SAM_STAT_TASK_SET_FULL) &&
  2107. lscsi_status != cpu_to_le16((uint16_t)SAM_STAT_BUSY)) {
  2108. /*
  2109. * scsi status of task set and busy are considered
  2110. * to be task not completed.
  2111. */
  2112. ql_dbg(ql_dbg_io, fcport->vha, 0x3054,
  2113. "Dropped frame(s) detected (0x%x "
  2114. "of 0x%x bytes).\n", resid,
  2115. scsi_bufflen(cp));
  2116. res = DID_ERROR << 16 | le16_to_cpu(lscsi_status);
  2117. goto check_scsi_status;
  2118. } else {
  2119. ql_dbg(ql_dbg_io, fcport->vha, 0x3055,
  2120. "scsi_status: 0x%x, lscsi_status: 0x%x\n",
  2121. scsi_status, lscsi_status);
  2122. }
  2123. res = DID_OK << 16 | le16_to_cpu(lscsi_status);
  2124. logit = 0;
  2125. check_scsi_status:
  2126. /*
  2127. * Check to see if SCSI Status is non zero. If so report SCSI
  2128. * Status.
  2129. */
  2130. if (lscsi_status != 0) {
  2131. if (lscsi_status ==
  2132. cpu_to_le16((uint16_t)SAM_STAT_TASK_SET_FULL)) {
  2133. ql_dbg(ql_dbg_io, fcport->vha, 0x3056,
  2134. "QUEUE FULL detected.\n");
  2135. logit = 1;
  2136. break;
  2137. }
  2138. if (lscsi_status !=
  2139. cpu_to_le16((uint16_t)SS_CHECK_CONDITION))
  2140. break;
  2141. memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
  2142. if (!(scsi_status &
  2143. cpu_to_le16((uint16_t)SS_SENSE_LEN_VALID)))
  2144. break;
  2145. qlafx00_handle_sense(sp, sense_data, par_sense_len,
  2146. sense_len, rsp, res);
  2147. }
  2148. break;
  2149. case CS_PORT_LOGGED_OUT:
  2150. case CS_PORT_CONFIG_CHG:
  2151. case CS_PORT_BUSY:
  2152. case CS_INCOMPLETE:
  2153. case CS_PORT_UNAVAILABLE:
  2154. case CS_TIMEOUT:
  2155. case CS_RESET:
  2156. /*
  2157. * We are going to have the fc class block the rport
  2158. * while we try to recover so instruct the mid layer
  2159. * to requeue until the class decides how to handle this.
  2160. */
  2161. res = DID_TRANSPORT_DISRUPTED << 16;
  2162. ql_dbg(ql_dbg_io, fcport->vha, 0x3057,
  2163. "Port down status: port-state=0x%x.\n",
  2164. atomic_read(&fcport->state));
  2165. if (atomic_read(&fcport->state) == FCS_ONLINE)
  2166. qla2x00_mark_device_lost(fcport->vha, fcport, 1, 1);
  2167. break;
  2168. case CS_ABORTED:
  2169. res = DID_RESET << 16;
  2170. break;
  2171. default:
  2172. res = DID_ERROR << 16;
  2173. break;
  2174. }
  2175. if (logit)
  2176. ql_dbg(ql_dbg_io, fcport->vha, 0x3058,
  2177. "FCP command status: 0x%x-0x%x (0x%x) nexus=%ld:%d:%llu "
  2178. "tgt_id: 0x%x lscsi_status: 0x%x cdb=%10phN len=0x%x "
  2179. "rsp_info=%p resid=0x%x fw_resid=0x%x sense_len=0x%x, "
  2180. "par_sense_len=0x%x, rsp_info_len=0x%x\n",
  2181. comp_status, scsi_status, res, vha->host_no,
  2182. cp->device->id, cp->device->lun, fcport->tgt_id,
  2183. lscsi_status, cp->cmnd, scsi_bufflen(cp),
  2184. rsp_info, resid_len, fw_resid_len, sense_len,
  2185. par_sense_len, rsp_info_len);
  2186. if (rsp->status_srb == NULL)
  2187. sp->done(sp, res);
  2188. }
  2189. /**
  2190. * qlafx00_status_cont_entry() - Process a Status Continuations entry.
  2191. * @rsp: response queue
  2192. * @pkt: Entry pointer
  2193. *
  2194. * Extended sense data.
  2195. */
  2196. static void
  2197. qlafx00_status_cont_entry(struct rsp_que *rsp, sts_cont_entry_t *pkt)
  2198. {
  2199. uint8_t sense_sz = 0;
  2200. struct qla_hw_data *ha = rsp->hw;
  2201. struct scsi_qla_host *vha = pci_get_drvdata(ha->pdev);
  2202. srb_t *sp = rsp->status_srb;
  2203. struct scsi_cmnd *cp;
  2204. uint32_t sense_len;
  2205. uint8_t *sense_ptr;
  2206. if (!sp) {
  2207. ql_dbg(ql_dbg_io, vha, 0x3037,
  2208. "no SP, sp = %p\n", sp);
  2209. return;
  2210. }
  2211. if (!GET_FW_SENSE_LEN(sp)) {
  2212. ql_dbg(ql_dbg_io, vha, 0x304b,
  2213. "no fw sense data, sp = %p\n", sp);
  2214. return;
  2215. }
  2216. cp = GET_CMD_SP(sp);
  2217. if (cp == NULL) {
  2218. ql_log(ql_log_warn, vha, 0x303b,
  2219. "cmd is NULL: already returned to OS (sp=%p).\n", sp);
  2220. rsp->status_srb = NULL;
  2221. return;
  2222. }
  2223. if (!GET_CMD_SENSE_LEN(sp)) {
  2224. ql_dbg(ql_dbg_io, vha, 0x304c,
  2225. "no sense data, sp = %p\n", sp);
  2226. } else {
  2227. sense_len = GET_CMD_SENSE_LEN(sp);
  2228. sense_ptr = GET_CMD_SENSE_PTR(sp);
  2229. ql_dbg(ql_dbg_io, vha, 0x304f,
  2230. "sp=%p sense_len=0x%x sense_ptr=%p.\n",
  2231. sp, sense_len, sense_ptr);
  2232. if (sense_len > sizeof(pkt->data))
  2233. sense_sz = sizeof(pkt->data);
  2234. else
  2235. sense_sz = sense_len;
  2236. /* Move sense data. */
  2237. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x304e,
  2238. (uint8_t *)pkt, sizeof(sts_cont_entry_t));
  2239. memcpy(sense_ptr, pkt->data, sense_sz);
  2240. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x304a,
  2241. sense_ptr, sense_sz);
  2242. sense_len -= sense_sz;
  2243. sense_ptr += sense_sz;
  2244. SET_CMD_SENSE_PTR(sp, sense_ptr);
  2245. SET_CMD_SENSE_LEN(sp, sense_len);
  2246. }
  2247. sense_len = GET_FW_SENSE_LEN(sp);
  2248. sense_len = (sense_len > sizeof(pkt->data)) ?
  2249. (sense_len - sizeof(pkt->data)) : 0;
  2250. SET_FW_SENSE_LEN(sp, sense_len);
  2251. /* Place command on done queue. */
  2252. if (sense_len == 0) {
  2253. rsp->status_srb = NULL;
  2254. sp->done(sp, cp->result);
  2255. }
  2256. }
  2257. /**
  2258. * qlafx00_multistatus_entry() - Process Multi response queue entries.
  2259. * @vha: SCSI driver HA context
  2260. * @rsp: response queue
  2261. * @pkt:
  2262. */
  2263. static void
  2264. qlafx00_multistatus_entry(struct scsi_qla_host *vha,
  2265. struct rsp_que *rsp, void *pkt)
  2266. {
  2267. srb_t *sp;
  2268. struct multi_sts_entry_fx00 *stsmfx;
  2269. struct qla_hw_data *ha = vha->hw;
  2270. uint32_t handle, hindex, handle_count, i;
  2271. uint16_t que;
  2272. struct req_que *req;
  2273. __le32 *handle_ptr;
  2274. stsmfx = (struct multi_sts_entry_fx00 *) pkt;
  2275. handle_count = stsmfx->handle_count;
  2276. if (handle_count > MAX_HANDLE_COUNT) {
  2277. ql_dbg(ql_dbg_io, vha, 0x3035,
  2278. "Invalid handle count (0x%x).\n", handle_count);
  2279. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2280. qla2xxx_wake_dpc(vha);
  2281. return;
  2282. }
  2283. handle_ptr = &stsmfx->handles[0];
  2284. for (i = 0; i < handle_count; i++) {
  2285. hindex = le32_to_cpu(*handle_ptr);
  2286. handle = LSW(hindex);
  2287. que = MSW(hindex);
  2288. req = ha->req_q_map[que];
  2289. /* Validate handle. */
  2290. if (handle < req->num_outstanding_cmds)
  2291. sp = req->outstanding_cmds[handle];
  2292. else
  2293. sp = NULL;
  2294. if (sp == NULL) {
  2295. ql_dbg(ql_dbg_io, vha, 0x3044,
  2296. "Invalid status handle (0x%x).\n", handle);
  2297. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2298. qla2xxx_wake_dpc(vha);
  2299. return;
  2300. }
  2301. qla2x00_process_completed_request(vha, req, handle);
  2302. handle_ptr++;
  2303. }
  2304. }
  2305. /**
  2306. * qlafx00_error_entry() - Process an error entry.
  2307. * @vha: SCSI driver HA context
  2308. * @rsp: response queue
  2309. * @pkt: Entry pointer
  2310. * @estatus:
  2311. * @etype:
  2312. */
  2313. static void
  2314. qlafx00_error_entry(scsi_qla_host_t *vha, struct rsp_que *rsp,
  2315. struct sts_entry_fx00 *pkt, uint8_t estatus, uint8_t etype)
  2316. {
  2317. srb_t *sp;
  2318. struct qla_hw_data *ha = vha->hw;
  2319. const char func[] = "ERROR-IOCB";
  2320. uint16_t que = 0;
  2321. struct req_que *req = NULL;
  2322. int res = DID_ERROR << 16;
  2323. ql_dbg(ql_dbg_async, vha, 0x507f,
  2324. "type of error status in response: 0x%x\n", estatus);
  2325. req = ha->req_q_map[que];
  2326. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  2327. if (sp) {
  2328. sp->done(sp, res);
  2329. return;
  2330. }
  2331. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2332. qla2xxx_wake_dpc(vha);
  2333. }
  2334. /**
  2335. * qlafx00_process_response_queue() - Process response queue entries.
  2336. * @vha: SCSI driver HA context
  2337. * @rsp: response queue
  2338. */
  2339. static void
  2340. qlafx00_process_response_queue(struct scsi_qla_host *vha,
  2341. struct rsp_que *rsp)
  2342. {
  2343. struct sts_entry_fx00 *pkt;
  2344. response_t *lptr;
  2345. uint16_t lreq_q_in = 0;
  2346. uint16_t lreq_q_out = 0;
  2347. lreq_q_in = RD_REG_DWORD(rsp->rsp_q_in);
  2348. lreq_q_out = rsp->ring_index;
  2349. while (lreq_q_in != lreq_q_out) {
  2350. lptr = rsp->ring_ptr;
  2351. memcpy_fromio(rsp->rsp_pkt, (void __iomem *)lptr,
  2352. sizeof(rsp->rsp_pkt));
  2353. pkt = (struct sts_entry_fx00 *)rsp->rsp_pkt;
  2354. rsp->ring_index++;
  2355. lreq_q_out++;
  2356. if (rsp->ring_index == rsp->length) {
  2357. lreq_q_out = 0;
  2358. rsp->ring_index = 0;
  2359. rsp->ring_ptr = rsp->ring;
  2360. } else {
  2361. rsp->ring_ptr++;
  2362. }
  2363. if (pkt->entry_status != 0 &&
  2364. pkt->entry_type != IOCTL_IOSB_TYPE_FX00) {
  2365. qlafx00_error_entry(vha, rsp,
  2366. (struct sts_entry_fx00 *)pkt, pkt->entry_status,
  2367. pkt->entry_type);
  2368. continue;
  2369. }
  2370. switch (pkt->entry_type) {
  2371. case STATUS_TYPE_FX00:
  2372. qlafx00_status_entry(vha, rsp, pkt);
  2373. break;
  2374. case STATUS_CONT_TYPE_FX00:
  2375. qlafx00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
  2376. break;
  2377. case MULTI_STATUS_TYPE_FX00:
  2378. qlafx00_multistatus_entry(vha, rsp, pkt);
  2379. break;
  2380. case ABORT_IOCB_TYPE_FX00:
  2381. qlafx00_abort_iocb_entry(vha, rsp->req,
  2382. (struct abort_iocb_entry_fx00 *)pkt);
  2383. break;
  2384. case IOCTL_IOSB_TYPE_FX00:
  2385. qlafx00_ioctl_iosb_entry(vha, rsp->req,
  2386. (struct ioctl_iocb_entry_fx00 *)pkt);
  2387. break;
  2388. default:
  2389. /* Type Not Supported. */
  2390. ql_dbg(ql_dbg_async, vha, 0x5081,
  2391. "Received unknown response pkt type %x "
  2392. "entry status=%x.\n",
  2393. pkt->entry_type, pkt->entry_status);
  2394. break;
  2395. }
  2396. }
  2397. /* Adjust ring index */
  2398. WRT_REG_DWORD(rsp->rsp_q_out, rsp->ring_index);
  2399. }
  2400. /**
  2401. * qlafx00_async_event() - Process aynchronous events.
  2402. * @vha: SCSI driver HA context
  2403. */
  2404. static void
  2405. qlafx00_async_event(scsi_qla_host_t *vha)
  2406. {
  2407. struct qla_hw_data *ha = vha->hw;
  2408. struct device_reg_fx00 __iomem *reg;
  2409. int data_size = 1;
  2410. reg = &ha->iobase->ispfx00;
  2411. /* Setup to process RIO completion. */
  2412. switch (ha->aenmb[0]) {
  2413. case QLAFX00_MBA_SYSTEM_ERR: /* System Error */
  2414. ql_log(ql_log_warn, vha, 0x5079,
  2415. "ISP System Error - mbx1=%x\n", ha->aenmb[0]);
  2416. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2417. break;
  2418. case QLAFX00_MBA_SHUTDOWN_RQSTD: /* Shutdown requested */
  2419. ql_dbg(ql_dbg_async, vha, 0x5076,
  2420. "Asynchronous FW shutdown requested.\n");
  2421. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2422. qla2xxx_wake_dpc(vha);
  2423. break;
  2424. case QLAFX00_MBA_PORT_UPDATE: /* Port database update */
  2425. ha->aenmb[1] = RD_REG_DWORD(&reg->aenmailbox1);
  2426. ha->aenmb[2] = RD_REG_DWORD(&reg->aenmailbox2);
  2427. ha->aenmb[3] = RD_REG_DWORD(&reg->aenmailbox3);
  2428. ql_dbg(ql_dbg_async, vha, 0x5077,
  2429. "Asynchronous port Update received "
  2430. "aenmb[0]: %x, aenmb[1]: %x, aenmb[2]: %x, aenmb[3]: %x\n",
  2431. ha->aenmb[0], ha->aenmb[1], ha->aenmb[2], ha->aenmb[3]);
  2432. data_size = 4;
  2433. break;
  2434. case QLAFX00_MBA_TEMP_OVER: /* Over temperature event */
  2435. ql_log(ql_log_info, vha, 0x5085,
  2436. "Asynchronous over temperature event received "
  2437. "aenmb[0]: %x\n",
  2438. ha->aenmb[0]);
  2439. break;
  2440. case QLAFX00_MBA_TEMP_NORM: /* Normal temperature event */
  2441. ql_log(ql_log_info, vha, 0x5086,
  2442. "Asynchronous normal temperature event received "
  2443. "aenmb[0]: %x\n",
  2444. ha->aenmb[0]);
  2445. break;
  2446. case QLAFX00_MBA_TEMP_CRIT: /* Critical temperature event */
  2447. ql_log(ql_log_info, vha, 0x5083,
  2448. "Asynchronous critical temperature event received "
  2449. "aenmb[0]: %x\n",
  2450. ha->aenmb[0]);
  2451. break;
  2452. default:
  2453. ha->aenmb[1] = RD_REG_WORD(&reg->aenmailbox1);
  2454. ha->aenmb[2] = RD_REG_WORD(&reg->aenmailbox2);
  2455. ha->aenmb[3] = RD_REG_WORD(&reg->aenmailbox3);
  2456. ha->aenmb[4] = RD_REG_WORD(&reg->aenmailbox4);
  2457. ha->aenmb[5] = RD_REG_WORD(&reg->aenmailbox5);
  2458. ha->aenmb[6] = RD_REG_WORD(&reg->aenmailbox6);
  2459. ha->aenmb[7] = RD_REG_WORD(&reg->aenmailbox7);
  2460. ql_dbg(ql_dbg_async, vha, 0x5078,
  2461. "AEN:%04x %04x %04x %04x :%04x %04x %04x %04x\n",
  2462. ha->aenmb[0], ha->aenmb[1], ha->aenmb[2], ha->aenmb[3],
  2463. ha->aenmb[4], ha->aenmb[5], ha->aenmb[6], ha->aenmb[7]);
  2464. break;
  2465. }
  2466. qlafx00_post_aenfx_work(vha, ha->aenmb[0],
  2467. (uint32_t *)ha->aenmb, data_size);
  2468. }
  2469. /**
  2470. * qlafx00x_mbx_completion() - Process mailbox command completions.
  2471. * @vha: SCSI driver HA context
  2472. * @mb0:
  2473. */
  2474. static void
  2475. qlafx00_mbx_completion(scsi_qla_host_t *vha, uint32_t mb0)
  2476. {
  2477. uint16_t cnt;
  2478. uint32_t __iomem *wptr;
  2479. struct qla_hw_data *ha = vha->hw;
  2480. struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
  2481. if (!ha->mcp32)
  2482. ql_dbg(ql_dbg_async, vha, 0x507e, "MBX pointer ERROR.\n");
  2483. /* Load return mailbox registers. */
  2484. ha->flags.mbox_int = 1;
  2485. ha->mailbox_out32[0] = mb0;
  2486. wptr = (uint32_t __iomem *)&reg->mailbox17;
  2487. for (cnt = 1; cnt < ha->mbx_count; cnt++) {
  2488. ha->mailbox_out32[cnt] = RD_REG_DWORD(wptr);
  2489. wptr++;
  2490. }
  2491. }
  2492. /**
  2493. * qlafx00_intr_handler() - Process interrupts for the ISPFX00.
  2494. * @irq:
  2495. * @dev_id: SCSI driver HA context
  2496. *
  2497. * Called by system whenever the host adapter generates an interrupt.
  2498. *
  2499. * Returns handled flag.
  2500. */
  2501. irqreturn_t
  2502. qlafx00_intr_handler(int irq, void *dev_id)
  2503. {
  2504. scsi_qla_host_t *vha;
  2505. struct qla_hw_data *ha;
  2506. struct device_reg_fx00 __iomem *reg;
  2507. int status;
  2508. unsigned long iter;
  2509. uint32_t stat;
  2510. uint32_t mb[8];
  2511. struct rsp_que *rsp;
  2512. unsigned long flags;
  2513. uint32_t clr_intr = 0;
  2514. uint32_t intr_stat = 0;
  2515. rsp = (struct rsp_que *) dev_id;
  2516. if (!rsp) {
  2517. ql_log(ql_log_info, NULL, 0x507d,
  2518. "%s: NULL response queue pointer.\n", __func__);
  2519. return IRQ_NONE;
  2520. }
  2521. ha = rsp->hw;
  2522. reg = &ha->iobase->ispfx00;
  2523. status = 0;
  2524. if (unlikely(pci_channel_offline(ha->pdev)))
  2525. return IRQ_HANDLED;
  2526. spin_lock_irqsave(&ha->hardware_lock, flags);
  2527. vha = pci_get_drvdata(ha->pdev);
  2528. for (iter = 50; iter--; clr_intr = 0) {
  2529. stat = QLAFX00_RD_INTR_REG(ha);
  2530. if (qla2x00_check_reg32_for_disconnect(vha, stat))
  2531. break;
  2532. intr_stat = stat & QLAFX00_HST_INT_STS_BITS;
  2533. if (!intr_stat)
  2534. break;
  2535. if (stat & QLAFX00_INTR_MB_CMPLT) {
  2536. mb[0] = RD_REG_WORD(&reg->mailbox16);
  2537. qlafx00_mbx_completion(vha, mb[0]);
  2538. status |= MBX_INTERRUPT;
  2539. clr_intr |= QLAFX00_INTR_MB_CMPLT;
  2540. }
  2541. if (intr_stat & QLAFX00_INTR_ASYNC_CMPLT) {
  2542. ha->aenmb[0] = RD_REG_WORD(&reg->aenmailbox0);
  2543. qlafx00_async_event(vha);
  2544. clr_intr |= QLAFX00_INTR_ASYNC_CMPLT;
  2545. }
  2546. if (intr_stat & QLAFX00_INTR_RSP_CMPLT) {
  2547. qlafx00_process_response_queue(vha, rsp);
  2548. clr_intr |= QLAFX00_INTR_RSP_CMPLT;
  2549. }
  2550. QLAFX00_CLR_INTR_REG(ha, clr_intr);
  2551. QLAFX00_RD_INTR_REG(ha);
  2552. }
  2553. qla2x00_handle_mbx_completion(ha, status);
  2554. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2555. return IRQ_HANDLED;
  2556. }
  2557. /** QLAFX00 specific IOCB implementation functions */
  2558. static inline cont_a64_entry_t *
  2559. qlafx00_prep_cont_type1_iocb(struct req_que *req,
  2560. cont_a64_entry_t *lcont_pkt)
  2561. {
  2562. cont_a64_entry_t *cont_pkt;
  2563. /* Adjust ring index. */
  2564. req->ring_index++;
  2565. if (req->ring_index == req->length) {
  2566. req->ring_index = 0;
  2567. req->ring_ptr = req->ring;
  2568. } else {
  2569. req->ring_ptr++;
  2570. }
  2571. cont_pkt = (cont_a64_entry_t *)req->ring_ptr;
  2572. /* Load packet defaults. */
  2573. lcont_pkt->entry_type = CONTINUE_A64_TYPE_FX00;
  2574. return cont_pkt;
  2575. }
  2576. static inline void
  2577. qlafx00_build_scsi_iocbs(srb_t *sp, struct cmd_type_7_fx00 *cmd_pkt,
  2578. uint16_t tot_dsds, struct cmd_type_7_fx00 *lcmd_pkt)
  2579. {
  2580. uint16_t avail_dsds;
  2581. __le32 *cur_dsd;
  2582. scsi_qla_host_t *vha;
  2583. struct scsi_cmnd *cmd;
  2584. struct scatterlist *sg;
  2585. int i, cont;
  2586. struct req_que *req;
  2587. cont_a64_entry_t lcont_pkt;
  2588. cont_a64_entry_t *cont_pkt;
  2589. vha = sp->vha;
  2590. req = vha->req;
  2591. cmd = GET_CMD_SP(sp);
  2592. cont = 0;
  2593. cont_pkt = NULL;
  2594. /* Update entry type to indicate Command Type 3 IOCB */
  2595. lcmd_pkt->entry_type = FX00_COMMAND_TYPE_7;
  2596. /* No data transfer */
  2597. if (!scsi_bufflen(cmd) || cmd->sc_data_direction == DMA_NONE) {
  2598. lcmd_pkt->byte_count = cpu_to_le32(0);
  2599. return;
  2600. }
  2601. /* Set transfer direction */
  2602. if (cmd->sc_data_direction == DMA_TO_DEVICE) {
  2603. lcmd_pkt->cntrl_flags = TMF_WRITE_DATA;
  2604. vha->qla_stats.output_bytes += scsi_bufflen(cmd);
  2605. } else if (cmd->sc_data_direction == DMA_FROM_DEVICE) {
  2606. lcmd_pkt->cntrl_flags = TMF_READ_DATA;
  2607. vha->qla_stats.input_bytes += scsi_bufflen(cmd);
  2608. }
  2609. /* One DSD is available in the Command Type 3 IOCB */
  2610. avail_dsds = 1;
  2611. cur_dsd = (__le32 *)&lcmd_pkt->dseg_0_address;
  2612. /* Load data segments */
  2613. scsi_for_each_sg(cmd, sg, tot_dsds, i) {
  2614. dma_addr_t sle_dma;
  2615. /* Allocate additional continuation packets? */
  2616. if (avail_dsds == 0) {
  2617. /*
  2618. * Five DSDs are available in the Continuation
  2619. * Type 1 IOCB.
  2620. */
  2621. memset(&lcont_pkt, 0, REQUEST_ENTRY_SIZE);
  2622. cont_pkt =
  2623. qlafx00_prep_cont_type1_iocb(req, &lcont_pkt);
  2624. cur_dsd = (__le32 *)lcont_pkt.dseg_0_address;
  2625. avail_dsds = 5;
  2626. cont = 1;
  2627. }
  2628. sle_dma = sg_dma_address(sg);
  2629. *cur_dsd++ = cpu_to_le32(LSD(sle_dma));
  2630. *cur_dsd++ = cpu_to_le32(MSD(sle_dma));
  2631. *cur_dsd++ = cpu_to_le32(sg_dma_len(sg));
  2632. avail_dsds--;
  2633. if (avail_dsds == 0 && cont == 1) {
  2634. cont = 0;
  2635. memcpy_toio((void __iomem *)cont_pkt, &lcont_pkt,
  2636. REQUEST_ENTRY_SIZE);
  2637. }
  2638. }
  2639. if (avail_dsds != 0 && cont == 1) {
  2640. memcpy_toio((void __iomem *)cont_pkt, &lcont_pkt,
  2641. REQUEST_ENTRY_SIZE);
  2642. }
  2643. }
  2644. /**
  2645. * qlafx00_start_scsi() - Send a SCSI command to the ISP
  2646. * @sp: command to send to the ISP
  2647. *
  2648. * Returns non-zero if a failure occurred, else zero.
  2649. */
  2650. int
  2651. qlafx00_start_scsi(srb_t *sp)
  2652. {
  2653. int nseg;
  2654. unsigned long flags;
  2655. uint32_t index;
  2656. uint32_t handle;
  2657. uint16_t cnt;
  2658. uint16_t req_cnt;
  2659. uint16_t tot_dsds;
  2660. struct req_que *req = NULL;
  2661. struct rsp_que *rsp = NULL;
  2662. struct scsi_cmnd *cmd = GET_CMD_SP(sp);
  2663. struct scsi_qla_host *vha = sp->vha;
  2664. struct qla_hw_data *ha = vha->hw;
  2665. struct cmd_type_7_fx00 *cmd_pkt;
  2666. struct cmd_type_7_fx00 lcmd_pkt;
  2667. struct scsi_lun llun;
  2668. /* Setup device pointers. */
  2669. rsp = ha->rsp_q_map[0];
  2670. req = vha->req;
  2671. /* So we know we haven't pci_map'ed anything yet */
  2672. tot_dsds = 0;
  2673. /* Acquire ring specific lock */
  2674. spin_lock_irqsave(&ha->hardware_lock, flags);
  2675. /* Check for room in outstanding command list. */
  2676. handle = req->current_outstanding_cmd;
  2677. for (index = 1; index < req->num_outstanding_cmds; index++) {
  2678. handle++;
  2679. if (handle == req->num_outstanding_cmds)
  2680. handle = 1;
  2681. if (!req->outstanding_cmds[handle])
  2682. break;
  2683. }
  2684. if (index == req->num_outstanding_cmds)
  2685. goto queuing_error;
  2686. /* Map the sg table so we have an accurate count of sg entries needed */
  2687. if (scsi_sg_count(cmd)) {
  2688. nseg = dma_map_sg(&ha->pdev->dev, scsi_sglist(cmd),
  2689. scsi_sg_count(cmd), cmd->sc_data_direction);
  2690. if (unlikely(!nseg))
  2691. goto queuing_error;
  2692. } else
  2693. nseg = 0;
  2694. tot_dsds = nseg;
  2695. req_cnt = qla24xx_calc_iocbs(vha, tot_dsds);
  2696. if (req->cnt < (req_cnt + 2)) {
  2697. cnt = RD_REG_DWORD_RELAXED(req->req_q_out);
  2698. if (req->ring_index < cnt)
  2699. req->cnt = cnt - req->ring_index;
  2700. else
  2701. req->cnt = req->length -
  2702. (req->ring_index - cnt);
  2703. if (req->cnt < (req_cnt + 2))
  2704. goto queuing_error;
  2705. }
  2706. /* Build command packet. */
  2707. req->current_outstanding_cmd = handle;
  2708. req->outstanding_cmds[handle] = sp;
  2709. sp->handle = handle;
  2710. cmd->host_scribble = (unsigned char *)(unsigned long)handle;
  2711. req->cnt -= req_cnt;
  2712. cmd_pkt = (struct cmd_type_7_fx00 *)req->ring_ptr;
  2713. memset(&lcmd_pkt, 0, REQUEST_ENTRY_SIZE);
  2714. lcmd_pkt.handle = MAKE_HANDLE(req->id, sp->handle);
  2715. lcmd_pkt.reserved_0 = 0;
  2716. lcmd_pkt.port_path_ctrl = 0;
  2717. lcmd_pkt.reserved_1 = 0;
  2718. lcmd_pkt.dseg_count = cpu_to_le16(tot_dsds);
  2719. lcmd_pkt.tgt_idx = cpu_to_le16(sp->fcport->tgt_id);
  2720. int_to_scsilun(cmd->device->lun, &llun);
  2721. host_to_adap((uint8_t *)&llun, (uint8_t *)&lcmd_pkt.lun,
  2722. sizeof(lcmd_pkt.lun));
  2723. /* Load SCSI command packet. */
  2724. host_to_adap(cmd->cmnd, lcmd_pkt.fcp_cdb, sizeof(lcmd_pkt.fcp_cdb));
  2725. lcmd_pkt.byte_count = cpu_to_le32((uint32_t)scsi_bufflen(cmd));
  2726. /* Build IOCB segments */
  2727. qlafx00_build_scsi_iocbs(sp, cmd_pkt, tot_dsds, &lcmd_pkt);
  2728. /* Set total data segment count. */
  2729. lcmd_pkt.entry_count = (uint8_t)req_cnt;
  2730. /* Specify response queue number where completion should happen */
  2731. lcmd_pkt.entry_status = (uint8_t) rsp->id;
  2732. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302e,
  2733. (uint8_t *)cmd->cmnd, cmd->cmd_len);
  2734. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x3032,
  2735. (uint8_t *)&lcmd_pkt, REQUEST_ENTRY_SIZE);
  2736. memcpy_toio((void __iomem *)cmd_pkt, &lcmd_pkt, REQUEST_ENTRY_SIZE);
  2737. wmb();
  2738. /* Adjust ring index. */
  2739. req->ring_index++;
  2740. if (req->ring_index == req->length) {
  2741. req->ring_index = 0;
  2742. req->ring_ptr = req->ring;
  2743. } else
  2744. req->ring_ptr++;
  2745. sp->flags |= SRB_DMA_VALID;
  2746. /* Set chip new ring index. */
  2747. WRT_REG_DWORD(req->req_q_in, req->ring_index);
  2748. QLAFX00_SET_HST_INTR(ha, ha->rqstq_intr_code);
  2749. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2750. return QLA_SUCCESS;
  2751. queuing_error:
  2752. if (tot_dsds)
  2753. scsi_dma_unmap(cmd);
  2754. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2755. return QLA_FUNCTION_FAILED;
  2756. }
  2757. void
  2758. qlafx00_tm_iocb(srb_t *sp, struct tsk_mgmt_entry_fx00 *ptm_iocb)
  2759. {
  2760. struct srb_iocb *fxio = &sp->u.iocb_cmd;
  2761. scsi_qla_host_t *vha = sp->vha;
  2762. struct req_que *req = vha->req;
  2763. struct tsk_mgmt_entry_fx00 tm_iocb;
  2764. struct scsi_lun llun;
  2765. memset(&tm_iocb, 0, sizeof(struct tsk_mgmt_entry_fx00));
  2766. tm_iocb.entry_type = TSK_MGMT_IOCB_TYPE_FX00;
  2767. tm_iocb.entry_count = 1;
  2768. tm_iocb.handle = cpu_to_le32(MAKE_HANDLE(req->id, sp->handle));
  2769. tm_iocb.reserved_0 = 0;
  2770. tm_iocb.tgt_id = cpu_to_le16(sp->fcport->tgt_id);
  2771. tm_iocb.control_flags = cpu_to_le32(fxio->u.tmf.flags);
  2772. if (tm_iocb.control_flags == cpu_to_le32((uint32_t)TCF_LUN_RESET)) {
  2773. int_to_scsilun(fxio->u.tmf.lun, &llun);
  2774. host_to_adap((uint8_t *)&llun, (uint8_t *)&tm_iocb.lun,
  2775. sizeof(struct scsi_lun));
  2776. }
  2777. memcpy((void *)ptm_iocb, &tm_iocb,
  2778. sizeof(struct tsk_mgmt_entry_fx00));
  2779. wmb();
  2780. }
  2781. void
  2782. qlafx00_abort_iocb(srb_t *sp, struct abort_iocb_entry_fx00 *pabt_iocb)
  2783. {
  2784. struct srb_iocb *fxio = &sp->u.iocb_cmd;
  2785. scsi_qla_host_t *vha = sp->vha;
  2786. struct req_que *req = vha->req;
  2787. struct abort_iocb_entry_fx00 abt_iocb;
  2788. memset(&abt_iocb, 0, sizeof(struct abort_iocb_entry_fx00));
  2789. abt_iocb.entry_type = ABORT_IOCB_TYPE_FX00;
  2790. abt_iocb.entry_count = 1;
  2791. abt_iocb.handle = cpu_to_le32(MAKE_HANDLE(req->id, sp->handle));
  2792. abt_iocb.abort_handle =
  2793. cpu_to_le32(MAKE_HANDLE(req->id, fxio->u.abt.cmd_hndl));
  2794. abt_iocb.tgt_id_sts = cpu_to_le16(sp->fcport->tgt_id);
  2795. abt_iocb.req_que_no = cpu_to_le16(req->id);
  2796. memcpy((void *)pabt_iocb, &abt_iocb,
  2797. sizeof(struct abort_iocb_entry_fx00));
  2798. wmb();
  2799. }
  2800. void
  2801. qlafx00_fxdisc_iocb(srb_t *sp, struct fxdisc_entry_fx00 *pfxiocb)
  2802. {
  2803. struct srb_iocb *fxio = &sp->u.iocb_cmd;
  2804. struct qla_mt_iocb_rqst_fx00 *piocb_rqst;
  2805. struct bsg_job *bsg_job;
  2806. struct fc_bsg_request *bsg_request;
  2807. struct fxdisc_entry_fx00 fx_iocb;
  2808. uint8_t entry_cnt = 1;
  2809. memset(&fx_iocb, 0, sizeof(struct fxdisc_entry_fx00));
  2810. fx_iocb.entry_type = FX00_IOCB_TYPE;
  2811. fx_iocb.handle = cpu_to_le32(sp->handle);
  2812. fx_iocb.entry_count = entry_cnt;
  2813. if (sp->type == SRB_FXIOCB_DCMD) {
  2814. fx_iocb.func_num =
  2815. sp->u.iocb_cmd.u.fxiocb.req_func_type;
  2816. fx_iocb.adapid = fxio->u.fxiocb.adapter_id;
  2817. fx_iocb.adapid_hi = fxio->u.fxiocb.adapter_id_hi;
  2818. fx_iocb.reserved_0 = fxio->u.fxiocb.reserved_0;
  2819. fx_iocb.reserved_1 = fxio->u.fxiocb.reserved_1;
  2820. fx_iocb.dataword_extra = fxio->u.fxiocb.req_data_extra;
  2821. if (fxio->u.fxiocb.flags & SRB_FXDISC_REQ_DMA_VALID) {
  2822. fx_iocb.req_dsdcnt = cpu_to_le16(1);
  2823. fx_iocb.req_xfrcnt =
  2824. cpu_to_le16(fxio->u.fxiocb.req_len);
  2825. fx_iocb.dseg_rq_address[0] =
  2826. cpu_to_le32(LSD(fxio->u.fxiocb.req_dma_handle));
  2827. fx_iocb.dseg_rq_address[1] =
  2828. cpu_to_le32(MSD(fxio->u.fxiocb.req_dma_handle));
  2829. fx_iocb.dseg_rq_len =
  2830. cpu_to_le32(fxio->u.fxiocb.req_len);
  2831. }
  2832. if (fxio->u.fxiocb.flags & SRB_FXDISC_RESP_DMA_VALID) {
  2833. fx_iocb.rsp_dsdcnt = cpu_to_le16(1);
  2834. fx_iocb.rsp_xfrcnt =
  2835. cpu_to_le16(fxio->u.fxiocb.rsp_len);
  2836. fx_iocb.dseg_rsp_address[0] =
  2837. cpu_to_le32(LSD(fxio->u.fxiocb.rsp_dma_handle));
  2838. fx_iocb.dseg_rsp_address[1] =
  2839. cpu_to_le32(MSD(fxio->u.fxiocb.rsp_dma_handle));
  2840. fx_iocb.dseg_rsp_len =
  2841. cpu_to_le32(fxio->u.fxiocb.rsp_len);
  2842. }
  2843. if (fxio->u.fxiocb.flags & SRB_FXDISC_REQ_DWRD_VALID) {
  2844. fx_iocb.dataword = fxio->u.fxiocb.req_data;
  2845. }
  2846. fx_iocb.flags = fxio->u.fxiocb.flags;
  2847. } else {
  2848. struct scatterlist *sg;
  2849. bsg_job = sp->u.bsg_job;
  2850. bsg_request = bsg_job->request;
  2851. piocb_rqst = (struct qla_mt_iocb_rqst_fx00 *)
  2852. &bsg_request->rqst_data.h_vendor.vendor_cmd[1];
  2853. fx_iocb.func_num = piocb_rqst->func_type;
  2854. fx_iocb.adapid = piocb_rqst->adapid;
  2855. fx_iocb.adapid_hi = piocb_rqst->adapid_hi;
  2856. fx_iocb.reserved_0 = piocb_rqst->reserved_0;
  2857. fx_iocb.reserved_1 = piocb_rqst->reserved_1;
  2858. fx_iocb.dataword_extra = piocb_rqst->dataword_extra;
  2859. fx_iocb.dataword = piocb_rqst->dataword;
  2860. fx_iocb.req_xfrcnt = piocb_rqst->req_len;
  2861. fx_iocb.rsp_xfrcnt = piocb_rqst->rsp_len;
  2862. if (piocb_rqst->flags & SRB_FXDISC_REQ_DMA_VALID) {
  2863. int avail_dsds, tot_dsds;
  2864. cont_a64_entry_t lcont_pkt;
  2865. cont_a64_entry_t *cont_pkt = NULL;
  2866. __le32 *cur_dsd;
  2867. int index = 0, cont = 0;
  2868. fx_iocb.req_dsdcnt =
  2869. cpu_to_le16(bsg_job->request_payload.sg_cnt);
  2870. tot_dsds =
  2871. bsg_job->request_payload.sg_cnt;
  2872. cur_dsd = (__le32 *)&fx_iocb.dseg_rq_address[0];
  2873. avail_dsds = 1;
  2874. for_each_sg(bsg_job->request_payload.sg_list, sg,
  2875. tot_dsds, index) {
  2876. dma_addr_t sle_dma;
  2877. /* Allocate additional continuation packets? */
  2878. if (avail_dsds == 0) {
  2879. /*
  2880. * Five DSDs are available in the Cont.
  2881. * Type 1 IOCB.
  2882. */
  2883. memset(&lcont_pkt, 0,
  2884. REQUEST_ENTRY_SIZE);
  2885. cont_pkt =
  2886. qlafx00_prep_cont_type1_iocb(
  2887. sp->vha->req, &lcont_pkt);
  2888. cur_dsd = (__le32 *)
  2889. lcont_pkt.dseg_0_address;
  2890. avail_dsds = 5;
  2891. cont = 1;
  2892. entry_cnt++;
  2893. }
  2894. sle_dma = sg_dma_address(sg);
  2895. *cur_dsd++ = cpu_to_le32(LSD(sle_dma));
  2896. *cur_dsd++ = cpu_to_le32(MSD(sle_dma));
  2897. *cur_dsd++ = cpu_to_le32(sg_dma_len(sg));
  2898. avail_dsds--;
  2899. if (avail_dsds == 0 && cont == 1) {
  2900. cont = 0;
  2901. memcpy_toio(
  2902. (void __iomem *)cont_pkt,
  2903. &lcont_pkt, REQUEST_ENTRY_SIZE);
  2904. ql_dump_buffer(
  2905. ql_dbg_user + ql_dbg_verbose,
  2906. sp->vha, 0x3042,
  2907. (uint8_t *)&lcont_pkt,
  2908. REQUEST_ENTRY_SIZE);
  2909. }
  2910. }
  2911. if (avail_dsds != 0 && cont == 1) {
  2912. memcpy_toio((void __iomem *)cont_pkt,
  2913. &lcont_pkt, REQUEST_ENTRY_SIZE);
  2914. ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
  2915. sp->vha, 0x3043,
  2916. (uint8_t *)&lcont_pkt, REQUEST_ENTRY_SIZE);
  2917. }
  2918. }
  2919. if (piocb_rqst->flags & SRB_FXDISC_RESP_DMA_VALID) {
  2920. int avail_dsds, tot_dsds;
  2921. cont_a64_entry_t lcont_pkt;
  2922. cont_a64_entry_t *cont_pkt = NULL;
  2923. __le32 *cur_dsd;
  2924. int index = 0, cont = 0;
  2925. fx_iocb.rsp_dsdcnt =
  2926. cpu_to_le16(bsg_job->reply_payload.sg_cnt);
  2927. tot_dsds = bsg_job->reply_payload.sg_cnt;
  2928. cur_dsd = (__le32 *)&fx_iocb.dseg_rsp_address[0];
  2929. avail_dsds = 1;
  2930. for_each_sg(bsg_job->reply_payload.sg_list, sg,
  2931. tot_dsds, index) {
  2932. dma_addr_t sle_dma;
  2933. /* Allocate additional continuation packets? */
  2934. if (avail_dsds == 0) {
  2935. /*
  2936. * Five DSDs are available in the Cont.
  2937. * Type 1 IOCB.
  2938. */
  2939. memset(&lcont_pkt, 0,
  2940. REQUEST_ENTRY_SIZE);
  2941. cont_pkt =
  2942. qlafx00_prep_cont_type1_iocb(
  2943. sp->vha->req, &lcont_pkt);
  2944. cur_dsd = (__le32 *)
  2945. lcont_pkt.dseg_0_address;
  2946. avail_dsds = 5;
  2947. cont = 1;
  2948. entry_cnt++;
  2949. }
  2950. sle_dma = sg_dma_address(sg);
  2951. *cur_dsd++ = cpu_to_le32(LSD(sle_dma));
  2952. *cur_dsd++ = cpu_to_le32(MSD(sle_dma));
  2953. *cur_dsd++ = cpu_to_le32(sg_dma_len(sg));
  2954. avail_dsds--;
  2955. if (avail_dsds == 0 && cont == 1) {
  2956. cont = 0;
  2957. memcpy_toio((void __iomem *)cont_pkt,
  2958. &lcont_pkt,
  2959. REQUEST_ENTRY_SIZE);
  2960. ql_dump_buffer(
  2961. ql_dbg_user + ql_dbg_verbose,
  2962. sp->vha, 0x3045,
  2963. (uint8_t *)&lcont_pkt,
  2964. REQUEST_ENTRY_SIZE);
  2965. }
  2966. }
  2967. if (avail_dsds != 0 && cont == 1) {
  2968. memcpy_toio((void __iomem *)cont_pkt,
  2969. &lcont_pkt, REQUEST_ENTRY_SIZE);
  2970. ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
  2971. sp->vha, 0x3046,
  2972. (uint8_t *)&lcont_pkt, REQUEST_ENTRY_SIZE);
  2973. }
  2974. }
  2975. if (piocb_rqst->flags & SRB_FXDISC_REQ_DWRD_VALID)
  2976. fx_iocb.dataword = piocb_rqst->dataword;
  2977. fx_iocb.flags = piocb_rqst->flags;
  2978. fx_iocb.entry_count = entry_cnt;
  2979. }
  2980. ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
  2981. sp->vha, 0x3047,
  2982. (uint8_t *)&fx_iocb, sizeof(struct fxdisc_entry_fx00));
  2983. memcpy_toio((void __iomem *)pfxiocb, &fx_iocb,
  2984. sizeof(struct fxdisc_entry_fx00));
  2985. wmb();
  2986. }