esas2r_init.c 46 KB

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  1. /*
  2. * linux/drivers/scsi/esas2r/esas2r_init.c
  3. * For use with ATTO ExpressSAS R6xx SAS/SATA RAID controllers
  4. *
  5. * Copyright (c) 2001-2013 ATTO Technology, Inc.
  6. * (mailto:linuxdrivers@attotech.com)mpt3sas/mpt3sas_trigger_diag.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License
  10. * as published by the Free Software Foundation; either version 2
  11. * of the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * NO WARRANTY
  19. * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
  20. * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
  21. * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
  22. * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
  23. * solely responsible for determining the appropriateness of using and
  24. * distributing the Program and assumes all risks associated with its
  25. * exercise of rights under this Agreement, including but not limited to
  26. * the risks and costs of program errors, damage to or loss of data,
  27. * programs or equipment, and unavailability or interruption of operations.
  28. *
  29. * DISCLAIMER OF LIABILITY
  30. * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
  31. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32. * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
  33. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  34. * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  35. * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
  36. * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
  37. *
  38. * You should have received a copy of the GNU General Public License
  39. * along with this program; if not, write to the Free Software
  40. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
  41. * USA.
  42. */
  43. #include "esas2r.h"
  44. static bool esas2r_initmem_alloc(struct esas2r_adapter *a,
  45. struct esas2r_mem_desc *mem_desc,
  46. u32 align)
  47. {
  48. mem_desc->esas2r_param = mem_desc->size + align;
  49. mem_desc->virt_addr = NULL;
  50. mem_desc->phys_addr = 0;
  51. mem_desc->esas2r_data = dma_alloc_coherent(&a->pcid->dev,
  52. (size_t)mem_desc->
  53. esas2r_param,
  54. (dma_addr_t *)&mem_desc->
  55. phys_addr,
  56. GFP_KERNEL);
  57. if (mem_desc->esas2r_data == NULL) {
  58. esas2r_log(ESAS2R_LOG_CRIT,
  59. "failed to allocate %lu bytes of consistent memory!",
  60. (long
  61. unsigned
  62. int)mem_desc->esas2r_param);
  63. return false;
  64. }
  65. mem_desc->virt_addr = PTR_ALIGN(mem_desc->esas2r_data, align);
  66. mem_desc->phys_addr = ALIGN(mem_desc->phys_addr, align);
  67. memset(mem_desc->virt_addr, 0, mem_desc->size);
  68. return true;
  69. }
  70. static void esas2r_initmem_free(struct esas2r_adapter *a,
  71. struct esas2r_mem_desc *mem_desc)
  72. {
  73. if (mem_desc->virt_addr == NULL)
  74. return;
  75. /*
  76. * Careful! phys_addr and virt_addr may have been adjusted from the
  77. * original allocation in order to return the desired alignment. That
  78. * means we have to use the original address (in esas2r_data) and size
  79. * (esas2r_param) and calculate the original physical address based on
  80. * the difference between the requested and actual allocation size.
  81. */
  82. if (mem_desc->phys_addr) {
  83. int unalign = ((u8 *)mem_desc->virt_addr) -
  84. ((u8 *)mem_desc->esas2r_data);
  85. dma_free_coherent(&a->pcid->dev,
  86. (size_t)mem_desc->esas2r_param,
  87. mem_desc->esas2r_data,
  88. (dma_addr_t)(mem_desc->phys_addr - unalign));
  89. } else {
  90. kfree(mem_desc->esas2r_data);
  91. }
  92. mem_desc->virt_addr = NULL;
  93. }
  94. static bool alloc_vda_req(struct esas2r_adapter *a,
  95. struct esas2r_request *rq)
  96. {
  97. struct esas2r_mem_desc *memdesc = kzalloc(
  98. sizeof(struct esas2r_mem_desc), GFP_KERNEL);
  99. if (memdesc == NULL) {
  100. esas2r_hdebug("could not alloc mem for vda request memdesc\n");
  101. return false;
  102. }
  103. memdesc->size = sizeof(union atto_vda_req) +
  104. ESAS2R_DATA_BUF_LEN;
  105. if (!esas2r_initmem_alloc(a, memdesc, 256)) {
  106. esas2r_hdebug("could not alloc mem for vda request\n");
  107. kfree(memdesc);
  108. return false;
  109. }
  110. a->num_vrqs++;
  111. list_add(&memdesc->next_desc, &a->vrq_mds_head);
  112. rq->vrq_md = memdesc;
  113. rq->vrq = (union atto_vda_req *)memdesc->virt_addr;
  114. rq->vrq->scsi.handle = a->num_vrqs;
  115. return true;
  116. }
  117. static void esas2r_unmap_regions(struct esas2r_adapter *a)
  118. {
  119. if (a->regs)
  120. iounmap((void __iomem *)a->regs);
  121. a->regs = NULL;
  122. pci_release_region(a->pcid, 2);
  123. if (a->data_window)
  124. iounmap((void __iomem *)a->data_window);
  125. a->data_window = NULL;
  126. pci_release_region(a->pcid, 0);
  127. }
  128. static int esas2r_map_regions(struct esas2r_adapter *a)
  129. {
  130. int error;
  131. a->regs = NULL;
  132. a->data_window = NULL;
  133. error = pci_request_region(a->pcid, 2, a->name);
  134. if (error != 0) {
  135. esas2r_log(ESAS2R_LOG_CRIT,
  136. "pci_request_region(2) failed, error %d",
  137. error);
  138. return error;
  139. }
  140. a->regs = (void __force *)ioremap(pci_resource_start(a->pcid, 2),
  141. pci_resource_len(a->pcid, 2));
  142. if (a->regs == NULL) {
  143. esas2r_log(ESAS2R_LOG_CRIT,
  144. "ioremap failed for regs mem region\n");
  145. pci_release_region(a->pcid, 2);
  146. return -EFAULT;
  147. }
  148. error = pci_request_region(a->pcid, 0, a->name);
  149. if (error != 0) {
  150. esas2r_log(ESAS2R_LOG_CRIT,
  151. "pci_request_region(2) failed, error %d",
  152. error);
  153. esas2r_unmap_regions(a);
  154. return error;
  155. }
  156. a->data_window = (void __force *)ioremap(pci_resource_start(a->pcid,
  157. 0),
  158. pci_resource_len(a->pcid, 0));
  159. if (a->data_window == NULL) {
  160. esas2r_log(ESAS2R_LOG_CRIT,
  161. "ioremap failed for data_window mem region\n");
  162. esas2r_unmap_regions(a);
  163. return -EFAULT;
  164. }
  165. return 0;
  166. }
  167. static void esas2r_setup_interrupts(struct esas2r_adapter *a, int intr_mode)
  168. {
  169. int i;
  170. /* Set up interrupt mode based on the requested value */
  171. switch (intr_mode) {
  172. case INTR_MODE_LEGACY:
  173. use_legacy_interrupts:
  174. a->intr_mode = INTR_MODE_LEGACY;
  175. break;
  176. case INTR_MODE_MSI:
  177. i = pci_enable_msi(a->pcid);
  178. if (i != 0) {
  179. esas2r_log(ESAS2R_LOG_WARN,
  180. "failed to enable MSI for adapter %d, "
  181. "falling back to legacy interrupts "
  182. "(err=%d)", a->index,
  183. i);
  184. goto use_legacy_interrupts;
  185. }
  186. a->intr_mode = INTR_MODE_MSI;
  187. set_bit(AF2_MSI_ENABLED, &a->flags2);
  188. break;
  189. default:
  190. esas2r_log(ESAS2R_LOG_WARN,
  191. "unknown interrupt_mode %d requested, "
  192. "falling back to legacy interrupt",
  193. interrupt_mode);
  194. goto use_legacy_interrupts;
  195. }
  196. }
  197. static void esas2r_claim_interrupts(struct esas2r_adapter *a)
  198. {
  199. unsigned long flags = 0;
  200. if (a->intr_mode == INTR_MODE_LEGACY)
  201. flags |= IRQF_SHARED;
  202. esas2r_log(ESAS2R_LOG_INFO,
  203. "esas2r_claim_interrupts irq=%d (%p, %s, %lx)",
  204. a->pcid->irq, a, a->name, flags);
  205. if (request_irq(a->pcid->irq,
  206. (a->intr_mode ==
  207. INTR_MODE_LEGACY) ? esas2r_interrupt :
  208. esas2r_msi_interrupt,
  209. flags,
  210. a->name,
  211. a)) {
  212. esas2r_log(ESAS2R_LOG_CRIT, "unable to request IRQ %02X",
  213. a->pcid->irq);
  214. return;
  215. }
  216. set_bit(AF2_IRQ_CLAIMED, &a->flags2);
  217. esas2r_log(ESAS2R_LOG_INFO,
  218. "claimed IRQ %d flags: 0x%lx",
  219. a->pcid->irq, flags);
  220. }
  221. int esas2r_init_adapter(struct Scsi_Host *host, struct pci_dev *pcid,
  222. int index)
  223. {
  224. struct esas2r_adapter *a;
  225. u64 bus_addr = 0;
  226. int i;
  227. void *next_uncached;
  228. struct esas2r_request *first_request, *last_request;
  229. if (index >= MAX_ADAPTERS) {
  230. esas2r_log(ESAS2R_LOG_CRIT,
  231. "tried to init invalid adapter index %u!",
  232. index);
  233. return 0;
  234. }
  235. if (esas2r_adapters[index]) {
  236. esas2r_log(ESAS2R_LOG_CRIT,
  237. "tried to init existing adapter index %u!",
  238. index);
  239. return 0;
  240. }
  241. a = (struct esas2r_adapter *)host->hostdata;
  242. memset(a, 0, sizeof(struct esas2r_adapter));
  243. a->pcid = pcid;
  244. a->host = host;
  245. if (sizeof(dma_addr_t) > 4) {
  246. const uint64_t required_mask = dma_get_required_mask
  247. (&pcid->dev);
  248. if (required_mask > DMA_BIT_MASK(32)
  249. && !pci_set_dma_mask(pcid, DMA_BIT_MASK(64))
  250. && !pci_set_consistent_dma_mask(pcid,
  251. DMA_BIT_MASK(64))) {
  252. esas2r_log_dev(ESAS2R_LOG_INFO,
  253. &(a->pcid->dev),
  254. "64-bit PCI addressing enabled\n");
  255. } else if (!pci_set_dma_mask(pcid, DMA_BIT_MASK(32))
  256. && !pci_set_consistent_dma_mask(pcid,
  257. DMA_BIT_MASK(32))) {
  258. esas2r_log_dev(ESAS2R_LOG_INFO,
  259. &(a->pcid->dev),
  260. "32-bit PCI addressing enabled\n");
  261. } else {
  262. esas2r_log(ESAS2R_LOG_CRIT,
  263. "failed to set DMA mask");
  264. esas2r_kill_adapter(index);
  265. return 0;
  266. }
  267. } else {
  268. if (!pci_set_dma_mask(pcid, DMA_BIT_MASK(32))
  269. && !pci_set_consistent_dma_mask(pcid,
  270. DMA_BIT_MASK(32))) {
  271. esas2r_log_dev(ESAS2R_LOG_INFO,
  272. &(a->pcid->dev),
  273. "32-bit PCI addressing enabled\n");
  274. } else {
  275. esas2r_log(ESAS2R_LOG_CRIT,
  276. "failed to set DMA mask");
  277. esas2r_kill_adapter(index);
  278. return 0;
  279. }
  280. }
  281. esas2r_adapters[index] = a;
  282. sprintf(a->name, ESAS2R_DRVR_NAME "_%02d", index);
  283. esas2r_debug("new adapter %p, name %s", a, a->name);
  284. spin_lock_init(&a->request_lock);
  285. spin_lock_init(&a->fw_event_lock);
  286. mutex_init(&a->fm_api_mutex);
  287. mutex_init(&a->fs_api_mutex);
  288. sema_init(&a->nvram_semaphore, 1);
  289. esas2r_fw_event_off(a);
  290. snprintf(a->fw_event_q_name, ESAS2R_KOBJ_NAME_LEN, "esas2r/%d",
  291. a->index);
  292. a->fw_event_q = create_singlethread_workqueue(a->fw_event_q_name);
  293. init_waitqueue_head(&a->buffered_ioctl_waiter);
  294. init_waitqueue_head(&a->nvram_waiter);
  295. init_waitqueue_head(&a->fm_api_waiter);
  296. init_waitqueue_head(&a->fs_api_waiter);
  297. init_waitqueue_head(&a->vda_waiter);
  298. INIT_LIST_HEAD(&a->general_req.req_list);
  299. INIT_LIST_HEAD(&a->active_list);
  300. INIT_LIST_HEAD(&a->defer_list);
  301. INIT_LIST_HEAD(&a->free_sg_list_head);
  302. INIT_LIST_HEAD(&a->avail_request);
  303. INIT_LIST_HEAD(&a->vrq_mds_head);
  304. INIT_LIST_HEAD(&a->fw_event_list);
  305. first_request = (struct esas2r_request *)((u8 *)(a + 1));
  306. for (last_request = first_request, i = 1; i < num_requests;
  307. last_request++, i++) {
  308. INIT_LIST_HEAD(&last_request->req_list);
  309. list_add_tail(&last_request->comp_list, &a->avail_request);
  310. if (!alloc_vda_req(a, last_request)) {
  311. esas2r_log(ESAS2R_LOG_CRIT,
  312. "failed to allocate a VDA request!");
  313. esas2r_kill_adapter(index);
  314. return 0;
  315. }
  316. }
  317. esas2r_debug("requests: %p to %p (%d, %d)", first_request,
  318. last_request,
  319. sizeof(*first_request),
  320. num_requests);
  321. if (esas2r_map_regions(a) != 0) {
  322. esas2r_log(ESAS2R_LOG_CRIT, "could not map PCI regions!");
  323. esas2r_kill_adapter(index);
  324. return 0;
  325. }
  326. a->index = index;
  327. /* interrupts will be disabled until we are done with init */
  328. atomic_inc(&a->dis_ints_cnt);
  329. atomic_inc(&a->disable_cnt);
  330. set_bit(AF_CHPRST_PENDING, &a->flags);
  331. set_bit(AF_DISC_PENDING, &a->flags);
  332. set_bit(AF_FIRST_INIT, &a->flags);
  333. set_bit(AF_LEGACY_SGE_MODE, &a->flags);
  334. a->init_msg = ESAS2R_INIT_MSG_START;
  335. a->max_vdareq_size = 128;
  336. a->build_sgl = esas2r_build_sg_list_sge;
  337. esas2r_setup_interrupts(a, interrupt_mode);
  338. a->uncached_size = esas2r_get_uncached_size(a);
  339. a->uncached = dma_alloc_coherent(&pcid->dev,
  340. (size_t)a->uncached_size,
  341. (dma_addr_t *)&bus_addr,
  342. GFP_KERNEL);
  343. if (a->uncached == NULL) {
  344. esas2r_log(ESAS2R_LOG_CRIT,
  345. "failed to allocate %d bytes of consistent memory!",
  346. a->uncached_size);
  347. esas2r_kill_adapter(index);
  348. return 0;
  349. }
  350. a->uncached_phys = bus_addr;
  351. esas2r_debug("%d bytes uncached memory allocated @ %p (%x:%x)",
  352. a->uncached_size,
  353. a->uncached,
  354. upper_32_bits(bus_addr),
  355. lower_32_bits(bus_addr));
  356. memset(a->uncached, 0, a->uncached_size);
  357. next_uncached = a->uncached;
  358. if (!esas2r_init_adapter_struct(a,
  359. &next_uncached)) {
  360. esas2r_log(ESAS2R_LOG_CRIT,
  361. "failed to initialize adapter structure (2)!");
  362. esas2r_kill_adapter(index);
  363. return 0;
  364. }
  365. tasklet_init(&a->tasklet,
  366. esas2r_adapter_tasklet,
  367. (unsigned long)a);
  368. /*
  369. * Disable chip interrupts to prevent spurious interrupts
  370. * until we claim the IRQ.
  371. */
  372. esas2r_disable_chip_interrupts(a);
  373. esas2r_check_adapter(a);
  374. if (!esas2r_init_adapter_hw(a, true))
  375. esas2r_log(ESAS2R_LOG_CRIT, "failed to initialize hardware!");
  376. else
  377. esas2r_debug("esas2r_init_adapter ok");
  378. esas2r_claim_interrupts(a);
  379. if (test_bit(AF2_IRQ_CLAIMED, &a->flags2))
  380. esas2r_enable_chip_interrupts(a);
  381. set_bit(AF2_INIT_DONE, &a->flags2);
  382. if (!test_bit(AF_DEGRADED_MODE, &a->flags))
  383. esas2r_kickoff_timer(a);
  384. esas2r_debug("esas2r_init_adapter done for %p (%d)",
  385. a, a->disable_cnt);
  386. return 1;
  387. }
  388. static void esas2r_adapter_power_down(struct esas2r_adapter *a,
  389. int power_management)
  390. {
  391. struct esas2r_mem_desc *memdesc, *next;
  392. if ((test_bit(AF2_INIT_DONE, &a->flags2))
  393. && (!test_bit(AF_DEGRADED_MODE, &a->flags))) {
  394. if (!power_management) {
  395. del_timer_sync(&a->timer);
  396. tasklet_kill(&a->tasklet);
  397. }
  398. esas2r_power_down(a);
  399. /*
  400. * There are versions of firmware that do not handle the sync
  401. * cache command correctly. Stall here to ensure that the
  402. * cache is lazily flushed.
  403. */
  404. mdelay(500);
  405. esas2r_debug("chip halted");
  406. }
  407. /* Remove sysfs binary files */
  408. if (a->sysfs_fw_created) {
  409. sysfs_remove_bin_file(&a->host->shost_dev.kobj, &bin_attr_fw);
  410. a->sysfs_fw_created = 0;
  411. }
  412. if (a->sysfs_fs_created) {
  413. sysfs_remove_bin_file(&a->host->shost_dev.kobj, &bin_attr_fs);
  414. a->sysfs_fs_created = 0;
  415. }
  416. if (a->sysfs_vda_created) {
  417. sysfs_remove_bin_file(&a->host->shost_dev.kobj, &bin_attr_vda);
  418. a->sysfs_vda_created = 0;
  419. }
  420. if (a->sysfs_hw_created) {
  421. sysfs_remove_bin_file(&a->host->shost_dev.kobj, &bin_attr_hw);
  422. a->sysfs_hw_created = 0;
  423. }
  424. if (a->sysfs_live_nvram_created) {
  425. sysfs_remove_bin_file(&a->host->shost_dev.kobj,
  426. &bin_attr_live_nvram);
  427. a->sysfs_live_nvram_created = 0;
  428. }
  429. if (a->sysfs_default_nvram_created) {
  430. sysfs_remove_bin_file(&a->host->shost_dev.kobj,
  431. &bin_attr_default_nvram);
  432. a->sysfs_default_nvram_created = 0;
  433. }
  434. /* Clean up interrupts */
  435. if (test_bit(AF2_IRQ_CLAIMED, &a->flags2)) {
  436. esas2r_log_dev(ESAS2R_LOG_INFO,
  437. &(a->pcid->dev),
  438. "free_irq(%d) called", a->pcid->irq);
  439. free_irq(a->pcid->irq, a);
  440. esas2r_debug("IRQ released");
  441. clear_bit(AF2_IRQ_CLAIMED, &a->flags2);
  442. }
  443. if (test_bit(AF2_MSI_ENABLED, &a->flags2)) {
  444. pci_disable_msi(a->pcid);
  445. clear_bit(AF2_MSI_ENABLED, &a->flags2);
  446. esas2r_debug("MSI disabled");
  447. }
  448. if (a->inbound_list_md.virt_addr)
  449. esas2r_initmem_free(a, &a->inbound_list_md);
  450. if (a->outbound_list_md.virt_addr)
  451. esas2r_initmem_free(a, &a->outbound_list_md);
  452. list_for_each_entry_safe(memdesc, next, &a->free_sg_list_head,
  453. next_desc) {
  454. esas2r_initmem_free(a, memdesc);
  455. }
  456. /* Following frees everything allocated via alloc_vda_req */
  457. list_for_each_entry_safe(memdesc, next, &a->vrq_mds_head, next_desc) {
  458. esas2r_initmem_free(a, memdesc);
  459. list_del(&memdesc->next_desc);
  460. kfree(memdesc);
  461. }
  462. kfree(a->first_ae_req);
  463. a->first_ae_req = NULL;
  464. kfree(a->sg_list_mds);
  465. a->sg_list_mds = NULL;
  466. kfree(a->req_table);
  467. a->req_table = NULL;
  468. if (a->regs) {
  469. esas2r_unmap_regions(a);
  470. a->regs = NULL;
  471. a->data_window = NULL;
  472. esas2r_debug("regions unmapped");
  473. }
  474. }
  475. /* Release/free allocated resources for specified adapters. */
  476. void esas2r_kill_adapter(int i)
  477. {
  478. struct esas2r_adapter *a = esas2r_adapters[i];
  479. if (a) {
  480. unsigned long flags;
  481. struct workqueue_struct *wq;
  482. esas2r_debug("killing adapter %p [%d] ", a, i);
  483. esas2r_fw_event_off(a);
  484. esas2r_adapter_power_down(a, 0);
  485. if (esas2r_buffered_ioctl &&
  486. (a->pcid == esas2r_buffered_ioctl_pcid)) {
  487. dma_free_coherent(&a->pcid->dev,
  488. (size_t)esas2r_buffered_ioctl_size,
  489. esas2r_buffered_ioctl,
  490. esas2r_buffered_ioctl_addr);
  491. esas2r_buffered_ioctl = NULL;
  492. }
  493. if (a->vda_buffer) {
  494. dma_free_coherent(&a->pcid->dev,
  495. (size_t)VDA_MAX_BUFFER_SIZE,
  496. a->vda_buffer,
  497. (dma_addr_t)a->ppvda_buffer);
  498. a->vda_buffer = NULL;
  499. }
  500. if (a->fs_api_buffer) {
  501. dma_free_coherent(&a->pcid->dev,
  502. (size_t)a->fs_api_buffer_size,
  503. a->fs_api_buffer,
  504. (dma_addr_t)a->ppfs_api_buffer);
  505. a->fs_api_buffer = NULL;
  506. }
  507. kfree(a->local_atto_ioctl);
  508. a->local_atto_ioctl = NULL;
  509. spin_lock_irqsave(&a->fw_event_lock, flags);
  510. wq = a->fw_event_q;
  511. a->fw_event_q = NULL;
  512. spin_unlock_irqrestore(&a->fw_event_lock, flags);
  513. if (wq)
  514. destroy_workqueue(wq);
  515. if (a->uncached) {
  516. dma_free_coherent(&a->pcid->dev,
  517. (size_t)a->uncached_size,
  518. a->uncached,
  519. (dma_addr_t)a->uncached_phys);
  520. a->uncached = NULL;
  521. esas2r_debug("uncached area freed");
  522. }
  523. esas2r_log_dev(ESAS2R_LOG_INFO,
  524. &(a->pcid->dev),
  525. "pci_disable_device() called. msix_enabled: %d "
  526. "msi_enabled: %d irq: %d pin: %d",
  527. a->pcid->msix_enabled,
  528. a->pcid->msi_enabled,
  529. a->pcid->irq,
  530. a->pcid->pin);
  531. esas2r_log_dev(ESAS2R_LOG_INFO,
  532. &(a->pcid->dev),
  533. "before pci_disable_device() enable_cnt: %d",
  534. a->pcid->enable_cnt.counter);
  535. pci_disable_device(a->pcid);
  536. esas2r_log_dev(ESAS2R_LOG_INFO,
  537. &(a->pcid->dev),
  538. "after pci_disable_device() enable_cnt: %d",
  539. a->pcid->enable_cnt.counter);
  540. esas2r_log_dev(ESAS2R_LOG_INFO,
  541. &(a->pcid->dev),
  542. "pci_set_drv_data(%p, NULL) called",
  543. a->pcid);
  544. pci_set_drvdata(a->pcid, NULL);
  545. esas2r_adapters[i] = NULL;
  546. if (test_bit(AF2_INIT_DONE, &a->flags2)) {
  547. clear_bit(AF2_INIT_DONE, &a->flags2);
  548. set_bit(AF_DEGRADED_MODE, &a->flags);
  549. esas2r_log_dev(ESAS2R_LOG_INFO,
  550. &(a->host->shost_gendev),
  551. "scsi_remove_host() called");
  552. scsi_remove_host(a->host);
  553. esas2r_log_dev(ESAS2R_LOG_INFO,
  554. &(a->host->shost_gendev),
  555. "scsi_host_put() called");
  556. scsi_host_put(a->host);
  557. }
  558. }
  559. }
  560. int esas2r_suspend(struct pci_dev *pdev, pm_message_t state)
  561. {
  562. struct Scsi_Host *host = pci_get_drvdata(pdev);
  563. u32 device_state;
  564. struct esas2r_adapter *a = (struct esas2r_adapter *)host->hostdata;
  565. esas2r_log_dev(ESAS2R_LOG_INFO, &(pdev->dev), "suspending adapter()");
  566. if (!a)
  567. return -ENODEV;
  568. esas2r_adapter_power_down(a, 1);
  569. device_state = pci_choose_state(pdev, state);
  570. esas2r_log_dev(ESAS2R_LOG_INFO, &(pdev->dev),
  571. "pci_save_state() called");
  572. pci_save_state(pdev);
  573. esas2r_log_dev(ESAS2R_LOG_INFO, &(pdev->dev),
  574. "pci_disable_device() called");
  575. pci_disable_device(pdev);
  576. esas2r_log_dev(ESAS2R_LOG_INFO, &(pdev->dev),
  577. "pci_set_power_state() called");
  578. pci_set_power_state(pdev, device_state);
  579. esas2r_log_dev(ESAS2R_LOG_INFO, &(pdev->dev), "esas2r_suspend(): 0");
  580. return 0;
  581. }
  582. int esas2r_resume(struct pci_dev *pdev)
  583. {
  584. struct Scsi_Host *host = pci_get_drvdata(pdev);
  585. struct esas2r_adapter *a = (struct esas2r_adapter *)host->hostdata;
  586. int rez;
  587. esas2r_log_dev(ESAS2R_LOG_INFO, &(pdev->dev), "resuming adapter()");
  588. esas2r_log_dev(ESAS2R_LOG_INFO, &(pdev->dev),
  589. "pci_set_power_state(PCI_D0) "
  590. "called");
  591. pci_set_power_state(pdev, PCI_D0);
  592. esas2r_log_dev(ESAS2R_LOG_INFO, &(pdev->dev),
  593. "pci_enable_wake(PCI_D0, 0) "
  594. "called");
  595. pci_enable_wake(pdev, PCI_D0, 0);
  596. esas2r_log_dev(ESAS2R_LOG_INFO, &(pdev->dev),
  597. "pci_restore_state() called");
  598. pci_restore_state(pdev);
  599. esas2r_log_dev(ESAS2R_LOG_INFO, &(pdev->dev),
  600. "pci_enable_device() called");
  601. rez = pci_enable_device(pdev);
  602. pci_set_master(pdev);
  603. if (!a) {
  604. rez = -ENODEV;
  605. goto error_exit;
  606. }
  607. if (esas2r_map_regions(a) != 0) {
  608. esas2r_log(ESAS2R_LOG_CRIT, "could not re-map PCI regions!");
  609. rez = -ENOMEM;
  610. goto error_exit;
  611. }
  612. /* Set up interupt mode */
  613. esas2r_setup_interrupts(a, a->intr_mode);
  614. /*
  615. * Disable chip interrupts to prevent spurious interrupts until we
  616. * claim the IRQ.
  617. */
  618. esas2r_disable_chip_interrupts(a);
  619. if (!esas2r_power_up(a, true)) {
  620. esas2r_debug("yikes, esas2r_power_up failed");
  621. rez = -ENOMEM;
  622. goto error_exit;
  623. }
  624. esas2r_claim_interrupts(a);
  625. if (test_bit(AF2_IRQ_CLAIMED, &a->flags2)) {
  626. /*
  627. * Now that system interrupt(s) are claimed, we can enable
  628. * chip interrupts.
  629. */
  630. esas2r_enable_chip_interrupts(a);
  631. esas2r_kickoff_timer(a);
  632. } else {
  633. esas2r_debug("yikes, unable to claim IRQ");
  634. esas2r_log(ESAS2R_LOG_CRIT, "could not re-claim IRQ!");
  635. rez = -ENOMEM;
  636. goto error_exit;
  637. }
  638. error_exit:
  639. esas2r_log_dev(ESAS2R_LOG_CRIT, &(pdev->dev), "esas2r_resume(): %d",
  640. rez);
  641. return rez;
  642. }
  643. bool esas2r_set_degraded_mode(struct esas2r_adapter *a, char *error_str)
  644. {
  645. set_bit(AF_DEGRADED_MODE, &a->flags);
  646. esas2r_log(ESAS2R_LOG_CRIT,
  647. "setting adapter to degraded mode: %s\n", error_str);
  648. return false;
  649. }
  650. u32 esas2r_get_uncached_size(struct esas2r_adapter *a)
  651. {
  652. return sizeof(struct esas2r_sas_nvram)
  653. + ALIGN(ESAS2R_DISC_BUF_LEN, 8)
  654. + ALIGN(sizeof(u32), 8) /* outbound list copy pointer */
  655. + 8
  656. + (num_sg_lists * (u16)sgl_page_size)
  657. + ALIGN((num_requests + num_ae_requests + 1 +
  658. ESAS2R_LIST_EXTRA) *
  659. sizeof(struct esas2r_inbound_list_source_entry),
  660. 8)
  661. + ALIGN((num_requests + num_ae_requests + 1 +
  662. ESAS2R_LIST_EXTRA) *
  663. sizeof(struct atto_vda_ob_rsp), 8)
  664. + 256; /* VDA request and buffer align */
  665. }
  666. static void esas2r_init_pci_cfg_space(struct esas2r_adapter *a)
  667. {
  668. int pcie_cap_reg;
  669. pcie_cap_reg = pci_find_capability(a->pcid, PCI_CAP_ID_EXP);
  670. if (pcie_cap_reg) {
  671. u16 devcontrol;
  672. pci_read_config_word(a->pcid, pcie_cap_reg + PCI_EXP_DEVCTL,
  673. &devcontrol);
  674. if ((devcontrol & PCI_EXP_DEVCTL_READRQ) >
  675. PCI_EXP_DEVCTL_READRQ_512B) {
  676. esas2r_log(ESAS2R_LOG_INFO,
  677. "max read request size > 512B");
  678. devcontrol &= ~PCI_EXP_DEVCTL_READRQ;
  679. devcontrol |= PCI_EXP_DEVCTL_READRQ_512B;
  680. pci_write_config_word(a->pcid,
  681. pcie_cap_reg + PCI_EXP_DEVCTL,
  682. devcontrol);
  683. }
  684. }
  685. }
  686. /*
  687. * Determine the organization of the uncached data area and
  688. * finish initializing the adapter structure
  689. */
  690. bool esas2r_init_adapter_struct(struct esas2r_adapter *a,
  691. void **uncached_area)
  692. {
  693. u32 i;
  694. u8 *high;
  695. struct esas2r_inbound_list_source_entry *element;
  696. struct esas2r_request *rq;
  697. struct esas2r_mem_desc *sgl;
  698. spin_lock_init(&a->sg_list_lock);
  699. spin_lock_init(&a->mem_lock);
  700. spin_lock_init(&a->queue_lock);
  701. a->targetdb_end = &a->targetdb[ESAS2R_MAX_TARGETS];
  702. if (!alloc_vda_req(a, &a->general_req)) {
  703. esas2r_hdebug(
  704. "failed to allocate a VDA request for the general req!");
  705. return false;
  706. }
  707. /* allocate requests for asynchronous events */
  708. a->first_ae_req =
  709. kcalloc(num_ae_requests, sizeof(struct esas2r_request),
  710. GFP_KERNEL);
  711. if (a->first_ae_req == NULL) {
  712. esas2r_log(ESAS2R_LOG_CRIT,
  713. "failed to allocate memory for asynchronous events");
  714. return false;
  715. }
  716. /* allocate the S/G list memory descriptors */
  717. a->sg_list_mds = kcalloc(num_sg_lists, sizeof(struct esas2r_mem_desc),
  718. GFP_KERNEL);
  719. if (a->sg_list_mds == NULL) {
  720. esas2r_log(ESAS2R_LOG_CRIT,
  721. "failed to allocate memory for s/g list descriptors");
  722. return false;
  723. }
  724. /* allocate the request table */
  725. a->req_table =
  726. kcalloc(num_requests + num_ae_requests + 1,
  727. sizeof(struct esas2r_request *),
  728. GFP_KERNEL);
  729. if (a->req_table == NULL) {
  730. esas2r_log(ESAS2R_LOG_CRIT,
  731. "failed to allocate memory for the request table");
  732. return false;
  733. }
  734. /* initialize PCI configuration space */
  735. esas2r_init_pci_cfg_space(a);
  736. /*
  737. * the thunder_stream boards all have a serial flash part that has a
  738. * different base address on the AHB bus.
  739. */
  740. if ((a->pcid->subsystem_vendor == ATTO_VENDOR_ID)
  741. && (a->pcid->subsystem_device & ATTO_SSDID_TBT))
  742. a->flags2 |= AF2_THUNDERBOLT;
  743. if (test_bit(AF2_THUNDERBOLT, &a->flags2))
  744. a->flags2 |= AF2_SERIAL_FLASH;
  745. if (a->pcid->subsystem_device == ATTO_TLSH_1068)
  746. a->flags2 |= AF2_THUNDERLINK;
  747. /* Uncached Area */
  748. high = (u8 *)*uncached_area;
  749. /* initialize the scatter/gather table pages */
  750. for (i = 0, sgl = a->sg_list_mds; i < num_sg_lists; i++, sgl++) {
  751. sgl->size = sgl_page_size;
  752. list_add_tail(&sgl->next_desc, &a->free_sg_list_head);
  753. if (!esas2r_initmem_alloc(a, sgl, ESAS2R_SGL_ALIGN)) {
  754. /* Allow the driver to load if the minimum count met. */
  755. if (i < NUM_SGL_MIN)
  756. return false;
  757. break;
  758. }
  759. }
  760. /* compute the size of the lists */
  761. a->list_size = num_requests + ESAS2R_LIST_EXTRA;
  762. /* allocate the inbound list */
  763. a->inbound_list_md.size = a->list_size *
  764. sizeof(struct
  765. esas2r_inbound_list_source_entry);
  766. if (!esas2r_initmem_alloc(a, &a->inbound_list_md, ESAS2R_LIST_ALIGN)) {
  767. esas2r_hdebug("failed to allocate IB list");
  768. return false;
  769. }
  770. /* allocate the outbound list */
  771. a->outbound_list_md.size = a->list_size *
  772. sizeof(struct atto_vda_ob_rsp);
  773. if (!esas2r_initmem_alloc(a, &a->outbound_list_md,
  774. ESAS2R_LIST_ALIGN)) {
  775. esas2r_hdebug("failed to allocate IB list");
  776. return false;
  777. }
  778. /* allocate the NVRAM structure */
  779. a->nvram = (struct esas2r_sas_nvram *)high;
  780. high += sizeof(struct esas2r_sas_nvram);
  781. /* allocate the discovery buffer */
  782. a->disc_buffer = high;
  783. high += ESAS2R_DISC_BUF_LEN;
  784. high = PTR_ALIGN(high, 8);
  785. /* allocate the outbound list copy pointer */
  786. a->outbound_copy = (u32 volatile *)high;
  787. high += sizeof(u32);
  788. if (!test_bit(AF_NVR_VALID, &a->flags))
  789. esas2r_nvram_set_defaults(a);
  790. /* update the caller's uncached memory area pointer */
  791. *uncached_area = (void *)high;
  792. /* initialize the allocated memory */
  793. if (test_bit(AF_FIRST_INIT, &a->flags)) {
  794. esas2r_targ_db_initialize(a);
  795. /* prime parts of the inbound list */
  796. element =
  797. (struct esas2r_inbound_list_source_entry *)a->
  798. inbound_list_md.
  799. virt_addr;
  800. for (i = 0; i < a->list_size; i++) {
  801. element->address = 0;
  802. element->reserved = 0;
  803. element->length = cpu_to_le32(HWILSE_INTERFACE_F0
  804. | (sizeof(union
  805. atto_vda_req)
  806. /
  807. sizeof(u32)));
  808. element++;
  809. }
  810. /* init the AE requests */
  811. for (rq = a->first_ae_req, i = 0; i < num_ae_requests; rq++,
  812. i++) {
  813. INIT_LIST_HEAD(&rq->req_list);
  814. if (!alloc_vda_req(a, rq)) {
  815. esas2r_hdebug(
  816. "failed to allocate a VDA request!");
  817. return false;
  818. }
  819. esas2r_rq_init_request(rq, a);
  820. /* override the completion function */
  821. rq->comp_cb = esas2r_ae_complete;
  822. }
  823. }
  824. return true;
  825. }
  826. /* This code will verify that the chip is operational. */
  827. bool esas2r_check_adapter(struct esas2r_adapter *a)
  828. {
  829. u32 starttime;
  830. u32 doorbell;
  831. u64 ppaddr;
  832. u32 dw;
  833. /*
  834. * if the chip reset detected flag is set, we can bypass a bunch of
  835. * stuff.
  836. */
  837. if (test_bit(AF_CHPRST_DETECTED, &a->flags))
  838. goto skip_chip_reset;
  839. /*
  840. * BEFORE WE DO ANYTHING, disable the chip interrupts! the boot driver
  841. * may have left them enabled or we may be recovering from a fault.
  842. */
  843. esas2r_write_register_dword(a, MU_INT_MASK_OUT, ESAS2R_INT_DIS_MASK);
  844. esas2r_flush_register_dword(a, MU_INT_MASK_OUT);
  845. /*
  846. * wait for the firmware to become ready by forcing an interrupt and
  847. * waiting for a response.
  848. */
  849. starttime = jiffies_to_msecs(jiffies);
  850. while (true) {
  851. esas2r_force_interrupt(a);
  852. doorbell = esas2r_read_register_dword(a, MU_DOORBELL_OUT);
  853. if (doorbell == 0xFFFFFFFF) {
  854. /*
  855. * Give the firmware up to two seconds to enable
  856. * register access after a reset.
  857. */
  858. if ((jiffies_to_msecs(jiffies) - starttime) > 2000)
  859. return esas2r_set_degraded_mode(a,
  860. "unable to access registers");
  861. } else if (doorbell & DRBL_FORCE_INT) {
  862. u32 ver = (doorbell & DRBL_FW_VER_MSK);
  863. /*
  864. * This driver supports version 0 and version 1 of
  865. * the API
  866. */
  867. esas2r_write_register_dword(a, MU_DOORBELL_OUT,
  868. doorbell);
  869. if (ver == DRBL_FW_VER_0) {
  870. set_bit(AF_LEGACY_SGE_MODE, &a->flags);
  871. a->max_vdareq_size = 128;
  872. a->build_sgl = esas2r_build_sg_list_sge;
  873. } else if (ver == DRBL_FW_VER_1) {
  874. clear_bit(AF_LEGACY_SGE_MODE, &a->flags);
  875. a->max_vdareq_size = 1024;
  876. a->build_sgl = esas2r_build_sg_list_prd;
  877. } else {
  878. return esas2r_set_degraded_mode(a,
  879. "unknown firmware version");
  880. }
  881. break;
  882. }
  883. schedule_timeout_interruptible(msecs_to_jiffies(100));
  884. if ((jiffies_to_msecs(jiffies) - starttime) > 180000) {
  885. esas2r_hdebug("FW ready TMO");
  886. esas2r_bugon();
  887. return esas2r_set_degraded_mode(a,
  888. "firmware start has timed out");
  889. }
  890. }
  891. /* purge any asynchronous events since we will repost them later */
  892. esas2r_write_register_dword(a, MU_DOORBELL_IN, DRBL_MSG_IFC_DOWN);
  893. starttime = jiffies_to_msecs(jiffies);
  894. while (true) {
  895. doorbell = esas2r_read_register_dword(a, MU_DOORBELL_OUT);
  896. if (doorbell & DRBL_MSG_IFC_DOWN) {
  897. esas2r_write_register_dword(a, MU_DOORBELL_OUT,
  898. doorbell);
  899. break;
  900. }
  901. schedule_timeout_interruptible(msecs_to_jiffies(50));
  902. if ((jiffies_to_msecs(jiffies) - starttime) > 3000) {
  903. esas2r_hdebug("timeout waiting for interface down");
  904. break;
  905. }
  906. }
  907. skip_chip_reset:
  908. /*
  909. * first things first, before we go changing any of these registers
  910. * disable the communication lists.
  911. */
  912. dw = esas2r_read_register_dword(a, MU_IN_LIST_CONFIG);
  913. dw &= ~MU_ILC_ENABLE;
  914. esas2r_write_register_dword(a, MU_IN_LIST_CONFIG, dw);
  915. dw = esas2r_read_register_dword(a, MU_OUT_LIST_CONFIG);
  916. dw &= ~MU_OLC_ENABLE;
  917. esas2r_write_register_dword(a, MU_OUT_LIST_CONFIG, dw);
  918. /* configure the communication list addresses */
  919. ppaddr = a->inbound_list_md.phys_addr;
  920. esas2r_write_register_dword(a, MU_IN_LIST_ADDR_LO,
  921. lower_32_bits(ppaddr));
  922. esas2r_write_register_dword(a, MU_IN_LIST_ADDR_HI,
  923. upper_32_bits(ppaddr));
  924. ppaddr = a->outbound_list_md.phys_addr;
  925. esas2r_write_register_dword(a, MU_OUT_LIST_ADDR_LO,
  926. lower_32_bits(ppaddr));
  927. esas2r_write_register_dword(a, MU_OUT_LIST_ADDR_HI,
  928. upper_32_bits(ppaddr));
  929. ppaddr = a->uncached_phys +
  930. ((u8 *)a->outbound_copy - a->uncached);
  931. esas2r_write_register_dword(a, MU_OUT_LIST_COPY_PTR_LO,
  932. lower_32_bits(ppaddr));
  933. esas2r_write_register_dword(a, MU_OUT_LIST_COPY_PTR_HI,
  934. upper_32_bits(ppaddr));
  935. /* reset the read and write pointers */
  936. *a->outbound_copy =
  937. a->last_write =
  938. a->last_read = a->list_size - 1;
  939. set_bit(AF_COMM_LIST_TOGGLE, &a->flags);
  940. esas2r_write_register_dword(a, MU_IN_LIST_WRITE, MU_ILW_TOGGLE |
  941. a->last_write);
  942. esas2r_write_register_dword(a, MU_OUT_LIST_COPY, MU_OLC_TOGGLE |
  943. a->last_write);
  944. esas2r_write_register_dword(a, MU_IN_LIST_READ, MU_ILR_TOGGLE |
  945. a->last_write);
  946. esas2r_write_register_dword(a, MU_OUT_LIST_WRITE,
  947. MU_OLW_TOGGLE | a->last_write);
  948. /* configure the interface select fields */
  949. dw = esas2r_read_register_dword(a, MU_IN_LIST_IFC_CONFIG);
  950. dw &= ~(MU_ILIC_LIST | MU_ILIC_DEST);
  951. esas2r_write_register_dword(a, MU_IN_LIST_IFC_CONFIG,
  952. (dw | MU_ILIC_LIST_F0 | MU_ILIC_DEST_DDR));
  953. dw = esas2r_read_register_dword(a, MU_OUT_LIST_IFC_CONFIG);
  954. dw &= ~(MU_OLIC_LIST | MU_OLIC_SOURCE);
  955. esas2r_write_register_dword(a, MU_OUT_LIST_IFC_CONFIG,
  956. (dw | MU_OLIC_LIST_F0 |
  957. MU_OLIC_SOURCE_DDR));
  958. /* finish configuring the communication lists */
  959. dw = esas2r_read_register_dword(a, MU_IN_LIST_CONFIG);
  960. dw &= ~(MU_ILC_ENTRY_MASK | MU_ILC_NUMBER_MASK);
  961. dw |= MU_ILC_ENTRY_4_DW | MU_ILC_DYNAMIC_SRC
  962. | (a->list_size << MU_ILC_NUMBER_SHIFT);
  963. esas2r_write_register_dword(a, MU_IN_LIST_CONFIG, dw);
  964. dw = esas2r_read_register_dword(a, MU_OUT_LIST_CONFIG);
  965. dw &= ~(MU_OLC_ENTRY_MASK | MU_OLC_NUMBER_MASK);
  966. dw |= MU_OLC_ENTRY_4_DW | (a->list_size << MU_OLC_NUMBER_SHIFT);
  967. esas2r_write_register_dword(a, MU_OUT_LIST_CONFIG, dw);
  968. /*
  969. * notify the firmware that we're done setting up the communication
  970. * list registers. wait here until the firmware is done configuring
  971. * its lists. it will signal that it is done by enabling the lists.
  972. */
  973. esas2r_write_register_dword(a, MU_DOORBELL_IN, DRBL_MSG_IFC_INIT);
  974. starttime = jiffies_to_msecs(jiffies);
  975. while (true) {
  976. doorbell = esas2r_read_register_dword(a, MU_DOORBELL_OUT);
  977. if (doorbell & DRBL_MSG_IFC_INIT) {
  978. esas2r_write_register_dword(a, MU_DOORBELL_OUT,
  979. doorbell);
  980. break;
  981. }
  982. schedule_timeout_interruptible(msecs_to_jiffies(100));
  983. if ((jiffies_to_msecs(jiffies) - starttime) > 3000) {
  984. esas2r_hdebug(
  985. "timeout waiting for communication list init");
  986. esas2r_bugon();
  987. return esas2r_set_degraded_mode(a,
  988. "timeout waiting for communication list init");
  989. }
  990. }
  991. /*
  992. * flag whether the firmware supports the power down doorbell. we
  993. * determine this by reading the inbound doorbell enable mask.
  994. */
  995. doorbell = esas2r_read_register_dword(a, MU_DOORBELL_IN_ENB);
  996. if (doorbell & DRBL_POWER_DOWN)
  997. set_bit(AF2_VDA_POWER_DOWN, &a->flags2);
  998. else
  999. clear_bit(AF2_VDA_POWER_DOWN, &a->flags2);
  1000. /*
  1001. * enable assertion of outbound queue and doorbell interrupts in the
  1002. * main interrupt cause register.
  1003. */
  1004. esas2r_write_register_dword(a, MU_OUT_LIST_INT_MASK, MU_OLIS_MASK);
  1005. esas2r_write_register_dword(a, MU_DOORBELL_OUT_ENB, DRBL_ENB_MASK);
  1006. return true;
  1007. }
  1008. /* Process the initialization message just completed and format the next one. */
  1009. static bool esas2r_format_init_msg(struct esas2r_adapter *a,
  1010. struct esas2r_request *rq)
  1011. {
  1012. u32 msg = a->init_msg;
  1013. struct atto_vda_cfg_init *ci;
  1014. a->init_msg = 0;
  1015. switch (msg) {
  1016. case ESAS2R_INIT_MSG_START:
  1017. case ESAS2R_INIT_MSG_REINIT:
  1018. {
  1019. esas2r_hdebug("CFG init");
  1020. esas2r_build_cfg_req(a,
  1021. rq,
  1022. VDA_CFG_INIT,
  1023. 0,
  1024. NULL);
  1025. ci = (struct atto_vda_cfg_init *)&rq->vrq->cfg.data.init;
  1026. ci->sgl_page_size = cpu_to_le32(sgl_page_size);
  1027. /* firmware interface overflows in y2106 */
  1028. ci->epoch_time = cpu_to_le32(ktime_get_real_seconds());
  1029. rq->flags |= RF_FAILURE_OK;
  1030. a->init_msg = ESAS2R_INIT_MSG_INIT;
  1031. break;
  1032. }
  1033. case ESAS2R_INIT_MSG_INIT:
  1034. if (rq->req_stat == RS_SUCCESS) {
  1035. u32 major;
  1036. u32 minor;
  1037. u16 fw_release;
  1038. a->fw_version = le16_to_cpu(
  1039. rq->func_rsp.cfg_rsp.vda_version);
  1040. a->fw_build = rq->func_rsp.cfg_rsp.fw_build;
  1041. fw_release = le16_to_cpu(
  1042. rq->func_rsp.cfg_rsp.fw_release);
  1043. major = LOBYTE(fw_release);
  1044. minor = HIBYTE(fw_release);
  1045. a->fw_version += (major << 16) + (minor << 24);
  1046. } else {
  1047. esas2r_hdebug("FAILED");
  1048. }
  1049. /*
  1050. * the 2.71 and earlier releases of R6xx firmware did not error
  1051. * unsupported config requests correctly.
  1052. */
  1053. if ((test_bit(AF2_THUNDERBOLT, &a->flags2))
  1054. || (be32_to_cpu(a->fw_version) > 0x00524702)) {
  1055. esas2r_hdebug("CFG get init");
  1056. esas2r_build_cfg_req(a,
  1057. rq,
  1058. VDA_CFG_GET_INIT2,
  1059. sizeof(struct atto_vda_cfg_init),
  1060. NULL);
  1061. rq->vrq->cfg.sg_list_offset = offsetof(
  1062. struct atto_vda_cfg_req,
  1063. data.sge);
  1064. rq->vrq->cfg.data.prde.ctl_len =
  1065. cpu_to_le32(sizeof(struct atto_vda_cfg_init));
  1066. rq->vrq->cfg.data.prde.address = cpu_to_le64(
  1067. rq->vrq_md->phys_addr +
  1068. sizeof(union atto_vda_req));
  1069. rq->flags |= RF_FAILURE_OK;
  1070. a->init_msg = ESAS2R_INIT_MSG_GET_INIT;
  1071. break;
  1072. }
  1073. case ESAS2R_INIT_MSG_GET_INIT:
  1074. if (msg == ESAS2R_INIT_MSG_GET_INIT) {
  1075. ci = (struct atto_vda_cfg_init *)rq->data_buf;
  1076. if (rq->req_stat == RS_SUCCESS) {
  1077. a->num_targets_backend =
  1078. le32_to_cpu(ci->num_targets_backend);
  1079. a->ioctl_tunnel =
  1080. le32_to_cpu(ci->ioctl_tunnel);
  1081. } else {
  1082. esas2r_hdebug("FAILED");
  1083. }
  1084. }
  1085. /* fall through */
  1086. default:
  1087. rq->req_stat = RS_SUCCESS;
  1088. return false;
  1089. }
  1090. return true;
  1091. }
  1092. /*
  1093. * Perform initialization messages via the request queue. Messages are
  1094. * performed with interrupts disabled.
  1095. */
  1096. bool esas2r_init_msgs(struct esas2r_adapter *a)
  1097. {
  1098. bool success = true;
  1099. struct esas2r_request *rq = &a->general_req;
  1100. esas2r_rq_init_request(rq, a);
  1101. rq->comp_cb = esas2r_dummy_complete;
  1102. if (a->init_msg == 0)
  1103. a->init_msg = ESAS2R_INIT_MSG_REINIT;
  1104. while (a->init_msg) {
  1105. if (esas2r_format_init_msg(a, rq)) {
  1106. unsigned long flags;
  1107. while (true) {
  1108. spin_lock_irqsave(&a->queue_lock, flags);
  1109. esas2r_start_vda_request(a, rq);
  1110. spin_unlock_irqrestore(&a->queue_lock, flags);
  1111. esas2r_wait_request(a, rq);
  1112. if (rq->req_stat != RS_PENDING)
  1113. break;
  1114. }
  1115. }
  1116. if (rq->req_stat == RS_SUCCESS
  1117. || ((rq->flags & RF_FAILURE_OK)
  1118. && rq->req_stat != RS_TIMEOUT))
  1119. continue;
  1120. esas2r_log(ESAS2R_LOG_CRIT, "init message %x failed (%x, %x)",
  1121. a->init_msg, rq->req_stat, rq->flags);
  1122. a->init_msg = ESAS2R_INIT_MSG_START;
  1123. success = false;
  1124. break;
  1125. }
  1126. esas2r_rq_destroy_request(rq, a);
  1127. return success;
  1128. }
  1129. /* Initialize the adapter chip */
  1130. bool esas2r_init_adapter_hw(struct esas2r_adapter *a, bool init_poll)
  1131. {
  1132. bool rslt = false;
  1133. struct esas2r_request *rq;
  1134. u32 i;
  1135. if (test_bit(AF_DEGRADED_MODE, &a->flags))
  1136. goto exit;
  1137. if (!test_bit(AF_NVR_VALID, &a->flags)) {
  1138. if (!esas2r_nvram_read_direct(a))
  1139. esas2r_log(ESAS2R_LOG_WARN,
  1140. "invalid/missing NVRAM parameters");
  1141. }
  1142. if (!esas2r_init_msgs(a)) {
  1143. esas2r_set_degraded_mode(a, "init messages failed");
  1144. goto exit;
  1145. }
  1146. /* The firmware is ready. */
  1147. clear_bit(AF_DEGRADED_MODE, &a->flags);
  1148. clear_bit(AF_CHPRST_PENDING, &a->flags);
  1149. /* Post all the async event requests */
  1150. for (i = 0, rq = a->first_ae_req; i < num_ae_requests; i++, rq++)
  1151. esas2r_start_ae_request(a, rq);
  1152. if (!a->flash_rev[0])
  1153. esas2r_read_flash_rev(a);
  1154. if (!a->image_type[0])
  1155. esas2r_read_image_type(a);
  1156. if (a->fw_version == 0)
  1157. a->fw_rev[0] = 0;
  1158. else
  1159. sprintf(a->fw_rev, "%1d.%02d",
  1160. (int)LOBYTE(HIWORD(a->fw_version)),
  1161. (int)HIBYTE(HIWORD(a->fw_version)));
  1162. esas2r_hdebug("firmware revision: %s", a->fw_rev);
  1163. if (test_bit(AF_CHPRST_DETECTED, &a->flags)
  1164. && (test_bit(AF_FIRST_INIT, &a->flags))) {
  1165. esas2r_enable_chip_interrupts(a);
  1166. return true;
  1167. }
  1168. /* initialize discovery */
  1169. esas2r_disc_initialize(a);
  1170. /*
  1171. * wait for the device wait time to expire here if requested. this is
  1172. * usually requested during initial driver load and possibly when
  1173. * resuming from a low power state. deferred device waiting will use
  1174. * interrupts. chip reset recovery always defers device waiting to
  1175. * avoid being in a TASKLET too long.
  1176. */
  1177. if (init_poll) {
  1178. u32 currtime = a->disc_start_time;
  1179. u32 nexttick = 100;
  1180. u32 deltatime;
  1181. /*
  1182. * Block Tasklets from getting scheduled and indicate this is
  1183. * polled discovery.
  1184. */
  1185. set_bit(AF_TASKLET_SCHEDULED, &a->flags);
  1186. set_bit(AF_DISC_POLLED, &a->flags);
  1187. /*
  1188. * Temporarily bring the disable count to zero to enable
  1189. * deferred processing. Note that the count is already zero
  1190. * after the first initialization.
  1191. */
  1192. if (test_bit(AF_FIRST_INIT, &a->flags))
  1193. atomic_dec(&a->disable_cnt);
  1194. while (test_bit(AF_DISC_PENDING, &a->flags)) {
  1195. schedule_timeout_interruptible(msecs_to_jiffies(100));
  1196. /*
  1197. * Determine the need for a timer tick based on the
  1198. * delta time between this and the last iteration of
  1199. * this loop. We don't use the absolute time because
  1200. * then we would have to worry about when nexttick
  1201. * wraps and currtime hasn't yet.
  1202. */
  1203. deltatime = jiffies_to_msecs(jiffies) - currtime;
  1204. currtime += deltatime;
  1205. /*
  1206. * Process any waiting discovery as long as the chip is
  1207. * up. If a chip reset happens during initial polling,
  1208. * we have to make sure the timer tick processes the
  1209. * doorbell indicating the firmware is ready.
  1210. */
  1211. if (!test_bit(AF_CHPRST_PENDING, &a->flags))
  1212. esas2r_disc_check_for_work(a);
  1213. /* Simulate a timer tick. */
  1214. if (nexttick <= deltatime) {
  1215. /* Time for a timer tick */
  1216. nexttick += 100;
  1217. esas2r_timer_tick(a);
  1218. }
  1219. if (nexttick > deltatime)
  1220. nexttick -= deltatime;
  1221. /* Do any deferred processing */
  1222. if (esas2r_is_tasklet_pending(a))
  1223. esas2r_do_tasklet_tasks(a);
  1224. }
  1225. if (test_bit(AF_FIRST_INIT, &a->flags))
  1226. atomic_inc(&a->disable_cnt);
  1227. clear_bit(AF_DISC_POLLED, &a->flags);
  1228. clear_bit(AF_TASKLET_SCHEDULED, &a->flags);
  1229. }
  1230. esas2r_targ_db_report_changes(a);
  1231. /*
  1232. * For cases where (a) the initialization messages processing may
  1233. * handle an interrupt for a port event and a discovery is waiting, but
  1234. * we are not waiting for devices, or (b) the device wait time has been
  1235. * exhausted but there is still discovery pending, start any leftover
  1236. * discovery in interrupt driven mode.
  1237. */
  1238. esas2r_disc_start_waiting(a);
  1239. /* Enable chip interrupts */
  1240. a->int_mask = ESAS2R_INT_STS_MASK;
  1241. esas2r_enable_chip_interrupts(a);
  1242. esas2r_enable_heartbeat(a);
  1243. rslt = true;
  1244. exit:
  1245. /*
  1246. * Regardless of whether initialization was successful, certain things
  1247. * need to get done before we exit.
  1248. */
  1249. if (test_bit(AF_CHPRST_DETECTED, &a->flags) &&
  1250. test_bit(AF_FIRST_INIT, &a->flags)) {
  1251. /*
  1252. * Reinitialization was performed during the first
  1253. * initialization. Only clear the chip reset flag so the
  1254. * original device polling is not cancelled.
  1255. */
  1256. if (!rslt)
  1257. clear_bit(AF_CHPRST_PENDING, &a->flags);
  1258. } else {
  1259. /* First initialization or a subsequent re-init is complete. */
  1260. if (!rslt) {
  1261. clear_bit(AF_CHPRST_PENDING, &a->flags);
  1262. clear_bit(AF_DISC_PENDING, &a->flags);
  1263. }
  1264. /* Enable deferred processing after the first initialization. */
  1265. if (test_bit(AF_FIRST_INIT, &a->flags)) {
  1266. clear_bit(AF_FIRST_INIT, &a->flags);
  1267. if (atomic_dec_return(&a->disable_cnt) == 0)
  1268. esas2r_do_deferred_processes(a);
  1269. }
  1270. }
  1271. return rslt;
  1272. }
  1273. void esas2r_reset_adapter(struct esas2r_adapter *a)
  1274. {
  1275. set_bit(AF_OS_RESET, &a->flags);
  1276. esas2r_local_reset_adapter(a);
  1277. esas2r_schedule_tasklet(a);
  1278. }
  1279. void esas2r_reset_chip(struct esas2r_adapter *a)
  1280. {
  1281. if (!esas2r_is_adapter_present(a))
  1282. return;
  1283. /*
  1284. * Before we reset the chip, save off the VDA core dump. The VDA core
  1285. * dump is located in the upper 512KB of the onchip SRAM. Make sure
  1286. * to not overwrite a previous crash that was saved.
  1287. */
  1288. if (test_bit(AF2_COREDUMP_AVAIL, &a->flags2) &&
  1289. !test_bit(AF2_COREDUMP_SAVED, &a->flags2)) {
  1290. esas2r_read_mem_block(a,
  1291. a->fw_coredump_buff,
  1292. MW_DATA_ADDR_SRAM + 0x80000,
  1293. ESAS2R_FWCOREDUMP_SZ);
  1294. set_bit(AF2_COREDUMP_SAVED, &a->flags2);
  1295. }
  1296. clear_bit(AF2_COREDUMP_AVAIL, &a->flags2);
  1297. /* Reset the chip */
  1298. if (a->pcid->revision == MVR_FREY_B2)
  1299. esas2r_write_register_dword(a, MU_CTL_STATUS_IN_B2,
  1300. MU_CTL_IN_FULL_RST2);
  1301. else
  1302. esas2r_write_register_dword(a, MU_CTL_STATUS_IN,
  1303. MU_CTL_IN_FULL_RST);
  1304. /* Stall a little while to let the reset condition clear */
  1305. mdelay(10);
  1306. }
  1307. static void esas2r_power_down_notify_firmware(struct esas2r_adapter *a)
  1308. {
  1309. u32 starttime;
  1310. u32 doorbell;
  1311. esas2r_write_register_dword(a, MU_DOORBELL_IN, DRBL_POWER_DOWN);
  1312. starttime = jiffies_to_msecs(jiffies);
  1313. while (true) {
  1314. doorbell = esas2r_read_register_dword(a, MU_DOORBELL_OUT);
  1315. if (doorbell & DRBL_POWER_DOWN) {
  1316. esas2r_write_register_dword(a, MU_DOORBELL_OUT,
  1317. doorbell);
  1318. break;
  1319. }
  1320. schedule_timeout_interruptible(msecs_to_jiffies(100));
  1321. if ((jiffies_to_msecs(jiffies) - starttime) > 30000) {
  1322. esas2r_hdebug("Timeout waiting for power down");
  1323. break;
  1324. }
  1325. }
  1326. }
  1327. /*
  1328. * Perform power management processing including managing device states, adapter
  1329. * states, interrupts, and I/O.
  1330. */
  1331. void esas2r_power_down(struct esas2r_adapter *a)
  1332. {
  1333. set_bit(AF_POWER_MGT, &a->flags);
  1334. set_bit(AF_POWER_DOWN, &a->flags);
  1335. if (!test_bit(AF_DEGRADED_MODE, &a->flags)) {
  1336. u32 starttime;
  1337. u32 doorbell;
  1338. /*
  1339. * We are currently running OK and will be reinitializing later.
  1340. * increment the disable count to coordinate with
  1341. * esas2r_init_adapter. We don't have to do this in degraded
  1342. * mode since we never enabled interrupts in the first place.
  1343. */
  1344. esas2r_disable_chip_interrupts(a);
  1345. esas2r_disable_heartbeat(a);
  1346. /* wait for any VDA activity to clear before continuing */
  1347. esas2r_write_register_dword(a, MU_DOORBELL_IN,
  1348. DRBL_MSG_IFC_DOWN);
  1349. starttime = jiffies_to_msecs(jiffies);
  1350. while (true) {
  1351. doorbell =
  1352. esas2r_read_register_dword(a, MU_DOORBELL_OUT);
  1353. if (doorbell & DRBL_MSG_IFC_DOWN) {
  1354. esas2r_write_register_dword(a, MU_DOORBELL_OUT,
  1355. doorbell);
  1356. break;
  1357. }
  1358. schedule_timeout_interruptible(msecs_to_jiffies(100));
  1359. if ((jiffies_to_msecs(jiffies) - starttime) > 3000) {
  1360. esas2r_hdebug(
  1361. "timeout waiting for interface down");
  1362. break;
  1363. }
  1364. }
  1365. /*
  1366. * For versions of firmware that support it tell them the driver
  1367. * is powering down.
  1368. */
  1369. if (test_bit(AF2_VDA_POWER_DOWN, &a->flags2))
  1370. esas2r_power_down_notify_firmware(a);
  1371. }
  1372. /* Suspend I/O processing. */
  1373. set_bit(AF_OS_RESET, &a->flags);
  1374. set_bit(AF_DISC_PENDING, &a->flags);
  1375. set_bit(AF_CHPRST_PENDING, &a->flags);
  1376. esas2r_process_adapter_reset(a);
  1377. /* Remove devices now that I/O is cleaned up. */
  1378. a->prev_dev_cnt = esas2r_targ_db_get_tgt_cnt(a);
  1379. esas2r_targ_db_remove_all(a, false);
  1380. }
  1381. /*
  1382. * Perform power management processing including managing device states, adapter
  1383. * states, interrupts, and I/O.
  1384. */
  1385. bool esas2r_power_up(struct esas2r_adapter *a, bool init_poll)
  1386. {
  1387. bool ret;
  1388. clear_bit(AF_POWER_DOWN, &a->flags);
  1389. esas2r_init_pci_cfg_space(a);
  1390. set_bit(AF_FIRST_INIT, &a->flags);
  1391. atomic_inc(&a->disable_cnt);
  1392. /* reinitialize the adapter */
  1393. ret = esas2r_check_adapter(a);
  1394. if (!esas2r_init_adapter_hw(a, init_poll))
  1395. ret = false;
  1396. /* send the reset asynchronous event */
  1397. esas2r_send_reset_ae(a, true);
  1398. /* clear this flag after initialization. */
  1399. clear_bit(AF_POWER_MGT, &a->flags);
  1400. return ret;
  1401. }
  1402. bool esas2r_is_adapter_present(struct esas2r_adapter *a)
  1403. {
  1404. if (test_bit(AF_NOT_PRESENT, &a->flags))
  1405. return false;
  1406. if (esas2r_read_register_dword(a, MU_DOORBELL_OUT) == 0xFFFFFFFF) {
  1407. set_bit(AF_NOT_PRESENT, &a->flags);
  1408. return false;
  1409. }
  1410. return true;
  1411. }
  1412. const char *esas2r_get_model_name(struct esas2r_adapter *a)
  1413. {
  1414. switch (a->pcid->subsystem_device) {
  1415. case ATTO_ESAS_R680:
  1416. return "ATTO ExpressSAS R680";
  1417. case ATTO_ESAS_R608:
  1418. return "ATTO ExpressSAS R608";
  1419. case ATTO_ESAS_R60F:
  1420. return "ATTO ExpressSAS R60F";
  1421. case ATTO_ESAS_R6F0:
  1422. return "ATTO ExpressSAS R6F0";
  1423. case ATTO_ESAS_R644:
  1424. return "ATTO ExpressSAS R644";
  1425. case ATTO_ESAS_R648:
  1426. return "ATTO ExpressSAS R648";
  1427. case ATTO_TSSC_3808:
  1428. return "ATTO ThunderStream SC 3808D";
  1429. case ATTO_TSSC_3808E:
  1430. return "ATTO ThunderStream SC 3808E";
  1431. case ATTO_TLSH_1068:
  1432. return "ATTO ThunderLink SH 1068";
  1433. }
  1434. return "ATTO SAS Controller";
  1435. }
  1436. const char *esas2r_get_model_name_short(struct esas2r_adapter *a)
  1437. {
  1438. switch (a->pcid->subsystem_device) {
  1439. case ATTO_ESAS_R680:
  1440. return "R680";
  1441. case ATTO_ESAS_R608:
  1442. return "R608";
  1443. case ATTO_ESAS_R60F:
  1444. return "R60F";
  1445. case ATTO_ESAS_R6F0:
  1446. return "R6F0";
  1447. case ATTO_ESAS_R644:
  1448. return "R644";
  1449. case ATTO_ESAS_R648:
  1450. return "R648";
  1451. case ATTO_TSSC_3808:
  1452. return "SC 3808D";
  1453. case ATTO_TSSC_3808E:
  1454. return "SC 3808E";
  1455. case ATTO_TLSH_1068:
  1456. return "SH 1068";
  1457. }
  1458. return "unknown";
  1459. }