ocxl_hw.h 2.6 KB

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  1. /*
  2. * CXL Flash Device Driver
  3. *
  4. * Written by: Matthew R. Ochs <mrochs@linux.vnet.ibm.com>, IBM Corporation
  5. * Uma Krishnan <ukrishn@linux.vnet.ibm.com>, IBM Corporation
  6. *
  7. * Copyright (C) 2018 IBM Corporation
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License
  11. * as published by the Free Software Foundation; either version
  12. * 2 of the License, or (at your option) any later version.
  13. */
  14. #define OCXL_MAX_IRQS 4 /* Max interrupts per process */
  15. struct ocxlflash_irqs {
  16. int hwirq;
  17. u32 virq;
  18. u64 ptrig;
  19. void __iomem *vtrig;
  20. };
  21. /* OCXL hardware AFU associated with the host */
  22. struct ocxl_hw_afu {
  23. struct ocxlflash_context *ocxl_ctx; /* Host context */
  24. struct pci_dev *pdev; /* PCI device */
  25. struct device *dev; /* Generic device */
  26. bool perst_same_image; /* Same image loaded on perst */
  27. struct ocxl_fn_config fcfg; /* DVSEC config of the function */
  28. struct ocxl_afu_config acfg; /* AFU configuration data */
  29. int fn_actag_base; /* Function acTag base */
  30. int fn_actag_enabled; /* Function acTag number enabled */
  31. int afu_actag_base; /* AFU acTag base */
  32. int afu_actag_enabled; /* AFU acTag number enabled */
  33. phys_addr_t ppmmio_phys; /* Per process MMIO space */
  34. phys_addr_t gmmio_phys; /* Global AFU MMIO space */
  35. void __iomem *gmmio_virt; /* Global MMIO map */
  36. void *link_token; /* Link token for the SPA */
  37. struct idr idr; /* IDR to manage contexts */
  38. int max_pasid; /* Maximum number of contexts */
  39. bool is_present; /* Function has AFUs defined */
  40. };
  41. enum ocxlflash_ctx_state {
  42. CLOSED,
  43. OPENED,
  44. STARTED
  45. };
  46. struct ocxlflash_context {
  47. struct ocxl_hw_afu *hw_afu; /* HW AFU back pointer */
  48. struct address_space *mapping; /* Mapping for pseudo filesystem */
  49. bool master; /* Whether this is a master context */
  50. int pe; /* Process element */
  51. phys_addr_t psn_phys; /* Process mapping */
  52. u64 psn_size; /* Process mapping size */
  53. spinlock_t slock; /* Protects irq/fault/event updates */
  54. wait_queue_head_t wq; /* Wait queue for poll and interrupts */
  55. struct mutex state_mutex; /* Mutex to update context state */
  56. enum ocxlflash_ctx_state state; /* Context state */
  57. struct ocxlflash_irqs *irqs; /* Pointer to array of structures */
  58. int num_irqs; /* Number of interrupts */
  59. bool pending_irq; /* Pending interrupt on the context */
  60. ulong irq_bitmap; /* Bits indicating pending irq num */
  61. u64 fault_addr; /* Address that triggered the fault */
  62. u64 fault_dsisr; /* Value of dsisr register at fault */
  63. bool pending_fault; /* Pending translation fault */
  64. };