arcmsr_hba.c 135 KB

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  1. /*
  2. *******************************************************************************
  3. ** O.S : Linux
  4. ** FILE NAME : arcmsr_hba.c
  5. ** BY : Nick Cheng, C.L. Huang
  6. ** Description: SCSI RAID Device Driver for Areca RAID Controller
  7. *******************************************************************************
  8. ** Copyright (C) 2002 - 2014, Areca Technology Corporation All rights reserved
  9. **
  10. ** Web site: www.areca.com.tw
  11. ** E-mail: support@areca.com.tw
  12. **
  13. ** This program is free software; you can redistribute it and/or modify
  14. ** it under the terms of the GNU General Public License version 2 as
  15. ** published by the Free Software Foundation.
  16. ** This program is distributed in the hope that it will be useful,
  17. ** but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. ** GNU General Public License for more details.
  20. *******************************************************************************
  21. ** Redistribution and use in source and binary forms, with or without
  22. ** modification, are permitted provided that the following conditions
  23. ** are met:
  24. ** 1. Redistributions of source code must retain the above copyright
  25. ** notice, this list of conditions and the following disclaimer.
  26. ** 2. Redistributions in binary form must reproduce the above copyright
  27. ** notice, this list of conditions and the following disclaimer in the
  28. ** documentation and/or other materials provided with the distribution.
  29. ** 3. The name of the author may not be used to endorse or promote products
  30. ** derived from this software without specific prior written permission.
  31. **
  32. ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  33. ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  34. ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  35. ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  36. ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING,BUT
  37. ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  38. ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY
  39. ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40. ** (INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF
  41. ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42. *******************************************************************************
  43. ** For history of changes, see Documentation/scsi/ChangeLog.arcmsr
  44. ** Firmware Specification, see Documentation/scsi/arcmsr_spec.txt
  45. *******************************************************************************
  46. */
  47. #include <linux/module.h>
  48. #include <linux/reboot.h>
  49. #include <linux/spinlock.h>
  50. #include <linux/pci_ids.h>
  51. #include <linux/interrupt.h>
  52. #include <linux/moduleparam.h>
  53. #include <linux/errno.h>
  54. #include <linux/types.h>
  55. #include <linux/delay.h>
  56. #include <linux/dma-mapping.h>
  57. #include <linux/timer.h>
  58. #include <linux/slab.h>
  59. #include <linux/pci.h>
  60. #include <linux/aer.h>
  61. #include <linux/circ_buf.h>
  62. #include <asm/dma.h>
  63. #include <asm/io.h>
  64. #include <linux/uaccess.h>
  65. #include <scsi/scsi_host.h>
  66. #include <scsi/scsi.h>
  67. #include <scsi/scsi_cmnd.h>
  68. #include <scsi/scsi_tcq.h>
  69. #include <scsi/scsi_device.h>
  70. #include <scsi/scsi_transport.h>
  71. #include <scsi/scsicam.h>
  72. #include "arcmsr.h"
  73. MODULE_AUTHOR("Nick Cheng, C.L. Huang <support@areca.com.tw>");
  74. MODULE_DESCRIPTION("Areca ARC11xx/12xx/16xx/188x SAS/SATA RAID Controller Driver");
  75. MODULE_LICENSE("Dual BSD/GPL");
  76. MODULE_VERSION(ARCMSR_DRIVER_VERSION);
  77. static int msix_enable = 1;
  78. module_param(msix_enable, int, S_IRUGO);
  79. MODULE_PARM_DESC(msix_enable, "Enable MSI-X interrupt(0 ~ 1), msix_enable=1(enable), =0(disable)");
  80. static int msi_enable = 1;
  81. module_param(msi_enable, int, S_IRUGO);
  82. MODULE_PARM_DESC(msi_enable, "Enable MSI interrupt(0 ~ 1), msi_enable=1(enable), =0(disable)");
  83. static int host_can_queue = ARCMSR_DEFAULT_OUTSTANDING_CMD;
  84. module_param(host_can_queue, int, S_IRUGO);
  85. MODULE_PARM_DESC(host_can_queue, " adapter queue depth(32 ~ 1024), default is 128");
  86. static int cmd_per_lun = ARCMSR_DEFAULT_CMD_PERLUN;
  87. module_param(cmd_per_lun, int, S_IRUGO);
  88. MODULE_PARM_DESC(cmd_per_lun, " device queue depth(1 ~ 128), default is 32");
  89. static int set_date_time = 0;
  90. module_param(set_date_time, int, S_IRUGO);
  91. MODULE_PARM_DESC(set_date_time, " send date, time to iop(0 ~ 1), set_date_time=1(enable), default(=0) is disable");
  92. #define ARCMSR_SLEEPTIME 10
  93. #define ARCMSR_RETRYCOUNT 12
  94. static wait_queue_head_t wait_q;
  95. static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb,
  96. struct scsi_cmnd *cmd);
  97. static int arcmsr_iop_confirm(struct AdapterControlBlock *acb);
  98. static int arcmsr_abort(struct scsi_cmnd *);
  99. static int arcmsr_bus_reset(struct scsi_cmnd *);
  100. static int arcmsr_bios_param(struct scsi_device *sdev,
  101. struct block_device *bdev, sector_t capacity, int *info);
  102. static int arcmsr_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
  103. static int arcmsr_probe(struct pci_dev *pdev,
  104. const struct pci_device_id *id);
  105. static int arcmsr_suspend(struct pci_dev *pdev, pm_message_t state);
  106. static int arcmsr_resume(struct pci_dev *pdev);
  107. static void arcmsr_remove(struct pci_dev *pdev);
  108. static void arcmsr_shutdown(struct pci_dev *pdev);
  109. static void arcmsr_iop_init(struct AdapterControlBlock *acb);
  110. static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb);
  111. static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb);
  112. static void arcmsr_enable_outbound_ints(struct AdapterControlBlock *acb,
  113. u32 intmask_org);
  114. static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb);
  115. static void arcmsr_hbaA_flush_cache(struct AdapterControlBlock *acb);
  116. static void arcmsr_hbaB_flush_cache(struct AdapterControlBlock *acb);
  117. static void arcmsr_request_device_map(struct timer_list *t);
  118. static void arcmsr_message_isr_bh_fn(struct work_struct *work);
  119. static bool arcmsr_get_firmware_spec(struct AdapterControlBlock *acb);
  120. static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb);
  121. static void arcmsr_hbaC_message_isr(struct AdapterControlBlock *pACB);
  122. static void arcmsr_hbaD_message_isr(struct AdapterControlBlock *acb);
  123. static void arcmsr_hbaE_message_isr(struct AdapterControlBlock *acb);
  124. static void arcmsr_hbaE_postqueue_isr(struct AdapterControlBlock *acb);
  125. static void arcmsr_hardware_reset(struct AdapterControlBlock *acb);
  126. static const char *arcmsr_info(struct Scsi_Host *);
  127. static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb);
  128. static void arcmsr_free_irq(struct pci_dev *, struct AdapterControlBlock *);
  129. static void arcmsr_wait_firmware_ready(struct AdapterControlBlock *acb);
  130. static void arcmsr_set_iop_datetime(struct timer_list *);
  131. static int arcmsr_adjust_disk_queue_depth(struct scsi_device *sdev, int queue_depth)
  132. {
  133. if (queue_depth > ARCMSR_MAX_CMD_PERLUN)
  134. queue_depth = ARCMSR_MAX_CMD_PERLUN;
  135. return scsi_change_queue_depth(sdev, queue_depth);
  136. }
  137. static struct scsi_host_template arcmsr_scsi_host_template = {
  138. .module = THIS_MODULE,
  139. .name = "Areca SAS/SATA RAID driver",
  140. .info = arcmsr_info,
  141. .queuecommand = arcmsr_queue_command,
  142. .eh_abort_handler = arcmsr_abort,
  143. .eh_bus_reset_handler = arcmsr_bus_reset,
  144. .bios_param = arcmsr_bios_param,
  145. .change_queue_depth = arcmsr_adjust_disk_queue_depth,
  146. .can_queue = ARCMSR_DEFAULT_OUTSTANDING_CMD,
  147. .this_id = ARCMSR_SCSI_INITIATOR_ID,
  148. .sg_tablesize = ARCMSR_DEFAULT_SG_ENTRIES,
  149. .max_sectors = ARCMSR_MAX_XFER_SECTORS_C,
  150. .cmd_per_lun = ARCMSR_DEFAULT_CMD_PERLUN,
  151. .use_clustering = ENABLE_CLUSTERING,
  152. .shost_attrs = arcmsr_host_attrs,
  153. .no_write_same = 1,
  154. };
  155. static struct pci_device_id arcmsr_device_id_table[] = {
  156. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1110),
  157. .driver_data = ACB_ADAPTER_TYPE_A},
  158. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1120),
  159. .driver_data = ACB_ADAPTER_TYPE_A},
  160. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1130),
  161. .driver_data = ACB_ADAPTER_TYPE_A},
  162. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1160),
  163. .driver_data = ACB_ADAPTER_TYPE_A},
  164. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1170),
  165. .driver_data = ACB_ADAPTER_TYPE_A},
  166. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1200),
  167. .driver_data = ACB_ADAPTER_TYPE_B},
  168. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1201),
  169. .driver_data = ACB_ADAPTER_TYPE_B},
  170. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1202),
  171. .driver_data = ACB_ADAPTER_TYPE_B},
  172. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1203),
  173. .driver_data = ACB_ADAPTER_TYPE_B},
  174. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1210),
  175. .driver_data = ACB_ADAPTER_TYPE_A},
  176. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1214),
  177. .driver_data = ACB_ADAPTER_TYPE_D},
  178. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1220),
  179. .driver_data = ACB_ADAPTER_TYPE_A},
  180. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1230),
  181. .driver_data = ACB_ADAPTER_TYPE_A},
  182. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1260),
  183. .driver_data = ACB_ADAPTER_TYPE_A},
  184. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1270),
  185. .driver_data = ACB_ADAPTER_TYPE_A},
  186. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1280),
  187. .driver_data = ACB_ADAPTER_TYPE_A},
  188. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1380),
  189. .driver_data = ACB_ADAPTER_TYPE_A},
  190. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1381),
  191. .driver_data = ACB_ADAPTER_TYPE_A},
  192. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1680),
  193. .driver_data = ACB_ADAPTER_TYPE_A},
  194. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1681),
  195. .driver_data = ACB_ADAPTER_TYPE_A},
  196. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1880),
  197. .driver_data = ACB_ADAPTER_TYPE_C},
  198. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1884),
  199. .driver_data = ACB_ADAPTER_TYPE_E},
  200. {0, 0}, /* Terminating entry */
  201. };
  202. MODULE_DEVICE_TABLE(pci, arcmsr_device_id_table);
  203. static struct pci_driver arcmsr_pci_driver = {
  204. .name = "arcmsr",
  205. .id_table = arcmsr_device_id_table,
  206. .probe = arcmsr_probe,
  207. .remove = arcmsr_remove,
  208. .suspend = arcmsr_suspend,
  209. .resume = arcmsr_resume,
  210. .shutdown = arcmsr_shutdown,
  211. };
  212. /*
  213. ****************************************************************************
  214. ****************************************************************************
  215. */
  216. static void arcmsr_free_mu(struct AdapterControlBlock *acb)
  217. {
  218. switch (acb->adapter_type) {
  219. case ACB_ADAPTER_TYPE_B:
  220. case ACB_ADAPTER_TYPE_D:
  221. case ACB_ADAPTER_TYPE_E: {
  222. dma_free_coherent(&acb->pdev->dev, acb->roundup_ccbsize,
  223. acb->dma_coherent2, acb->dma_coherent_handle2);
  224. break;
  225. }
  226. }
  227. }
  228. static bool arcmsr_remap_pciregion(struct AdapterControlBlock *acb)
  229. {
  230. struct pci_dev *pdev = acb->pdev;
  231. switch (acb->adapter_type){
  232. case ACB_ADAPTER_TYPE_A:{
  233. acb->pmuA = ioremap(pci_resource_start(pdev,0), pci_resource_len(pdev,0));
  234. if (!acb->pmuA) {
  235. printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
  236. return false;
  237. }
  238. break;
  239. }
  240. case ACB_ADAPTER_TYPE_B:{
  241. void __iomem *mem_base0, *mem_base1;
  242. mem_base0 = ioremap(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
  243. if (!mem_base0) {
  244. printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
  245. return false;
  246. }
  247. mem_base1 = ioremap(pci_resource_start(pdev, 2), pci_resource_len(pdev, 2));
  248. if (!mem_base1) {
  249. iounmap(mem_base0);
  250. printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
  251. return false;
  252. }
  253. acb->mem_base0 = mem_base0;
  254. acb->mem_base1 = mem_base1;
  255. break;
  256. }
  257. case ACB_ADAPTER_TYPE_C:{
  258. acb->pmuC = ioremap_nocache(pci_resource_start(pdev, 1), pci_resource_len(pdev, 1));
  259. if (!acb->pmuC) {
  260. printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
  261. return false;
  262. }
  263. if (readl(&acb->pmuC->outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
  264. writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &acb->pmuC->outbound_doorbell_clear);/*clear interrupt*/
  265. return true;
  266. }
  267. break;
  268. }
  269. case ACB_ADAPTER_TYPE_D: {
  270. void __iomem *mem_base0;
  271. unsigned long addr, range, flags;
  272. addr = (unsigned long)pci_resource_start(pdev, 0);
  273. range = pci_resource_len(pdev, 0);
  274. flags = pci_resource_flags(pdev, 0);
  275. mem_base0 = ioremap(addr, range);
  276. if (!mem_base0) {
  277. pr_notice("arcmsr%d: memory mapping region fail\n",
  278. acb->host->host_no);
  279. return false;
  280. }
  281. acb->mem_base0 = mem_base0;
  282. break;
  283. }
  284. case ACB_ADAPTER_TYPE_E: {
  285. acb->pmuE = ioremap(pci_resource_start(pdev, 1),
  286. pci_resource_len(pdev, 1));
  287. if (!acb->pmuE) {
  288. pr_notice("arcmsr%d: memory mapping region fail \n",
  289. acb->host->host_no);
  290. return false;
  291. }
  292. writel(0, &acb->pmuE->host_int_status); /*clear interrupt*/
  293. writel(ARCMSR_HBEMU_DOORBELL_SYNC, &acb->pmuE->iobound_doorbell); /* synchronize doorbell to 0 */
  294. acb->in_doorbell = 0;
  295. acb->out_doorbell = 0;
  296. break;
  297. }
  298. }
  299. return true;
  300. }
  301. static void arcmsr_unmap_pciregion(struct AdapterControlBlock *acb)
  302. {
  303. switch (acb->adapter_type) {
  304. case ACB_ADAPTER_TYPE_A:{
  305. iounmap(acb->pmuA);
  306. }
  307. break;
  308. case ACB_ADAPTER_TYPE_B:{
  309. iounmap(acb->mem_base0);
  310. iounmap(acb->mem_base1);
  311. }
  312. break;
  313. case ACB_ADAPTER_TYPE_C:{
  314. iounmap(acb->pmuC);
  315. }
  316. break;
  317. case ACB_ADAPTER_TYPE_D:
  318. iounmap(acb->mem_base0);
  319. break;
  320. case ACB_ADAPTER_TYPE_E:
  321. iounmap(acb->pmuE);
  322. break;
  323. }
  324. }
  325. static irqreturn_t arcmsr_do_interrupt(int irq, void *dev_id)
  326. {
  327. irqreturn_t handle_state;
  328. struct AdapterControlBlock *acb = dev_id;
  329. handle_state = arcmsr_interrupt(acb);
  330. return handle_state;
  331. }
  332. static int arcmsr_bios_param(struct scsi_device *sdev,
  333. struct block_device *bdev, sector_t capacity, int *geom)
  334. {
  335. int ret, heads, sectors, cylinders, total_capacity;
  336. unsigned char *buffer;/* return copy of block device's partition table */
  337. buffer = scsi_bios_ptable(bdev);
  338. if (buffer) {
  339. ret = scsi_partsize(buffer, capacity, &geom[2], &geom[0], &geom[1]);
  340. kfree(buffer);
  341. if (ret != -1)
  342. return ret;
  343. }
  344. total_capacity = capacity;
  345. heads = 64;
  346. sectors = 32;
  347. cylinders = total_capacity / (heads * sectors);
  348. if (cylinders > 1024) {
  349. heads = 255;
  350. sectors = 63;
  351. cylinders = total_capacity / (heads * sectors);
  352. }
  353. geom[0] = heads;
  354. geom[1] = sectors;
  355. geom[2] = cylinders;
  356. return 0;
  357. }
  358. static uint8_t arcmsr_hbaA_wait_msgint_ready(struct AdapterControlBlock *acb)
  359. {
  360. struct MessageUnit_A __iomem *reg = acb->pmuA;
  361. int i;
  362. for (i = 0; i < 2000; i++) {
  363. if (readl(&reg->outbound_intstatus) &
  364. ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
  365. writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT,
  366. &reg->outbound_intstatus);
  367. return true;
  368. }
  369. msleep(10);
  370. } /* max 20 seconds */
  371. return false;
  372. }
  373. static uint8_t arcmsr_hbaB_wait_msgint_ready(struct AdapterControlBlock *acb)
  374. {
  375. struct MessageUnit_B *reg = acb->pmuB;
  376. int i;
  377. for (i = 0; i < 2000; i++) {
  378. if (readl(reg->iop2drv_doorbell)
  379. & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
  380. writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN,
  381. reg->iop2drv_doorbell);
  382. writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT,
  383. reg->drv2iop_doorbell);
  384. return true;
  385. }
  386. msleep(10);
  387. } /* max 20 seconds */
  388. return false;
  389. }
  390. static uint8_t arcmsr_hbaC_wait_msgint_ready(struct AdapterControlBlock *pACB)
  391. {
  392. struct MessageUnit_C __iomem *phbcmu = pACB->pmuC;
  393. int i;
  394. for (i = 0; i < 2000; i++) {
  395. if (readl(&phbcmu->outbound_doorbell)
  396. & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
  397. writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR,
  398. &phbcmu->outbound_doorbell_clear); /*clear interrupt*/
  399. return true;
  400. }
  401. msleep(10);
  402. } /* max 20 seconds */
  403. return false;
  404. }
  405. static bool arcmsr_hbaD_wait_msgint_ready(struct AdapterControlBlock *pACB)
  406. {
  407. struct MessageUnit_D *reg = pACB->pmuD;
  408. int i;
  409. for (i = 0; i < 2000; i++) {
  410. if (readl(reg->outbound_doorbell)
  411. & ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE) {
  412. writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE,
  413. reg->outbound_doorbell);
  414. return true;
  415. }
  416. msleep(10);
  417. } /* max 20 seconds */
  418. return false;
  419. }
  420. static bool arcmsr_hbaE_wait_msgint_ready(struct AdapterControlBlock *pACB)
  421. {
  422. int i;
  423. uint32_t read_doorbell;
  424. struct MessageUnit_E __iomem *phbcmu = pACB->pmuE;
  425. for (i = 0; i < 2000; i++) {
  426. read_doorbell = readl(&phbcmu->iobound_doorbell);
  427. if ((read_doorbell ^ pACB->in_doorbell) & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) {
  428. writel(0, &phbcmu->host_int_status); /*clear interrupt*/
  429. pACB->in_doorbell = read_doorbell;
  430. return true;
  431. }
  432. msleep(10);
  433. } /* max 20 seconds */
  434. return false;
  435. }
  436. static void arcmsr_hbaA_flush_cache(struct AdapterControlBlock *acb)
  437. {
  438. struct MessageUnit_A __iomem *reg = acb->pmuA;
  439. int retry_count = 30;
  440. writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, &reg->inbound_msgaddr0);
  441. do {
  442. if (arcmsr_hbaA_wait_msgint_ready(acb))
  443. break;
  444. else {
  445. retry_count--;
  446. printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
  447. timeout, retry count down = %d \n", acb->host->host_no, retry_count);
  448. }
  449. } while (retry_count != 0);
  450. }
  451. static void arcmsr_hbaB_flush_cache(struct AdapterControlBlock *acb)
  452. {
  453. struct MessageUnit_B *reg = acb->pmuB;
  454. int retry_count = 30;
  455. writel(ARCMSR_MESSAGE_FLUSH_CACHE, reg->drv2iop_doorbell);
  456. do {
  457. if (arcmsr_hbaB_wait_msgint_ready(acb))
  458. break;
  459. else {
  460. retry_count--;
  461. printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
  462. timeout,retry count down = %d \n", acb->host->host_no, retry_count);
  463. }
  464. } while (retry_count != 0);
  465. }
  466. static void arcmsr_hbaC_flush_cache(struct AdapterControlBlock *pACB)
  467. {
  468. struct MessageUnit_C __iomem *reg = pACB->pmuC;
  469. int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
  470. writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, &reg->inbound_msgaddr0);
  471. writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
  472. do {
  473. if (arcmsr_hbaC_wait_msgint_ready(pACB)) {
  474. break;
  475. } else {
  476. retry_count--;
  477. printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
  478. timeout,retry count down = %d \n", pACB->host->host_no, retry_count);
  479. }
  480. } while (retry_count != 0);
  481. return;
  482. }
  483. static void arcmsr_hbaD_flush_cache(struct AdapterControlBlock *pACB)
  484. {
  485. int retry_count = 15;
  486. struct MessageUnit_D *reg = pACB->pmuD;
  487. writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, reg->inbound_msgaddr0);
  488. do {
  489. if (arcmsr_hbaD_wait_msgint_ready(pACB))
  490. break;
  491. retry_count--;
  492. pr_notice("arcmsr%d: wait 'flush adapter "
  493. "cache' timeout, retry count down = %d\n",
  494. pACB->host->host_no, retry_count);
  495. } while (retry_count != 0);
  496. }
  497. static void arcmsr_hbaE_flush_cache(struct AdapterControlBlock *pACB)
  498. {
  499. int retry_count = 30;
  500. struct MessageUnit_E __iomem *reg = pACB->pmuE;
  501. writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, &reg->inbound_msgaddr0);
  502. pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
  503. writel(pACB->out_doorbell, &reg->iobound_doorbell);
  504. do {
  505. if (arcmsr_hbaE_wait_msgint_ready(pACB))
  506. break;
  507. retry_count--;
  508. pr_notice("arcmsr%d: wait 'flush adapter "
  509. "cache' timeout, retry count down = %d\n",
  510. pACB->host->host_no, retry_count);
  511. } while (retry_count != 0);
  512. }
  513. static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb)
  514. {
  515. switch (acb->adapter_type) {
  516. case ACB_ADAPTER_TYPE_A: {
  517. arcmsr_hbaA_flush_cache(acb);
  518. }
  519. break;
  520. case ACB_ADAPTER_TYPE_B: {
  521. arcmsr_hbaB_flush_cache(acb);
  522. }
  523. break;
  524. case ACB_ADAPTER_TYPE_C: {
  525. arcmsr_hbaC_flush_cache(acb);
  526. }
  527. break;
  528. case ACB_ADAPTER_TYPE_D:
  529. arcmsr_hbaD_flush_cache(acb);
  530. break;
  531. case ACB_ADAPTER_TYPE_E:
  532. arcmsr_hbaE_flush_cache(acb);
  533. break;
  534. }
  535. }
  536. static bool arcmsr_alloc_io_queue(struct AdapterControlBlock *acb)
  537. {
  538. bool rtn = true;
  539. void *dma_coherent;
  540. dma_addr_t dma_coherent_handle;
  541. struct pci_dev *pdev = acb->pdev;
  542. switch (acb->adapter_type) {
  543. case ACB_ADAPTER_TYPE_B: {
  544. struct MessageUnit_B *reg;
  545. acb->roundup_ccbsize = roundup(sizeof(struct MessageUnit_B), 32);
  546. dma_coherent = dma_zalloc_coherent(&pdev->dev, acb->roundup_ccbsize,
  547. &dma_coherent_handle, GFP_KERNEL);
  548. if (!dma_coherent) {
  549. pr_notice("arcmsr%d: DMA allocation failed\n", acb->host->host_no);
  550. return false;
  551. }
  552. acb->dma_coherent_handle2 = dma_coherent_handle;
  553. acb->dma_coherent2 = dma_coherent;
  554. reg = (struct MessageUnit_B *)dma_coherent;
  555. acb->pmuB = reg;
  556. if (acb->pdev->device == PCI_DEVICE_ID_ARECA_1203) {
  557. reg->drv2iop_doorbell = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL_1203);
  558. reg->drv2iop_doorbell_mask = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL_MASK_1203);
  559. reg->iop2drv_doorbell = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL_1203);
  560. reg->iop2drv_doorbell_mask = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL_MASK_1203);
  561. } else {
  562. reg->drv2iop_doorbell = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL);
  563. reg->drv2iop_doorbell_mask = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL_MASK);
  564. reg->iop2drv_doorbell = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL);
  565. reg->iop2drv_doorbell_mask = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL_MASK);
  566. }
  567. reg->message_wbuffer = MEM_BASE1(ARCMSR_MESSAGE_WBUFFER);
  568. reg->message_rbuffer = MEM_BASE1(ARCMSR_MESSAGE_RBUFFER);
  569. reg->message_rwbuffer = MEM_BASE1(ARCMSR_MESSAGE_RWBUFFER);
  570. }
  571. break;
  572. case ACB_ADAPTER_TYPE_D: {
  573. struct MessageUnit_D *reg;
  574. acb->roundup_ccbsize = roundup(sizeof(struct MessageUnit_D), 32);
  575. dma_coherent = dma_zalloc_coherent(&pdev->dev, acb->roundup_ccbsize,
  576. &dma_coherent_handle, GFP_KERNEL);
  577. if (!dma_coherent) {
  578. pr_notice("arcmsr%d: DMA allocation failed\n", acb->host->host_no);
  579. return false;
  580. }
  581. acb->dma_coherent_handle2 = dma_coherent_handle;
  582. acb->dma_coherent2 = dma_coherent;
  583. reg = (struct MessageUnit_D *)dma_coherent;
  584. acb->pmuD = reg;
  585. reg->chip_id = MEM_BASE0(ARCMSR_ARC1214_CHIP_ID);
  586. reg->cpu_mem_config = MEM_BASE0(ARCMSR_ARC1214_CPU_MEMORY_CONFIGURATION);
  587. reg->i2o_host_interrupt_mask = MEM_BASE0(ARCMSR_ARC1214_I2_HOST_INTERRUPT_MASK);
  588. reg->sample_at_reset = MEM_BASE0(ARCMSR_ARC1214_SAMPLE_RESET);
  589. reg->reset_request = MEM_BASE0(ARCMSR_ARC1214_RESET_REQUEST);
  590. reg->host_int_status = MEM_BASE0(ARCMSR_ARC1214_MAIN_INTERRUPT_STATUS);
  591. reg->pcief0_int_enable = MEM_BASE0(ARCMSR_ARC1214_PCIE_F0_INTERRUPT_ENABLE);
  592. reg->inbound_msgaddr0 = MEM_BASE0(ARCMSR_ARC1214_INBOUND_MESSAGE0);
  593. reg->inbound_msgaddr1 = MEM_BASE0(ARCMSR_ARC1214_INBOUND_MESSAGE1);
  594. reg->outbound_msgaddr0 = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_MESSAGE0);
  595. reg->outbound_msgaddr1 = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_MESSAGE1);
  596. reg->inbound_doorbell = MEM_BASE0(ARCMSR_ARC1214_INBOUND_DOORBELL);
  597. reg->outbound_doorbell = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_DOORBELL);
  598. reg->outbound_doorbell_enable = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_DOORBELL_ENABLE);
  599. reg->inboundlist_base_low = MEM_BASE0(ARCMSR_ARC1214_INBOUND_LIST_BASE_LOW);
  600. reg->inboundlist_base_high = MEM_BASE0(ARCMSR_ARC1214_INBOUND_LIST_BASE_HIGH);
  601. reg->inboundlist_write_pointer = MEM_BASE0(ARCMSR_ARC1214_INBOUND_LIST_WRITE_POINTER);
  602. reg->outboundlist_base_low = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_BASE_LOW);
  603. reg->outboundlist_base_high = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_BASE_HIGH);
  604. reg->outboundlist_copy_pointer = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_COPY_POINTER);
  605. reg->outboundlist_read_pointer = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_READ_POINTER);
  606. reg->outboundlist_interrupt_cause = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_INTERRUPT_CAUSE);
  607. reg->outboundlist_interrupt_enable = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_INTERRUPT_ENABLE);
  608. reg->message_wbuffer = MEM_BASE0(ARCMSR_ARC1214_MESSAGE_WBUFFER);
  609. reg->message_rbuffer = MEM_BASE0(ARCMSR_ARC1214_MESSAGE_RBUFFER);
  610. reg->msgcode_rwbuffer = MEM_BASE0(ARCMSR_ARC1214_MESSAGE_RWBUFFER);
  611. }
  612. break;
  613. case ACB_ADAPTER_TYPE_E: {
  614. uint32_t completeQ_size;
  615. completeQ_size = sizeof(struct deliver_completeQ) * ARCMSR_MAX_HBE_DONEQUEUE + 128;
  616. acb->roundup_ccbsize = roundup(completeQ_size, 32);
  617. dma_coherent = dma_zalloc_coherent(&pdev->dev, acb->roundup_ccbsize,
  618. &dma_coherent_handle, GFP_KERNEL);
  619. if (!dma_coherent){
  620. pr_notice("arcmsr%d: DMA allocation failed\n", acb->host->host_no);
  621. return false;
  622. }
  623. acb->dma_coherent_handle2 = dma_coherent_handle;
  624. acb->dma_coherent2 = dma_coherent;
  625. acb->pCompletionQ = dma_coherent;
  626. acb->completionQ_entry = acb->roundup_ccbsize / sizeof(struct deliver_completeQ);
  627. acb->doneq_index = 0;
  628. }
  629. break;
  630. default:
  631. break;
  632. }
  633. return rtn;
  634. }
  635. static int arcmsr_alloc_ccb_pool(struct AdapterControlBlock *acb)
  636. {
  637. struct pci_dev *pdev = acb->pdev;
  638. void *dma_coherent;
  639. dma_addr_t dma_coherent_handle;
  640. struct CommandControlBlock *ccb_tmp;
  641. int i = 0, j = 0;
  642. dma_addr_t cdb_phyaddr;
  643. unsigned long roundup_ccbsize;
  644. unsigned long max_xfer_len;
  645. unsigned long max_sg_entrys;
  646. uint32_t firm_config_version;
  647. for (i = 0; i < ARCMSR_MAX_TARGETID; i++)
  648. for (j = 0; j < ARCMSR_MAX_TARGETLUN; j++)
  649. acb->devstate[i][j] = ARECA_RAID_GONE;
  650. max_xfer_len = ARCMSR_MAX_XFER_LEN;
  651. max_sg_entrys = ARCMSR_DEFAULT_SG_ENTRIES;
  652. firm_config_version = acb->firm_cfg_version;
  653. if((firm_config_version & 0xFF) >= 3){
  654. max_xfer_len = (ARCMSR_CDB_SG_PAGE_LENGTH << ((firm_config_version >> 8) & 0xFF)) * 1024;/* max 4M byte */
  655. max_sg_entrys = (max_xfer_len/4096);
  656. }
  657. acb->host->max_sectors = max_xfer_len/512;
  658. acb->host->sg_tablesize = max_sg_entrys;
  659. roundup_ccbsize = roundup(sizeof(struct CommandControlBlock) + (max_sg_entrys - 1) * sizeof(struct SG64ENTRY), 32);
  660. acb->uncache_size = roundup_ccbsize * acb->maxFreeCCB;
  661. dma_coherent = dma_alloc_coherent(&pdev->dev, acb->uncache_size, &dma_coherent_handle, GFP_KERNEL);
  662. if(!dma_coherent){
  663. printk(KERN_NOTICE "arcmsr%d: dma_alloc_coherent got error\n", acb->host->host_no);
  664. return -ENOMEM;
  665. }
  666. acb->dma_coherent = dma_coherent;
  667. acb->dma_coherent_handle = dma_coherent_handle;
  668. memset(dma_coherent, 0, acb->uncache_size);
  669. acb->ccbsize = roundup_ccbsize;
  670. ccb_tmp = dma_coherent;
  671. acb->vir2phy_offset = (unsigned long)dma_coherent - (unsigned long)dma_coherent_handle;
  672. for(i = 0; i < acb->maxFreeCCB; i++){
  673. cdb_phyaddr = dma_coherent_handle + offsetof(struct CommandControlBlock, arcmsr_cdb);
  674. switch (acb->adapter_type) {
  675. case ACB_ADAPTER_TYPE_A:
  676. case ACB_ADAPTER_TYPE_B:
  677. ccb_tmp->cdb_phyaddr = cdb_phyaddr >> 5;
  678. break;
  679. case ACB_ADAPTER_TYPE_C:
  680. case ACB_ADAPTER_TYPE_D:
  681. case ACB_ADAPTER_TYPE_E:
  682. ccb_tmp->cdb_phyaddr = cdb_phyaddr;
  683. break;
  684. }
  685. acb->pccb_pool[i] = ccb_tmp;
  686. ccb_tmp->acb = acb;
  687. ccb_tmp->smid = (u32)i << 16;
  688. INIT_LIST_HEAD(&ccb_tmp->list);
  689. list_add_tail(&ccb_tmp->list, &acb->ccb_free_list);
  690. ccb_tmp = (struct CommandControlBlock *)((unsigned long)ccb_tmp + roundup_ccbsize);
  691. dma_coherent_handle = dma_coherent_handle + roundup_ccbsize;
  692. }
  693. return 0;
  694. }
  695. static void arcmsr_message_isr_bh_fn(struct work_struct *work)
  696. {
  697. struct AdapterControlBlock *acb = container_of(work,
  698. struct AdapterControlBlock, arcmsr_do_message_isr_bh);
  699. char *acb_dev_map = (char *)acb->device_map;
  700. uint32_t __iomem *signature = NULL;
  701. char __iomem *devicemap = NULL;
  702. int target, lun;
  703. struct scsi_device *psdev;
  704. char diff, temp;
  705. acb->acb_flags &= ~ACB_F_MSG_GET_CONFIG;
  706. switch (acb->adapter_type) {
  707. case ACB_ADAPTER_TYPE_A: {
  708. struct MessageUnit_A __iomem *reg = acb->pmuA;
  709. signature = (uint32_t __iomem *)(&reg->message_rwbuffer[0]);
  710. devicemap = (char __iomem *)(&reg->message_rwbuffer[21]);
  711. break;
  712. }
  713. case ACB_ADAPTER_TYPE_B: {
  714. struct MessageUnit_B *reg = acb->pmuB;
  715. signature = (uint32_t __iomem *)(&reg->message_rwbuffer[0]);
  716. devicemap = (char __iomem *)(&reg->message_rwbuffer[21]);
  717. break;
  718. }
  719. case ACB_ADAPTER_TYPE_C: {
  720. struct MessageUnit_C __iomem *reg = acb->pmuC;
  721. signature = (uint32_t __iomem *)(&reg->msgcode_rwbuffer[0]);
  722. devicemap = (char __iomem *)(&reg->msgcode_rwbuffer[21]);
  723. break;
  724. }
  725. case ACB_ADAPTER_TYPE_D: {
  726. struct MessageUnit_D *reg = acb->pmuD;
  727. signature = (uint32_t __iomem *)(&reg->msgcode_rwbuffer[0]);
  728. devicemap = (char __iomem *)(&reg->msgcode_rwbuffer[21]);
  729. break;
  730. }
  731. case ACB_ADAPTER_TYPE_E: {
  732. struct MessageUnit_E __iomem *reg = acb->pmuE;
  733. signature = (uint32_t __iomem *)(&reg->msgcode_rwbuffer[0]);
  734. devicemap = (char __iomem *)(&reg->msgcode_rwbuffer[21]);
  735. break;
  736. }
  737. }
  738. atomic_inc(&acb->rq_map_token);
  739. if (readl(signature) != ARCMSR_SIGNATURE_GET_CONFIG)
  740. return;
  741. for (target = 0; target < ARCMSR_MAX_TARGETID - 1;
  742. target++) {
  743. temp = readb(devicemap);
  744. diff = (*acb_dev_map) ^ temp;
  745. if (diff != 0) {
  746. *acb_dev_map = temp;
  747. for (lun = 0; lun < ARCMSR_MAX_TARGETLUN;
  748. lun++) {
  749. if ((diff & 0x01) == 1 &&
  750. (temp & 0x01) == 1) {
  751. scsi_add_device(acb->host,
  752. 0, target, lun);
  753. } else if ((diff & 0x01) == 1
  754. && (temp & 0x01) == 0) {
  755. psdev = scsi_device_lookup(acb->host,
  756. 0, target, lun);
  757. if (psdev != NULL) {
  758. scsi_remove_device(psdev);
  759. scsi_device_put(psdev);
  760. }
  761. }
  762. temp >>= 1;
  763. diff >>= 1;
  764. }
  765. }
  766. devicemap++;
  767. acb_dev_map++;
  768. }
  769. }
  770. static int
  771. arcmsr_request_irq(struct pci_dev *pdev, struct AdapterControlBlock *acb)
  772. {
  773. unsigned long flags;
  774. int nvec, i;
  775. if (msix_enable == 0)
  776. goto msi_int0;
  777. nvec = pci_alloc_irq_vectors(pdev, 1, ARCMST_NUM_MSIX_VECTORS,
  778. PCI_IRQ_MSIX);
  779. if (nvec > 0) {
  780. pr_info("arcmsr%d: msi-x enabled\n", acb->host->host_no);
  781. flags = 0;
  782. } else {
  783. msi_int0:
  784. if (msi_enable == 1) {
  785. nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
  786. if (nvec == 1) {
  787. dev_info(&pdev->dev, "msi enabled\n");
  788. goto msi_int1;
  789. }
  790. }
  791. nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_LEGACY);
  792. if (nvec < 1)
  793. return FAILED;
  794. msi_int1:
  795. flags = IRQF_SHARED;
  796. }
  797. acb->vector_count = nvec;
  798. for (i = 0; i < nvec; i++) {
  799. if (request_irq(pci_irq_vector(pdev, i), arcmsr_do_interrupt,
  800. flags, "arcmsr", acb)) {
  801. pr_warn("arcmsr%d: request_irq =%d failed!\n",
  802. acb->host->host_no, pci_irq_vector(pdev, i));
  803. goto out_free_irq;
  804. }
  805. }
  806. return SUCCESS;
  807. out_free_irq:
  808. while (--i >= 0)
  809. free_irq(pci_irq_vector(pdev, i), acb);
  810. pci_free_irq_vectors(pdev);
  811. return FAILED;
  812. }
  813. static void arcmsr_init_get_devmap_timer(struct AdapterControlBlock *pacb)
  814. {
  815. INIT_WORK(&pacb->arcmsr_do_message_isr_bh, arcmsr_message_isr_bh_fn);
  816. atomic_set(&pacb->rq_map_token, 16);
  817. atomic_set(&pacb->ante_token_value, 16);
  818. pacb->fw_flag = FW_NORMAL;
  819. timer_setup(&pacb->eternal_timer, arcmsr_request_device_map, 0);
  820. pacb->eternal_timer.expires = jiffies + msecs_to_jiffies(6 * HZ);
  821. add_timer(&pacb->eternal_timer);
  822. }
  823. static void arcmsr_init_set_datetime_timer(struct AdapterControlBlock *pacb)
  824. {
  825. timer_setup(&pacb->refresh_timer, arcmsr_set_iop_datetime, 0);
  826. pacb->refresh_timer.expires = jiffies + msecs_to_jiffies(60 * 1000);
  827. add_timer(&pacb->refresh_timer);
  828. }
  829. static int arcmsr_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  830. {
  831. struct Scsi_Host *host;
  832. struct AdapterControlBlock *acb;
  833. uint8_t bus,dev_fun;
  834. int error;
  835. error = pci_enable_device(pdev);
  836. if(error){
  837. return -ENODEV;
  838. }
  839. host = scsi_host_alloc(&arcmsr_scsi_host_template, sizeof(struct AdapterControlBlock));
  840. if(!host){
  841. goto pci_disable_dev;
  842. }
  843. error = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
  844. if(error){
  845. error = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  846. if(error){
  847. printk(KERN_WARNING
  848. "scsi%d: No suitable DMA mask available\n",
  849. host->host_no);
  850. goto scsi_host_release;
  851. }
  852. }
  853. init_waitqueue_head(&wait_q);
  854. bus = pdev->bus->number;
  855. dev_fun = pdev->devfn;
  856. acb = (struct AdapterControlBlock *) host->hostdata;
  857. memset(acb,0,sizeof(struct AdapterControlBlock));
  858. acb->pdev = pdev;
  859. acb->host = host;
  860. host->max_lun = ARCMSR_MAX_TARGETLUN;
  861. host->max_id = ARCMSR_MAX_TARGETID; /*16:8*/
  862. host->max_cmd_len = 16; /*this is issue of 64bit LBA ,over 2T byte*/
  863. if ((host_can_queue < ARCMSR_MIN_OUTSTANDING_CMD) || (host_can_queue > ARCMSR_MAX_OUTSTANDING_CMD))
  864. host_can_queue = ARCMSR_DEFAULT_OUTSTANDING_CMD;
  865. host->can_queue = host_can_queue; /* max simultaneous cmds */
  866. if ((cmd_per_lun < ARCMSR_MIN_CMD_PERLUN) || (cmd_per_lun > ARCMSR_MAX_CMD_PERLUN))
  867. cmd_per_lun = ARCMSR_DEFAULT_CMD_PERLUN;
  868. host->cmd_per_lun = cmd_per_lun;
  869. host->this_id = ARCMSR_SCSI_INITIATOR_ID;
  870. host->unique_id = (bus << 8) | dev_fun;
  871. pci_set_drvdata(pdev, host);
  872. pci_set_master(pdev);
  873. error = pci_request_regions(pdev, "arcmsr");
  874. if(error){
  875. goto scsi_host_release;
  876. }
  877. spin_lock_init(&acb->eh_lock);
  878. spin_lock_init(&acb->ccblist_lock);
  879. spin_lock_init(&acb->postq_lock);
  880. spin_lock_init(&acb->doneq_lock);
  881. spin_lock_init(&acb->rqbuffer_lock);
  882. spin_lock_init(&acb->wqbuffer_lock);
  883. acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED |
  884. ACB_F_MESSAGE_RQBUFFER_CLEARED |
  885. ACB_F_MESSAGE_WQBUFFER_READED);
  886. acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER;
  887. INIT_LIST_HEAD(&acb->ccb_free_list);
  888. acb->adapter_type = id->driver_data;
  889. error = arcmsr_remap_pciregion(acb);
  890. if(!error){
  891. goto pci_release_regs;
  892. }
  893. error = arcmsr_alloc_io_queue(acb);
  894. if (!error)
  895. goto unmap_pci_region;
  896. error = arcmsr_get_firmware_spec(acb);
  897. if(!error){
  898. goto free_hbb_mu;
  899. }
  900. error = arcmsr_alloc_ccb_pool(acb);
  901. if(error){
  902. goto free_hbb_mu;
  903. }
  904. error = scsi_add_host(host, &pdev->dev);
  905. if(error){
  906. goto free_ccb_pool;
  907. }
  908. if (arcmsr_request_irq(pdev, acb) == FAILED)
  909. goto scsi_host_remove;
  910. arcmsr_iop_init(acb);
  911. arcmsr_init_get_devmap_timer(acb);
  912. if (set_date_time)
  913. arcmsr_init_set_datetime_timer(acb);
  914. if(arcmsr_alloc_sysfs_attr(acb))
  915. goto out_free_sysfs;
  916. scsi_scan_host(host);
  917. return 0;
  918. out_free_sysfs:
  919. if (set_date_time)
  920. del_timer_sync(&acb->refresh_timer);
  921. del_timer_sync(&acb->eternal_timer);
  922. flush_work(&acb->arcmsr_do_message_isr_bh);
  923. arcmsr_stop_adapter_bgrb(acb);
  924. arcmsr_flush_adapter_cache(acb);
  925. arcmsr_free_irq(pdev, acb);
  926. scsi_host_remove:
  927. scsi_remove_host(host);
  928. free_ccb_pool:
  929. arcmsr_free_ccb_pool(acb);
  930. free_hbb_mu:
  931. arcmsr_free_mu(acb);
  932. unmap_pci_region:
  933. arcmsr_unmap_pciregion(acb);
  934. pci_release_regs:
  935. pci_release_regions(pdev);
  936. scsi_host_release:
  937. scsi_host_put(host);
  938. pci_disable_dev:
  939. pci_disable_device(pdev);
  940. return -ENODEV;
  941. }
  942. static void arcmsr_free_irq(struct pci_dev *pdev,
  943. struct AdapterControlBlock *acb)
  944. {
  945. int i;
  946. for (i = 0; i < acb->vector_count; i++)
  947. free_irq(pci_irq_vector(pdev, i), acb);
  948. pci_free_irq_vectors(pdev);
  949. }
  950. static int arcmsr_suspend(struct pci_dev *pdev, pm_message_t state)
  951. {
  952. uint32_t intmask_org;
  953. struct Scsi_Host *host = pci_get_drvdata(pdev);
  954. struct AdapterControlBlock *acb =
  955. (struct AdapterControlBlock *)host->hostdata;
  956. intmask_org = arcmsr_disable_outbound_ints(acb);
  957. arcmsr_free_irq(pdev, acb);
  958. del_timer_sync(&acb->eternal_timer);
  959. if (set_date_time)
  960. del_timer_sync(&acb->refresh_timer);
  961. flush_work(&acb->arcmsr_do_message_isr_bh);
  962. arcmsr_stop_adapter_bgrb(acb);
  963. arcmsr_flush_adapter_cache(acb);
  964. pci_set_drvdata(pdev, host);
  965. pci_save_state(pdev);
  966. pci_disable_device(pdev);
  967. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  968. return 0;
  969. }
  970. static int arcmsr_resume(struct pci_dev *pdev)
  971. {
  972. int error;
  973. struct Scsi_Host *host = pci_get_drvdata(pdev);
  974. struct AdapterControlBlock *acb =
  975. (struct AdapterControlBlock *)host->hostdata;
  976. pci_set_power_state(pdev, PCI_D0);
  977. pci_enable_wake(pdev, PCI_D0, 0);
  978. pci_restore_state(pdev);
  979. if (pci_enable_device(pdev)) {
  980. pr_warn("%s: pci_enable_device error\n", __func__);
  981. return -ENODEV;
  982. }
  983. error = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
  984. if (error) {
  985. error = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  986. if (error) {
  987. pr_warn("scsi%d: No suitable DMA mask available\n",
  988. host->host_no);
  989. goto controller_unregister;
  990. }
  991. }
  992. pci_set_master(pdev);
  993. if (arcmsr_request_irq(pdev, acb) == FAILED)
  994. goto controller_stop;
  995. if (acb->adapter_type == ACB_ADAPTER_TYPE_E) {
  996. writel(0, &acb->pmuE->host_int_status);
  997. writel(ARCMSR_HBEMU_DOORBELL_SYNC, &acb->pmuE->iobound_doorbell);
  998. acb->in_doorbell = 0;
  999. acb->out_doorbell = 0;
  1000. acb->doneq_index = 0;
  1001. }
  1002. arcmsr_iop_init(acb);
  1003. arcmsr_init_get_devmap_timer(acb);
  1004. if (set_date_time)
  1005. arcmsr_init_set_datetime_timer(acb);
  1006. return 0;
  1007. controller_stop:
  1008. arcmsr_stop_adapter_bgrb(acb);
  1009. arcmsr_flush_adapter_cache(acb);
  1010. controller_unregister:
  1011. scsi_remove_host(host);
  1012. arcmsr_free_ccb_pool(acb);
  1013. arcmsr_unmap_pciregion(acb);
  1014. pci_release_regions(pdev);
  1015. scsi_host_put(host);
  1016. pci_disable_device(pdev);
  1017. return -ENODEV;
  1018. }
  1019. static uint8_t arcmsr_hbaA_abort_allcmd(struct AdapterControlBlock *acb)
  1020. {
  1021. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1022. writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, &reg->inbound_msgaddr0);
  1023. if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
  1024. printk(KERN_NOTICE
  1025. "arcmsr%d: wait 'abort all outstanding command' timeout\n"
  1026. , acb->host->host_no);
  1027. return false;
  1028. }
  1029. return true;
  1030. }
  1031. static uint8_t arcmsr_hbaB_abort_allcmd(struct AdapterControlBlock *acb)
  1032. {
  1033. struct MessageUnit_B *reg = acb->pmuB;
  1034. writel(ARCMSR_MESSAGE_ABORT_CMD, reg->drv2iop_doorbell);
  1035. if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
  1036. printk(KERN_NOTICE
  1037. "arcmsr%d: wait 'abort all outstanding command' timeout\n"
  1038. , acb->host->host_no);
  1039. return false;
  1040. }
  1041. return true;
  1042. }
  1043. static uint8_t arcmsr_hbaC_abort_allcmd(struct AdapterControlBlock *pACB)
  1044. {
  1045. struct MessageUnit_C __iomem *reg = pACB->pmuC;
  1046. writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, &reg->inbound_msgaddr0);
  1047. writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
  1048. if (!arcmsr_hbaC_wait_msgint_ready(pACB)) {
  1049. printk(KERN_NOTICE
  1050. "arcmsr%d: wait 'abort all outstanding command' timeout\n"
  1051. , pACB->host->host_no);
  1052. return false;
  1053. }
  1054. return true;
  1055. }
  1056. static uint8_t arcmsr_hbaD_abort_allcmd(struct AdapterControlBlock *pACB)
  1057. {
  1058. struct MessageUnit_D *reg = pACB->pmuD;
  1059. writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, reg->inbound_msgaddr0);
  1060. if (!arcmsr_hbaD_wait_msgint_ready(pACB)) {
  1061. pr_notice("arcmsr%d: wait 'abort all outstanding "
  1062. "command' timeout\n", pACB->host->host_no);
  1063. return false;
  1064. }
  1065. return true;
  1066. }
  1067. static uint8_t arcmsr_hbaE_abort_allcmd(struct AdapterControlBlock *pACB)
  1068. {
  1069. struct MessageUnit_E __iomem *reg = pACB->pmuE;
  1070. writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, &reg->inbound_msgaddr0);
  1071. pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
  1072. writel(pACB->out_doorbell, &reg->iobound_doorbell);
  1073. if (!arcmsr_hbaE_wait_msgint_ready(pACB)) {
  1074. pr_notice("arcmsr%d: wait 'abort all outstanding "
  1075. "command' timeout\n", pACB->host->host_no);
  1076. return false;
  1077. }
  1078. return true;
  1079. }
  1080. static uint8_t arcmsr_abort_allcmd(struct AdapterControlBlock *acb)
  1081. {
  1082. uint8_t rtnval = 0;
  1083. switch (acb->adapter_type) {
  1084. case ACB_ADAPTER_TYPE_A: {
  1085. rtnval = arcmsr_hbaA_abort_allcmd(acb);
  1086. }
  1087. break;
  1088. case ACB_ADAPTER_TYPE_B: {
  1089. rtnval = arcmsr_hbaB_abort_allcmd(acb);
  1090. }
  1091. break;
  1092. case ACB_ADAPTER_TYPE_C: {
  1093. rtnval = arcmsr_hbaC_abort_allcmd(acb);
  1094. }
  1095. break;
  1096. case ACB_ADAPTER_TYPE_D:
  1097. rtnval = arcmsr_hbaD_abort_allcmd(acb);
  1098. break;
  1099. case ACB_ADAPTER_TYPE_E:
  1100. rtnval = arcmsr_hbaE_abort_allcmd(acb);
  1101. break;
  1102. }
  1103. return rtnval;
  1104. }
  1105. static void arcmsr_pci_unmap_dma(struct CommandControlBlock *ccb)
  1106. {
  1107. struct scsi_cmnd *pcmd = ccb->pcmd;
  1108. scsi_dma_unmap(pcmd);
  1109. }
  1110. static void arcmsr_ccb_complete(struct CommandControlBlock *ccb)
  1111. {
  1112. struct AdapterControlBlock *acb = ccb->acb;
  1113. struct scsi_cmnd *pcmd = ccb->pcmd;
  1114. unsigned long flags;
  1115. atomic_dec(&acb->ccboutstandingcount);
  1116. arcmsr_pci_unmap_dma(ccb);
  1117. ccb->startdone = ARCMSR_CCB_DONE;
  1118. spin_lock_irqsave(&acb->ccblist_lock, flags);
  1119. list_add_tail(&ccb->list, &acb->ccb_free_list);
  1120. spin_unlock_irqrestore(&acb->ccblist_lock, flags);
  1121. pcmd->scsi_done(pcmd);
  1122. }
  1123. static void arcmsr_report_sense_info(struct CommandControlBlock *ccb)
  1124. {
  1125. struct scsi_cmnd *pcmd = ccb->pcmd;
  1126. struct SENSE_DATA *sensebuffer = (struct SENSE_DATA *)pcmd->sense_buffer;
  1127. pcmd->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  1128. if (sensebuffer) {
  1129. int sense_data_length =
  1130. sizeof(struct SENSE_DATA) < SCSI_SENSE_BUFFERSIZE
  1131. ? sizeof(struct SENSE_DATA) : SCSI_SENSE_BUFFERSIZE;
  1132. memset(sensebuffer, 0, SCSI_SENSE_BUFFERSIZE);
  1133. memcpy(sensebuffer, ccb->arcmsr_cdb.SenseData, sense_data_length);
  1134. sensebuffer->ErrorCode = SCSI_SENSE_CURRENT_ERRORS;
  1135. sensebuffer->Valid = 1;
  1136. pcmd->result |= (DRIVER_SENSE << 24);
  1137. }
  1138. }
  1139. static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb)
  1140. {
  1141. u32 orig_mask = 0;
  1142. switch (acb->adapter_type) {
  1143. case ACB_ADAPTER_TYPE_A : {
  1144. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1145. orig_mask = readl(&reg->outbound_intmask);
  1146. writel(orig_mask|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE, \
  1147. &reg->outbound_intmask);
  1148. }
  1149. break;
  1150. case ACB_ADAPTER_TYPE_B : {
  1151. struct MessageUnit_B *reg = acb->pmuB;
  1152. orig_mask = readl(reg->iop2drv_doorbell_mask);
  1153. writel(0, reg->iop2drv_doorbell_mask);
  1154. }
  1155. break;
  1156. case ACB_ADAPTER_TYPE_C:{
  1157. struct MessageUnit_C __iomem *reg = acb->pmuC;
  1158. /* disable all outbound interrupt */
  1159. orig_mask = readl(&reg->host_int_mask); /* disable outbound message0 int */
  1160. writel(orig_mask|ARCMSR_HBCMU_ALL_INTMASKENABLE, &reg->host_int_mask);
  1161. }
  1162. break;
  1163. case ACB_ADAPTER_TYPE_D: {
  1164. struct MessageUnit_D *reg = acb->pmuD;
  1165. /* disable all outbound interrupt */
  1166. writel(ARCMSR_ARC1214_ALL_INT_DISABLE, reg->pcief0_int_enable);
  1167. }
  1168. break;
  1169. case ACB_ADAPTER_TYPE_E: {
  1170. struct MessageUnit_E __iomem *reg = acb->pmuE;
  1171. orig_mask = readl(&reg->host_int_mask);
  1172. writel(orig_mask | ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR | ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR, &reg->host_int_mask);
  1173. readl(&reg->host_int_mask); /* Dummy readl to force pci flush */
  1174. }
  1175. break;
  1176. }
  1177. return orig_mask;
  1178. }
  1179. static void arcmsr_report_ccb_state(struct AdapterControlBlock *acb,
  1180. struct CommandControlBlock *ccb, bool error)
  1181. {
  1182. uint8_t id, lun;
  1183. id = ccb->pcmd->device->id;
  1184. lun = ccb->pcmd->device->lun;
  1185. if (!error) {
  1186. if (acb->devstate[id][lun] == ARECA_RAID_GONE)
  1187. acb->devstate[id][lun] = ARECA_RAID_GOOD;
  1188. ccb->pcmd->result = DID_OK << 16;
  1189. arcmsr_ccb_complete(ccb);
  1190. }else{
  1191. switch (ccb->arcmsr_cdb.DeviceStatus) {
  1192. case ARCMSR_DEV_SELECT_TIMEOUT: {
  1193. acb->devstate[id][lun] = ARECA_RAID_GONE;
  1194. ccb->pcmd->result = DID_NO_CONNECT << 16;
  1195. arcmsr_ccb_complete(ccb);
  1196. }
  1197. break;
  1198. case ARCMSR_DEV_ABORTED:
  1199. case ARCMSR_DEV_INIT_FAIL: {
  1200. acb->devstate[id][lun] = ARECA_RAID_GONE;
  1201. ccb->pcmd->result = DID_BAD_TARGET << 16;
  1202. arcmsr_ccb_complete(ccb);
  1203. }
  1204. break;
  1205. case ARCMSR_DEV_CHECK_CONDITION: {
  1206. acb->devstate[id][lun] = ARECA_RAID_GOOD;
  1207. arcmsr_report_sense_info(ccb);
  1208. arcmsr_ccb_complete(ccb);
  1209. }
  1210. break;
  1211. default:
  1212. printk(KERN_NOTICE
  1213. "arcmsr%d: scsi id = %d lun = %d isr get command error done, \
  1214. but got unknown DeviceStatus = 0x%x \n"
  1215. , acb->host->host_no
  1216. , id
  1217. , lun
  1218. , ccb->arcmsr_cdb.DeviceStatus);
  1219. acb->devstate[id][lun] = ARECA_RAID_GONE;
  1220. ccb->pcmd->result = DID_NO_CONNECT << 16;
  1221. arcmsr_ccb_complete(ccb);
  1222. break;
  1223. }
  1224. }
  1225. }
  1226. static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, struct CommandControlBlock *pCCB, bool error)
  1227. {
  1228. int id, lun;
  1229. if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) {
  1230. if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
  1231. struct scsi_cmnd *abortcmd = pCCB->pcmd;
  1232. if (abortcmd) {
  1233. id = abortcmd->device->id;
  1234. lun = abortcmd->device->lun;
  1235. abortcmd->result |= DID_ABORT << 16;
  1236. arcmsr_ccb_complete(pCCB);
  1237. printk(KERN_NOTICE "arcmsr%d: pCCB ='0x%p' isr got aborted command \n",
  1238. acb->host->host_no, pCCB);
  1239. }
  1240. return;
  1241. }
  1242. printk(KERN_NOTICE "arcmsr%d: isr get an illegal ccb command \
  1243. done acb = '0x%p'"
  1244. "ccb = '0x%p' ccbacb = '0x%p' startdone = 0x%x"
  1245. " ccboutstandingcount = %d \n"
  1246. , acb->host->host_no
  1247. , acb
  1248. , pCCB
  1249. , pCCB->acb
  1250. , pCCB->startdone
  1251. , atomic_read(&acb->ccboutstandingcount));
  1252. return;
  1253. }
  1254. arcmsr_report_ccb_state(acb, pCCB, error);
  1255. }
  1256. static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb)
  1257. {
  1258. int i = 0;
  1259. uint32_t flag_ccb, ccb_cdb_phy;
  1260. struct ARCMSR_CDB *pARCMSR_CDB;
  1261. bool error;
  1262. struct CommandControlBlock *pCCB;
  1263. switch (acb->adapter_type) {
  1264. case ACB_ADAPTER_TYPE_A: {
  1265. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1266. uint32_t outbound_intstatus;
  1267. outbound_intstatus = readl(&reg->outbound_intstatus) &
  1268. acb->outbound_int_enable;
  1269. /*clear and abort all outbound posted Q*/
  1270. writel(outbound_intstatus, &reg->outbound_intstatus);/*clear interrupt*/
  1271. while(((flag_ccb = readl(&reg->outbound_queueport)) != 0xFFFFFFFF)
  1272. && (i++ < acb->maxOutstanding)) {
  1273. pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));/*frame must be 32 bytes aligned*/
  1274. pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
  1275. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
  1276. arcmsr_drain_donequeue(acb, pCCB, error);
  1277. }
  1278. }
  1279. break;
  1280. case ACB_ADAPTER_TYPE_B: {
  1281. struct MessageUnit_B *reg = acb->pmuB;
  1282. /*clear all outbound posted Q*/
  1283. writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell); /* clear doorbell interrupt */
  1284. for (i = 0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) {
  1285. flag_ccb = reg->done_qbuffer[i];
  1286. if (flag_ccb != 0) {
  1287. reg->done_qbuffer[i] = 0;
  1288. pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset+(flag_ccb << 5));/*frame must be 32 bytes aligned*/
  1289. pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
  1290. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
  1291. arcmsr_drain_donequeue(acb, pCCB, error);
  1292. }
  1293. reg->post_qbuffer[i] = 0;
  1294. }
  1295. reg->doneq_index = 0;
  1296. reg->postq_index = 0;
  1297. }
  1298. break;
  1299. case ACB_ADAPTER_TYPE_C: {
  1300. struct MessageUnit_C __iomem *reg = acb->pmuC;
  1301. while ((readl(&reg->host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < acb->maxOutstanding)) {
  1302. /*need to do*/
  1303. flag_ccb = readl(&reg->outbound_queueport_low);
  1304. ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
  1305. pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset+ccb_cdb_phy);/*frame must be 32 bytes aligned*/
  1306. pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
  1307. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
  1308. arcmsr_drain_donequeue(acb, pCCB, error);
  1309. }
  1310. }
  1311. break;
  1312. case ACB_ADAPTER_TYPE_D: {
  1313. struct MessageUnit_D *pmu = acb->pmuD;
  1314. uint32_t outbound_write_pointer;
  1315. uint32_t doneq_index, index_stripped, addressLow, residual, toggle;
  1316. unsigned long flags;
  1317. residual = atomic_read(&acb->ccboutstandingcount);
  1318. for (i = 0; i < residual; i++) {
  1319. spin_lock_irqsave(&acb->doneq_lock, flags);
  1320. outbound_write_pointer =
  1321. pmu->done_qbuffer[0].addressLow + 1;
  1322. doneq_index = pmu->doneq_index;
  1323. if ((doneq_index & 0xFFF) !=
  1324. (outbound_write_pointer & 0xFFF)) {
  1325. toggle = doneq_index & 0x4000;
  1326. index_stripped = (doneq_index & 0xFFF) + 1;
  1327. index_stripped %= ARCMSR_MAX_ARC1214_DONEQUEUE;
  1328. pmu->doneq_index = index_stripped ? (index_stripped | toggle) :
  1329. ((toggle ^ 0x4000) + 1);
  1330. doneq_index = pmu->doneq_index;
  1331. spin_unlock_irqrestore(&acb->doneq_lock, flags);
  1332. addressLow = pmu->done_qbuffer[doneq_index &
  1333. 0xFFF].addressLow;
  1334. ccb_cdb_phy = (addressLow & 0xFFFFFFF0);
  1335. pARCMSR_CDB = (struct ARCMSR_CDB *)
  1336. (acb->vir2phy_offset + ccb_cdb_phy);
  1337. pCCB = container_of(pARCMSR_CDB,
  1338. struct CommandControlBlock, arcmsr_cdb);
  1339. error = (addressLow &
  1340. ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ?
  1341. true : false;
  1342. arcmsr_drain_donequeue(acb, pCCB, error);
  1343. writel(doneq_index,
  1344. pmu->outboundlist_read_pointer);
  1345. } else {
  1346. spin_unlock_irqrestore(&acb->doneq_lock, flags);
  1347. mdelay(10);
  1348. }
  1349. }
  1350. pmu->postq_index = 0;
  1351. pmu->doneq_index = 0x40FF;
  1352. }
  1353. break;
  1354. case ACB_ADAPTER_TYPE_E:
  1355. arcmsr_hbaE_postqueue_isr(acb);
  1356. break;
  1357. }
  1358. }
  1359. static void arcmsr_remove_scsi_devices(struct AdapterControlBlock *acb)
  1360. {
  1361. char *acb_dev_map = (char *)acb->device_map;
  1362. int target, lun, i;
  1363. struct scsi_device *psdev;
  1364. struct CommandControlBlock *ccb;
  1365. char temp;
  1366. for (i = 0; i < acb->maxFreeCCB; i++) {
  1367. ccb = acb->pccb_pool[i];
  1368. if (ccb->startdone == ARCMSR_CCB_START) {
  1369. ccb->pcmd->result = DID_NO_CONNECT << 16;
  1370. arcmsr_pci_unmap_dma(ccb);
  1371. ccb->pcmd->scsi_done(ccb->pcmd);
  1372. }
  1373. }
  1374. for (target = 0; target < ARCMSR_MAX_TARGETID; target++) {
  1375. temp = *acb_dev_map;
  1376. if (temp) {
  1377. for (lun = 0; lun < ARCMSR_MAX_TARGETLUN; lun++) {
  1378. if (temp & 1) {
  1379. psdev = scsi_device_lookup(acb->host,
  1380. 0, target, lun);
  1381. if (psdev != NULL) {
  1382. scsi_remove_device(psdev);
  1383. scsi_device_put(psdev);
  1384. }
  1385. }
  1386. temp >>= 1;
  1387. }
  1388. *acb_dev_map = 0;
  1389. }
  1390. acb_dev_map++;
  1391. }
  1392. }
  1393. static void arcmsr_free_pcidev(struct AdapterControlBlock *acb)
  1394. {
  1395. struct pci_dev *pdev;
  1396. struct Scsi_Host *host;
  1397. host = acb->host;
  1398. arcmsr_free_sysfs_attr(acb);
  1399. scsi_remove_host(host);
  1400. flush_work(&acb->arcmsr_do_message_isr_bh);
  1401. del_timer_sync(&acb->eternal_timer);
  1402. if (set_date_time)
  1403. del_timer_sync(&acb->refresh_timer);
  1404. pdev = acb->pdev;
  1405. arcmsr_free_irq(pdev, acb);
  1406. arcmsr_free_ccb_pool(acb);
  1407. arcmsr_free_mu(acb);
  1408. arcmsr_unmap_pciregion(acb);
  1409. pci_release_regions(pdev);
  1410. scsi_host_put(host);
  1411. pci_disable_device(pdev);
  1412. }
  1413. static void arcmsr_remove(struct pci_dev *pdev)
  1414. {
  1415. struct Scsi_Host *host = pci_get_drvdata(pdev);
  1416. struct AdapterControlBlock *acb =
  1417. (struct AdapterControlBlock *) host->hostdata;
  1418. int poll_count = 0;
  1419. uint16_t dev_id;
  1420. pci_read_config_word(pdev, PCI_DEVICE_ID, &dev_id);
  1421. if (dev_id == 0xffff) {
  1422. acb->acb_flags &= ~ACB_F_IOP_INITED;
  1423. acb->acb_flags |= ACB_F_ADAPTER_REMOVED;
  1424. arcmsr_remove_scsi_devices(acb);
  1425. arcmsr_free_pcidev(acb);
  1426. return;
  1427. }
  1428. arcmsr_free_sysfs_attr(acb);
  1429. scsi_remove_host(host);
  1430. flush_work(&acb->arcmsr_do_message_isr_bh);
  1431. del_timer_sync(&acb->eternal_timer);
  1432. if (set_date_time)
  1433. del_timer_sync(&acb->refresh_timer);
  1434. arcmsr_disable_outbound_ints(acb);
  1435. arcmsr_stop_adapter_bgrb(acb);
  1436. arcmsr_flush_adapter_cache(acb);
  1437. acb->acb_flags |= ACB_F_SCSISTOPADAPTER;
  1438. acb->acb_flags &= ~ACB_F_IOP_INITED;
  1439. for (poll_count = 0; poll_count < acb->maxOutstanding; poll_count++){
  1440. if (!atomic_read(&acb->ccboutstandingcount))
  1441. break;
  1442. arcmsr_interrupt(acb);/* FIXME: need spinlock */
  1443. msleep(25);
  1444. }
  1445. if (atomic_read(&acb->ccboutstandingcount)) {
  1446. int i;
  1447. arcmsr_abort_allcmd(acb);
  1448. arcmsr_done4abort_postqueue(acb);
  1449. for (i = 0; i < acb->maxFreeCCB; i++) {
  1450. struct CommandControlBlock *ccb = acb->pccb_pool[i];
  1451. if (ccb->startdone == ARCMSR_CCB_START) {
  1452. ccb->startdone = ARCMSR_CCB_ABORTED;
  1453. ccb->pcmd->result = DID_ABORT << 16;
  1454. arcmsr_ccb_complete(ccb);
  1455. }
  1456. }
  1457. }
  1458. arcmsr_free_irq(pdev, acb);
  1459. arcmsr_free_ccb_pool(acb);
  1460. arcmsr_free_mu(acb);
  1461. arcmsr_unmap_pciregion(acb);
  1462. pci_release_regions(pdev);
  1463. scsi_host_put(host);
  1464. pci_disable_device(pdev);
  1465. }
  1466. static void arcmsr_shutdown(struct pci_dev *pdev)
  1467. {
  1468. struct Scsi_Host *host = pci_get_drvdata(pdev);
  1469. struct AdapterControlBlock *acb =
  1470. (struct AdapterControlBlock *)host->hostdata;
  1471. if (acb->acb_flags & ACB_F_ADAPTER_REMOVED)
  1472. return;
  1473. del_timer_sync(&acb->eternal_timer);
  1474. if (set_date_time)
  1475. del_timer_sync(&acb->refresh_timer);
  1476. arcmsr_disable_outbound_ints(acb);
  1477. arcmsr_free_irq(pdev, acb);
  1478. flush_work(&acb->arcmsr_do_message_isr_bh);
  1479. arcmsr_stop_adapter_bgrb(acb);
  1480. arcmsr_flush_adapter_cache(acb);
  1481. }
  1482. static int arcmsr_module_init(void)
  1483. {
  1484. int error = 0;
  1485. error = pci_register_driver(&arcmsr_pci_driver);
  1486. return error;
  1487. }
  1488. static void arcmsr_module_exit(void)
  1489. {
  1490. pci_unregister_driver(&arcmsr_pci_driver);
  1491. }
  1492. module_init(arcmsr_module_init);
  1493. module_exit(arcmsr_module_exit);
  1494. static void arcmsr_enable_outbound_ints(struct AdapterControlBlock *acb,
  1495. u32 intmask_org)
  1496. {
  1497. u32 mask;
  1498. switch (acb->adapter_type) {
  1499. case ACB_ADAPTER_TYPE_A: {
  1500. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1501. mask = intmask_org & ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE |
  1502. ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE|
  1503. ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE);
  1504. writel(mask, &reg->outbound_intmask);
  1505. acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff;
  1506. }
  1507. break;
  1508. case ACB_ADAPTER_TYPE_B: {
  1509. struct MessageUnit_B *reg = acb->pmuB;
  1510. mask = intmask_org | (ARCMSR_IOP2DRV_DATA_WRITE_OK |
  1511. ARCMSR_IOP2DRV_DATA_READ_OK |
  1512. ARCMSR_IOP2DRV_CDB_DONE |
  1513. ARCMSR_IOP2DRV_MESSAGE_CMD_DONE);
  1514. writel(mask, reg->iop2drv_doorbell_mask);
  1515. acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f;
  1516. }
  1517. break;
  1518. case ACB_ADAPTER_TYPE_C: {
  1519. struct MessageUnit_C __iomem *reg = acb->pmuC;
  1520. mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK|ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK);
  1521. writel(intmask_org & mask, &reg->host_int_mask);
  1522. acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f;
  1523. }
  1524. break;
  1525. case ACB_ADAPTER_TYPE_D: {
  1526. struct MessageUnit_D *reg = acb->pmuD;
  1527. mask = ARCMSR_ARC1214_ALL_INT_ENABLE;
  1528. writel(intmask_org | mask, reg->pcief0_int_enable);
  1529. break;
  1530. }
  1531. case ACB_ADAPTER_TYPE_E: {
  1532. struct MessageUnit_E __iomem *reg = acb->pmuE;
  1533. mask = ~(ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR | ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR);
  1534. writel(intmask_org & mask, &reg->host_int_mask);
  1535. break;
  1536. }
  1537. }
  1538. }
  1539. static int arcmsr_build_ccb(struct AdapterControlBlock *acb,
  1540. struct CommandControlBlock *ccb, struct scsi_cmnd *pcmd)
  1541. {
  1542. struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb;
  1543. int8_t *psge = (int8_t *)&arcmsr_cdb->u;
  1544. __le32 address_lo, address_hi;
  1545. int arccdbsize = 0x30;
  1546. __le32 length = 0;
  1547. int i;
  1548. struct scatterlist *sg;
  1549. int nseg;
  1550. ccb->pcmd = pcmd;
  1551. memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB));
  1552. arcmsr_cdb->TargetID = pcmd->device->id;
  1553. arcmsr_cdb->LUN = pcmd->device->lun;
  1554. arcmsr_cdb->Function = 1;
  1555. arcmsr_cdb->msgContext = 0;
  1556. memcpy(arcmsr_cdb->Cdb, pcmd->cmnd, pcmd->cmd_len);
  1557. nseg = scsi_dma_map(pcmd);
  1558. if (unlikely(nseg > acb->host->sg_tablesize || nseg < 0))
  1559. return FAILED;
  1560. scsi_for_each_sg(pcmd, sg, nseg, i) {
  1561. /* Get the physical address of the current data pointer */
  1562. length = cpu_to_le32(sg_dma_len(sg));
  1563. address_lo = cpu_to_le32(dma_addr_lo32(sg_dma_address(sg)));
  1564. address_hi = cpu_to_le32(dma_addr_hi32(sg_dma_address(sg)));
  1565. if (address_hi == 0) {
  1566. struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge;
  1567. pdma_sg->address = address_lo;
  1568. pdma_sg->length = length;
  1569. psge += sizeof (struct SG32ENTRY);
  1570. arccdbsize += sizeof (struct SG32ENTRY);
  1571. } else {
  1572. struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge;
  1573. pdma_sg->addresshigh = address_hi;
  1574. pdma_sg->address = address_lo;
  1575. pdma_sg->length = length|cpu_to_le32(IS_SG64_ADDR);
  1576. psge += sizeof (struct SG64ENTRY);
  1577. arccdbsize += sizeof (struct SG64ENTRY);
  1578. }
  1579. }
  1580. arcmsr_cdb->sgcount = (uint8_t)nseg;
  1581. arcmsr_cdb->DataLength = scsi_bufflen(pcmd);
  1582. arcmsr_cdb->msgPages = arccdbsize/0x100 + (arccdbsize % 0x100 ? 1 : 0);
  1583. if ( arccdbsize > 256)
  1584. arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE;
  1585. if (pcmd->sc_data_direction == DMA_TO_DEVICE)
  1586. arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE;
  1587. ccb->arc_cdb_size = arccdbsize;
  1588. return SUCCESS;
  1589. }
  1590. static void arcmsr_post_ccb(struct AdapterControlBlock *acb, struct CommandControlBlock *ccb)
  1591. {
  1592. uint32_t cdb_phyaddr = ccb->cdb_phyaddr;
  1593. struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb;
  1594. atomic_inc(&acb->ccboutstandingcount);
  1595. ccb->startdone = ARCMSR_CCB_START;
  1596. switch (acb->adapter_type) {
  1597. case ACB_ADAPTER_TYPE_A: {
  1598. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1599. if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE)
  1600. writel(cdb_phyaddr | ARCMSR_CCBPOST_FLAG_SGL_BSIZE,
  1601. &reg->inbound_queueport);
  1602. else
  1603. writel(cdb_phyaddr, &reg->inbound_queueport);
  1604. break;
  1605. }
  1606. case ACB_ADAPTER_TYPE_B: {
  1607. struct MessageUnit_B *reg = acb->pmuB;
  1608. uint32_t ending_index, index = reg->postq_index;
  1609. ending_index = ((index + 1) % ARCMSR_MAX_HBB_POSTQUEUE);
  1610. reg->post_qbuffer[ending_index] = 0;
  1611. if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) {
  1612. reg->post_qbuffer[index] =
  1613. cdb_phyaddr | ARCMSR_CCBPOST_FLAG_SGL_BSIZE;
  1614. } else {
  1615. reg->post_qbuffer[index] = cdb_phyaddr;
  1616. }
  1617. index++;
  1618. index %= ARCMSR_MAX_HBB_POSTQUEUE;/*if last index number set it to 0 */
  1619. reg->postq_index = index;
  1620. writel(ARCMSR_DRV2IOP_CDB_POSTED, reg->drv2iop_doorbell);
  1621. }
  1622. break;
  1623. case ACB_ADAPTER_TYPE_C: {
  1624. struct MessageUnit_C __iomem *phbcmu = acb->pmuC;
  1625. uint32_t ccb_post_stamp, arc_cdb_size;
  1626. arc_cdb_size = (ccb->arc_cdb_size > 0x300) ? 0x300 : ccb->arc_cdb_size;
  1627. ccb_post_stamp = (cdb_phyaddr | ((arc_cdb_size - 1) >> 6) | 1);
  1628. if (acb->cdb_phyaddr_hi32) {
  1629. writel(acb->cdb_phyaddr_hi32, &phbcmu->inbound_queueport_high);
  1630. writel(ccb_post_stamp, &phbcmu->inbound_queueport_low);
  1631. } else {
  1632. writel(ccb_post_stamp, &phbcmu->inbound_queueport_low);
  1633. }
  1634. }
  1635. break;
  1636. case ACB_ADAPTER_TYPE_D: {
  1637. struct MessageUnit_D *pmu = acb->pmuD;
  1638. u16 index_stripped;
  1639. u16 postq_index, toggle;
  1640. unsigned long flags;
  1641. struct InBound_SRB *pinbound_srb;
  1642. spin_lock_irqsave(&acb->postq_lock, flags);
  1643. postq_index = pmu->postq_index;
  1644. pinbound_srb = (struct InBound_SRB *)&(pmu->post_qbuffer[postq_index & 0xFF]);
  1645. pinbound_srb->addressHigh = dma_addr_hi32(cdb_phyaddr);
  1646. pinbound_srb->addressLow = dma_addr_lo32(cdb_phyaddr);
  1647. pinbound_srb->length = ccb->arc_cdb_size >> 2;
  1648. arcmsr_cdb->msgContext = dma_addr_lo32(cdb_phyaddr);
  1649. toggle = postq_index & 0x4000;
  1650. index_stripped = postq_index + 1;
  1651. index_stripped &= (ARCMSR_MAX_ARC1214_POSTQUEUE - 1);
  1652. pmu->postq_index = index_stripped ? (index_stripped | toggle) :
  1653. (toggle ^ 0x4000);
  1654. writel(postq_index, pmu->inboundlist_write_pointer);
  1655. spin_unlock_irqrestore(&acb->postq_lock, flags);
  1656. break;
  1657. }
  1658. case ACB_ADAPTER_TYPE_E: {
  1659. struct MessageUnit_E __iomem *pmu = acb->pmuE;
  1660. u32 ccb_post_stamp, arc_cdb_size;
  1661. arc_cdb_size = (ccb->arc_cdb_size > 0x300) ? 0x300 : ccb->arc_cdb_size;
  1662. ccb_post_stamp = (ccb->smid | ((arc_cdb_size - 1) >> 6));
  1663. writel(0, &pmu->inbound_queueport_high);
  1664. writel(ccb_post_stamp, &pmu->inbound_queueport_low);
  1665. break;
  1666. }
  1667. }
  1668. }
  1669. static void arcmsr_hbaA_stop_bgrb(struct AdapterControlBlock *acb)
  1670. {
  1671. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1672. acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
  1673. writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, &reg->inbound_msgaddr0);
  1674. if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
  1675. printk(KERN_NOTICE
  1676. "arcmsr%d: wait 'stop adapter background rebulid' timeout\n"
  1677. , acb->host->host_no);
  1678. }
  1679. }
  1680. static void arcmsr_hbaB_stop_bgrb(struct AdapterControlBlock *acb)
  1681. {
  1682. struct MessageUnit_B *reg = acb->pmuB;
  1683. acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
  1684. writel(ARCMSR_MESSAGE_STOP_BGRB, reg->drv2iop_doorbell);
  1685. if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
  1686. printk(KERN_NOTICE
  1687. "arcmsr%d: wait 'stop adapter background rebulid' timeout\n"
  1688. , acb->host->host_no);
  1689. }
  1690. }
  1691. static void arcmsr_hbaC_stop_bgrb(struct AdapterControlBlock *pACB)
  1692. {
  1693. struct MessageUnit_C __iomem *reg = pACB->pmuC;
  1694. pACB->acb_flags &= ~ACB_F_MSG_START_BGRB;
  1695. writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, &reg->inbound_msgaddr0);
  1696. writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
  1697. if (!arcmsr_hbaC_wait_msgint_ready(pACB)) {
  1698. printk(KERN_NOTICE
  1699. "arcmsr%d: wait 'stop adapter background rebulid' timeout\n"
  1700. , pACB->host->host_no);
  1701. }
  1702. return;
  1703. }
  1704. static void arcmsr_hbaD_stop_bgrb(struct AdapterControlBlock *pACB)
  1705. {
  1706. struct MessageUnit_D *reg = pACB->pmuD;
  1707. pACB->acb_flags &= ~ACB_F_MSG_START_BGRB;
  1708. writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, reg->inbound_msgaddr0);
  1709. if (!arcmsr_hbaD_wait_msgint_ready(pACB))
  1710. pr_notice("arcmsr%d: wait 'stop adapter background rebulid' "
  1711. "timeout\n", pACB->host->host_no);
  1712. }
  1713. static void arcmsr_hbaE_stop_bgrb(struct AdapterControlBlock *pACB)
  1714. {
  1715. struct MessageUnit_E __iomem *reg = pACB->pmuE;
  1716. pACB->acb_flags &= ~ACB_F_MSG_START_BGRB;
  1717. writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, &reg->inbound_msgaddr0);
  1718. pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
  1719. writel(pACB->out_doorbell, &reg->iobound_doorbell);
  1720. if (!arcmsr_hbaE_wait_msgint_ready(pACB)) {
  1721. pr_notice("arcmsr%d: wait 'stop adapter background rebulid' "
  1722. "timeout\n", pACB->host->host_no);
  1723. }
  1724. }
  1725. static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb)
  1726. {
  1727. switch (acb->adapter_type) {
  1728. case ACB_ADAPTER_TYPE_A: {
  1729. arcmsr_hbaA_stop_bgrb(acb);
  1730. }
  1731. break;
  1732. case ACB_ADAPTER_TYPE_B: {
  1733. arcmsr_hbaB_stop_bgrb(acb);
  1734. }
  1735. break;
  1736. case ACB_ADAPTER_TYPE_C: {
  1737. arcmsr_hbaC_stop_bgrb(acb);
  1738. }
  1739. break;
  1740. case ACB_ADAPTER_TYPE_D:
  1741. arcmsr_hbaD_stop_bgrb(acb);
  1742. break;
  1743. case ACB_ADAPTER_TYPE_E:
  1744. arcmsr_hbaE_stop_bgrb(acb);
  1745. break;
  1746. }
  1747. }
  1748. static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb)
  1749. {
  1750. dma_free_coherent(&acb->pdev->dev, acb->uncache_size, acb->dma_coherent, acb->dma_coherent_handle);
  1751. }
  1752. static void arcmsr_iop_message_read(struct AdapterControlBlock *acb)
  1753. {
  1754. switch (acb->adapter_type) {
  1755. case ACB_ADAPTER_TYPE_A: {
  1756. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1757. writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, &reg->inbound_doorbell);
  1758. }
  1759. break;
  1760. case ACB_ADAPTER_TYPE_B: {
  1761. struct MessageUnit_B *reg = acb->pmuB;
  1762. writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell);
  1763. }
  1764. break;
  1765. case ACB_ADAPTER_TYPE_C: {
  1766. struct MessageUnit_C __iomem *reg = acb->pmuC;
  1767. writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, &reg->inbound_doorbell);
  1768. }
  1769. break;
  1770. case ACB_ADAPTER_TYPE_D: {
  1771. struct MessageUnit_D *reg = acb->pmuD;
  1772. writel(ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ,
  1773. reg->inbound_doorbell);
  1774. }
  1775. break;
  1776. case ACB_ADAPTER_TYPE_E: {
  1777. struct MessageUnit_E __iomem *reg = acb->pmuE;
  1778. acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK;
  1779. writel(acb->out_doorbell, &reg->iobound_doorbell);
  1780. }
  1781. break;
  1782. }
  1783. }
  1784. static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb)
  1785. {
  1786. switch (acb->adapter_type) {
  1787. case ACB_ADAPTER_TYPE_A: {
  1788. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1789. /*
  1790. ** push inbound doorbell tell iop, driver data write ok
  1791. ** and wait reply on next hwinterrupt for next Qbuffer post
  1792. */
  1793. writel(ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK, &reg->inbound_doorbell);
  1794. }
  1795. break;
  1796. case ACB_ADAPTER_TYPE_B: {
  1797. struct MessageUnit_B *reg = acb->pmuB;
  1798. /*
  1799. ** push inbound doorbell tell iop, driver data write ok
  1800. ** and wait reply on next hwinterrupt for next Qbuffer post
  1801. */
  1802. writel(ARCMSR_DRV2IOP_DATA_WRITE_OK, reg->drv2iop_doorbell);
  1803. }
  1804. break;
  1805. case ACB_ADAPTER_TYPE_C: {
  1806. struct MessageUnit_C __iomem *reg = acb->pmuC;
  1807. /*
  1808. ** push inbound doorbell tell iop, driver data write ok
  1809. ** and wait reply on next hwinterrupt for next Qbuffer post
  1810. */
  1811. writel(ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK, &reg->inbound_doorbell);
  1812. }
  1813. break;
  1814. case ACB_ADAPTER_TYPE_D: {
  1815. struct MessageUnit_D *reg = acb->pmuD;
  1816. writel(ARCMSR_ARC1214_DRV2IOP_DATA_IN_READY,
  1817. reg->inbound_doorbell);
  1818. }
  1819. break;
  1820. case ACB_ADAPTER_TYPE_E: {
  1821. struct MessageUnit_E __iomem *reg = acb->pmuE;
  1822. acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_WRITE_OK;
  1823. writel(acb->out_doorbell, &reg->iobound_doorbell);
  1824. }
  1825. break;
  1826. }
  1827. }
  1828. struct QBUFFER __iomem *arcmsr_get_iop_rqbuffer(struct AdapterControlBlock *acb)
  1829. {
  1830. struct QBUFFER __iomem *qbuffer = NULL;
  1831. switch (acb->adapter_type) {
  1832. case ACB_ADAPTER_TYPE_A: {
  1833. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1834. qbuffer = (struct QBUFFER __iomem *)&reg->message_rbuffer;
  1835. }
  1836. break;
  1837. case ACB_ADAPTER_TYPE_B: {
  1838. struct MessageUnit_B *reg = acb->pmuB;
  1839. qbuffer = (struct QBUFFER __iomem *)reg->message_rbuffer;
  1840. }
  1841. break;
  1842. case ACB_ADAPTER_TYPE_C: {
  1843. struct MessageUnit_C __iomem *phbcmu = acb->pmuC;
  1844. qbuffer = (struct QBUFFER __iomem *)&phbcmu->message_rbuffer;
  1845. }
  1846. break;
  1847. case ACB_ADAPTER_TYPE_D: {
  1848. struct MessageUnit_D *reg = acb->pmuD;
  1849. qbuffer = (struct QBUFFER __iomem *)reg->message_rbuffer;
  1850. }
  1851. break;
  1852. case ACB_ADAPTER_TYPE_E: {
  1853. struct MessageUnit_E __iomem *reg = acb->pmuE;
  1854. qbuffer = (struct QBUFFER __iomem *)&reg->message_rbuffer;
  1855. }
  1856. break;
  1857. }
  1858. return qbuffer;
  1859. }
  1860. static struct QBUFFER __iomem *arcmsr_get_iop_wqbuffer(struct AdapterControlBlock *acb)
  1861. {
  1862. struct QBUFFER __iomem *pqbuffer = NULL;
  1863. switch (acb->adapter_type) {
  1864. case ACB_ADAPTER_TYPE_A: {
  1865. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1866. pqbuffer = (struct QBUFFER __iomem *) &reg->message_wbuffer;
  1867. }
  1868. break;
  1869. case ACB_ADAPTER_TYPE_B: {
  1870. struct MessageUnit_B *reg = acb->pmuB;
  1871. pqbuffer = (struct QBUFFER __iomem *)reg->message_wbuffer;
  1872. }
  1873. break;
  1874. case ACB_ADAPTER_TYPE_C: {
  1875. struct MessageUnit_C __iomem *reg = acb->pmuC;
  1876. pqbuffer = (struct QBUFFER __iomem *)&reg->message_wbuffer;
  1877. }
  1878. break;
  1879. case ACB_ADAPTER_TYPE_D: {
  1880. struct MessageUnit_D *reg = acb->pmuD;
  1881. pqbuffer = (struct QBUFFER __iomem *)reg->message_wbuffer;
  1882. }
  1883. break;
  1884. case ACB_ADAPTER_TYPE_E: {
  1885. struct MessageUnit_E __iomem *reg = acb->pmuE;
  1886. pqbuffer = (struct QBUFFER __iomem *)&reg->message_wbuffer;
  1887. }
  1888. break;
  1889. }
  1890. return pqbuffer;
  1891. }
  1892. static uint32_t
  1893. arcmsr_Read_iop_rqbuffer_in_DWORD(struct AdapterControlBlock *acb,
  1894. struct QBUFFER __iomem *prbuffer)
  1895. {
  1896. uint8_t *pQbuffer;
  1897. uint8_t *buf1 = NULL;
  1898. uint32_t __iomem *iop_data;
  1899. uint32_t iop_len, data_len, *buf2 = NULL;
  1900. iop_data = (uint32_t __iomem *)prbuffer->data;
  1901. iop_len = readl(&prbuffer->data_len);
  1902. if (iop_len > 0) {
  1903. buf1 = kmalloc(128, GFP_ATOMIC);
  1904. buf2 = (uint32_t *)buf1;
  1905. if (buf1 == NULL)
  1906. return 0;
  1907. data_len = iop_len;
  1908. while (data_len >= 4) {
  1909. *buf2++ = readl(iop_data);
  1910. iop_data++;
  1911. data_len -= 4;
  1912. }
  1913. if (data_len)
  1914. *buf2 = readl(iop_data);
  1915. buf2 = (uint32_t *)buf1;
  1916. }
  1917. while (iop_len > 0) {
  1918. pQbuffer = &acb->rqbuffer[acb->rqbuf_putIndex];
  1919. *pQbuffer = *buf1;
  1920. acb->rqbuf_putIndex++;
  1921. /* if last, index number set it to 0 */
  1922. acb->rqbuf_putIndex %= ARCMSR_MAX_QBUFFER;
  1923. buf1++;
  1924. iop_len--;
  1925. }
  1926. kfree(buf2);
  1927. /* let IOP know data has been read */
  1928. arcmsr_iop_message_read(acb);
  1929. return 1;
  1930. }
  1931. uint32_t
  1932. arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb,
  1933. struct QBUFFER __iomem *prbuffer) {
  1934. uint8_t *pQbuffer;
  1935. uint8_t __iomem *iop_data;
  1936. uint32_t iop_len;
  1937. if (acb->adapter_type > ACB_ADAPTER_TYPE_B)
  1938. return arcmsr_Read_iop_rqbuffer_in_DWORD(acb, prbuffer);
  1939. iop_data = (uint8_t __iomem *)prbuffer->data;
  1940. iop_len = readl(&prbuffer->data_len);
  1941. while (iop_len > 0) {
  1942. pQbuffer = &acb->rqbuffer[acb->rqbuf_putIndex];
  1943. *pQbuffer = readb(iop_data);
  1944. acb->rqbuf_putIndex++;
  1945. acb->rqbuf_putIndex %= ARCMSR_MAX_QBUFFER;
  1946. iop_data++;
  1947. iop_len--;
  1948. }
  1949. arcmsr_iop_message_read(acb);
  1950. return 1;
  1951. }
  1952. static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb)
  1953. {
  1954. unsigned long flags;
  1955. struct QBUFFER __iomem *prbuffer;
  1956. int32_t buf_empty_len;
  1957. spin_lock_irqsave(&acb->rqbuffer_lock, flags);
  1958. prbuffer = arcmsr_get_iop_rqbuffer(acb);
  1959. buf_empty_len = (acb->rqbuf_putIndex - acb->rqbuf_getIndex - 1) &
  1960. (ARCMSR_MAX_QBUFFER - 1);
  1961. if (buf_empty_len >= readl(&prbuffer->data_len)) {
  1962. if (arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
  1963. acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
  1964. } else
  1965. acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
  1966. spin_unlock_irqrestore(&acb->rqbuffer_lock, flags);
  1967. }
  1968. static void arcmsr_write_ioctldata2iop_in_DWORD(struct AdapterControlBlock *acb)
  1969. {
  1970. uint8_t *pQbuffer;
  1971. struct QBUFFER __iomem *pwbuffer;
  1972. uint8_t *buf1 = NULL;
  1973. uint32_t __iomem *iop_data;
  1974. uint32_t allxfer_len = 0, data_len, *buf2 = NULL, data;
  1975. if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READED) {
  1976. buf1 = kmalloc(128, GFP_ATOMIC);
  1977. buf2 = (uint32_t *)buf1;
  1978. if (buf1 == NULL)
  1979. return;
  1980. acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED);
  1981. pwbuffer = arcmsr_get_iop_wqbuffer(acb);
  1982. iop_data = (uint32_t __iomem *)pwbuffer->data;
  1983. while ((acb->wqbuf_getIndex != acb->wqbuf_putIndex)
  1984. && (allxfer_len < 124)) {
  1985. pQbuffer = &acb->wqbuffer[acb->wqbuf_getIndex];
  1986. *buf1 = *pQbuffer;
  1987. acb->wqbuf_getIndex++;
  1988. acb->wqbuf_getIndex %= ARCMSR_MAX_QBUFFER;
  1989. buf1++;
  1990. allxfer_len++;
  1991. }
  1992. data_len = allxfer_len;
  1993. buf1 = (uint8_t *)buf2;
  1994. while (data_len >= 4) {
  1995. data = *buf2++;
  1996. writel(data, iop_data);
  1997. iop_data++;
  1998. data_len -= 4;
  1999. }
  2000. if (data_len) {
  2001. data = *buf2;
  2002. writel(data, iop_data);
  2003. }
  2004. writel(allxfer_len, &pwbuffer->data_len);
  2005. kfree(buf1);
  2006. arcmsr_iop_message_wrote(acb);
  2007. }
  2008. }
  2009. void
  2010. arcmsr_write_ioctldata2iop(struct AdapterControlBlock *acb)
  2011. {
  2012. uint8_t *pQbuffer;
  2013. struct QBUFFER __iomem *pwbuffer;
  2014. uint8_t __iomem *iop_data;
  2015. int32_t allxfer_len = 0;
  2016. if (acb->adapter_type > ACB_ADAPTER_TYPE_B) {
  2017. arcmsr_write_ioctldata2iop_in_DWORD(acb);
  2018. return;
  2019. }
  2020. if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READED) {
  2021. acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED);
  2022. pwbuffer = arcmsr_get_iop_wqbuffer(acb);
  2023. iop_data = (uint8_t __iomem *)pwbuffer->data;
  2024. while ((acb->wqbuf_getIndex != acb->wqbuf_putIndex)
  2025. && (allxfer_len < 124)) {
  2026. pQbuffer = &acb->wqbuffer[acb->wqbuf_getIndex];
  2027. writeb(*pQbuffer, iop_data);
  2028. acb->wqbuf_getIndex++;
  2029. acb->wqbuf_getIndex %= ARCMSR_MAX_QBUFFER;
  2030. iop_data++;
  2031. allxfer_len++;
  2032. }
  2033. writel(allxfer_len, &pwbuffer->data_len);
  2034. arcmsr_iop_message_wrote(acb);
  2035. }
  2036. }
  2037. static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb)
  2038. {
  2039. unsigned long flags;
  2040. spin_lock_irqsave(&acb->wqbuffer_lock, flags);
  2041. acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READED;
  2042. if (acb->wqbuf_getIndex != acb->wqbuf_putIndex)
  2043. arcmsr_write_ioctldata2iop(acb);
  2044. if (acb->wqbuf_getIndex == acb->wqbuf_putIndex)
  2045. acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED;
  2046. spin_unlock_irqrestore(&acb->wqbuffer_lock, flags);
  2047. }
  2048. static void arcmsr_hbaA_doorbell_isr(struct AdapterControlBlock *acb)
  2049. {
  2050. uint32_t outbound_doorbell;
  2051. struct MessageUnit_A __iomem *reg = acb->pmuA;
  2052. outbound_doorbell = readl(&reg->outbound_doorbell);
  2053. do {
  2054. writel(outbound_doorbell, &reg->outbound_doorbell);
  2055. if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK)
  2056. arcmsr_iop2drv_data_wrote_handle(acb);
  2057. if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK)
  2058. arcmsr_iop2drv_data_read_handle(acb);
  2059. outbound_doorbell = readl(&reg->outbound_doorbell);
  2060. } while (outbound_doorbell & (ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK
  2061. | ARCMSR_OUTBOUND_IOP331_DATA_READ_OK));
  2062. }
  2063. static void arcmsr_hbaC_doorbell_isr(struct AdapterControlBlock *pACB)
  2064. {
  2065. uint32_t outbound_doorbell;
  2066. struct MessageUnit_C __iomem *reg = pACB->pmuC;
  2067. /*
  2068. *******************************************************************
  2069. ** Maybe here we need to check wrqbuffer_lock is lock or not
  2070. ** DOORBELL: din! don!
  2071. ** check if there are any mail need to pack from firmware
  2072. *******************************************************************
  2073. */
  2074. outbound_doorbell = readl(&reg->outbound_doorbell);
  2075. do {
  2076. writel(outbound_doorbell, &reg->outbound_doorbell_clear);
  2077. readl(&reg->outbound_doorbell_clear);
  2078. if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK)
  2079. arcmsr_iop2drv_data_wrote_handle(pACB);
  2080. if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK)
  2081. arcmsr_iop2drv_data_read_handle(pACB);
  2082. if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE)
  2083. arcmsr_hbaC_message_isr(pACB);
  2084. outbound_doorbell = readl(&reg->outbound_doorbell);
  2085. } while (outbound_doorbell & (ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK
  2086. | ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK
  2087. | ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE));
  2088. }
  2089. static void arcmsr_hbaD_doorbell_isr(struct AdapterControlBlock *pACB)
  2090. {
  2091. uint32_t outbound_doorbell;
  2092. struct MessageUnit_D *pmu = pACB->pmuD;
  2093. outbound_doorbell = readl(pmu->outbound_doorbell);
  2094. do {
  2095. writel(outbound_doorbell, pmu->outbound_doorbell);
  2096. if (outbound_doorbell & ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE)
  2097. arcmsr_hbaD_message_isr(pACB);
  2098. if (outbound_doorbell & ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK)
  2099. arcmsr_iop2drv_data_wrote_handle(pACB);
  2100. if (outbound_doorbell & ARCMSR_ARC1214_IOP2DRV_DATA_READ_OK)
  2101. arcmsr_iop2drv_data_read_handle(pACB);
  2102. outbound_doorbell = readl(pmu->outbound_doorbell);
  2103. } while (outbound_doorbell & (ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK
  2104. | ARCMSR_ARC1214_IOP2DRV_DATA_READ_OK
  2105. | ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE));
  2106. }
  2107. static void arcmsr_hbaE_doorbell_isr(struct AdapterControlBlock *pACB)
  2108. {
  2109. uint32_t outbound_doorbell, in_doorbell, tmp;
  2110. struct MessageUnit_E __iomem *reg = pACB->pmuE;
  2111. in_doorbell = readl(&reg->iobound_doorbell);
  2112. outbound_doorbell = in_doorbell ^ pACB->in_doorbell;
  2113. do {
  2114. writel(0, &reg->host_int_status); /* clear interrupt */
  2115. if (outbound_doorbell & ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK) {
  2116. arcmsr_iop2drv_data_wrote_handle(pACB);
  2117. }
  2118. if (outbound_doorbell & ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK) {
  2119. arcmsr_iop2drv_data_read_handle(pACB);
  2120. }
  2121. if (outbound_doorbell & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) {
  2122. arcmsr_hbaE_message_isr(pACB);
  2123. }
  2124. tmp = in_doorbell;
  2125. in_doorbell = readl(&reg->iobound_doorbell);
  2126. outbound_doorbell = tmp ^ in_doorbell;
  2127. } while (outbound_doorbell & (ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK
  2128. | ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK
  2129. | ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE));
  2130. pACB->in_doorbell = in_doorbell;
  2131. }
  2132. static void arcmsr_hbaA_postqueue_isr(struct AdapterControlBlock *acb)
  2133. {
  2134. uint32_t flag_ccb;
  2135. struct MessageUnit_A __iomem *reg = acb->pmuA;
  2136. struct ARCMSR_CDB *pARCMSR_CDB;
  2137. struct CommandControlBlock *pCCB;
  2138. bool error;
  2139. while ((flag_ccb = readl(&reg->outbound_queueport)) != 0xFFFFFFFF) {
  2140. pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));/*frame must be 32 bytes aligned*/
  2141. pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
  2142. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
  2143. arcmsr_drain_donequeue(acb, pCCB, error);
  2144. }
  2145. }
  2146. static void arcmsr_hbaB_postqueue_isr(struct AdapterControlBlock *acb)
  2147. {
  2148. uint32_t index;
  2149. uint32_t flag_ccb;
  2150. struct MessageUnit_B *reg = acb->pmuB;
  2151. struct ARCMSR_CDB *pARCMSR_CDB;
  2152. struct CommandControlBlock *pCCB;
  2153. bool error;
  2154. index = reg->doneq_index;
  2155. while ((flag_ccb = reg->done_qbuffer[index]) != 0) {
  2156. reg->done_qbuffer[index] = 0;
  2157. pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset+(flag_ccb << 5));/*frame must be 32 bytes aligned*/
  2158. pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
  2159. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
  2160. arcmsr_drain_donequeue(acb, pCCB, error);
  2161. index++;
  2162. index %= ARCMSR_MAX_HBB_POSTQUEUE;
  2163. reg->doneq_index = index;
  2164. }
  2165. }
  2166. static void arcmsr_hbaC_postqueue_isr(struct AdapterControlBlock *acb)
  2167. {
  2168. struct MessageUnit_C __iomem *phbcmu;
  2169. struct ARCMSR_CDB *arcmsr_cdb;
  2170. struct CommandControlBlock *ccb;
  2171. uint32_t flag_ccb, ccb_cdb_phy, throttling = 0;
  2172. int error;
  2173. phbcmu = acb->pmuC;
  2174. /* areca cdb command done */
  2175. /* Use correct offset and size for syncing */
  2176. while ((flag_ccb = readl(&phbcmu->outbound_queueport_low)) !=
  2177. 0xFFFFFFFF) {
  2178. ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
  2179. arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset
  2180. + ccb_cdb_phy);
  2181. ccb = container_of(arcmsr_cdb, struct CommandControlBlock,
  2182. arcmsr_cdb);
  2183. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1)
  2184. ? true : false;
  2185. /* check if command done with no error */
  2186. arcmsr_drain_donequeue(acb, ccb, error);
  2187. throttling++;
  2188. if (throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) {
  2189. writel(ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING,
  2190. &phbcmu->inbound_doorbell);
  2191. throttling = 0;
  2192. }
  2193. }
  2194. }
  2195. static void arcmsr_hbaD_postqueue_isr(struct AdapterControlBlock *acb)
  2196. {
  2197. u32 outbound_write_pointer, doneq_index, index_stripped, toggle;
  2198. uint32_t addressLow, ccb_cdb_phy;
  2199. int error;
  2200. struct MessageUnit_D *pmu;
  2201. struct ARCMSR_CDB *arcmsr_cdb;
  2202. struct CommandControlBlock *ccb;
  2203. unsigned long flags;
  2204. spin_lock_irqsave(&acb->doneq_lock, flags);
  2205. pmu = acb->pmuD;
  2206. outbound_write_pointer = pmu->done_qbuffer[0].addressLow + 1;
  2207. doneq_index = pmu->doneq_index;
  2208. if ((doneq_index & 0xFFF) != (outbound_write_pointer & 0xFFF)) {
  2209. do {
  2210. toggle = doneq_index & 0x4000;
  2211. index_stripped = (doneq_index & 0xFFF) + 1;
  2212. index_stripped %= ARCMSR_MAX_ARC1214_DONEQUEUE;
  2213. pmu->doneq_index = index_stripped ? (index_stripped | toggle) :
  2214. ((toggle ^ 0x4000) + 1);
  2215. doneq_index = pmu->doneq_index;
  2216. addressLow = pmu->done_qbuffer[doneq_index &
  2217. 0xFFF].addressLow;
  2218. ccb_cdb_phy = (addressLow & 0xFFFFFFF0);
  2219. arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset
  2220. + ccb_cdb_phy);
  2221. ccb = container_of(arcmsr_cdb,
  2222. struct CommandControlBlock, arcmsr_cdb);
  2223. error = (addressLow & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1)
  2224. ? true : false;
  2225. arcmsr_drain_donequeue(acb, ccb, error);
  2226. writel(doneq_index, pmu->outboundlist_read_pointer);
  2227. } while ((doneq_index & 0xFFF) !=
  2228. (outbound_write_pointer & 0xFFF));
  2229. }
  2230. writel(ARCMSR_ARC1214_OUTBOUND_LIST_INTERRUPT_CLEAR,
  2231. pmu->outboundlist_interrupt_cause);
  2232. readl(pmu->outboundlist_interrupt_cause);
  2233. spin_unlock_irqrestore(&acb->doneq_lock, flags);
  2234. }
  2235. static void arcmsr_hbaE_postqueue_isr(struct AdapterControlBlock *acb)
  2236. {
  2237. uint32_t doneq_index;
  2238. uint16_t cmdSMID;
  2239. int error;
  2240. struct MessageUnit_E __iomem *pmu;
  2241. struct CommandControlBlock *ccb;
  2242. unsigned long flags;
  2243. spin_lock_irqsave(&acb->doneq_lock, flags);
  2244. doneq_index = acb->doneq_index;
  2245. pmu = acb->pmuE;
  2246. while ((readl(&pmu->reply_post_producer_index) & 0xFFFF) != doneq_index) {
  2247. cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID;
  2248. ccb = acb->pccb_pool[cmdSMID];
  2249. error = (acb->pCompletionQ[doneq_index].cmdFlag
  2250. & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
  2251. arcmsr_drain_donequeue(acb, ccb, error);
  2252. doneq_index++;
  2253. if (doneq_index >= acb->completionQ_entry)
  2254. doneq_index = 0;
  2255. }
  2256. acb->doneq_index = doneq_index;
  2257. writel(doneq_index, &pmu->reply_post_consumer_index);
  2258. spin_unlock_irqrestore(&acb->doneq_lock, flags);
  2259. }
  2260. /*
  2261. **********************************************************************************
  2262. ** Handle a message interrupt
  2263. **
  2264. ** The only message interrupt we expect is in response to a query for the current adapter config.
  2265. ** We want this in order to compare the drivemap so that we can detect newly-attached drives.
  2266. **********************************************************************************
  2267. */
  2268. static void arcmsr_hbaA_message_isr(struct AdapterControlBlock *acb)
  2269. {
  2270. struct MessageUnit_A __iomem *reg = acb->pmuA;
  2271. /*clear interrupt and message state*/
  2272. writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT, &reg->outbound_intstatus);
  2273. if (acb->acb_flags & ACB_F_MSG_GET_CONFIG)
  2274. schedule_work(&acb->arcmsr_do_message_isr_bh);
  2275. }
  2276. static void arcmsr_hbaB_message_isr(struct AdapterControlBlock *acb)
  2277. {
  2278. struct MessageUnit_B *reg = acb->pmuB;
  2279. /*clear interrupt and message state*/
  2280. writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
  2281. if (acb->acb_flags & ACB_F_MSG_GET_CONFIG)
  2282. schedule_work(&acb->arcmsr_do_message_isr_bh);
  2283. }
  2284. /*
  2285. **********************************************************************************
  2286. ** Handle a message interrupt
  2287. **
  2288. ** The only message interrupt we expect is in response to a query for the
  2289. ** current adapter config.
  2290. ** We want this in order to compare the drivemap so that we can detect newly-attached drives.
  2291. **********************************************************************************
  2292. */
  2293. static void arcmsr_hbaC_message_isr(struct AdapterControlBlock *acb)
  2294. {
  2295. struct MessageUnit_C __iomem *reg = acb->pmuC;
  2296. /*clear interrupt and message state*/
  2297. writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &reg->outbound_doorbell_clear);
  2298. if (acb->acb_flags & ACB_F_MSG_GET_CONFIG)
  2299. schedule_work(&acb->arcmsr_do_message_isr_bh);
  2300. }
  2301. static void arcmsr_hbaD_message_isr(struct AdapterControlBlock *acb)
  2302. {
  2303. struct MessageUnit_D *reg = acb->pmuD;
  2304. writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE, reg->outbound_doorbell);
  2305. readl(reg->outbound_doorbell);
  2306. if (acb->acb_flags & ACB_F_MSG_GET_CONFIG)
  2307. schedule_work(&acb->arcmsr_do_message_isr_bh);
  2308. }
  2309. static void arcmsr_hbaE_message_isr(struct AdapterControlBlock *acb)
  2310. {
  2311. struct MessageUnit_E __iomem *reg = acb->pmuE;
  2312. writel(0, &reg->host_int_status);
  2313. if (acb->acb_flags & ACB_F_MSG_GET_CONFIG)
  2314. schedule_work(&acb->arcmsr_do_message_isr_bh);
  2315. }
  2316. static int arcmsr_hbaA_handle_isr(struct AdapterControlBlock *acb)
  2317. {
  2318. uint32_t outbound_intstatus;
  2319. struct MessageUnit_A __iomem *reg = acb->pmuA;
  2320. outbound_intstatus = readl(&reg->outbound_intstatus) &
  2321. acb->outbound_int_enable;
  2322. if (!(outbound_intstatus & ARCMSR_MU_OUTBOUND_HANDLE_INT))
  2323. return IRQ_NONE;
  2324. do {
  2325. writel(outbound_intstatus, &reg->outbound_intstatus);
  2326. if (outbound_intstatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT)
  2327. arcmsr_hbaA_doorbell_isr(acb);
  2328. if (outbound_intstatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT)
  2329. arcmsr_hbaA_postqueue_isr(acb);
  2330. if (outbound_intstatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT)
  2331. arcmsr_hbaA_message_isr(acb);
  2332. outbound_intstatus = readl(&reg->outbound_intstatus) &
  2333. acb->outbound_int_enable;
  2334. } while (outbound_intstatus & (ARCMSR_MU_OUTBOUND_DOORBELL_INT
  2335. | ARCMSR_MU_OUTBOUND_POSTQUEUE_INT
  2336. | ARCMSR_MU_OUTBOUND_MESSAGE0_INT));
  2337. return IRQ_HANDLED;
  2338. }
  2339. static int arcmsr_hbaB_handle_isr(struct AdapterControlBlock *acb)
  2340. {
  2341. uint32_t outbound_doorbell;
  2342. struct MessageUnit_B *reg = acb->pmuB;
  2343. outbound_doorbell = readl(reg->iop2drv_doorbell) &
  2344. acb->outbound_int_enable;
  2345. if (!outbound_doorbell)
  2346. return IRQ_NONE;
  2347. do {
  2348. writel(~outbound_doorbell, reg->iop2drv_doorbell);
  2349. writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell);
  2350. if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK)
  2351. arcmsr_iop2drv_data_wrote_handle(acb);
  2352. if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK)
  2353. arcmsr_iop2drv_data_read_handle(acb);
  2354. if (outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE)
  2355. arcmsr_hbaB_postqueue_isr(acb);
  2356. if (outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE)
  2357. arcmsr_hbaB_message_isr(acb);
  2358. outbound_doorbell = readl(reg->iop2drv_doorbell) &
  2359. acb->outbound_int_enable;
  2360. } while (outbound_doorbell & (ARCMSR_IOP2DRV_DATA_WRITE_OK
  2361. | ARCMSR_IOP2DRV_DATA_READ_OK
  2362. | ARCMSR_IOP2DRV_CDB_DONE
  2363. | ARCMSR_IOP2DRV_MESSAGE_CMD_DONE));
  2364. return IRQ_HANDLED;
  2365. }
  2366. static int arcmsr_hbaC_handle_isr(struct AdapterControlBlock *pACB)
  2367. {
  2368. uint32_t host_interrupt_status;
  2369. struct MessageUnit_C __iomem *phbcmu = pACB->pmuC;
  2370. /*
  2371. *********************************************
  2372. ** check outbound intstatus
  2373. *********************************************
  2374. */
  2375. host_interrupt_status = readl(&phbcmu->host_int_status) &
  2376. (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR |
  2377. ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR);
  2378. if (!host_interrupt_status)
  2379. return IRQ_NONE;
  2380. do {
  2381. if (host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR)
  2382. arcmsr_hbaC_doorbell_isr(pACB);
  2383. /* MU post queue interrupts*/
  2384. if (host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR)
  2385. arcmsr_hbaC_postqueue_isr(pACB);
  2386. host_interrupt_status = readl(&phbcmu->host_int_status);
  2387. } while (host_interrupt_status & (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR |
  2388. ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR));
  2389. return IRQ_HANDLED;
  2390. }
  2391. static irqreturn_t arcmsr_hbaD_handle_isr(struct AdapterControlBlock *pACB)
  2392. {
  2393. u32 host_interrupt_status;
  2394. struct MessageUnit_D *pmu = pACB->pmuD;
  2395. host_interrupt_status = readl(pmu->host_int_status) &
  2396. (ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR |
  2397. ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR);
  2398. if (!host_interrupt_status)
  2399. return IRQ_NONE;
  2400. do {
  2401. /* MU post queue interrupts*/
  2402. if (host_interrupt_status &
  2403. ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR)
  2404. arcmsr_hbaD_postqueue_isr(pACB);
  2405. if (host_interrupt_status &
  2406. ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR)
  2407. arcmsr_hbaD_doorbell_isr(pACB);
  2408. host_interrupt_status = readl(pmu->host_int_status);
  2409. } while (host_interrupt_status &
  2410. (ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR |
  2411. ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR));
  2412. return IRQ_HANDLED;
  2413. }
  2414. static irqreturn_t arcmsr_hbaE_handle_isr(struct AdapterControlBlock *pACB)
  2415. {
  2416. uint32_t host_interrupt_status;
  2417. struct MessageUnit_E __iomem *pmu = pACB->pmuE;
  2418. host_interrupt_status = readl(&pmu->host_int_status) &
  2419. (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR |
  2420. ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR);
  2421. if (!host_interrupt_status)
  2422. return IRQ_NONE;
  2423. do {
  2424. /* MU ioctl transfer doorbell interrupts*/
  2425. if (host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR) {
  2426. arcmsr_hbaE_doorbell_isr(pACB);
  2427. }
  2428. /* MU post queue interrupts*/
  2429. if (host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR) {
  2430. arcmsr_hbaE_postqueue_isr(pACB);
  2431. }
  2432. host_interrupt_status = readl(&pmu->host_int_status);
  2433. } while (host_interrupt_status & (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR |
  2434. ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR));
  2435. return IRQ_HANDLED;
  2436. }
  2437. static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb)
  2438. {
  2439. switch (acb->adapter_type) {
  2440. case ACB_ADAPTER_TYPE_A:
  2441. return arcmsr_hbaA_handle_isr(acb);
  2442. break;
  2443. case ACB_ADAPTER_TYPE_B:
  2444. return arcmsr_hbaB_handle_isr(acb);
  2445. break;
  2446. case ACB_ADAPTER_TYPE_C:
  2447. return arcmsr_hbaC_handle_isr(acb);
  2448. case ACB_ADAPTER_TYPE_D:
  2449. return arcmsr_hbaD_handle_isr(acb);
  2450. case ACB_ADAPTER_TYPE_E:
  2451. return arcmsr_hbaE_handle_isr(acb);
  2452. default:
  2453. return IRQ_NONE;
  2454. }
  2455. }
  2456. static void arcmsr_iop_parking(struct AdapterControlBlock *acb)
  2457. {
  2458. if (acb) {
  2459. /* stop adapter background rebuild */
  2460. if (acb->acb_flags & ACB_F_MSG_START_BGRB) {
  2461. uint32_t intmask_org;
  2462. acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
  2463. intmask_org = arcmsr_disable_outbound_ints(acb);
  2464. arcmsr_stop_adapter_bgrb(acb);
  2465. arcmsr_flush_adapter_cache(acb);
  2466. arcmsr_enable_outbound_ints(acb, intmask_org);
  2467. }
  2468. }
  2469. }
  2470. void arcmsr_clear_iop2drv_rqueue_buffer(struct AdapterControlBlock *acb)
  2471. {
  2472. uint32_t i;
  2473. if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
  2474. for (i = 0; i < 15; i++) {
  2475. if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
  2476. acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
  2477. acb->rqbuf_getIndex = 0;
  2478. acb->rqbuf_putIndex = 0;
  2479. arcmsr_iop_message_read(acb);
  2480. mdelay(30);
  2481. } else if (acb->rqbuf_getIndex !=
  2482. acb->rqbuf_putIndex) {
  2483. acb->rqbuf_getIndex = 0;
  2484. acb->rqbuf_putIndex = 0;
  2485. mdelay(30);
  2486. } else
  2487. break;
  2488. }
  2489. }
  2490. }
  2491. static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb,
  2492. struct scsi_cmnd *cmd)
  2493. {
  2494. char *buffer;
  2495. unsigned short use_sg;
  2496. int retvalue = 0, transfer_len = 0;
  2497. unsigned long flags;
  2498. struct CMD_MESSAGE_FIELD *pcmdmessagefld;
  2499. uint32_t controlcode = (uint32_t)cmd->cmnd[5] << 24 |
  2500. (uint32_t)cmd->cmnd[6] << 16 |
  2501. (uint32_t)cmd->cmnd[7] << 8 |
  2502. (uint32_t)cmd->cmnd[8];
  2503. struct scatterlist *sg;
  2504. use_sg = scsi_sg_count(cmd);
  2505. sg = scsi_sglist(cmd);
  2506. buffer = kmap_atomic(sg_page(sg)) + sg->offset;
  2507. if (use_sg > 1) {
  2508. retvalue = ARCMSR_MESSAGE_FAIL;
  2509. goto message_out;
  2510. }
  2511. transfer_len += sg->length;
  2512. if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) {
  2513. retvalue = ARCMSR_MESSAGE_FAIL;
  2514. pr_info("%s: ARCMSR_MESSAGE_FAIL!\n", __func__);
  2515. goto message_out;
  2516. }
  2517. pcmdmessagefld = (struct CMD_MESSAGE_FIELD *)buffer;
  2518. switch (controlcode) {
  2519. case ARCMSR_MESSAGE_READ_RQBUFFER: {
  2520. unsigned char *ver_addr;
  2521. uint8_t *ptmpQbuffer;
  2522. uint32_t allxfer_len = 0;
  2523. ver_addr = kmalloc(ARCMSR_API_DATA_BUFLEN, GFP_ATOMIC);
  2524. if (!ver_addr) {
  2525. retvalue = ARCMSR_MESSAGE_FAIL;
  2526. pr_info("%s: memory not enough!\n", __func__);
  2527. goto message_out;
  2528. }
  2529. ptmpQbuffer = ver_addr;
  2530. spin_lock_irqsave(&acb->rqbuffer_lock, flags);
  2531. if (acb->rqbuf_getIndex != acb->rqbuf_putIndex) {
  2532. unsigned int tail = acb->rqbuf_getIndex;
  2533. unsigned int head = acb->rqbuf_putIndex;
  2534. unsigned int cnt_to_end = CIRC_CNT_TO_END(head, tail, ARCMSR_MAX_QBUFFER);
  2535. allxfer_len = CIRC_CNT(head, tail, ARCMSR_MAX_QBUFFER);
  2536. if (allxfer_len > ARCMSR_API_DATA_BUFLEN)
  2537. allxfer_len = ARCMSR_API_DATA_BUFLEN;
  2538. if (allxfer_len <= cnt_to_end)
  2539. memcpy(ptmpQbuffer, acb->rqbuffer + tail, allxfer_len);
  2540. else {
  2541. memcpy(ptmpQbuffer, acb->rqbuffer + tail, cnt_to_end);
  2542. memcpy(ptmpQbuffer + cnt_to_end, acb->rqbuffer, allxfer_len - cnt_to_end);
  2543. }
  2544. acb->rqbuf_getIndex = (acb->rqbuf_getIndex + allxfer_len) % ARCMSR_MAX_QBUFFER;
  2545. }
  2546. memcpy(pcmdmessagefld->messagedatabuffer, ver_addr,
  2547. allxfer_len);
  2548. if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
  2549. struct QBUFFER __iomem *prbuffer;
  2550. acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
  2551. prbuffer = arcmsr_get_iop_rqbuffer(acb);
  2552. if (arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
  2553. acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
  2554. }
  2555. spin_unlock_irqrestore(&acb->rqbuffer_lock, flags);
  2556. kfree(ver_addr);
  2557. pcmdmessagefld->cmdmessage.Length = allxfer_len;
  2558. if (acb->fw_flag == FW_DEADLOCK)
  2559. pcmdmessagefld->cmdmessage.ReturnCode =
  2560. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  2561. else
  2562. pcmdmessagefld->cmdmessage.ReturnCode =
  2563. ARCMSR_MESSAGE_RETURNCODE_OK;
  2564. break;
  2565. }
  2566. case ARCMSR_MESSAGE_WRITE_WQBUFFER: {
  2567. unsigned char *ver_addr;
  2568. uint32_t user_len;
  2569. int32_t cnt2end;
  2570. uint8_t *pQbuffer, *ptmpuserbuffer;
  2571. user_len = pcmdmessagefld->cmdmessage.Length;
  2572. if (user_len > ARCMSR_API_DATA_BUFLEN) {
  2573. retvalue = ARCMSR_MESSAGE_FAIL;
  2574. goto message_out;
  2575. }
  2576. ver_addr = kmalloc(ARCMSR_API_DATA_BUFLEN, GFP_ATOMIC);
  2577. if (!ver_addr) {
  2578. retvalue = ARCMSR_MESSAGE_FAIL;
  2579. goto message_out;
  2580. }
  2581. ptmpuserbuffer = ver_addr;
  2582. memcpy(ptmpuserbuffer,
  2583. pcmdmessagefld->messagedatabuffer, user_len);
  2584. spin_lock_irqsave(&acb->wqbuffer_lock, flags);
  2585. if (acb->wqbuf_putIndex != acb->wqbuf_getIndex) {
  2586. struct SENSE_DATA *sensebuffer =
  2587. (struct SENSE_DATA *)cmd->sense_buffer;
  2588. arcmsr_write_ioctldata2iop(acb);
  2589. /* has error report sensedata */
  2590. sensebuffer->ErrorCode = SCSI_SENSE_CURRENT_ERRORS;
  2591. sensebuffer->SenseKey = ILLEGAL_REQUEST;
  2592. sensebuffer->AdditionalSenseLength = 0x0A;
  2593. sensebuffer->AdditionalSenseCode = 0x20;
  2594. sensebuffer->Valid = 1;
  2595. retvalue = ARCMSR_MESSAGE_FAIL;
  2596. } else {
  2597. pQbuffer = &acb->wqbuffer[acb->wqbuf_putIndex];
  2598. cnt2end = ARCMSR_MAX_QBUFFER - acb->wqbuf_putIndex;
  2599. if (user_len > cnt2end) {
  2600. memcpy(pQbuffer, ptmpuserbuffer, cnt2end);
  2601. ptmpuserbuffer += cnt2end;
  2602. user_len -= cnt2end;
  2603. acb->wqbuf_putIndex = 0;
  2604. pQbuffer = acb->wqbuffer;
  2605. }
  2606. memcpy(pQbuffer, ptmpuserbuffer, user_len);
  2607. acb->wqbuf_putIndex += user_len;
  2608. acb->wqbuf_putIndex %= ARCMSR_MAX_QBUFFER;
  2609. if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) {
  2610. acb->acb_flags &=
  2611. ~ACB_F_MESSAGE_WQBUFFER_CLEARED;
  2612. arcmsr_write_ioctldata2iop(acb);
  2613. }
  2614. }
  2615. spin_unlock_irqrestore(&acb->wqbuffer_lock, flags);
  2616. kfree(ver_addr);
  2617. if (acb->fw_flag == FW_DEADLOCK)
  2618. pcmdmessagefld->cmdmessage.ReturnCode =
  2619. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  2620. else
  2621. pcmdmessagefld->cmdmessage.ReturnCode =
  2622. ARCMSR_MESSAGE_RETURNCODE_OK;
  2623. break;
  2624. }
  2625. case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
  2626. uint8_t *pQbuffer = acb->rqbuffer;
  2627. arcmsr_clear_iop2drv_rqueue_buffer(acb);
  2628. spin_lock_irqsave(&acb->rqbuffer_lock, flags);
  2629. acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
  2630. acb->rqbuf_getIndex = 0;
  2631. acb->rqbuf_putIndex = 0;
  2632. memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
  2633. spin_unlock_irqrestore(&acb->rqbuffer_lock, flags);
  2634. if (acb->fw_flag == FW_DEADLOCK)
  2635. pcmdmessagefld->cmdmessage.ReturnCode =
  2636. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  2637. else
  2638. pcmdmessagefld->cmdmessage.ReturnCode =
  2639. ARCMSR_MESSAGE_RETURNCODE_OK;
  2640. break;
  2641. }
  2642. case ARCMSR_MESSAGE_CLEAR_WQBUFFER: {
  2643. uint8_t *pQbuffer = acb->wqbuffer;
  2644. spin_lock_irqsave(&acb->wqbuffer_lock, flags);
  2645. acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED |
  2646. ACB_F_MESSAGE_WQBUFFER_READED);
  2647. acb->wqbuf_getIndex = 0;
  2648. acb->wqbuf_putIndex = 0;
  2649. memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
  2650. spin_unlock_irqrestore(&acb->wqbuffer_lock, flags);
  2651. if (acb->fw_flag == FW_DEADLOCK)
  2652. pcmdmessagefld->cmdmessage.ReturnCode =
  2653. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  2654. else
  2655. pcmdmessagefld->cmdmessage.ReturnCode =
  2656. ARCMSR_MESSAGE_RETURNCODE_OK;
  2657. break;
  2658. }
  2659. case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
  2660. uint8_t *pQbuffer;
  2661. arcmsr_clear_iop2drv_rqueue_buffer(acb);
  2662. spin_lock_irqsave(&acb->rqbuffer_lock, flags);
  2663. acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
  2664. acb->rqbuf_getIndex = 0;
  2665. acb->rqbuf_putIndex = 0;
  2666. pQbuffer = acb->rqbuffer;
  2667. memset(pQbuffer, 0, sizeof(struct QBUFFER));
  2668. spin_unlock_irqrestore(&acb->rqbuffer_lock, flags);
  2669. spin_lock_irqsave(&acb->wqbuffer_lock, flags);
  2670. acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED |
  2671. ACB_F_MESSAGE_WQBUFFER_READED);
  2672. acb->wqbuf_getIndex = 0;
  2673. acb->wqbuf_putIndex = 0;
  2674. pQbuffer = acb->wqbuffer;
  2675. memset(pQbuffer, 0, sizeof(struct QBUFFER));
  2676. spin_unlock_irqrestore(&acb->wqbuffer_lock, flags);
  2677. if (acb->fw_flag == FW_DEADLOCK)
  2678. pcmdmessagefld->cmdmessage.ReturnCode =
  2679. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  2680. else
  2681. pcmdmessagefld->cmdmessage.ReturnCode =
  2682. ARCMSR_MESSAGE_RETURNCODE_OK;
  2683. break;
  2684. }
  2685. case ARCMSR_MESSAGE_RETURN_CODE_3F: {
  2686. if (acb->fw_flag == FW_DEADLOCK)
  2687. pcmdmessagefld->cmdmessage.ReturnCode =
  2688. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  2689. else
  2690. pcmdmessagefld->cmdmessage.ReturnCode =
  2691. ARCMSR_MESSAGE_RETURNCODE_3F;
  2692. break;
  2693. }
  2694. case ARCMSR_MESSAGE_SAY_HELLO: {
  2695. int8_t *hello_string = "Hello! I am ARCMSR";
  2696. if (acb->fw_flag == FW_DEADLOCK)
  2697. pcmdmessagefld->cmdmessage.ReturnCode =
  2698. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  2699. else
  2700. pcmdmessagefld->cmdmessage.ReturnCode =
  2701. ARCMSR_MESSAGE_RETURNCODE_OK;
  2702. memcpy(pcmdmessagefld->messagedatabuffer,
  2703. hello_string, (int16_t)strlen(hello_string));
  2704. break;
  2705. }
  2706. case ARCMSR_MESSAGE_SAY_GOODBYE: {
  2707. if (acb->fw_flag == FW_DEADLOCK)
  2708. pcmdmessagefld->cmdmessage.ReturnCode =
  2709. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  2710. else
  2711. pcmdmessagefld->cmdmessage.ReturnCode =
  2712. ARCMSR_MESSAGE_RETURNCODE_OK;
  2713. arcmsr_iop_parking(acb);
  2714. break;
  2715. }
  2716. case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: {
  2717. if (acb->fw_flag == FW_DEADLOCK)
  2718. pcmdmessagefld->cmdmessage.ReturnCode =
  2719. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  2720. else
  2721. pcmdmessagefld->cmdmessage.ReturnCode =
  2722. ARCMSR_MESSAGE_RETURNCODE_OK;
  2723. arcmsr_flush_adapter_cache(acb);
  2724. break;
  2725. }
  2726. default:
  2727. retvalue = ARCMSR_MESSAGE_FAIL;
  2728. pr_info("%s: unknown controlcode!\n", __func__);
  2729. }
  2730. message_out:
  2731. if (use_sg) {
  2732. struct scatterlist *sg = scsi_sglist(cmd);
  2733. kunmap_atomic(buffer - sg->offset);
  2734. }
  2735. return retvalue;
  2736. }
  2737. static struct CommandControlBlock *arcmsr_get_freeccb(struct AdapterControlBlock *acb)
  2738. {
  2739. struct list_head *head = &acb->ccb_free_list;
  2740. struct CommandControlBlock *ccb = NULL;
  2741. unsigned long flags;
  2742. spin_lock_irqsave(&acb->ccblist_lock, flags);
  2743. if (!list_empty(head)) {
  2744. ccb = list_entry(head->next, struct CommandControlBlock, list);
  2745. list_del_init(&ccb->list);
  2746. }else{
  2747. spin_unlock_irqrestore(&acb->ccblist_lock, flags);
  2748. return NULL;
  2749. }
  2750. spin_unlock_irqrestore(&acb->ccblist_lock, flags);
  2751. return ccb;
  2752. }
  2753. static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb,
  2754. struct scsi_cmnd *cmd)
  2755. {
  2756. switch (cmd->cmnd[0]) {
  2757. case INQUIRY: {
  2758. unsigned char inqdata[36];
  2759. char *buffer;
  2760. struct scatterlist *sg;
  2761. if (cmd->device->lun) {
  2762. cmd->result = (DID_TIME_OUT << 16);
  2763. cmd->scsi_done(cmd);
  2764. return;
  2765. }
  2766. inqdata[0] = TYPE_PROCESSOR;
  2767. /* Periph Qualifier & Periph Dev Type */
  2768. inqdata[1] = 0;
  2769. /* rem media bit & Dev Type Modifier */
  2770. inqdata[2] = 0;
  2771. /* ISO, ECMA, & ANSI versions */
  2772. inqdata[4] = 31;
  2773. /* length of additional data */
  2774. strncpy(&inqdata[8], "Areca ", 8);
  2775. /* Vendor Identification */
  2776. strncpy(&inqdata[16], "RAID controller ", 16);
  2777. /* Product Identification */
  2778. strncpy(&inqdata[32], "R001", 4); /* Product Revision */
  2779. sg = scsi_sglist(cmd);
  2780. buffer = kmap_atomic(sg_page(sg)) + sg->offset;
  2781. memcpy(buffer, inqdata, sizeof(inqdata));
  2782. sg = scsi_sglist(cmd);
  2783. kunmap_atomic(buffer - sg->offset);
  2784. cmd->scsi_done(cmd);
  2785. }
  2786. break;
  2787. case WRITE_BUFFER:
  2788. case READ_BUFFER: {
  2789. if (arcmsr_iop_message_xfer(acb, cmd))
  2790. cmd->result = (DID_ERROR << 16);
  2791. cmd->scsi_done(cmd);
  2792. }
  2793. break;
  2794. default:
  2795. cmd->scsi_done(cmd);
  2796. }
  2797. }
  2798. static int arcmsr_queue_command_lck(struct scsi_cmnd *cmd,
  2799. void (* done)(struct scsi_cmnd *))
  2800. {
  2801. struct Scsi_Host *host = cmd->device->host;
  2802. struct AdapterControlBlock *acb = (struct AdapterControlBlock *) host->hostdata;
  2803. struct CommandControlBlock *ccb;
  2804. int target = cmd->device->id;
  2805. if (acb->acb_flags & ACB_F_ADAPTER_REMOVED) {
  2806. cmd->result = (DID_NO_CONNECT << 16);
  2807. cmd->scsi_done(cmd);
  2808. return 0;
  2809. }
  2810. cmd->scsi_done = done;
  2811. cmd->host_scribble = NULL;
  2812. cmd->result = 0;
  2813. if (target == 16) {
  2814. /* virtual device for iop message transfer */
  2815. arcmsr_handle_virtual_command(acb, cmd);
  2816. return 0;
  2817. }
  2818. ccb = arcmsr_get_freeccb(acb);
  2819. if (!ccb)
  2820. return SCSI_MLQUEUE_HOST_BUSY;
  2821. if (arcmsr_build_ccb( acb, ccb, cmd ) == FAILED) {
  2822. cmd->result = (DID_ERROR << 16) | (RESERVATION_CONFLICT << 1);
  2823. cmd->scsi_done(cmd);
  2824. return 0;
  2825. }
  2826. arcmsr_post_ccb(acb, ccb);
  2827. return 0;
  2828. }
  2829. static DEF_SCSI_QCMD(arcmsr_queue_command)
  2830. static void arcmsr_get_adapter_config(struct AdapterControlBlock *pACB, uint32_t *rwbuffer)
  2831. {
  2832. int count;
  2833. uint32_t *acb_firm_model = (uint32_t *)pACB->firm_model;
  2834. uint32_t *acb_firm_version = (uint32_t *)pACB->firm_version;
  2835. uint32_t *acb_device_map = (uint32_t *)pACB->device_map;
  2836. uint32_t *firm_model = &rwbuffer[15];
  2837. uint32_t *firm_version = &rwbuffer[17];
  2838. uint32_t *device_map = &rwbuffer[21];
  2839. count = 2;
  2840. while (count) {
  2841. *acb_firm_model = readl(firm_model);
  2842. acb_firm_model++;
  2843. firm_model++;
  2844. count--;
  2845. }
  2846. count = 4;
  2847. while (count) {
  2848. *acb_firm_version = readl(firm_version);
  2849. acb_firm_version++;
  2850. firm_version++;
  2851. count--;
  2852. }
  2853. count = 4;
  2854. while (count) {
  2855. *acb_device_map = readl(device_map);
  2856. acb_device_map++;
  2857. device_map++;
  2858. count--;
  2859. }
  2860. pACB->signature = readl(&rwbuffer[0]);
  2861. pACB->firm_request_len = readl(&rwbuffer[1]);
  2862. pACB->firm_numbers_queue = readl(&rwbuffer[2]);
  2863. pACB->firm_sdram_size = readl(&rwbuffer[3]);
  2864. pACB->firm_hd_channels = readl(&rwbuffer[4]);
  2865. pACB->firm_cfg_version = readl(&rwbuffer[25]);
  2866. pr_notice("Areca RAID Controller%d: Model %s, F/W %s\n",
  2867. pACB->host->host_no,
  2868. pACB->firm_model,
  2869. pACB->firm_version);
  2870. }
  2871. static bool arcmsr_hbaA_get_config(struct AdapterControlBlock *acb)
  2872. {
  2873. struct MessageUnit_A __iomem *reg = acb->pmuA;
  2874. arcmsr_wait_firmware_ready(acb);
  2875. writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
  2876. if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
  2877. printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
  2878. miscellaneous data' timeout \n", acb->host->host_no);
  2879. return false;
  2880. }
  2881. arcmsr_get_adapter_config(acb, reg->message_rwbuffer);
  2882. return true;
  2883. }
  2884. static bool arcmsr_hbaB_get_config(struct AdapterControlBlock *acb)
  2885. {
  2886. struct MessageUnit_B *reg = acb->pmuB;
  2887. arcmsr_wait_firmware_ready(acb);
  2888. writel(ARCMSR_MESSAGE_START_DRIVER_MODE, reg->drv2iop_doorbell);
  2889. if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
  2890. printk(KERN_ERR "arcmsr%d: can't set driver mode.\n", acb->host->host_no);
  2891. return false;
  2892. }
  2893. writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell);
  2894. if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
  2895. printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
  2896. miscellaneous data' timeout \n", acb->host->host_no);
  2897. return false;
  2898. }
  2899. arcmsr_get_adapter_config(acb, reg->message_rwbuffer);
  2900. return true;
  2901. }
  2902. static bool arcmsr_hbaC_get_config(struct AdapterControlBlock *pACB)
  2903. {
  2904. uint32_t intmask_org;
  2905. struct MessageUnit_C __iomem *reg = pACB->pmuC;
  2906. /* disable all outbound interrupt */
  2907. intmask_org = readl(&reg->host_int_mask); /* disable outbound message0 int */
  2908. writel(intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE, &reg->host_int_mask);
  2909. /* wait firmware ready */
  2910. arcmsr_wait_firmware_ready(pACB);
  2911. /* post "get config" instruction */
  2912. writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
  2913. writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
  2914. /* wait message ready */
  2915. if (!arcmsr_hbaC_wait_msgint_ready(pACB)) {
  2916. printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
  2917. miscellaneous data' timeout \n", pACB->host->host_no);
  2918. return false;
  2919. }
  2920. arcmsr_get_adapter_config(pACB, reg->msgcode_rwbuffer);
  2921. return true;
  2922. }
  2923. static bool arcmsr_hbaD_get_config(struct AdapterControlBlock *acb)
  2924. {
  2925. struct MessageUnit_D *reg = acb->pmuD;
  2926. if (readl(acb->pmuD->outbound_doorbell) &
  2927. ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE) {
  2928. writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE,
  2929. acb->pmuD->outbound_doorbell);/*clear interrupt*/
  2930. }
  2931. arcmsr_wait_firmware_ready(acb);
  2932. /* post "get config" instruction */
  2933. writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, reg->inbound_msgaddr0);
  2934. /* wait message ready */
  2935. if (!arcmsr_hbaD_wait_msgint_ready(acb)) {
  2936. pr_notice("arcmsr%d: wait get adapter firmware "
  2937. "miscellaneous data timeout\n", acb->host->host_no);
  2938. return false;
  2939. }
  2940. arcmsr_get_adapter_config(acb, reg->msgcode_rwbuffer);
  2941. return true;
  2942. }
  2943. static bool arcmsr_hbaE_get_config(struct AdapterControlBlock *pACB)
  2944. {
  2945. struct MessageUnit_E __iomem *reg = pACB->pmuE;
  2946. uint32_t intmask_org;
  2947. /* disable all outbound interrupt */
  2948. intmask_org = readl(&reg->host_int_mask); /* disable outbound message0 int */
  2949. writel(intmask_org | ARCMSR_HBEMU_ALL_INTMASKENABLE, &reg->host_int_mask);
  2950. /* wait firmware ready */
  2951. arcmsr_wait_firmware_ready(pACB);
  2952. mdelay(20);
  2953. /* post "get config" instruction */
  2954. writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
  2955. pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
  2956. writel(pACB->out_doorbell, &reg->iobound_doorbell);
  2957. /* wait message ready */
  2958. if (!arcmsr_hbaE_wait_msgint_ready(pACB)) {
  2959. pr_notice("arcmsr%d: wait get adapter firmware "
  2960. "miscellaneous data timeout\n", pACB->host->host_no);
  2961. return false;
  2962. }
  2963. arcmsr_get_adapter_config(pACB, reg->msgcode_rwbuffer);
  2964. return true;
  2965. }
  2966. static bool arcmsr_get_firmware_spec(struct AdapterControlBlock *acb)
  2967. {
  2968. bool rtn = false;
  2969. switch (acb->adapter_type) {
  2970. case ACB_ADAPTER_TYPE_A:
  2971. rtn = arcmsr_hbaA_get_config(acb);
  2972. break;
  2973. case ACB_ADAPTER_TYPE_B:
  2974. rtn = arcmsr_hbaB_get_config(acb);
  2975. break;
  2976. case ACB_ADAPTER_TYPE_C:
  2977. rtn = arcmsr_hbaC_get_config(acb);
  2978. break;
  2979. case ACB_ADAPTER_TYPE_D:
  2980. rtn = arcmsr_hbaD_get_config(acb);
  2981. break;
  2982. case ACB_ADAPTER_TYPE_E:
  2983. rtn = arcmsr_hbaE_get_config(acb);
  2984. break;
  2985. default:
  2986. break;
  2987. }
  2988. acb->maxOutstanding = acb->firm_numbers_queue - 1;
  2989. if (acb->host->can_queue >= acb->firm_numbers_queue)
  2990. acb->host->can_queue = acb->maxOutstanding;
  2991. else
  2992. acb->maxOutstanding = acb->host->can_queue;
  2993. acb->maxFreeCCB = acb->host->can_queue;
  2994. if (acb->maxFreeCCB < ARCMSR_MAX_FREECCB_NUM)
  2995. acb->maxFreeCCB += 64;
  2996. return rtn;
  2997. }
  2998. static int arcmsr_hbaA_polling_ccbdone(struct AdapterControlBlock *acb,
  2999. struct CommandControlBlock *poll_ccb)
  3000. {
  3001. struct MessageUnit_A __iomem *reg = acb->pmuA;
  3002. struct CommandControlBlock *ccb;
  3003. struct ARCMSR_CDB *arcmsr_cdb;
  3004. uint32_t flag_ccb, outbound_intstatus, poll_ccb_done = 0, poll_count = 0;
  3005. int rtn;
  3006. bool error;
  3007. polling_hba_ccb_retry:
  3008. poll_count++;
  3009. outbound_intstatus = readl(&reg->outbound_intstatus) & acb->outbound_int_enable;
  3010. writel(outbound_intstatus, &reg->outbound_intstatus);/*clear interrupt*/
  3011. while (1) {
  3012. if ((flag_ccb = readl(&reg->outbound_queueport)) == 0xFFFFFFFF) {
  3013. if (poll_ccb_done){
  3014. rtn = SUCCESS;
  3015. break;
  3016. }else {
  3017. msleep(25);
  3018. if (poll_count > 100){
  3019. rtn = FAILED;
  3020. break;
  3021. }
  3022. goto polling_hba_ccb_retry;
  3023. }
  3024. }
  3025. arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));
  3026. ccb = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
  3027. poll_ccb_done |= (ccb == poll_ccb) ? 1 : 0;
  3028. if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) {
  3029. if ((ccb->startdone == ARCMSR_CCB_ABORTED) || (ccb == poll_ccb)) {
  3030. printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
  3031. " poll command abort successfully \n"
  3032. , acb->host->host_no
  3033. , ccb->pcmd->device->id
  3034. , (u32)ccb->pcmd->device->lun
  3035. , ccb);
  3036. ccb->pcmd->result = DID_ABORT << 16;
  3037. arcmsr_ccb_complete(ccb);
  3038. continue;
  3039. }
  3040. printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
  3041. " command done ccb = '0x%p'"
  3042. "ccboutstandingcount = %d \n"
  3043. , acb->host->host_no
  3044. , ccb
  3045. , atomic_read(&acb->ccboutstandingcount));
  3046. continue;
  3047. }
  3048. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
  3049. arcmsr_report_ccb_state(acb, ccb, error);
  3050. }
  3051. return rtn;
  3052. }
  3053. static int arcmsr_hbaB_polling_ccbdone(struct AdapterControlBlock *acb,
  3054. struct CommandControlBlock *poll_ccb)
  3055. {
  3056. struct MessageUnit_B *reg = acb->pmuB;
  3057. struct ARCMSR_CDB *arcmsr_cdb;
  3058. struct CommandControlBlock *ccb;
  3059. uint32_t flag_ccb, poll_ccb_done = 0, poll_count = 0;
  3060. int index, rtn;
  3061. bool error;
  3062. polling_hbb_ccb_retry:
  3063. poll_count++;
  3064. /* clear doorbell interrupt */
  3065. writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
  3066. while(1){
  3067. index = reg->doneq_index;
  3068. flag_ccb = reg->done_qbuffer[index];
  3069. if (flag_ccb == 0) {
  3070. if (poll_ccb_done){
  3071. rtn = SUCCESS;
  3072. break;
  3073. }else {
  3074. msleep(25);
  3075. if (poll_count > 100){
  3076. rtn = FAILED;
  3077. break;
  3078. }
  3079. goto polling_hbb_ccb_retry;
  3080. }
  3081. }
  3082. reg->done_qbuffer[index] = 0;
  3083. index++;
  3084. /*if last index number set it to 0 */
  3085. index %= ARCMSR_MAX_HBB_POSTQUEUE;
  3086. reg->doneq_index = index;
  3087. /* check if command done with no error*/
  3088. arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));
  3089. ccb = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
  3090. poll_ccb_done |= (ccb == poll_ccb) ? 1 : 0;
  3091. if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) {
  3092. if ((ccb->startdone == ARCMSR_CCB_ABORTED) || (ccb == poll_ccb)) {
  3093. printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
  3094. " poll command abort successfully \n"
  3095. ,acb->host->host_no
  3096. ,ccb->pcmd->device->id
  3097. ,(u32)ccb->pcmd->device->lun
  3098. ,ccb);
  3099. ccb->pcmd->result = DID_ABORT << 16;
  3100. arcmsr_ccb_complete(ccb);
  3101. continue;
  3102. }
  3103. printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
  3104. " command done ccb = '0x%p'"
  3105. "ccboutstandingcount = %d \n"
  3106. , acb->host->host_no
  3107. , ccb
  3108. , atomic_read(&acb->ccboutstandingcount));
  3109. continue;
  3110. }
  3111. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
  3112. arcmsr_report_ccb_state(acb, ccb, error);
  3113. }
  3114. return rtn;
  3115. }
  3116. static int arcmsr_hbaC_polling_ccbdone(struct AdapterControlBlock *acb,
  3117. struct CommandControlBlock *poll_ccb)
  3118. {
  3119. struct MessageUnit_C __iomem *reg = acb->pmuC;
  3120. uint32_t flag_ccb, ccb_cdb_phy;
  3121. struct ARCMSR_CDB *arcmsr_cdb;
  3122. bool error;
  3123. struct CommandControlBlock *pCCB;
  3124. uint32_t poll_ccb_done = 0, poll_count = 0;
  3125. int rtn;
  3126. polling_hbc_ccb_retry:
  3127. poll_count++;
  3128. while (1) {
  3129. if ((readl(&reg->host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) == 0) {
  3130. if (poll_ccb_done) {
  3131. rtn = SUCCESS;
  3132. break;
  3133. } else {
  3134. msleep(25);
  3135. if (poll_count > 100) {
  3136. rtn = FAILED;
  3137. break;
  3138. }
  3139. goto polling_hbc_ccb_retry;
  3140. }
  3141. }
  3142. flag_ccb = readl(&reg->outbound_queueport_low);
  3143. ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
  3144. arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy);/*frame must be 32 bytes aligned*/
  3145. pCCB = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
  3146. poll_ccb_done |= (pCCB == poll_ccb) ? 1 : 0;
  3147. /* check ifcommand done with no error*/
  3148. if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) {
  3149. if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
  3150. printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
  3151. " poll command abort successfully \n"
  3152. , acb->host->host_no
  3153. , pCCB->pcmd->device->id
  3154. , (u32)pCCB->pcmd->device->lun
  3155. , pCCB);
  3156. pCCB->pcmd->result = DID_ABORT << 16;
  3157. arcmsr_ccb_complete(pCCB);
  3158. continue;
  3159. }
  3160. printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
  3161. " command done ccb = '0x%p'"
  3162. "ccboutstandingcount = %d \n"
  3163. , acb->host->host_no
  3164. , pCCB
  3165. , atomic_read(&acb->ccboutstandingcount));
  3166. continue;
  3167. }
  3168. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
  3169. arcmsr_report_ccb_state(acb, pCCB, error);
  3170. }
  3171. return rtn;
  3172. }
  3173. static int arcmsr_hbaD_polling_ccbdone(struct AdapterControlBlock *acb,
  3174. struct CommandControlBlock *poll_ccb)
  3175. {
  3176. bool error;
  3177. uint32_t poll_ccb_done = 0, poll_count = 0, flag_ccb, ccb_cdb_phy;
  3178. int rtn, doneq_index, index_stripped, outbound_write_pointer, toggle;
  3179. unsigned long flags;
  3180. struct ARCMSR_CDB *arcmsr_cdb;
  3181. struct CommandControlBlock *pCCB;
  3182. struct MessageUnit_D *pmu = acb->pmuD;
  3183. polling_hbaD_ccb_retry:
  3184. poll_count++;
  3185. while (1) {
  3186. spin_lock_irqsave(&acb->doneq_lock, flags);
  3187. outbound_write_pointer = pmu->done_qbuffer[0].addressLow + 1;
  3188. doneq_index = pmu->doneq_index;
  3189. if ((outbound_write_pointer & 0xFFF) == (doneq_index & 0xFFF)) {
  3190. spin_unlock_irqrestore(&acb->doneq_lock, flags);
  3191. if (poll_ccb_done) {
  3192. rtn = SUCCESS;
  3193. break;
  3194. } else {
  3195. msleep(25);
  3196. if (poll_count > 40) {
  3197. rtn = FAILED;
  3198. break;
  3199. }
  3200. goto polling_hbaD_ccb_retry;
  3201. }
  3202. }
  3203. toggle = doneq_index & 0x4000;
  3204. index_stripped = (doneq_index & 0xFFF) + 1;
  3205. index_stripped %= ARCMSR_MAX_ARC1214_DONEQUEUE;
  3206. pmu->doneq_index = index_stripped ? (index_stripped | toggle) :
  3207. ((toggle ^ 0x4000) + 1);
  3208. doneq_index = pmu->doneq_index;
  3209. spin_unlock_irqrestore(&acb->doneq_lock, flags);
  3210. flag_ccb = pmu->done_qbuffer[doneq_index & 0xFFF].addressLow;
  3211. ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
  3212. arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset +
  3213. ccb_cdb_phy);
  3214. pCCB = container_of(arcmsr_cdb, struct CommandControlBlock,
  3215. arcmsr_cdb);
  3216. poll_ccb_done |= (pCCB == poll_ccb) ? 1 : 0;
  3217. if ((pCCB->acb != acb) ||
  3218. (pCCB->startdone != ARCMSR_CCB_START)) {
  3219. if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
  3220. pr_notice("arcmsr%d: scsi id = %d "
  3221. "lun = %d ccb = '0x%p' poll command "
  3222. "abort successfully\n"
  3223. , acb->host->host_no
  3224. , pCCB->pcmd->device->id
  3225. , (u32)pCCB->pcmd->device->lun
  3226. , pCCB);
  3227. pCCB->pcmd->result = DID_ABORT << 16;
  3228. arcmsr_ccb_complete(pCCB);
  3229. continue;
  3230. }
  3231. pr_notice("arcmsr%d: polling an illegal "
  3232. "ccb command done ccb = '0x%p' "
  3233. "ccboutstandingcount = %d\n"
  3234. , acb->host->host_no
  3235. , pCCB
  3236. , atomic_read(&acb->ccboutstandingcount));
  3237. continue;
  3238. }
  3239. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1)
  3240. ? true : false;
  3241. arcmsr_report_ccb_state(acb, pCCB, error);
  3242. }
  3243. return rtn;
  3244. }
  3245. static int arcmsr_hbaE_polling_ccbdone(struct AdapterControlBlock *acb,
  3246. struct CommandControlBlock *poll_ccb)
  3247. {
  3248. bool error;
  3249. uint32_t poll_ccb_done = 0, poll_count = 0, doneq_index;
  3250. uint16_t cmdSMID;
  3251. unsigned long flags;
  3252. int rtn;
  3253. struct CommandControlBlock *pCCB;
  3254. struct MessageUnit_E __iomem *reg = acb->pmuE;
  3255. polling_hbaC_ccb_retry:
  3256. poll_count++;
  3257. while (1) {
  3258. spin_lock_irqsave(&acb->doneq_lock, flags);
  3259. doneq_index = acb->doneq_index;
  3260. if ((readl(&reg->reply_post_producer_index) & 0xFFFF) ==
  3261. doneq_index) {
  3262. spin_unlock_irqrestore(&acb->doneq_lock, flags);
  3263. if (poll_ccb_done) {
  3264. rtn = SUCCESS;
  3265. break;
  3266. } else {
  3267. msleep(25);
  3268. if (poll_count > 40) {
  3269. rtn = FAILED;
  3270. break;
  3271. }
  3272. goto polling_hbaC_ccb_retry;
  3273. }
  3274. }
  3275. cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID;
  3276. doneq_index++;
  3277. if (doneq_index >= acb->completionQ_entry)
  3278. doneq_index = 0;
  3279. acb->doneq_index = doneq_index;
  3280. spin_unlock_irqrestore(&acb->doneq_lock, flags);
  3281. pCCB = acb->pccb_pool[cmdSMID];
  3282. poll_ccb_done |= (pCCB == poll_ccb) ? 1 : 0;
  3283. /* check if command done with no error*/
  3284. if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) {
  3285. if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
  3286. pr_notice("arcmsr%d: scsi id = %d "
  3287. "lun = %d ccb = '0x%p' poll command "
  3288. "abort successfully\n"
  3289. , acb->host->host_no
  3290. , pCCB->pcmd->device->id
  3291. , (u32)pCCB->pcmd->device->lun
  3292. , pCCB);
  3293. pCCB->pcmd->result = DID_ABORT << 16;
  3294. arcmsr_ccb_complete(pCCB);
  3295. continue;
  3296. }
  3297. pr_notice("arcmsr%d: polling an illegal "
  3298. "ccb command done ccb = '0x%p' "
  3299. "ccboutstandingcount = %d\n"
  3300. , acb->host->host_no
  3301. , pCCB
  3302. , atomic_read(&acb->ccboutstandingcount));
  3303. continue;
  3304. }
  3305. error = (acb->pCompletionQ[doneq_index].cmdFlag &
  3306. ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
  3307. arcmsr_report_ccb_state(acb, pCCB, error);
  3308. }
  3309. writel(doneq_index, &reg->reply_post_consumer_index);
  3310. return rtn;
  3311. }
  3312. static int arcmsr_polling_ccbdone(struct AdapterControlBlock *acb,
  3313. struct CommandControlBlock *poll_ccb)
  3314. {
  3315. int rtn = 0;
  3316. switch (acb->adapter_type) {
  3317. case ACB_ADAPTER_TYPE_A: {
  3318. rtn = arcmsr_hbaA_polling_ccbdone(acb, poll_ccb);
  3319. }
  3320. break;
  3321. case ACB_ADAPTER_TYPE_B: {
  3322. rtn = arcmsr_hbaB_polling_ccbdone(acb, poll_ccb);
  3323. }
  3324. break;
  3325. case ACB_ADAPTER_TYPE_C: {
  3326. rtn = arcmsr_hbaC_polling_ccbdone(acb, poll_ccb);
  3327. }
  3328. break;
  3329. case ACB_ADAPTER_TYPE_D:
  3330. rtn = arcmsr_hbaD_polling_ccbdone(acb, poll_ccb);
  3331. break;
  3332. case ACB_ADAPTER_TYPE_E:
  3333. rtn = arcmsr_hbaE_polling_ccbdone(acb, poll_ccb);
  3334. break;
  3335. }
  3336. return rtn;
  3337. }
  3338. static void arcmsr_set_iop_datetime(struct timer_list *t)
  3339. {
  3340. struct AdapterControlBlock *pacb = from_timer(pacb, t, refresh_timer);
  3341. unsigned int next_time;
  3342. struct tm tm;
  3343. union {
  3344. struct {
  3345. uint16_t signature;
  3346. uint8_t year;
  3347. uint8_t month;
  3348. uint8_t date;
  3349. uint8_t hour;
  3350. uint8_t minute;
  3351. uint8_t second;
  3352. } a;
  3353. struct {
  3354. uint32_t msg_time[2];
  3355. } b;
  3356. } datetime;
  3357. time64_to_tm(ktime_get_real_seconds(), -sys_tz.tz_minuteswest * 60, &tm);
  3358. datetime.a.signature = 0x55AA;
  3359. datetime.a.year = tm.tm_year - 100; /* base 2000 instead of 1900 */
  3360. datetime.a.month = tm.tm_mon;
  3361. datetime.a.date = tm.tm_mday;
  3362. datetime.a.hour = tm.tm_hour;
  3363. datetime.a.minute = tm.tm_min;
  3364. datetime.a.second = tm.tm_sec;
  3365. switch (pacb->adapter_type) {
  3366. case ACB_ADAPTER_TYPE_A: {
  3367. struct MessageUnit_A __iomem *reg = pacb->pmuA;
  3368. writel(datetime.b.msg_time[0], &reg->message_rwbuffer[0]);
  3369. writel(datetime.b.msg_time[1], &reg->message_rwbuffer[1]);
  3370. writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, &reg->inbound_msgaddr0);
  3371. break;
  3372. }
  3373. case ACB_ADAPTER_TYPE_B: {
  3374. uint32_t __iomem *rwbuffer;
  3375. struct MessageUnit_B *reg = pacb->pmuB;
  3376. rwbuffer = reg->message_rwbuffer;
  3377. writel(datetime.b.msg_time[0], rwbuffer++);
  3378. writel(datetime.b.msg_time[1], rwbuffer++);
  3379. writel(ARCMSR_MESSAGE_SYNC_TIMER, reg->drv2iop_doorbell);
  3380. break;
  3381. }
  3382. case ACB_ADAPTER_TYPE_C: {
  3383. struct MessageUnit_C __iomem *reg = pacb->pmuC;
  3384. writel(datetime.b.msg_time[0], &reg->msgcode_rwbuffer[0]);
  3385. writel(datetime.b.msg_time[1], &reg->msgcode_rwbuffer[1]);
  3386. writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, &reg->inbound_msgaddr0);
  3387. writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
  3388. break;
  3389. }
  3390. case ACB_ADAPTER_TYPE_D: {
  3391. uint32_t __iomem *rwbuffer;
  3392. struct MessageUnit_D *reg = pacb->pmuD;
  3393. rwbuffer = reg->msgcode_rwbuffer;
  3394. writel(datetime.b.msg_time[0], rwbuffer++);
  3395. writel(datetime.b.msg_time[1], rwbuffer++);
  3396. writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, reg->inbound_msgaddr0);
  3397. break;
  3398. }
  3399. case ACB_ADAPTER_TYPE_E: {
  3400. struct MessageUnit_E __iomem *reg = pacb->pmuE;
  3401. writel(datetime.b.msg_time[0], &reg->msgcode_rwbuffer[0]);
  3402. writel(datetime.b.msg_time[1], &reg->msgcode_rwbuffer[1]);
  3403. writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, &reg->inbound_msgaddr0);
  3404. pacb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
  3405. writel(pacb->out_doorbell, &reg->iobound_doorbell);
  3406. break;
  3407. }
  3408. }
  3409. if (sys_tz.tz_minuteswest)
  3410. next_time = ARCMSR_HOURS;
  3411. else
  3412. next_time = ARCMSR_MINUTES;
  3413. mod_timer(&pacb->refresh_timer, jiffies + msecs_to_jiffies(next_time));
  3414. }
  3415. static int arcmsr_iop_confirm(struct AdapterControlBlock *acb)
  3416. {
  3417. uint32_t cdb_phyaddr, cdb_phyaddr_hi32;
  3418. dma_addr_t dma_coherent_handle;
  3419. /*
  3420. ********************************************************************
  3421. ** here we need to tell iop 331 our freeccb.HighPart
  3422. ** if freeccb.HighPart is not zero
  3423. ********************************************************************
  3424. */
  3425. switch (acb->adapter_type) {
  3426. case ACB_ADAPTER_TYPE_B:
  3427. case ACB_ADAPTER_TYPE_D:
  3428. dma_coherent_handle = acb->dma_coherent_handle2;
  3429. break;
  3430. case ACB_ADAPTER_TYPE_E:
  3431. dma_coherent_handle = acb->dma_coherent_handle +
  3432. offsetof(struct CommandControlBlock, arcmsr_cdb);
  3433. break;
  3434. default:
  3435. dma_coherent_handle = acb->dma_coherent_handle;
  3436. break;
  3437. }
  3438. cdb_phyaddr = lower_32_bits(dma_coherent_handle);
  3439. cdb_phyaddr_hi32 = upper_32_bits(dma_coherent_handle);
  3440. acb->cdb_phyaddr_hi32 = cdb_phyaddr_hi32;
  3441. /*
  3442. ***********************************************************************
  3443. ** if adapter type B, set window of "post command Q"
  3444. ***********************************************************************
  3445. */
  3446. switch (acb->adapter_type) {
  3447. case ACB_ADAPTER_TYPE_A: {
  3448. if (cdb_phyaddr_hi32 != 0) {
  3449. struct MessageUnit_A __iomem *reg = acb->pmuA;
  3450. writel(ARCMSR_SIGNATURE_SET_CONFIG, \
  3451. &reg->message_rwbuffer[0]);
  3452. writel(cdb_phyaddr_hi32, &reg->message_rwbuffer[1]);
  3453. writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, \
  3454. &reg->inbound_msgaddr0);
  3455. if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
  3456. printk(KERN_NOTICE "arcmsr%d: ""set ccb high \
  3457. part physical address timeout\n",
  3458. acb->host->host_no);
  3459. return 1;
  3460. }
  3461. }
  3462. }
  3463. break;
  3464. case ACB_ADAPTER_TYPE_B: {
  3465. uint32_t __iomem *rwbuffer;
  3466. struct MessageUnit_B *reg = acb->pmuB;
  3467. reg->postq_index = 0;
  3468. reg->doneq_index = 0;
  3469. writel(ARCMSR_MESSAGE_SET_POST_WINDOW, reg->drv2iop_doorbell);
  3470. if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
  3471. printk(KERN_NOTICE "arcmsr%d: cannot set driver mode\n", \
  3472. acb->host->host_no);
  3473. return 1;
  3474. }
  3475. rwbuffer = reg->message_rwbuffer;
  3476. /* driver "set config" signature */
  3477. writel(ARCMSR_SIGNATURE_SET_CONFIG, rwbuffer++);
  3478. /* normal should be zero */
  3479. writel(cdb_phyaddr_hi32, rwbuffer++);
  3480. /* postQ size (256 + 8)*4 */
  3481. writel(cdb_phyaddr, rwbuffer++);
  3482. /* doneQ size (256 + 8)*4 */
  3483. writel(cdb_phyaddr + 1056, rwbuffer++);
  3484. /* ccb maxQ size must be --> [(256 + 8)*4]*/
  3485. writel(1056, rwbuffer);
  3486. writel(ARCMSR_MESSAGE_SET_CONFIG, reg->drv2iop_doorbell);
  3487. if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
  3488. printk(KERN_NOTICE "arcmsr%d: 'set command Q window' \
  3489. timeout \n",acb->host->host_no);
  3490. return 1;
  3491. }
  3492. writel(ARCMSR_MESSAGE_START_DRIVER_MODE, reg->drv2iop_doorbell);
  3493. if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
  3494. pr_err("arcmsr%d: can't set driver mode.\n",
  3495. acb->host->host_no);
  3496. return 1;
  3497. }
  3498. }
  3499. break;
  3500. case ACB_ADAPTER_TYPE_C: {
  3501. if (cdb_phyaddr_hi32 != 0) {
  3502. struct MessageUnit_C __iomem *reg = acb->pmuC;
  3503. printk(KERN_NOTICE "arcmsr%d: cdb_phyaddr_hi32=0x%x\n",
  3504. acb->adapter_index, cdb_phyaddr_hi32);
  3505. writel(ARCMSR_SIGNATURE_SET_CONFIG, &reg->msgcode_rwbuffer[0]);
  3506. writel(cdb_phyaddr_hi32, &reg->msgcode_rwbuffer[1]);
  3507. writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, &reg->inbound_msgaddr0);
  3508. writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
  3509. if (!arcmsr_hbaC_wait_msgint_ready(acb)) {
  3510. printk(KERN_NOTICE "arcmsr%d: 'set command Q window' \
  3511. timeout \n", acb->host->host_no);
  3512. return 1;
  3513. }
  3514. }
  3515. }
  3516. break;
  3517. case ACB_ADAPTER_TYPE_D: {
  3518. uint32_t __iomem *rwbuffer;
  3519. struct MessageUnit_D *reg = acb->pmuD;
  3520. reg->postq_index = 0;
  3521. reg->doneq_index = 0;
  3522. rwbuffer = reg->msgcode_rwbuffer;
  3523. writel(ARCMSR_SIGNATURE_SET_CONFIG, rwbuffer++);
  3524. writel(cdb_phyaddr_hi32, rwbuffer++);
  3525. writel(cdb_phyaddr, rwbuffer++);
  3526. writel(cdb_phyaddr + (ARCMSR_MAX_ARC1214_POSTQUEUE *
  3527. sizeof(struct InBound_SRB)), rwbuffer++);
  3528. writel(0x100, rwbuffer);
  3529. writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, reg->inbound_msgaddr0);
  3530. if (!arcmsr_hbaD_wait_msgint_ready(acb)) {
  3531. pr_notice("arcmsr%d: 'set command Q window' timeout\n",
  3532. acb->host->host_no);
  3533. return 1;
  3534. }
  3535. }
  3536. break;
  3537. case ACB_ADAPTER_TYPE_E: {
  3538. struct MessageUnit_E __iomem *reg = acb->pmuE;
  3539. writel(ARCMSR_SIGNATURE_SET_CONFIG, &reg->msgcode_rwbuffer[0]);
  3540. writel(ARCMSR_SIGNATURE_1884, &reg->msgcode_rwbuffer[1]);
  3541. writel(cdb_phyaddr, &reg->msgcode_rwbuffer[2]);
  3542. writel(cdb_phyaddr_hi32, &reg->msgcode_rwbuffer[3]);
  3543. writel(acb->ccbsize, &reg->msgcode_rwbuffer[4]);
  3544. dma_coherent_handle = acb->dma_coherent_handle2;
  3545. cdb_phyaddr = (uint32_t)(dma_coherent_handle & 0xffffffff);
  3546. cdb_phyaddr_hi32 = (uint32_t)((dma_coherent_handle >> 16) >> 16);
  3547. writel(cdb_phyaddr, &reg->msgcode_rwbuffer[5]);
  3548. writel(cdb_phyaddr_hi32, &reg->msgcode_rwbuffer[6]);
  3549. writel(acb->roundup_ccbsize, &reg->msgcode_rwbuffer[7]);
  3550. writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, &reg->inbound_msgaddr0);
  3551. acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
  3552. writel(acb->out_doorbell, &reg->iobound_doorbell);
  3553. if (!arcmsr_hbaE_wait_msgint_ready(acb)) {
  3554. pr_notice("arcmsr%d: 'set command Q window' timeout \n",
  3555. acb->host->host_no);
  3556. return 1;
  3557. }
  3558. }
  3559. break;
  3560. }
  3561. return 0;
  3562. }
  3563. static void arcmsr_wait_firmware_ready(struct AdapterControlBlock *acb)
  3564. {
  3565. uint32_t firmware_state = 0;
  3566. switch (acb->adapter_type) {
  3567. case ACB_ADAPTER_TYPE_A: {
  3568. struct MessageUnit_A __iomem *reg = acb->pmuA;
  3569. do {
  3570. if (!(acb->acb_flags & ACB_F_IOP_INITED))
  3571. msleep(20);
  3572. firmware_state = readl(&reg->outbound_msgaddr1);
  3573. } while ((firmware_state & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0);
  3574. }
  3575. break;
  3576. case ACB_ADAPTER_TYPE_B: {
  3577. struct MessageUnit_B *reg = acb->pmuB;
  3578. do {
  3579. if (!(acb->acb_flags & ACB_F_IOP_INITED))
  3580. msleep(20);
  3581. firmware_state = readl(reg->iop2drv_doorbell);
  3582. } while ((firmware_state & ARCMSR_MESSAGE_FIRMWARE_OK) == 0);
  3583. writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell);
  3584. }
  3585. break;
  3586. case ACB_ADAPTER_TYPE_C: {
  3587. struct MessageUnit_C __iomem *reg = acb->pmuC;
  3588. do {
  3589. if (!(acb->acb_flags & ACB_F_IOP_INITED))
  3590. msleep(20);
  3591. firmware_state = readl(&reg->outbound_msgaddr1);
  3592. } while ((firmware_state & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0);
  3593. }
  3594. break;
  3595. case ACB_ADAPTER_TYPE_D: {
  3596. struct MessageUnit_D *reg = acb->pmuD;
  3597. do {
  3598. if (!(acb->acb_flags & ACB_F_IOP_INITED))
  3599. msleep(20);
  3600. firmware_state = readl(reg->outbound_msgaddr1);
  3601. } while ((firmware_state &
  3602. ARCMSR_ARC1214_MESSAGE_FIRMWARE_OK) == 0);
  3603. }
  3604. break;
  3605. case ACB_ADAPTER_TYPE_E: {
  3606. struct MessageUnit_E __iomem *reg = acb->pmuE;
  3607. do {
  3608. if (!(acb->acb_flags & ACB_F_IOP_INITED))
  3609. msleep(20);
  3610. firmware_state = readl(&reg->outbound_msgaddr1);
  3611. } while ((firmware_state & ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK) == 0);
  3612. }
  3613. break;
  3614. }
  3615. }
  3616. static void arcmsr_request_device_map(struct timer_list *t)
  3617. {
  3618. struct AdapterControlBlock *acb = from_timer(acb, t, eternal_timer);
  3619. if (unlikely(atomic_read(&acb->rq_map_token) == 0) ||
  3620. (acb->acb_flags & ACB_F_BUS_RESET) ||
  3621. (acb->acb_flags & ACB_F_ABORT)) {
  3622. mod_timer(&acb->eternal_timer,
  3623. jiffies + msecs_to_jiffies(6 * HZ));
  3624. } else {
  3625. acb->fw_flag = FW_NORMAL;
  3626. if (atomic_read(&acb->ante_token_value) ==
  3627. atomic_read(&acb->rq_map_token)) {
  3628. atomic_set(&acb->rq_map_token, 16);
  3629. }
  3630. atomic_set(&acb->ante_token_value,
  3631. atomic_read(&acb->rq_map_token));
  3632. if (atomic_dec_and_test(&acb->rq_map_token)) {
  3633. mod_timer(&acb->eternal_timer, jiffies +
  3634. msecs_to_jiffies(6 * HZ));
  3635. return;
  3636. }
  3637. switch (acb->adapter_type) {
  3638. case ACB_ADAPTER_TYPE_A: {
  3639. struct MessageUnit_A __iomem *reg = acb->pmuA;
  3640. writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
  3641. break;
  3642. }
  3643. case ACB_ADAPTER_TYPE_B: {
  3644. struct MessageUnit_B *reg = acb->pmuB;
  3645. writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell);
  3646. break;
  3647. }
  3648. case ACB_ADAPTER_TYPE_C: {
  3649. struct MessageUnit_C __iomem *reg = acb->pmuC;
  3650. writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
  3651. writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
  3652. break;
  3653. }
  3654. case ACB_ADAPTER_TYPE_D: {
  3655. struct MessageUnit_D *reg = acb->pmuD;
  3656. writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, reg->inbound_msgaddr0);
  3657. break;
  3658. }
  3659. case ACB_ADAPTER_TYPE_E: {
  3660. struct MessageUnit_E __iomem *reg = acb->pmuE;
  3661. writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
  3662. acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
  3663. writel(acb->out_doorbell, &reg->iobound_doorbell);
  3664. break;
  3665. }
  3666. default:
  3667. return;
  3668. }
  3669. acb->acb_flags |= ACB_F_MSG_GET_CONFIG;
  3670. mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
  3671. }
  3672. }
  3673. static void arcmsr_hbaA_start_bgrb(struct AdapterControlBlock *acb)
  3674. {
  3675. struct MessageUnit_A __iomem *reg = acb->pmuA;
  3676. acb->acb_flags |= ACB_F_MSG_START_BGRB;
  3677. writel(ARCMSR_INBOUND_MESG0_START_BGRB, &reg->inbound_msgaddr0);
  3678. if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
  3679. printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
  3680. rebulid' timeout \n", acb->host->host_no);
  3681. }
  3682. }
  3683. static void arcmsr_hbaB_start_bgrb(struct AdapterControlBlock *acb)
  3684. {
  3685. struct MessageUnit_B *reg = acb->pmuB;
  3686. acb->acb_flags |= ACB_F_MSG_START_BGRB;
  3687. writel(ARCMSR_MESSAGE_START_BGRB, reg->drv2iop_doorbell);
  3688. if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
  3689. printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
  3690. rebulid' timeout \n",acb->host->host_no);
  3691. }
  3692. }
  3693. static void arcmsr_hbaC_start_bgrb(struct AdapterControlBlock *pACB)
  3694. {
  3695. struct MessageUnit_C __iomem *phbcmu = pACB->pmuC;
  3696. pACB->acb_flags |= ACB_F_MSG_START_BGRB;
  3697. writel(ARCMSR_INBOUND_MESG0_START_BGRB, &phbcmu->inbound_msgaddr0);
  3698. writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &phbcmu->inbound_doorbell);
  3699. if (!arcmsr_hbaC_wait_msgint_ready(pACB)) {
  3700. printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
  3701. rebulid' timeout \n", pACB->host->host_no);
  3702. }
  3703. return;
  3704. }
  3705. static void arcmsr_hbaD_start_bgrb(struct AdapterControlBlock *pACB)
  3706. {
  3707. struct MessageUnit_D *pmu = pACB->pmuD;
  3708. pACB->acb_flags |= ACB_F_MSG_START_BGRB;
  3709. writel(ARCMSR_INBOUND_MESG0_START_BGRB, pmu->inbound_msgaddr0);
  3710. if (!arcmsr_hbaD_wait_msgint_ready(pACB)) {
  3711. pr_notice("arcmsr%d: wait 'start adapter "
  3712. "background rebulid' timeout\n", pACB->host->host_no);
  3713. }
  3714. }
  3715. static void arcmsr_hbaE_start_bgrb(struct AdapterControlBlock *pACB)
  3716. {
  3717. struct MessageUnit_E __iomem *pmu = pACB->pmuE;
  3718. pACB->acb_flags |= ACB_F_MSG_START_BGRB;
  3719. writel(ARCMSR_INBOUND_MESG0_START_BGRB, &pmu->inbound_msgaddr0);
  3720. pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
  3721. writel(pACB->out_doorbell, &pmu->iobound_doorbell);
  3722. if (!arcmsr_hbaE_wait_msgint_ready(pACB)) {
  3723. pr_notice("arcmsr%d: wait 'start adapter "
  3724. "background rebulid' timeout \n", pACB->host->host_no);
  3725. }
  3726. }
  3727. static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb)
  3728. {
  3729. switch (acb->adapter_type) {
  3730. case ACB_ADAPTER_TYPE_A:
  3731. arcmsr_hbaA_start_bgrb(acb);
  3732. break;
  3733. case ACB_ADAPTER_TYPE_B:
  3734. arcmsr_hbaB_start_bgrb(acb);
  3735. break;
  3736. case ACB_ADAPTER_TYPE_C:
  3737. arcmsr_hbaC_start_bgrb(acb);
  3738. break;
  3739. case ACB_ADAPTER_TYPE_D:
  3740. arcmsr_hbaD_start_bgrb(acb);
  3741. break;
  3742. case ACB_ADAPTER_TYPE_E:
  3743. arcmsr_hbaE_start_bgrb(acb);
  3744. break;
  3745. }
  3746. }
  3747. static void arcmsr_clear_doorbell_queue_buffer(struct AdapterControlBlock *acb)
  3748. {
  3749. switch (acb->adapter_type) {
  3750. case ACB_ADAPTER_TYPE_A: {
  3751. struct MessageUnit_A __iomem *reg = acb->pmuA;
  3752. uint32_t outbound_doorbell;
  3753. /* empty doorbell Qbuffer if door bell ringed */
  3754. outbound_doorbell = readl(&reg->outbound_doorbell);
  3755. /*clear doorbell interrupt */
  3756. writel(outbound_doorbell, &reg->outbound_doorbell);
  3757. writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, &reg->inbound_doorbell);
  3758. }
  3759. break;
  3760. case ACB_ADAPTER_TYPE_B: {
  3761. struct MessageUnit_B *reg = acb->pmuB;
  3762. uint32_t outbound_doorbell, i;
  3763. writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
  3764. writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell);
  3765. /* let IOP know data has been read */
  3766. for(i=0; i < 200; i++) {
  3767. msleep(20);
  3768. outbound_doorbell = readl(reg->iop2drv_doorbell);
  3769. if( outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) {
  3770. writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
  3771. writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell);
  3772. } else
  3773. break;
  3774. }
  3775. }
  3776. break;
  3777. case ACB_ADAPTER_TYPE_C: {
  3778. struct MessageUnit_C __iomem *reg = acb->pmuC;
  3779. uint32_t outbound_doorbell, i;
  3780. /* empty doorbell Qbuffer if door bell ringed */
  3781. outbound_doorbell = readl(&reg->outbound_doorbell);
  3782. writel(outbound_doorbell, &reg->outbound_doorbell_clear);
  3783. writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, &reg->inbound_doorbell);
  3784. for (i = 0; i < 200; i++) {
  3785. msleep(20);
  3786. outbound_doorbell = readl(&reg->outbound_doorbell);
  3787. if (outbound_doorbell &
  3788. ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) {
  3789. writel(outbound_doorbell,
  3790. &reg->outbound_doorbell_clear);
  3791. writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK,
  3792. &reg->inbound_doorbell);
  3793. } else
  3794. break;
  3795. }
  3796. }
  3797. break;
  3798. case ACB_ADAPTER_TYPE_D: {
  3799. struct MessageUnit_D *reg = acb->pmuD;
  3800. uint32_t outbound_doorbell, i;
  3801. /* empty doorbell Qbuffer if door bell ringed */
  3802. outbound_doorbell = readl(reg->outbound_doorbell);
  3803. writel(outbound_doorbell, reg->outbound_doorbell);
  3804. writel(ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ,
  3805. reg->inbound_doorbell);
  3806. for (i = 0; i < 200; i++) {
  3807. msleep(20);
  3808. outbound_doorbell = readl(reg->outbound_doorbell);
  3809. if (outbound_doorbell &
  3810. ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK) {
  3811. writel(outbound_doorbell,
  3812. reg->outbound_doorbell);
  3813. writel(ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ,
  3814. reg->inbound_doorbell);
  3815. } else
  3816. break;
  3817. }
  3818. }
  3819. break;
  3820. case ACB_ADAPTER_TYPE_E: {
  3821. struct MessageUnit_E __iomem *reg = acb->pmuE;
  3822. uint32_t i, tmp;
  3823. acb->in_doorbell = readl(&reg->iobound_doorbell);
  3824. writel(0, &reg->host_int_status); /*clear interrupt*/
  3825. acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK;
  3826. writel(acb->out_doorbell, &reg->iobound_doorbell);
  3827. for(i=0; i < 200; i++) {
  3828. msleep(20);
  3829. tmp = acb->in_doorbell;
  3830. acb->in_doorbell = readl(&reg->iobound_doorbell);
  3831. if((tmp ^ acb->in_doorbell) & ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK) {
  3832. writel(0, &reg->host_int_status); /*clear interrupt*/
  3833. acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK;
  3834. writel(acb->out_doorbell, &reg->iobound_doorbell);
  3835. } else
  3836. break;
  3837. }
  3838. }
  3839. break;
  3840. }
  3841. }
  3842. static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb)
  3843. {
  3844. switch (acb->adapter_type) {
  3845. case ACB_ADAPTER_TYPE_A:
  3846. return;
  3847. case ACB_ADAPTER_TYPE_B:
  3848. {
  3849. struct MessageUnit_B *reg = acb->pmuB;
  3850. writel(ARCMSR_MESSAGE_ACTIVE_EOI_MODE, reg->drv2iop_doorbell);
  3851. if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
  3852. printk(KERN_NOTICE "ARCMSR IOP enables EOI_MODE TIMEOUT");
  3853. return;
  3854. }
  3855. }
  3856. break;
  3857. case ACB_ADAPTER_TYPE_C:
  3858. return;
  3859. }
  3860. return;
  3861. }
  3862. static void arcmsr_hardware_reset(struct AdapterControlBlock *acb)
  3863. {
  3864. uint8_t value[64];
  3865. int i, count = 0;
  3866. struct MessageUnit_A __iomem *pmuA = acb->pmuA;
  3867. struct MessageUnit_C __iomem *pmuC = acb->pmuC;
  3868. struct MessageUnit_D *pmuD = acb->pmuD;
  3869. /* backup pci config data */
  3870. printk(KERN_NOTICE "arcmsr%d: executing hw bus reset .....\n", acb->host->host_no);
  3871. for (i = 0; i < 64; i++) {
  3872. pci_read_config_byte(acb->pdev, i, &value[i]);
  3873. }
  3874. /* hardware reset signal */
  3875. if (acb->dev_id == 0x1680) {
  3876. writel(ARCMSR_ARC1680_BUS_RESET, &pmuA->reserved1[0]);
  3877. } else if (acb->dev_id == 0x1880) {
  3878. do {
  3879. count++;
  3880. writel(0xF, &pmuC->write_sequence);
  3881. writel(0x4, &pmuC->write_sequence);
  3882. writel(0xB, &pmuC->write_sequence);
  3883. writel(0x2, &pmuC->write_sequence);
  3884. writel(0x7, &pmuC->write_sequence);
  3885. writel(0xD, &pmuC->write_sequence);
  3886. } while (((readl(&pmuC->host_diagnostic) & ARCMSR_ARC1880_DiagWrite_ENABLE) == 0) && (count < 5));
  3887. writel(ARCMSR_ARC1880_RESET_ADAPTER, &pmuC->host_diagnostic);
  3888. } else if (acb->dev_id == 0x1884) {
  3889. struct MessageUnit_E __iomem *pmuE = acb->pmuE;
  3890. do {
  3891. count++;
  3892. writel(0x4, &pmuE->write_sequence_3xxx);
  3893. writel(0xB, &pmuE->write_sequence_3xxx);
  3894. writel(0x2, &pmuE->write_sequence_3xxx);
  3895. writel(0x7, &pmuE->write_sequence_3xxx);
  3896. writel(0xD, &pmuE->write_sequence_3xxx);
  3897. mdelay(10);
  3898. } while (((readl(&pmuE->host_diagnostic_3xxx) &
  3899. ARCMSR_ARC1884_DiagWrite_ENABLE) == 0) && (count < 5));
  3900. writel(ARCMSR_ARC188X_RESET_ADAPTER, &pmuE->host_diagnostic_3xxx);
  3901. } else if (acb->dev_id == 0x1214) {
  3902. writel(0x20, pmuD->reset_request);
  3903. } else {
  3904. pci_write_config_byte(acb->pdev, 0x84, 0x20);
  3905. }
  3906. msleep(2000);
  3907. /* write back pci config data */
  3908. for (i = 0; i < 64; i++) {
  3909. pci_write_config_byte(acb->pdev, i, value[i]);
  3910. }
  3911. msleep(1000);
  3912. return;
  3913. }
  3914. static bool arcmsr_reset_in_progress(struct AdapterControlBlock *acb)
  3915. {
  3916. bool rtn = true;
  3917. switch(acb->adapter_type) {
  3918. case ACB_ADAPTER_TYPE_A:{
  3919. struct MessageUnit_A __iomem *reg = acb->pmuA;
  3920. rtn = ((readl(&reg->outbound_msgaddr1) &
  3921. ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0) ? true : false;
  3922. }
  3923. break;
  3924. case ACB_ADAPTER_TYPE_B:{
  3925. struct MessageUnit_B *reg = acb->pmuB;
  3926. rtn = ((readl(reg->iop2drv_doorbell) &
  3927. ARCMSR_MESSAGE_FIRMWARE_OK) == 0) ? true : false;
  3928. }
  3929. break;
  3930. case ACB_ADAPTER_TYPE_C:{
  3931. struct MessageUnit_C __iomem *reg = acb->pmuC;
  3932. rtn = (readl(&reg->host_diagnostic) & 0x04) ? true : false;
  3933. }
  3934. break;
  3935. case ACB_ADAPTER_TYPE_D:{
  3936. struct MessageUnit_D *reg = acb->pmuD;
  3937. rtn = ((readl(reg->sample_at_reset) & 0x80) == 0) ?
  3938. true : false;
  3939. }
  3940. break;
  3941. case ACB_ADAPTER_TYPE_E:{
  3942. struct MessageUnit_E __iomem *reg = acb->pmuE;
  3943. rtn = (readl(&reg->host_diagnostic_3xxx) &
  3944. ARCMSR_ARC188X_RESET_ADAPTER) ? true : false;
  3945. }
  3946. break;
  3947. }
  3948. return rtn;
  3949. }
  3950. static void arcmsr_iop_init(struct AdapterControlBlock *acb)
  3951. {
  3952. uint32_t intmask_org;
  3953. /* disable all outbound interrupt */
  3954. intmask_org = arcmsr_disable_outbound_ints(acb);
  3955. arcmsr_wait_firmware_ready(acb);
  3956. arcmsr_iop_confirm(acb);
  3957. /*start background rebuild*/
  3958. arcmsr_start_adapter_bgrb(acb);
  3959. /* empty doorbell Qbuffer if door bell ringed */
  3960. arcmsr_clear_doorbell_queue_buffer(acb);
  3961. arcmsr_enable_eoi_mode(acb);
  3962. /* enable outbound Post Queue,outbound doorbell Interrupt */
  3963. arcmsr_enable_outbound_ints(acb, intmask_org);
  3964. acb->acb_flags |= ACB_F_IOP_INITED;
  3965. }
  3966. static uint8_t arcmsr_iop_reset(struct AdapterControlBlock *acb)
  3967. {
  3968. struct CommandControlBlock *ccb;
  3969. uint32_t intmask_org;
  3970. uint8_t rtnval = 0x00;
  3971. int i = 0;
  3972. unsigned long flags;
  3973. if (atomic_read(&acb->ccboutstandingcount) != 0) {
  3974. /* disable all outbound interrupt */
  3975. intmask_org = arcmsr_disable_outbound_ints(acb);
  3976. /* talk to iop 331 outstanding command aborted */
  3977. rtnval = arcmsr_abort_allcmd(acb);
  3978. /* clear all outbound posted Q */
  3979. arcmsr_done4abort_postqueue(acb);
  3980. for (i = 0; i < acb->maxFreeCCB; i++) {
  3981. ccb = acb->pccb_pool[i];
  3982. if (ccb->startdone == ARCMSR_CCB_START) {
  3983. scsi_dma_unmap(ccb->pcmd);
  3984. ccb->startdone = ARCMSR_CCB_DONE;
  3985. ccb->ccb_flags = 0;
  3986. spin_lock_irqsave(&acb->ccblist_lock, flags);
  3987. list_add_tail(&ccb->list, &acb->ccb_free_list);
  3988. spin_unlock_irqrestore(&acb->ccblist_lock, flags);
  3989. }
  3990. }
  3991. atomic_set(&acb->ccboutstandingcount, 0);
  3992. /* enable all outbound interrupt */
  3993. arcmsr_enable_outbound_ints(acb, intmask_org);
  3994. return rtnval;
  3995. }
  3996. return rtnval;
  3997. }
  3998. static int arcmsr_bus_reset(struct scsi_cmnd *cmd)
  3999. {
  4000. struct AdapterControlBlock *acb;
  4001. int retry_count = 0;
  4002. int rtn = FAILED;
  4003. acb = (struct AdapterControlBlock *) cmd->device->host->hostdata;
  4004. if (acb->acb_flags & ACB_F_ADAPTER_REMOVED)
  4005. return SUCCESS;
  4006. pr_notice("arcmsr: executing bus reset eh.....num_resets = %d,"
  4007. " num_aborts = %d \n", acb->num_resets, acb->num_aborts);
  4008. acb->num_resets++;
  4009. if (acb->acb_flags & ACB_F_BUS_RESET) {
  4010. long timeout;
  4011. pr_notice("arcmsr: there is a bus reset eh proceeding...\n");
  4012. timeout = wait_event_timeout(wait_q, (acb->acb_flags
  4013. & ACB_F_BUS_RESET) == 0, 220 * HZ);
  4014. if (timeout)
  4015. return SUCCESS;
  4016. }
  4017. acb->acb_flags |= ACB_F_BUS_RESET;
  4018. if (!arcmsr_iop_reset(acb)) {
  4019. arcmsr_hardware_reset(acb);
  4020. acb->acb_flags &= ~ACB_F_IOP_INITED;
  4021. wait_reset_done:
  4022. ssleep(ARCMSR_SLEEPTIME);
  4023. if (arcmsr_reset_in_progress(acb)) {
  4024. if (retry_count > ARCMSR_RETRYCOUNT) {
  4025. acb->fw_flag = FW_DEADLOCK;
  4026. pr_notice("arcmsr%d: waiting for hw bus reset"
  4027. " return, RETRY TERMINATED!!\n",
  4028. acb->host->host_no);
  4029. return FAILED;
  4030. }
  4031. retry_count++;
  4032. goto wait_reset_done;
  4033. }
  4034. arcmsr_iop_init(acb);
  4035. atomic_set(&acb->rq_map_token, 16);
  4036. atomic_set(&acb->ante_token_value, 16);
  4037. acb->fw_flag = FW_NORMAL;
  4038. mod_timer(&acb->eternal_timer, jiffies +
  4039. msecs_to_jiffies(6 * HZ));
  4040. acb->acb_flags &= ~ACB_F_BUS_RESET;
  4041. rtn = SUCCESS;
  4042. pr_notice("arcmsr: scsi bus reset eh returns with success\n");
  4043. } else {
  4044. acb->acb_flags &= ~ACB_F_BUS_RESET;
  4045. atomic_set(&acb->rq_map_token, 16);
  4046. atomic_set(&acb->ante_token_value, 16);
  4047. acb->fw_flag = FW_NORMAL;
  4048. mod_timer(&acb->eternal_timer, jiffies +
  4049. msecs_to_jiffies(6 * HZ));
  4050. rtn = SUCCESS;
  4051. }
  4052. return rtn;
  4053. }
  4054. static int arcmsr_abort_one_cmd(struct AdapterControlBlock *acb,
  4055. struct CommandControlBlock *ccb)
  4056. {
  4057. int rtn;
  4058. rtn = arcmsr_polling_ccbdone(acb, ccb);
  4059. return rtn;
  4060. }
  4061. static int arcmsr_abort(struct scsi_cmnd *cmd)
  4062. {
  4063. struct AdapterControlBlock *acb =
  4064. (struct AdapterControlBlock *)cmd->device->host->hostdata;
  4065. int i = 0;
  4066. int rtn = FAILED;
  4067. uint32_t intmask_org;
  4068. if (acb->acb_flags & ACB_F_ADAPTER_REMOVED)
  4069. return SUCCESS;
  4070. printk(KERN_NOTICE
  4071. "arcmsr%d: abort device command of scsi id = %d lun = %d\n",
  4072. acb->host->host_no, cmd->device->id, (u32)cmd->device->lun);
  4073. acb->acb_flags |= ACB_F_ABORT;
  4074. acb->num_aborts++;
  4075. /*
  4076. ************************************************
  4077. ** the all interrupt service routine is locked
  4078. ** we need to handle it as soon as possible and exit
  4079. ************************************************
  4080. */
  4081. if (!atomic_read(&acb->ccboutstandingcount)) {
  4082. acb->acb_flags &= ~ACB_F_ABORT;
  4083. return rtn;
  4084. }
  4085. intmask_org = arcmsr_disable_outbound_ints(acb);
  4086. for (i = 0; i < acb->maxFreeCCB; i++) {
  4087. struct CommandControlBlock *ccb = acb->pccb_pool[i];
  4088. if (ccb->startdone == ARCMSR_CCB_START && ccb->pcmd == cmd) {
  4089. ccb->startdone = ARCMSR_CCB_ABORTED;
  4090. rtn = arcmsr_abort_one_cmd(acb, ccb);
  4091. break;
  4092. }
  4093. }
  4094. acb->acb_flags &= ~ACB_F_ABORT;
  4095. arcmsr_enable_outbound_ints(acb, intmask_org);
  4096. return rtn;
  4097. }
  4098. static const char *arcmsr_info(struct Scsi_Host *host)
  4099. {
  4100. struct AdapterControlBlock *acb =
  4101. (struct AdapterControlBlock *) host->hostdata;
  4102. static char buf[256];
  4103. char *type;
  4104. int raid6 = 1;
  4105. switch (acb->pdev->device) {
  4106. case PCI_DEVICE_ID_ARECA_1110:
  4107. case PCI_DEVICE_ID_ARECA_1200:
  4108. case PCI_DEVICE_ID_ARECA_1202:
  4109. case PCI_DEVICE_ID_ARECA_1210:
  4110. raid6 = 0;
  4111. /*FALLTHRU*/
  4112. case PCI_DEVICE_ID_ARECA_1120:
  4113. case PCI_DEVICE_ID_ARECA_1130:
  4114. case PCI_DEVICE_ID_ARECA_1160:
  4115. case PCI_DEVICE_ID_ARECA_1170:
  4116. case PCI_DEVICE_ID_ARECA_1201:
  4117. case PCI_DEVICE_ID_ARECA_1203:
  4118. case PCI_DEVICE_ID_ARECA_1220:
  4119. case PCI_DEVICE_ID_ARECA_1230:
  4120. case PCI_DEVICE_ID_ARECA_1260:
  4121. case PCI_DEVICE_ID_ARECA_1270:
  4122. case PCI_DEVICE_ID_ARECA_1280:
  4123. type = "SATA";
  4124. break;
  4125. case PCI_DEVICE_ID_ARECA_1214:
  4126. case PCI_DEVICE_ID_ARECA_1380:
  4127. case PCI_DEVICE_ID_ARECA_1381:
  4128. case PCI_DEVICE_ID_ARECA_1680:
  4129. case PCI_DEVICE_ID_ARECA_1681:
  4130. case PCI_DEVICE_ID_ARECA_1880:
  4131. case PCI_DEVICE_ID_ARECA_1884:
  4132. type = "SAS/SATA";
  4133. break;
  4134. default:
  4135. type = "unknown";
  4136. raid6 = 0;
  4137. break;
  4138. }
  4139. sprintf(buf, "Areca %s RAID Controller %s\narcmsr version %s\n",
  4140. type, raid6 ? "(RAID6 capable)" : "", ARCMSR_DRIVER_VERSION);
  4141. return buf;
  4142. }