aic79xx_reg.h_shipped 44 KB

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  1. /*
  2. * DO NOT EDIT - This file is automatically generated
  3. * from the following source files:
  4. *
  5. * $Id: //depot/aic7xxx/aic7xxx/aic79xx.seq#120 $
  6. * $Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#77 $
  7. */
  8. typedef int (ahd_reg_print_t)(u_int, u_int *, u_int);
  9. typedef struct ahd_reg_parse_entry {
  10. char *name;
  11. uint8_t value;
  12. uint8_t mask;
  13. } ahd_reg_parse_entry_t;
  14. #if AIC_DEBUG_REGISTERS
  15. ahd_reg_print_t ahd_intstat_print;
  16. #else
  17. #define ahd_intstat_print(regvalue, cur_col, wrap) \
  18. ahd_print_register(NULL, 0, "INTSTAT", 0x01, regvalue, cur_col, wrap)
  19. #endif
  20. #if AIC_DEBUG_REGISTERS
  21. ahd_reg_print_t ahd_hs_mailbox_print;
  22. #else
  23. #define ahd_hs_mailbox_print(regvalue, cur_col, wrap) \
  24. ahd_print_register(NULL, 0, "HS_MAILBOX", 0x0b, regvalue, cur_col, wrap)
  25. #endif
  26. #if AIC_DEBUG_REGISTERS
  27. ahd_reg_print_t ahd_seqintstat_print;
  28. #else
  29. #define ahd_seqintstat_print(regvalue, cur_col, wrap) \
  30. ahd_print_register(NULL, 0, "SEQINTSTAT", 0x0c, regvalue, cur_col, wrap)
  31. #endif
  32. #if AIC_DEBUG_REGISTERS
  33. ahd_reg_print_t ahd_intctl_print;
  34. #else
  35. #define ahd_intctl_print(regvalue, cur_col, wrap) \
  36. ahd_print_register(NULL, 0, "INTCTL", 0x18, regvalue, cur_col, wrap)
  37. #endif
  38. #if AIC_DEBUG_REGISTERS
  39. ahd_reg_print_t ahd_dfcntrl_print;
  40. #else
  41. #define ahd_dfcntrl_print(regvalue, cur_col, wrap) \
  42. ahd_print_register(NULL, 0, "DFCNTRL", 0x19, regvalue, cur_col, wrap)
  43. #endif
  44. #if AIC_DEBUG_REGISTERS
  45. ahd_reg_print_t ahd_dfstatus_print;
  46. #else
  47. #define ahd_dfstatus_print(regvalue, cur_col, wrap) \
  48. ahd_print_register(NULL, 0, "DFSTATUS", 0x1a, regvalue, cur_col, wrap)
  49. #endif
  50. #if AIC_DEBUG_REGISTERS
  51. ahd_reg_print_t ahd_sg_cache_shadow_print;
  52. #else
  53. #define ahd_sg_cache_shadow_print(regvalue, cur_col, wrap) \
  54. ahd_print_register(NULL, 0, "SG_CACHE_SHADOW", 0x1b, regvalue, cur_col, wrap)
  55. #endif
  56. #if AIC_DEBUG_REGISTERS
  57. ahd_reg_print_t ahd_scsiseq0_print;
  58. #else
  59. #define ahd_scsiseq0_print(regvalue, cur_col, wrap) \
  60. ahd_print_register(NULL, 0, "SCSISEQ0", 0x3a, regvalue, cur_col, wrap)
  61. #endif
  62. #if AIC_DEBUG_REGISTERS
  63. ahd_reg_print_t ahd_scsiseq1_print;
  64. #else
  65. #define ahd_scsiseq1_print(regvalue, cur_col, wrap) \
  66. ahd_print_register(NULL, 0, "SCSISEQ1", 0x3b, regvalue, cur_col, wrap)
  67. #endif
  68. #if AIC_DEBUG_REGISTERS
  69. ahd_reg_print_t ahd_dffstat_print;
  70. #else
  71. #define ahd_dffstat_print(regvalue, cur_col, wrap) \
  72. ahd_print_register(NULL, 0, "DFFSTAT", 0x3f, regvalue, cur_col, wrap)
  73. #endif
  74. #if AIC_DEBUG_REGISTERS
  75. ahd_reg_print_t ahd_scsisigi_print;
  76. #else
  77. #define ahd_scsisigi_print(regvalue, cur_col, wrap) \
  78. ahd_print_register(NULL, 0, "SCSISIGI", 0x41, regvalue, cur_col, wrap)
  79. #endif
  80. #if AIC_DEBUG_REGISTERS
  81. ahd_reg_print_t ahd_scsiphase_print;
  82. #else
  83. #define ahd_scsiphase_print(regvalue, cur_col, wrap) \
  84. ahd_print_register(NULL, 0, "SCSIPHASE", 0x42, regvalue, cur_col, wrap)
  85. #endif
  86. #if AIC_DEBUG_REGISTERS
  87. ahd_reg_print_t ahd_scsibus_print;
  88. #else
  89. #define ahd_scsibus_print(regvalue, cur_col, wrap) \
  90. ahd_print_register(NULL, 0, "SCSIBUS", 0x46, regvalue, cur_col, wrap)
  91. #endif
  92. #if AIC_DEBUG_REGISTERS
  93. ahd_reg_print_t ahd_selid_print;
  94. #else
  95. #define ahd_selid_print(regvalue, cur_col, wrap) \
  96. ahd_print_register(NULL, 0, "SELID", 0x49, regvalue, cur_col, wrap)
  97. #endif
  98. #if AIC_DEBUG_REGISTERS
  99. ahd_reg_print_t ahd_simode0_print;
  100. #else
  101. #define ahd_simode0_print(regvalue, cur_col, wrap) \
  102. ahd_print_register(NULL, 0, "SIMODE0", 0x4b, regvalue, cur_col, wrap)
  103. #endif
  104. #if AIC_DEBUG_REGISTERS
  105. ahd_reg_print_t ahd_sstat0_print;
  106. #else
  107. #define ahd_sstat0_print(regvalue, cur_col, wrap) \
  108. ahd_print_register(NULL, 0, "SSTAT0", 0x4b, regvalue, cur_col, wrap)
  109. #endif
  110. #if AIC_DEBUG_REGISTERS
  111. ahd_reg_print_t ahd_sstat1_print;
  112. #else
  113. #define ahd_sstat1_print(regvalue, cur_col, wrap) \
  114. ahd_print_register(NULL, 0, "SSTAT1", 0x4c, regvalue, cur_col, wrap)
  115. #endif
  116. #if AIC_DEBUG_REGISTERS
  117. ahd_reg_print_t ahd_sstat2_print;
  118. #else
  119. #define ahd_sstat2_print(regvalue, cur_col, wrap) \
  120. ahd_print_register(NULL, 0, "SSTAT2", 0x4d, regvalue, cur_col, wrap)
  121. #endif
  122. #if AIC_DEBUG_REGISTERS
  123. ahd_reg_print_t ahd_perrdiag_print;
  124. #else
  125. #define ahd_perrdiag_print(regvalue, cur_col, wrap) \
  126. ahd_print_register(NULL, 0, "PERRDIAG", 0x4e, regvalue, cur_col, wrap)
  127. #endif
  128. #if AIC_DEBUG_REGISTERS
  129. ahd_reg_print_t ahd_soffcnt_print;
  130. #else
  131. #define ahd_soffcnt_print(regvalue, cur_col, wrap) \
  132. ahd_print_register(NULL, 0, "SOFFCNT", 0x4f, regvalue, cur_col, wrap)
  133. #endif
  134. #if AIC_DEBUG_REGISTERS
  135. ahd_reg_print_t ahd_lqistat0_print;
  136. #else
  137. #define ahd_lqistat0_print(regvalue, cur_col, wrap) \
  138. ahd_print_register(NULL, 0, "LQISTAT0", 0x50, regvalue, cur_col, wrap)
  139. #endif
  140. #if AIC_DEBUG_REGISTERS
  141. ahd_reg_print_t ahd_lqistat1_print;
  142. #else
  143. #define ahd_lqistat1_print(regvalue, cur_col, wrap) \
  144. ahd_print_register(NULL, 0, "LQISTAT1", 0x51, regvalue, cur_col, wrap)
  145. #endif
  146. #if AIC_DEBUG_REGISTERS
  147. ahd_reg_print_t ahd_lqistat2_print;
  148. #else
  149. #define ahd_lqistat2_print(regvalue, cur_col, wrap) \
  150. ahd_print_register(NULL, 0, "LQISTAT2", 0x52, regvalue, cur_col, wrap)
  151. #endif
  152. #if AIC_DEBUG_REGISTERS
  153. ahd_reg_print_t ahd_sstat3_print;
  154. #else
  155. #define ahd_sstat3_print(regvalue, cur_col, wrap) \
  156. ahd_print_register(NULL, 0, "SSTAT3", 0x53, regvalue, cur_col, wrap)
  157. #endif
  158. #if AIC_DEBUG_REGISTERS
  159. ahd_reg_print_t ahd_lqostat0_print;
  160. #else
  161. #define ahd_lqostat0_print(regvalue, cur_col, wrap) \
  162. ahd_print_register(NULL, 0, "LQOSTAT0", 0x54, regvalue, cur_col, wrap)
  163. #endif
  164. #if AIC_DEBUG_REGISTERS
  165. ahd_reg_print_t ahd_lqostat1_print;
  166. #else
  167. #define ahd_lqostat1_print(regvalue, cur_col, wrap) \
  168. ahd_print_register(NULL, 0, "LQOSTAT1", 0x55, regvalue, cur_col, wrap)
  169. #endif
  170. #if AIC_DEBUG_REGISTERS
  171. ahd_reg_print_t ahd_lqostat2_print;
  172. #else
  173. #define ahd_lqostat2_print(regvalue, cur_col, wrap) \
  174. ahd_print_register(NULL, 0, "LQOSTAT2", 0x56, regvalue, cur_col, wrap)
  175. #endif
  176. #if AIC_DEBUG_REGISTERS
  177. ahd_reg_print_t ahd_simode1_print;
  178. #else
  179. #define ahd_simode1_print(regvalue, cur_col, wrap) \
  180. ahd_print_register(NULL, 0, "SIMODE1", 0x57, regvalue, cur_col, wrap)
  181. #endif
  182. #if AIC_DEBUG_REGISTERS
  183. ahd_reg_print_t ahd_dffsxfrctl_print;
  184. #else
  185. #define ahd_dffsxfrctl_print(regvalue, cur_col, wrap) \
  186. ahd_print_register(NULL, 0, "DFFSXFRCTL", 0x5a, regvalue, cur_col, wrap)
  187. #endif
  188. #if AIC_DEBUG_REGISTERS
  189. ahd_reg_print_t ahd_seqintsrc_print;
  190. #else
  191. #define ahd_seqintsrc_print(regvalue, cur_col, wrap) \
  192. ahd_print_register(NULL, 0, "SEQINTSRC", 0x5b, regvalue, cur_col, wrap)
  193. #endif
  194. #if AIC_DEBUG_REGISTERS
  195. ahd_reg_print_t ahd_seqimode_print;
  196. #else
  197. #define ahd_seqimode_print(regvalue, cur_col, wrap) \
  198. ahd_print_register(NULL, 0, "SEQIMODE", 0x5c, regvalue, cur_col, wrap)
  199. #endif
  200. #if AIC_DEBUG_REGISTERS
  201. ahd_reg_print_t ahd_mdffstat_print;
  202. #else
  203. #define ahd_mdffstat_print(regvalue, cur_col, wrap) \
  204. ahd_print_register(NULL, 0, "MDFFSTAT", 0x5d, regvalue, cur_col, wrap)
  205. #endif
  206. #if AIC_DEBUG_REGISTERS
  207. ahd_reg_print_t ahd_seloid_print;
  208. #else
  209. #define ahd_seloid_print(regvalue, cur_col, wrap) \
  210. ahd_print_register(NULL, 0, "SELOID", 0x6b, regvalue, cur_col, wrap)
  211. #endif
  212. #if AIC_DEBUG_REGISTERS
  213. ahd_reg_print_t ahd_sg_state_print;
  214. #else
  215. #define ahd_sg_state_print(regvalue, cur_col, wrap) \
  216. ahd_print_register(NULL, 0, "SG_STATE", 0xa6, regvalue, cur_col, wrap)
  217. #endif
  218. #if AIC_DEBUG_REGISTERS
  219. ahd_reg_print_t ahd_ccscbctl_print;
  220. #else
  221. #define ahd_ccscbctl_print(regvalue, cur_col, wrap) \
  222. ahd_print_register(NULL, 0, "CCSCBCTL", 0xad, regvalue, cur_col, wrap)
  223. #endif
  224. #if AIC_DEBUG_REGISTERS
  225. ahd_reg_print_t ahd_ccsgctl_print;
  226. #else
  227. #define ahd_ccsgctl_print(regvalue, cur_col, wrap) \
  228. ahd_print_register(NULL, 0, "CCSGCTL", 0xad, regvalue, cur_col, wrap)
  229. #endif
  230. #if AIC_DEBUG_REGISTERS
  231. ahd_reg_print_t ahd_seqctl0_print;
  232. #else
  233. #define ahd_seqctl0_print(regvalue, cur_col, wrap) \
  234. ahd_print_register(NULL, 0, "SEQCTL0", 0xd6, regvalue, cur_col, wrap)
  235. #endif
  236. #if AIC_DEBUG_REGISTERS
  237. ahd_reg_print_t ahd_seqintctl_print;
  238. #else
  239. #define ahd_seqintctl_print(regvalue, cur_col, wrap) \
  240. ahd_print_register(NULL, 0, "SEQINTCTL", 0xd9, regvalue, cur_col, wrap)
  241. #endif
  242. #if AIC_DEBUG_REGISTERS
  243. ahd_reg_print_t ahd_sram_base_print;
  244. #else
  245. #define ahd_sram_base_print(regvalue, cur_col, wrap) \
  246. ahd_print_register(NULL, 0, "SRAM_BASE", 0x100, regvalue, cur_col, wrap)
  247. #endif
  248. #if AIC_DEBUG_REGISTERS
  249. ahd_reg_print_t ahd_qfreeze_count_print;
  250. #else
  251. #define ahd_qfreeze_count_print(regvalue, cur_col, wrap) \
  252. ahd_print_register(NULL, 0, "QFREEZE_COUNT", 0x132, regvalue, cur_col, wrap)
  253. #endif
  254. #if AIC_DEBUG_REGISTERS
  255. ahd_reg_print_t ahd_kernel_qfreeze_count_print;
  256. #else
  257. #define ahd_kernel_qfreeze_count_print(regvalue, cur_col, wrap) \
  258. ahd_print_register(NULL, 0, "KERNEL_QFREEZE_COUNT", 0x134, regvalue, cur_col, wrap)
  259. #endif
  260. #if AIC_DEBUG_REGISTERS
  261. ahd_reg_print_t ahd_saved_mode_print;
  262. #else
  263. #define ahd_saved_mode_print(regvalue, cur_col, wrap) \
  264. ahd_print_register(NULL, 0, "SAVED_MODE", 0x136, regvalue, cur_col, wrap)
  265. #endif
  266. #if AIC_DEBUG_REGISTERS
  267. ahd_reg_print_t ahd_seq_flags_print;
  268. #else
  269. #define ahd_seq_flags_print(regvalue, cur_col, wrap) \
  270. ahd_print_register(NULL, 0, "SEQ_FLAGS", 0x139, regvalue, cur_col, wrap)
  271. #endif
  272. #if AIC_DEBUG_REGISTERS
  273. ahd_reg_print_t ahd_lastphase_print;
  274. #else
  275. #define ahd_lastphase_print(regvalue, cur_col, wrap) \
  276. ahd_print_register(NULL, 0, "LASTPHASE", 0x13c, regvalue, cur_col, wrap)
  277. #endif
  278. #if AIC_DEBUG_REGISTERS
  279. ahd_reg_print_t ahd_seq_flags2_print;
  280. #else
  281. #define ahd_seq_flags2_print(regvalue, cur_col, wrap) \
  282. ahd_print_register(NULL, 0, "SEQ_FLAGS2", 0x14d, regvalue, cur_col, wrap)
  283. #endif
  284. #if AIC_DEBUG_REGISTERS
  285. ahd_reg_print_t ahd_mk_message_scb_print;
  286. #else
  287. #define ahd_mk_message_scb_print(regvalue, cur_col, wrap) \
  288. ahd_print_register(NULL, 0, "MK_MESSAGE_SCB", 0x160, regvalue, cur_col, wrap)
  289. #endif
  290. #if AIC_DEBUG_REGISTERS
  291. ahd_reg_print_t ahd_mk_message_scsiid_print;
  292. #else
  293. #define ahd_mk_message_scsiid_print(regvalue, cur_col, wrap) \
  294. ahd_print_register(NULL, 0, "MK_MESSAGE_SCSIID", 0x162, regvalue, cur_col, wrap)
  295. #endif
  296. #if AIC_DEBUG_REGISTERS
  297. ahd_reg_print_t ahd_scb_base_print;
  298. #else
  299. #define ahd_scb_base_print(regvalue, cur_col, wrap) \
  300. ahd_print_register(NULL, 0, "SCB_BASE", 0x180, regvalue, cur_col, wrap)
  301. #endif
  302. #if AIC_DEBUG_REGISTERS
  303. ahd_reg_print_t ahd_scb_control_print;
  304. #else
  305. #define ahd_scb_control_print(regvalue, cur_col, wrap) \
  306. ahd_print_register(NULL, 0, "SCB_CONTROL", 0x192, regvalue, cur_col, wrap)
  307. #endif
  308. #if AIC_DEBUG_REGISTERS
  309. ahd_reg_print_t ahd_scb_scsiid_print;
  310. #else
  311. #define ahd_scb_scsiid_print(regvalue, cur_col, wrap) \
  312. ahd_print_register(NULL, 0, "SCB_SCSIID", 0x193, regvalue, cur_col, wrap)
  313. #endif
  314. #define MODE_PTR 0x00
  315. #define DST_MODE 0x70
  316. #define SRC_MODE 0x07
  317. #define INTSTAT 0x01
  318. #define INT_PEND 0xff
  319. #define HWERRINT 0x80
  320. #define BRKADRINT 0x40
  321. #define SWTMINT 0x20
  322. #define PCIINT 0x10
  323. #define SCSIINT 0x08
  324. #define SEQINT 0x04
  325. #define CMDCMPLT 0x02
  326. #define SPLTINT 0x01
  327. #define SEQINTCODE 0x02
  328. #define BAD_SCB_STATUS 0x1a
  329. #define SAW_HWERR 0x19
  330. #define TRACEPOINT3 0x18
  331. #define TRACEPOINT2 0x17
  332. #define TRACEPOINT1 0x16
  333. #define TRACEPOINT0 0x15
  334. #define TASKMGMT_CMD_CMPLT_OKAY 0x14
  335. #define TASKMGMT_FUNC_COMPLETE 0x13
  336. #define ENTERING_NONPACK 0x12
  337. #define CFG4OVERRUN 0x11
  338. #define STATUS_OVERRUN 0x10
  339. #define CFG4ISTAT_INTR 0x0f
  340. #define INVALID_SEQINT 0x0e
  341. #define ILLEGAL_PHASE 0x0d
  342. #define DUMP_CARD_STATE 0x0c
  343. #define MISSED_BUSFREE 0x0b
  344. #define MKMSG_FAILED 0x0a
  345. #define DATA_OVERRUN 0x09
  346. #define BAD_STATUS 0x08
  347. #define HOST_MSG_LOOP 0x07
  348. #define PDATA_REINIT 0x06
  349. #define IGN_WIDE_RES 0x05
  350. #define NO_MATCH 0x04
  351. #define PROTO_VIOLATION 0x03
  352. #define SEND_REJECT 0x02
  353. #define BAD_PHASE 0x01
  354. #define NO_SEQINT 0x00
  355. #define CLRINT 0x03
  356. #define CLRHWERRINT 0x80
  357. #define CLRBRKADRINT 0x40
  358. #define CLRSWTMINT 0x20
  359. #define CLRPCIINT 0x10
  360. #define CLRSCSIINT 0x08
  361. #define CLRSEQINT 0x04
  362. #define CLRCMDINT 0x02
  363. #define CLRSPLTINT 0x01
  364. #define CLRERR 0x04
  365. #define CLRCIOPARERR 0x80
  366. #define CLRCIOACCESFAIL 0x40
  367. #define CLRMPARERR 0x20
  368. #define CLRDPARERR 0x10
  369. #define CLRSQPARERR 0x08
  370. #define CLRILLOPCODE 0x04
  371. #define CLRDSCTMOUT 0x02
  372. #define ERROR 0x04
  373. #define CIOPARERR 0x80
  374. #define CIOACCESFAIL 0x40
  375. #define MPARERR 0x20
  376. #define DPARERR 0x10
  377. #define SQPARERR 0x08
  378. #define ILLOPCODE 0x04
  379. #define DSCTMOUT 0x02
  380. #define HCNTRL 0x05
  381. #define SEQ_RESET 0x80
  382. #define POWRDN 0x40
  383. #define SWINT 0x10
  384. #define SWTIMER_START_B 0x08
  385. #define PAUSE 0x04
  386. #define INTEN 0x02
  387. #define CHIPRST 0x01
  388. #define CHIPRSTACK 0x01
  389. #define HNSCB_QOFF 0x06
  390. #define HESCB_QOFF 0x08
  391. #define HS_MAILBOX 0x0b
  392. #define HOST_TQINPOS 0x80
  393. #define ENINT_COALESCE 0x40
  394. #define SEQINTSTAT 0x0c
  395. #define SEQ_SWTMRTO 0x10
  396. #define SEQ_SEQINT 0x08
  397. #define SEQ_SCSIINT 0x04
  398. #define SEQ_PCIINT 0x02
  399. #define SEQ_SPLTINT 0x01
  400. #define CLRSEQINTSTAT 0x0c
  401. #define CLRSEQ_SWTMRTO 0x10
  402. #define CLRSEQ_SEQINT 0x08
  403. #define CLRSEQ_SCSIINT 0x04
  404. #define CLRSEQ_PCIINT 0x02
  405. #define CLRSEQ_SPLTINT 0x01
  406. #define SWTIMER 0x0e
  407. #define SNSCB_QOFF 0x10
  408. #define SESCB_QOFF 0x12
  409. #define SDSCB_QOFF 0x14
  410. #define QOFF_CTLSTA 0x16
  411. #define EMPTY_SCB_AVAIL 0x80
  412. #define NEW_SCB_AVAIL 0x40
  413. #define SDSCB_ROLLOVR 0x20
  414. #define HS_MAILBOX_ACT 0x10
  415. #define SCB_QSIZE 0x0f
  416. #define SCB_QSIZE_16384 0x0c
  417. #define SCB_QSIZE_8192 0x0b
  418. #define SCB_QSIZE_4096 0x0a
  419. #define SCB_QSIZE_2048 0x09
  420. #define SCB_QSIZE_1024 0x08
  421. #define SCB_QSIZE_512 0x07
  422. #define SCB_QSIZE_256 0x06
  423. #define SCB_QSIZE_128 0x05
  424. #define SCB_QSIZE_64 0x04
  425. #define SCB_QSIZE_32 0x03
  426. #define SCB_QSIZE_16 0x02
  427. #define SCB_QSIZE_8 0x01
  428. #define SCB_QSIZE_4 0x00
  429. #define INTCTL 0x18
  430. #define SWTMINTMASK 0x80
  431. #define SWTMINTEN 0x40
  432. #define SWTIMER_START 0x20
  433. #define AUTOCLRCMDINT 0x10
  434. #define PCIINTEN 0x08
  435. #define SCSIINTEN 0x04
  436. #define SEQINTEN 0x02
  437. #define SPLTINTEN 0x01
  438. #define DFCNTRL 0x19
  439. #define SCSIENWRDIS 0x40
  440. #define SCSIENACK 0x20
  441. #define DIRECTIONACK 0x04
  442. #define FIFOFLUSHACK 0x02
  443. #define DIRECTIONEN 0x01
  444. #define DSCOMMAND0 0x19
  445. #define CACHETHEN 0x80
  446. #define DPARCKEN 0x40
  447. #define MPARCKEN 0x20
  448. #define EXTREQLCK 0x10
  449. #define DISABLE_TWATE 0x02
  450. #define CIOPARCKEN 0x01
  451. #define DFSTATUS 0x1a
  452. #define PRELOAD_AVAIL 0x80
  453. #define PKT_PRELOAD_AVAIL 0x40
  454. #define MREQPEND 0x10
  455. #define HDONE 0x08
  456. #define DFTHRESH 0x04
  457. #define FIFOFULL 0x02
  458. #define FIFOEMP 0x01
  459. #define ARBCTL 0x1b
  460. #define RESET_HARB 0x80
  461. #define RETRY_SWEN 0x08
  462. #define USE_TIME 0x07
  463. #define SG_CACHE_SHADOW 0x1b
  464. #define ODD_SEG 0x04
  465. #define LAST_SEG 0x02
  466. #define LAST_SEG_DONE 0x01
  467. #define SG_CACHE_PRE 0x1b
  468. #define TYPEPTR 0x20
  469. #define LQIN 0x20
  470. #define TAGPTR 0x21
  471. #define LUNPTR 0x22
  472. #define DATALENPTR 0x23
  473. #define STATLENPTR 0x24
  474. #define CMDLENPTR 0x25
  475. #define ATTRPTR 0x26
  476. #define FLAGPTR 0x27
  477. #define CMDPTR 0x28
  478. #define QNEXTPTR 0x29
  479. #define IDPTR 0x2a
  480. #define ABRTBYTEPTR 0x2b
  481. #define ABRTBITPTR 0x2c
  482. #define MAXCMDBYTES 0x2d
  483. #define MAXCMD2RCV 0x2e
  484. #define SHORTTHRESH 0x2f
  485. #define LUNLEN 0x30
  486. #define TLUNLEN 0xf0
  487. #define ILUNLEN 0x0f
  488. #define CDBLIMIT 0x31
  489. #define MAXCMD 0x32
  490. #define MAXCMDCNT 0x33
  491. #define LQRSVD01 0x34
  492. #define LQRSVD16 0x35
  493. #define LQRSVD17 0x36
  494. #define CMDRSVD0 0x37
  495. #define LQCTL0 0x38
  496. #define LQITARGCLT 0xc0
  497. #define LQIINITGCLT 0x30
  498. #define LQ0TARGCLT 0x0c
  499. #define LQ0INITGCLT 0x03
  500. #define LQCTL1 0x38
  501. #define PCI2PCI 0x04
  502. #define SINGLECMD 0x02
  503. #define ABORTPENDING 0x01
  504. #define LQCTL2 0x39
  505. #define LQIRETRY 0x80
  506. #define LQICONTINUE 0x40
  507. #define LQITOIDLE 0x20
  508. #define LQIPAUSE 0x10
  509. #define LQORETRY 0x08
  510. #define LQOCONTINUE 0x04
  511. #define LQOTOIDLE 0x02
  512. #define LQOPAUSE 0x01
  513. #define SCSBIST0 0x39
  514. #define GSBISTERR 0x40
  515. #define GSBISTDONE 0x20
  516. #define GSBISTRUN 0x10
  517. #define OSBISTERR 0x04
  518. #define OSBISTDONE 0x02
  519. #define OSBISTRUN 0x01
  520. #define SCSISEQ0 0x3a
  521. #define TEMODEO 0x80
  522. #define ENSELO 0x40
  523. #define ENARBO 0x20
  524. #define FORCEBUSFREE 0x10
  525. #define SCSIRSTO 0x01
  526. #define SCSBIST1 0x3a
  527. #define NTBISTERR 0x04
  528. #define NTBISTDONE 0x02
  529. #define NTBISTRUN 0x01
  530. #define SCSISEQ1 0x3b
  531. #define BUSINITID 0x3c
  532. #define SXFRCTL0 0x3c
  533. #define DFON 0x80
  534. #define DFPEXP 0x40
  535. #define BIOSCANCELEN 0x10
  536. #define SPIOEN 0x08
  537. #define DLCOUNT 0x3c
  538. #define SXFRCTL1 0x3d
  539. #define BITBUCKET 0x80
  540. #define ENSACHK 0x40
  541. #define ENSPCHK 0x20
  542. #define STIMESEL 0x18
  543. #define ENSTIMER 0x04
  544. #define ACTNEGEN 0x02
  545. #define STPWEN 0x01
  546. #define BUSTARGID 0x3e
  547. #define SXFRCTL2 0x3e
  548. #define AUTORSTDIS 0x10
  549. #define CMDDMAEN 0x08
  550. #define ASU 0x07
  551. #define DFFSTAT 0x3f
  552. #define CURRFIFO 0x03
  553. #define FIFO1FREE 0x20
  554. #define FIFO0FREE 0x10
  555. #define CURRFIFO_NONE 0x03
  556. #define CURRFIFO_1 0x01
  557. #define CURRFIFO_0 0x00
  558. #define MULTARGID 0x40
  559. #define SCSISIGO 0x40
  560. #define CDO 0x80
  561. #define IOO 0x40
  562. #define MSGO 0x20
  563. #define ATNO 0x10
  564. #define SELO 0x08
  565. #define BSYO 0x04
  566. #define REQO 0x02
  567. #define ACKO 0x01
  568. #define SCSISIGI 0x41
  569. #define ATNI 0x10
  570. #define SELI 0x08
  571. #define BSYI 0x04
  572. #define REQI 0x02
  573. #define ACKI 0x01
  574. #define SCSIPHASE 0x42
  575. #define STATUS_PHASE 0x20
  576. #define COMMAND_PHASE 0x10
  577. #define MSG_IN_PHASE 0x08
  578. #define MSG_OUT_PHASE 0x04
  579. #define DATA_PHASE_MASK 0x03
  580. #define DATA_IN_PHASE 0x02
  581. #define DATA_OUT_PHASE 0x01
  582. #define SCSIDAT0_IMG 0x43
  583. #define SCSIDAT 0x44
  584. #define SCSIBUS 0x46
  585. #define TARGIDIN 0x48
  586. #define CLKOUT 0x80
  587. #define TARGID 0x0f
  588. #define SELID 0x49
  589. #define SELID_MASK 0xf0
  590. #define ONEBIT 0x08
  591. #define OPTIONMODE 0x4a
  592. #define OPTIONMODE_DEFAULTS 0x02
  593. #define BIOSCANCTL 0x80
  594. #define AUTOACKEN 0x40
  595. #define BIASCANCTL 0x20
  596. #define BUSFREEREV 0x10
  597. #define ENDGFORMCHK 0x04
  598. #define AUTO_MSGOUT_DE 0x02
  599. #define SBLKCTL 0x4a
  600. #define DIAGLEDEN 0x80
  601. #define DIAGLEDON 0x40
  602. #define ENAB40 0x08
  603. #define ENAB20 0x04
  604. #define SELWIDE 0x02
  605. #define SIMODE0 0x4b
  606. #define ENSELDO 0x40
  607. #define ENSELDI 0x20
  608. #define ENSELINGO 0x10
  609. #define ENIOERR 0x08
  610. #define ENOVERRUN 0x04
  611. #define ENSPIORDY 0x02
  612. #define ENARBDO 0x01
  613. #define SSTAT0 0x4b
  614. #define TARGET 0x80
  615. #define SELDO 0x40
  616. #define SELDI 0x20
  617. #define SELINGO 0x10
  618. #define IOERR 0x08
  619. #define OVERRUN 0x04
  620. #define SPIORDY 0x02
  621. #define ARBDO 0x01
  622. #define CLRSINT0 0x4b
  623. #define CLRSELDO 0x40
  624. #define CLRSELDI 0x20
  625. #define CLRSELINGO 0x10
  626. #define CLRIOERR 0x08
  627. #define CLROVERRUN 0x04
  628. #define CLRSPIORDY 0x02
  629. #define CLRARBDO 0x01
  630. #define SSTAT1 0x4c
  631. #define SELTO 0x80
  632. #define ATNTARG 0x40
  633. #define SCSIRSTI 0x20
  634. #define PHASEMIS 0x10
  635. #define BUSFREE 0x08
  636. #define SCSIPERR 0x04
  637. #define STRB2FAST 0x02
  638. #define REQINIT 0x01
  639. #define CLRSINT1 0x4c
  640. #define CLRSELTIMEO 0x80
  641. #define CLRATNO 0x40
  642. #define CLRSCSIRSTI 0x20
  643. #define CLRBUSFREE 0x08
  644. #define CLRSCSIPERR 0x04
  645. #define CLRSTRB2FAST 0x02
  646. #define CLRREQINIT 0x01
  647. #define SIMODE2 0x4d
  648. #define ENWIDE_RES 0x04
  649. #define ENSDONE 0x02
  650. #define ENDMADONE 0x01
  651. #define SSTAT2 0x4d
  652. #define BUSFREETIME 0xc0
  653. #define NONPACKREQ 0x20
  654. #define EXP_ACTIVE 0x10
  655. #define BSYX 0x08
  656. #define WIDE_RES 0x04
  657. #define SDONE 0x02
  658. #define DMADONE 0x01
  659. #define BUSFREE_DFF1 0xc0
  660. #define BUSFREE_DFF0 0x80
  661. #define BUSFREE_LQO 0x40
  662. #define CLRSINT2 0x4d
  663. #define CLRNONPACKREQ 0x20
  664. #define CLRWIDE_RES 0x04
  665. #define CLRSDONE 0x02
  666. #define CLRDMADONE 0x01
  667. #define PERRDIAG 0x4e
  668. #define HIZERO 0x80
  669. #define HIPERR 0x40
  670. #define PREVPHASE 0x20
  671. #define PARITYERR 0x10
  672. #define AIPERR 0x08
  673. #define CRCERR 0x04
  674. #define DGFORMERR 0x02
  675. #define DTERR 0x01
  676. #define LQISTATE 0x4e
  677. #define LQOSTATE 0x4f
  678. #define SOFFCNT 0x4f
  679. #define LQISTAT0 0x50
  680. #define LQIATNQAS 0x20
  681. #define LQICRCT1 0x10
  682. #define LQICRCT2 0x08
  683. #define LQIBADLQT 0x04
  684. #define LQIATNLQ 0x02
  685. #define LQIATNCMD 0x01
  686. #define LQIMODE0 0x50
  687. #define ENLQIATNQASK 0x20
  688. #define ENLQICRCT1 0x10
  689. #define ENLQICRCT2 0x08
  690. #define ENLQIBADLQT 0x04
  691. #define ENLQIATNLQ 0x02
  692. #define ENLQIATNCMD 0x01
  693. #define CLRLQIINT0 0x50
  694. #define CLRLQIATNQAS 0x20
  695. #define CLRLQICRCT1 0x10
  696. #define CLRLQICRCT2 0x08
  697. #define CLRLQIBADLQT 0x04
  698. #define CLRLQIATNLQ 0x02
  699. #define CLRLQIATNCMD 0x01
  700. #define LQIMODE1 0x51
  701. #define ENLQIPHASE_LQ 0x80
  702. #define ENLQIPHASE_NLQ 0x40
  703. #define ENLIQABORT 0x20
  704. #define ENLQICRCI_LQ 0x10
  705. #define ENLQICRCI_NLQ 0x08
  706. #define ENLQIBADLQI 0x04
  707. #define ENLQIOVERI_LQ 0x02
  708. #define ENLQIOVERI_NLQ 0x01
  709. #define LQISTAT1 0x51
  710. #define LQIPHASE_LQ 0x80
  711. #define LQIPHASE_NLQ 0x40
  712. #define LQIABORT 0x20
  713. #define LQICRCI_LQ 0x10
  714. #define LQICRCI_NLQ 0x08
  715. #define LQIBADLQI 0x04
  716. #define LQIOVERI_LQ 0x02
  717. #define LQIOVERI_NLQ 0x01
  718. #define CLRLQIINT1 0x51
  719. #define CLRLQIPHASE_LQ 0x80
  720. #define CLRLQIPHASE_NLQ 0x40
  721. #define CLRLIQABORT 0x20
  722. #define CLRLQICRCI_LQ 0x10
  723. #define CLRLQICRCI_NLQ 0x08
  724. #define CLRLQIBADLQI 0x04
  725. #define CLRLQIOVERI_LQ 0x02
  726. #define CLRLQIOVERI_NLQ 0x01
  727. #define LQISTAT2 0x52
  728. #define PACKETIZED 0x80
  729. #define LQIPHASE_OUTPKT 0x40
  730. #define LQIWORKONLQ 0x20
  731. #define LQIWAITFIFO 0x10
  732. #define LQISTOPPKT 0x08
  733. #define LQISTOPLQ 0x04
  734. #define LQISTOPCMD 0x02
  735. #define LQIGSAVAIL 0x01
  736. #define SIMODE3 0x53
  737. #define ENNTRAMPERR 0x02
  738. #define ENOSRAMPERR 0x01
  739. #define SSTAT3 0x53
  740. #define NTRAMPERR 0x02
  741. #define OSRAMPERR 0x01
  742. #define CLRSINT3 0x53
  743. #define CLRNTRAMPERR 0x02
  744. #define CLROSRAMPERR 0x01
  745. #define CLRLQOINT0 0x54
  746. #define CLRLQOTARGSCBPERR 0x10
  747. #define CLRLQOSTOPT2 0x08
  748. #define CLRLQOATNLQ 0x04
  749. #define CLRLQOATNPKT 0x02
  750. #define CLRLQOTCRC 0x01
  751. #define LQOSTAT0 0x54
  752. #define LQOTARGSCBPERR 0x10
  753. #define LQOSTOPT2 0x08
  754. #define LQOATNLQ 0x04
  755. #define LQOATNPKT 0x02
  756. #define LQOTCRC 0x01
  757. #define LQOMODE0 0x54
  758. #define ENLQOTARGSCBPERR 0x10
  759. #define ENLQOSTOPT2 0x08
  760. #define ENLQOATNLQ 0x04
  761. #define ENLQOATNPKT 0x02
  762. #define ENLQOTCRC 0x01
  763. #define LQOMODE1 0x55
  764. #define ENLQOINITSCBPERR 0x10
  765. #define ENLQOSTOPI2 0x08
  766. #define ENLQOBADQAS 0x04
  767. #define ENLQOBUSFREE 0x02
  768. #define ENLQOPHACHGINPKT 0x01
  769. #define CLRLQOINT1 0x55
  770. #define CLRLQOINITSCBPERR 0x10
  771. #define CLRLQOSTOPI2 0x08
  772. #define CLRLQOBADQAS 0x04
  773. #define CLRLQOBUSFREE 0x02
  774. #define CLRLQOPHACHGINPKT 0x01
  775. #define LQOSTAT1 0x55
  776. #define LQOINITSCBPERR 0x10
  777. #define LQOSTOPI2 0x08
  778. #define LQOBADQAS 0x04
  779. #define LQOBUSFREE 0x02
  780. #define LQOPHACHGINPKT 0x01
  781. #define LQOSTAT2 0x56
  782. #define LQOPKT 0xe0
  783. #define LQOWAITFIFO 0x10
  784. #define LQOPHACHGOUTPKT 0x02
  785. #define LQOSTOP0 0x01
  786. #define OS_SPACE_CNT 0x56
  787. #define SIMODE1 0x57
  788. #define ENSELTIMO 0x80
  789. #define ENATNTARG 0x40
  790. #define ENSCSIRST 0x20
  791. #define ENPHASEMIS 0x10
  792. #define ENBUSFREE 0x08
  793. #define ENSCSIPERR 0x04
  794. #define ENSTRB2FAST 0x02
  795. #define ENREQINIT 0x01
  796. #define GSFIFO 0x58
  797. #define DFFSXFRCTL 0x5a
  798. #define DFFBITBUCKET 0x08
  799. #define CLRSHCNT 0x04
  800. #define CLRCHN 0x02
  801. #define RSTCHN 0x01
  802. #define LQOSCSCTL 0x5a
  803. #define LQOH2A_VERSION 0x80
  804. #define LQOBUSETDLY 0x40
  805. #define LQONOHOLDLACK 0x02
  806. #define LQONOCHKOVER 0x01
  807. #define NEXTSCB 0x5a
  808. #define CLRSEQINTSRC 0x5b
  809. #define CLRCTXTDONE 0x40
  810. #define CLRSAVEPTRS 0x20
  811. #define CLRCFG4DATA 0x10
  812. #define CLRCFG4ISTAT 0x08
  813. #define CLRCFG4TSTAT 0x04
  814. #define CLRCFG4ICMD 0x02
  815. #define CLRCFG4TCMD 0x01
  816. #define SEQINTSRC 0x5b
  817. #define CTXTDONE 0x40
  818. #define SAVEPTRS 0x20
  819. #define CFG4DATA 0x10
  820. #define CFG4ISTAT 0x08
  821. #define CFG4TSTAT 0x04
  822. #define CFG4ICMD 0x02
  823. #define CFG4TCMD 0x01
  824. #define SEQIMODE 0x5c
  825. #define ENCTXTDONE 0x40
  826. #define ENSAVEPTRS 0x20
  827. #define ENCFG4DATA 0x10
  828. #define ENCFG4ISTAT 0x08
  829. #define ENCFG4TSTAT 0x04
  830. #define ENCFG4ICMD 0x02
  831. #define ENCFG4TCMD 0x01
  832. #define CURRSCB 0x5c
  833. #define CRCCONTROL 0x5d
  834. #define CRCVALCHKEN 0x40
  835. #define MDFFSTAT 0x5d
  836. #define SHCNTNEGATIVE 0x40
  837. #define SHCNTMINUS1 0x20
  838. #define LASTSDONE 0x10
  839. #define SHVALID 0x08
  840. #define DLZERO 0x04
  841. #define DATAINFIFO 0x02
  842. #define FIFOFREE 0x01
  843. #define DFFTAG 0x5e
  844. #define SCSITEST 0x5e
  845. #define CNTRTEST 0x08
  846. #define SEL_TXPLL_DEBUG 0x04
  847. #define LASTSCB 0x5e
  848. #define IOPDNCTL 0x5f
  849. #define DISABLE_OE 0x80
  850. #define PDN_IDIST 0x04
  851. #define PDN_DIFFSENSE 0x01
  852. #define DGRPCRCI 0x60
  853. #define NEGOADDR 0x60
  854. #define SHADDR 0x60
  855. #define NEGPERIOD 0x61
  856. #define NEGOFFSET 0x62
  857. #define PACKCRCI 0x62
  858. #define NEGPPROPTS 0x63
  859. #define PPROPT_PACE 0x08
  860. #define PPROPT_QAS 0x04
  861. #define PPROPT_DT 0x02
  862. #define PPROPT_IUT 0x01
  863. #define NEGCONOPTS 0x64
  864. #define ENSNAPSHOT 0x40
  865. #define RTI_WRTDIS 0x20
  866. #define RTI_OVRDTRN 0x10
  867. #define ENSLOWCRC 0x08
  868. #define ENAUTOATNI 0x04
  869. #define ENAUTOATNO 0x02
  870. #define WIDEXFER 0x01
  871. #define ANNEXCOL 0x65
  872. #define ANNEXDAT 0x66
  873. #define SCSCHKN 0x66
  874. #define BIDICHKDIS 0x80
  875. #define STSELSKIDDIS 0x40
  876. #define CURRFIFODEF 0x20
  877. #define WIDERESEN 0x10
  878. #define SDONEMSKDIS 0x08
  879. #define DFFACTCLR 0x04
  880. #define SHVALIDSTDIS 0x02
  881. #define LSTSGCLRDIS 0x01
  882. #define IOWNID 0x67
  883. #define PLL960CTL0 0x68
  884. #define SHCNT 0x68
  885. #define PLL960CTL1 0x69
  886. #define TOWNID 0x69
  887. #define PLL960CNT0 0x6a
  888. #define XSIG 0x6a
  889. #define SELOID 0x6b
  890. #define FAIRNESS 0x6c
  891. #define PLL400CTL0 0x6c
  892. #define PLL_VCOSEL 0x80
  893. #define PLL_PWDN 0x40
  894. #define PLL_NS 0x30
  895. #define PLL_ENLUD 0x08
  896. #define PLL_ENLPF 0x04
  897. #define PLL_DLPF 0x02
  898. #define PLL_ENFBM 0x01
  899. #define PLL400CTL1 0x6d
  900. #define PLL_CNTEN 0x80
  901. #define PLL_CNTCLR 0x40
  902. #define PLL_RST 0x01
  903. #define UNFAIRNESS 0x6e
  904. #define PLL400CNT0 0x6e
  905. #define HADDR 0x70
  906. #define HODMAADR 0x70
  907. #define PLLDELAY 0x70
  908. #define SPLIT_DROP_REQ 0x80
  909. #define HCNT 0x78
  910. #define HODMACNT 0x78
  911. #define HODMAEN 0x7a
  912. #define SGHADDR 0x7c
  913. #define SCBHADDR 0x7c
  914. #define SGHCNT 0x84
  915. #define SCBHCNT 0x84
  916. #define DFF_THRSH 0x88
  917. #define WR_DFTHRSH 0x70
  918. #define RD_DFTHRSH 0x07
  919. #define WR_DFTHRSH_MAX 0x70
  920. #define WR_DFTHRSH_90 0x60
  921. #define WR_DFTHRSH_85 0x50
  922. #define WR_DFTHRSH_75 0x40
  923. #define WR_DFTHRSH_63 0x30
  924. #define WR_DFTHRSH_50 0x20
  925. #define WR_DFTHRSH_25 0x10
  926. #define RD_DFTHRSH_MAX 0x07
  927. #define RD_DFTHRSH_90 0x06
  928. #define RD_DFTHRSH_85 0x05
  929. #define RD_DFTHRSH_75 0x04
  930. #define RD_DFTHRSH_63 0x03
  931. #define RD_DFTHRSH_50 0x02
  932. #define RD_DFTHRSH_25 0x01
  933. #define RD_DFTHRSH_MIN 0x00
  934. #define WR_DFTHRSH_MIN 0x00
  935. #define ROMADDR 0x8a
  936. #define ROMCNTRL 0x8d
  937. #define ROMOP 0xe0
  938. #define ROMSPD 0x18
  939. #define REPEAT 0x02
  940. #define RDY 0x01
  941. #define ROMDATA 0x8e
  942. #define CMCRXMSG0 0x90
  943. #define OVLYRXMSG0 0x90
  944. #define DCHRXMSG0 0x90
  945. #define ROENABLE 0x90
  946. #define MSIROEN 0x20
  947. #define OVLYROEN 0x10
  948. #define CMCROEN 0x08
  949. #define SGROEN 0x04
  950. #define DCH1ROEN 0x02
  951. #define DCH0ROEN 0x01
  952. #define OVLYRXMSG1 0x91
  953. #define CMCRXMSG1 0x91
  954. #define DCHRXMSG1 0x91
  955. #define NSENABLE 0x91
  956. #define MSINSEN 0x20
  957. #define OVLYNSEN 0x10
  958. #define CMCNSEN 0x08
  959. #define SGNSEN 0x04
  960. #define DCH1NSEN 0x02
  961. #define DCH0NSEN 0x01
  962. #define DCHRXMSG2 0x92
  963. #define CMCRXMSG2 0x92
  964. #define OST 0x92
  965. #define OVLYRXMSG2 0x92
  966. #define DCHRXMSG3 0x93
  967. #define OVLYRXMSG3 0x93
  968. #define CMCRXMSG3 0x93
  969. #define PCIXCTL 0x93
  970. #define SERRPULSE 0x80
  971. #define UNEXPSCIEN 0x20
  972. #define SPLTSMADIS 0x10
  973. #define SPLTSTADIS 0x08
  974. #define SRSPDPEEN 0x04
  975. #define TSCSERREN 0x02
  976. #define CMPABCDIS 0x01
  977. #define CMCSEQBCNT 0x94
  978. #define OVLYSEQBCNT 0x94
  979. #define DCHSEQBCNT 0x94
  980. #define DCHSPLTSTAT0 0x96
  981. #define OVLYSPLTSTAT0 0x96
  982. #define CMCSPLTSTAT0 0x96
  983. #define OVLYSPLTSTAT1 0x97
  984. #define DCHSPLTSTAT1 0x97
  985. #define CMCSPLTSTAT1 0x97
  986. #define SGRXMSG0 0x98
  987. #define CDNUM 0xf8
  988. #define CFNUM 0x07
  989. #define SLVSPLTOUTADR0 0x98
  990. #define LOWER_ADDR 0x7f
  991. #define SGRXMSG1 0x99
  992. #define CBNUM 0xff
  993. #define SLVSPLTOUTADR1 0x99
  994. #define REQ_DNUM 0xf8
  995. #define REQ_FNUM 0x07
  996. #define SGRXMSG2 0x9a
  997. #define MINDEX 0xff
  998. #define SLVSPLTOUTADR2 0x9a
  999. #define REQ_BNUM 0xff
  1000. #define SGRXMSG3 0x9b
  1001. #define MCLASS 0x0f
  1002. #define SLVSPLTOUTADR3 0x9b
  1003. #define TAG_NUM 0x1f
  1004. #define RLXORD 0x10
  1005. #define SLVSPLTOUTATTR0 0x9c
  1006. #define LOWER_BCNT 0xff
  1007. #define SGSEQBCNT 0x9c
  1008. #define SLVSPLTOUTATTR1 0x9d
  1009. #define CMPLT_DNUM 0xf8
  1010. #define CMPLT_FNUM 0x07
  1011. #define SGSPLTSTAT0 0x9e
  1012. #define STAETERM 0x80
  1013. #define SCBCERR 0x40
  1014. #define SCADERR 0x20
  1015. #define SCDATBUCKET 0x10
  1016. #define CNTNOTCMPLT 0x08
  1017. #define RXOVRUN 0x04
  1018. #define RXSCEMSG 0x02
  1019. #define RXSPLTRSP 0x01
  1020. #define SLVSPLTOUTATTR2 0x9e
  1021. #define CMPLT_BNUM 0xff
  1022. #define SGSPLTSTAT1 0x9f
  1023. #define RXDATABUCKET 0x01
  1024. #define SFUNCT 0x9f
  1025. #define TEST_GROUP 0xf0
  1026. #define TEST_NUM 0x0f
  1027. #define DF0PCISTAT 0xa0
  1028. #define REG0 0xa0
  1029. #define DF1PCISTAT 0xa1
  1030. #define SGPCISTAT 0xa2
  1031. #define REG1 0xa2
  1032. #define CMCPCISTAT 0xa3
  1033. #define OVLYPCISTAT 0xa4
  1034. #define SCAAPERR 0x08
  1035. #define RDPERR 0x04
  1036. #define REG_ISR 0xa4
  1037. #define SG_STATE 0xa6
  1038. #define FETCH_INPROG 0x04
  1039. #define LOADING_NEEDED 0x02
  1040. #define SEGS_AVAIL 0x01
  1041. #define MSIPCISTAT 0xa6
  1042. #define RMA 0x20
  1043. #define RTA 0x10
  1044. #define CLRPENDMSI 0x08
  1045. #define DPR 0x01
  1046. #define DATA_COUNT_ODD 0xa7
  1047. #define TARGPCISTAT 0xa7
  1048. #define DPE 0x80
  1049. #define SSE 0x40
  1050. #define STA 0x08
  1051. #define TWATERR 0x02
  1052. #define SCBPTR 0xa8
  1053. #define CCSCBACNT 0xab
  1054. #define SCBAUTOPTR 0xab
  1055. #define AUSCBPTR_EN 0x80
  1056. #define SCBPTR_ADDR 0x38
  1057. #define SCBPTR_OFF 0x07
  1058. #define CCSGADDR 0xac
  1059. #define CCSCBADDR 0xac
  1060. #define CCSCBADR_BK 0xac
  1061. #define CMC_RAMBIST 0xad
  1062. #define SG_ELEMENT_SIZE 0x80
  1063. #define SCBRAMBIST_FAIL 0x40
  1064. #define SG_BIST_FAIL 0x20
  1065. #define SG_BIST_EN 0x10
  1066. #define CMC_BUFFER_BIST_FAIL 0x02
  1067. #define CMC_BUFFER_BIST_EN 0x01
  1068. #define CCSCBCTL 0xad
  1069. #define CCSCBDONE 0x80
  1070. #define ARRDONE 0x40
  1071. #define CCARREN 0x10
  1072. #define CCSCBEN 0x08
  1073. #define CCSCBDIR 0x04
  1074. #define CCSCBRESET 0x01
  1075. #define CCSGCTL 0xad
  1076. #define CCSGEN 0x0c
  1077. #define CCSGDONE 0x80
  1078. #define SG_CACHE_AVAIL 0x10
  1079. #define CCSGENACK 0x08
  1080. #define SG_FETCH_REQ 0x02
  1081. #define CCSGRESET 0x01
  1082. #define CCSGRAM 0xb0
  1083. #define FLEXADR 0xb0
  1084. #define CCSCBRAM 0xb0
  1085. #define FLEXCNT 0xb3
  1086. #define FLEXDMASTAT 0xb5
  1087. #define FLEXDMAERR 0x02
  1088. #define FLEXDMADONE 0x01
  1089. #define FLEXDATA 0xb6
  1090. #define BRDDAT 0xb8
  1091. #define BRDCTL 0xb9
  1092. #define FLXARBACK 0x80
  1093. #define FLXARBREQ 0x40
  1094. #define BRDADDR 0x38
  1095. #define BRDEN 0x04
  1096. #define BRDRW 0x02
  1097. #define BRDSTB 0x01
  1098. #define SEEADR 0xba
  1099. #define SEEDAT 0xbc
  1100. #define SEECTL 0xbe
  1101. #define SEEOP_EWDS 0x40
  1102. #define SEEOP_WALL 0x40
  1103. #define SEEOP_EWEN 0x40
  1104. #define SEEOPCODE 0x70
  1105. #define SEERST 0x02
  1106. #define SEESTART 0x01
  1107. #define SEEOP_ERASE 0x70
  1108. #define SEEOP_READ 0x60
  1109. #define SEEOP_WRITE 0x50
  1110. #define SEEOP_ERAL 0x40
  1111. #define SEESTAT 0xbe
  1112. #define INIT_DONE 0x80
  1113. #define LDALTID_L 0x08
  1114. #define SEEARBACK 0x04
  1115. #define SEEBUSY 0x02
  1116. #define SCBCNT 0xbf
  1117. #define DSPFLTRCTL 0xc0
  1118. #define FLTRDISABLE 0x20
  1119. #define EDGESENSE 0x10
  1120. #define DSPFCNTSEL 0x0f
  1121. #define DFWADDR 0xc0
  1122. #define DSPDATACTL 0xc1
  1123. #define BYPASSENAB 0x80
  1124. #define DESQDIS 0x10
  1125. #define RCVROFFSTDIS 0x04
  1126. #define XMITOFFSTDIS 0x02
  1127. #define DSPREQCTL 0xc2
  1128. #define MANREQCTL 0xc0
  1129. #define MANREQDLY 0x3f
  1130. #define DFRADDR 0xc2
  1131. #define DSPACKCTL 0xc3
  1132. #define MANACKCTL 0xc0
  1133. #define MANACKDLY 0x3f
  1134. #define DFDAT 0xc4
  1135. #define DSPSELECT 0xc4
  1136. #define AUTOINCEN 0x80
  1137. #define DSPSEL 0x1f
  1138. #define WRTBIASCTL 0xc5
  1139. #define AUTOXBCDIS 0x80
  1140. #define XMITMANVAL 0x3f
  1141. #define RCVRBIOSCTL 0xc6
  1142. #define AUTORBCDIS 0x80
  1143. #define RCVRMANVAL 0x3f
  1144. #define WRTBIASCALC 0xc7
  1145. #define DFPTRS 0xc8
  1146. #define RCVRBIASCALC 0xc8
  1147. #define DFBKPTR 0xc9
  1148. #define SKEWCALC 0xc9
  1149. #define DFDBCTL 0xcb
  1150. #define DFF_CIO_WR_RDY 0x20
  1151. #define DFF_CIO_RD_RDY 0x10
  1152. #define DFF_DIR_ERR 0x08
  1153. #define DFF_RAMBIST_FAIL 0x04
  1154. #define DFF_RAMBIST_DONE 0x02
  1155. #define DFF_RAMBIST_EN 0x01
  1156. #define DFSCNT 0xcc
  1157. #define DFBCNT 0xce
  1158. #define OVLYADDR 0xd4
  1159. #define SEQCTL0 0xd6
  1160. #define PERRORDIS 0x80
  1161. #define PAUSEDIS 0x40
  1162. #define FAILDIS 0x20
  1163. #define FASTMODE 0x10
  1164. #define BRKADRINTEN 0x08
  1165. #define STEP 0x04
  1166. #define SEQRESET 0x02
  1167. #define LOADRAM 0x01
  1168. #define SEQCTL1 0xd7
  1169. #define OVRLAY_DATA_CHK 0x08
  1170. #define RAMBIST_DONE 0x04
  1171. #define RAMBIST_FAIL 0x02
  1172. #define RAMBIST_EN 0x01
  1173. #define FLAGS 0xd8
  1174. #define ZERO 0x02
  1175. #define CARRY 0x01
  1176. #define SEQINTCTL 0xd9
  1177. #define INTVEC1DSL 0x80
  1178. #define INT1_CONTEXT 0x20
  1179. #define SCS_SEQ_INT1M1 0x10
  1180. #define SCS_SEQ_INT1M0 0x08
  1181. #define INTMASK2 0x04
  1182. #define INTMASK1 0x02
  1183. #define IRET 0x01
  1184. #define SEQRAM 0xda
  1185. #define PRGMCNT 0xde
  1186. #define ACCUM 0xe0
  1187. #define SINDEX 0xe2
  1188. #define DINDEX 0xe4
  1189. #define BRKADDR0 0xe6
  1190. #define BRKADDR1 0xe6
  1191. #define BRKDIS 0x80
  1192. #define ALLONES 0xe8
  1193. #define ALLZEROS 0xea
  1194. #define NONE 0xea
  1195. #define SINDIR 0xec
  1196. #define DINDIR 0xed
  1197. #define FUNCTION1 0xf0
  1198. #define STACK 0xf2
  1199. #define INTVEC1_ADDR 0xf4
  1200. #define CURADDR 0xf4
  1201. #define LASTADDR 0xf6
  1202. #define INTVEC2_ADDR 0xf6
  1203. #define LONGJMP_ADDR 0xf8
  1204. #define ACCUM_SAVE 0xfa
  1205. #define AHD_PCI_CONFIG_BASE 0x100
  1206. #define SRAM_BASE 0x100
  1207. #define WAITING_SCB_TAILS 0x100
  1208. #define WAITING_TID_HEAD 0x120
  1209. #define WAITING_TID_TAIL 0x122
  1210. #define NEXT_QUEUED_SCB_ADDR 0x124
  1211. #define COMPLETE_SCB_HEAD 0x128
  1212. #define COMPLETE_SCB_DMAINPROG_HEAD 0x12a
  1213. #define COMPLETE_DMA_SCB_HEAD 0x12c
  1214. #define COMPLETE_DMA_SCB_TAIL 0x12e
  1215. #define COMPLETE_ON_QFREEZE_HEAD 0x130
  1216. #define QFREEZE_COUNT 0x132
  1217. #define KERNEL_QFREEZE_COUNT 0x134
  1218. #define SAVED_MODE 0x136
  1219. #define MSG_OUT 0x137
  1220. #define DMAPARAMS 0x138
  1221. #define PRELOADEN 0x80
  1222. #define WIDEODD 0x40
  1223. #define SCSIEN 0x20
  1224. #define SDMAENACK 0x10
  1225. #define SDMAEN 0x10
  1226. #define HDMAEN 0x08
  1227. #define HDMAENACK 0x08
  1228. #define DIRECTION 0x04
  1229. #define FIFOFLUSH 0x02
  1230. #define FIFORESET 0x01
  1231. #define SEQ_FLAGS 0x139
  1232. #define NOT_IDENTIFIED 0x80
  1233. #define NO_CDB_SENT 0x40
  1234. #define TARGET_CMD_IS_TAGGED 0x40
  1235. #define DPHASE 0x20
  1236. #define TARG_CMD_PENDING 0x10
  1237. #define CMDPHASE_PENDING 0x08
  1238. #define DPHASE_PENDING 0x04
  1239. #define SPHASE_PENDING 0x02
  1240. #define NO_DISCONNECT 0x01
  1241. #define SAVED_SCSIID 0x13a
  1242. #define SAVED_LUN 0x13b
  1243. #define LASTPHASE 0x13c
  1244. #define PHASE_MASK 0xe0
  1245. #define CDI 0x80
  1246. #define IOI 0x40
  1247. #define MSGI 0x20
  1248. #define P_BUSFREE 0x01
  1249. #define P_MESGIN 0xe0
  1250. #define P_STATUS 0xc0
  1251. #define P_MESGOUT 0xa0
  1252. #define P_COMMAND 0x80
  1253. #define P_DATAIN_DT 0x60
  1254. #define P_DATAIN 0x40
  1255. #define P_DATAOUT_DT 0x20
  1256. #define P_DATAOUT 0x00
  1257. #define QOUTFIFO_ENTRY_VALID_TAG 0x13d
  1258. #define KERNEL_TQINPOS 0x13e
  1259. #define TQINPOS 0x13f
  1260. #define SHARED_DATA_ADDR 0x140
  1261. #define QOUTFIFO_NEXT_ADDR 0x144
  1262. #define ARG_1 0x148
  1263. #define RETURN_1 0x148
  1264. #define SEND_MSG 0x80
  1265. #define SEND_SENSE 0x40
  1266. #define SEND_REJ 0x20
  1267. #define MSGOUT_PHASEMIS 0x10
  1268. #define EXIT_MSG_LOOP 0x08
  1269. #define CONT_MSG_LOOP_WRITE 0x04
  1270. #define CONT_MSG_LOOP_READ 0x03
  1271. #define CONT_MSG_LOOP_TARG 0x02
  1272. #define ARG_2 0x149
  1273. #define RETURN_2 0x149
  1274. #define LAST_MSG 0x14a
  1275. #define SCSISEQ_TEMPLATE 0x14b
  1276. #define MANUALCTL 0x40
  1277. #define ENSELI 0x20
  1278. #define ENRSELI 0x10
  1279. #define MANUALP 0x0c
  1280. #define ENAUTOATNP 0x02
  1281. #define ALTSTIM 0x01
  1282. #define INITIATOR_TAG 0x14c
  1283. #define SEQ_FLAGS2 0x14d
  1284. #define SELECTOUT_QFROZEN 0x04
  1285. #define TARGET_MSG_PENDING 0x02
  1286. #define PENDING_MK_MESSAGE 0x01
  1287. #define ALLOCFIFO_SCBPTR 0x14e
  1288. #define INT_COALESCING_TIMER 0x150
  1289. #define INT_COALESCING_MAXCMDS 0x152
  1290. #define INT_COALESCING_MINCMDS 0x153
  1291. #define CMDS_PENDING 0x154
  1292. #define INT_COALESCING_CMDCOUNT 0x156
  1293. #define LOCAL_HS_MAILBOX 0x157
  1294. #define CMDSIZE_TABLE 0x158
  1295. #define MK_MESSAGE_SCB 0x160
  1296. #define MK_MESSAGE_SCSIID 0x162
  1297. #define SCB_RESIDUAL_DATACNT 0x180
  1298. #define SCB_CDB_STORE 0x180
  1299. #define SCB_HOST_CDB_PTR 0x180
  1300. #define SCB_BASE 0x180
  1301. #define SCB_RESIDUAL_SGPTR 0x184
  1302. #define SG_ADDR_MASK 0xf8
  1303. #define SG_OVERRUN_RESID 0x02
  1304. #define SCB_SCSI_STATUS 0x188
  1305. #define SCB_HOST_CDB_LEN 0x188
  1306. #define SCB_TARGET_PHASES 0x189
  1307. #define SCB_TARGET_DATA_DIR 0x18a
  1308. #define SCB_TARGET_ITAG 0x18b
  1309. #define SCB_SENSE_BUSADDR 0x18c
  1310. #define SCB_NEXT_COMPLETE 0x18c
  1311. #define SCB_TAG 0x190
  1312. #define SCB_FIFO_USE_COUNT 0x190
  1313. #define SCB_CONTROL 0x192
  1314. #define TARGET_SCB 0x80
  1315. #define DISCENB 0x40
  1316. #define TAG_ENB 0x20
  1317. #define MK_MESSAGE 0x10
  1318. #define STATUS_RCVD 0x08
  1319. #define DISCONNECTED 0x04
  1320. #define SCB_TAG_TYPE 0x03
  1321. #define SCB_SCSIID 0x193
  1322. #define TID 0xf0
  1323. #define OID 0x0f
  1324. #define SCB_LUN 0x194
  1325. #define LID 0xff
  1326. #define SCB_TASK_ATTRIBUTE 0x195
  1327. #define SCB_XFERLEN_ODD 0x01
  1328. #define SCB_CDB_LEN 0x196
  1329. #define SCB_CDB_LEN_PTR 0x80
  1330. #define SCB_TASK_MANAGEMENT 0x197
  1331. #define SCB_DATAPTR 0x198
  1332. #define SCB_DATACNT 0x1a0
  1333. #define SG_LAST_SEG 0x80
  1334. #define SG_HIGH_ADDR_BITS 0x7f
  1335. #define SCB_SGPTR 0x1a4
  1336. #define SG_STATUS_VALID 0x04
  1337. #define SG_FULL_RESID 0x02
  1338. #define SG_LIST_NULL 0x01
  1339. #define SCB_BUSADDR 0x1a8
  1340. #define SCB_NEXT 0x1ac
  1341. #define SCB_NEXT_SCB_BUSADDR 0x1ac
  1342. #define SCB_NEXT2 0x1ae
  1343. #define SCB_SPARE 0x1b0
  1344. #define SCB_PKT_LUN 0x1b0
  1345. #define SCB_DISCONNECTED_LISTS 0x1b8
  1346. #define STIMESEL_SHIFT 0x03
  1347. #define STIMESEL_MIN 0x18
  1348. #define INVALID_ADDR 0x80
  1349. #define CMD_GROUP_CODE_SHIFT 0x05
  1350. #define AHD_PRECOMP_MASK 0x07
  1351. #define TARGET_DATA_IN 0x01
  1352. #define SEEOP_EWEN_ADDR 0xc0
  1353. #define NUMDSPS 0x14
  1354. #define DST_MODE_SHIFT 0x04
  1355. #define CCSCBADDR_MAX 0x80
  1356. #define AHD_ANNEXCOL_PER_DEV0 0x04
  1357. #define TARGET_CMD_CMPLT 0xfe
  1358. #define SEEOP_WRAL_ADDR 0x40
  1359. #define BUS_8_BIT 0x00
  1360. #define AHD_TIMER_MAX_US 0x18ffe7
  1361. #define AHD_TIMER_MAX_TICKS 0xffff
  1362. #define AHD_SENSE_BUFSIZE 0x100
  1363. #define AHD_PRECOMP_SHIFT 0x00
  1364. #define AHD_PRECOMP_CUTBACK_37 0x07
  1365. #define AHD_ANNEXCOL_PRECOMP_SLEW 0x04
  1366. #define AHD_AMPLITUDE_DEF 0x07
  1367. #define WRTBIASCTL_HP_DEFAULT 0x00
  1368. #define TID_SHIFT 0x04
  1369. #define STATUS_QUEUE_FULL 0x28
  1370. #define STATUS_BUSY 0x08
  1371. #define SEEOP_EWDS_ADDR 0x00
  1372. #define SCB_TRANSFER_SIZE_FULL_LUN 0x38
  1373. #define MK_MESSAGE_BIT_OFFSET 0x04
  1374. #define MAX_OFFSET_PACED 0xfe
  1375. #define MAX_OFFSET_NON_PACED 0x7f
  1376. #define LUNLEN_SINGLE_LEVEL_LUN 0x0f
  1377. #define CCSGADDR_MAX 0x80
  1378. #define B_CURRFIFO_0 0x02
  1379. #define BUS_32_BIT 0x02
  1380. #define AHD_TIMER_US_PER_TICK 0x19
  1381. #define AHD_SLEWRATE_SHIFT 0x03
  1382. #define AHD_SLEWRATE_MASK 0x78
  1383. #define AHD_SLEWRATE_DEF_REVA 0x08
  1384. #define AHD_PRECOMP_CUTBACK_29 0x06
  1385. #define AHD_NUM_PER_DEV_ANNEXCOLS 0x04
  1386. #define AHD_ANNEXCOL_AMPLITUDE 0x06
  1387. #define AHD_AMPLITUDE_SHIFT 0x00
  1388. #define AHD_AMPLITUDE_MASK 0x07
  1389. #define STIMESEL_BUG_ADJ 0x08
  1390. #define STATUS_PKT_SENSE 0xff
  1391. #define SRC_MODE_SHIFT 0x00
  1392. #define SEEOP_ERAL_ADDR 0x80
  1393. #define NVRAM_SCB_OFFSET 0x2c
  1394. #define MAX_OFFSET_PACED_BUG 0x7f
  1395. #define CCSGRAM_MAXSEGS 0x10
  1396. #define AHD_SLEWRATE_DEF_REVB 0x08
  1397. #define AHD_PRECOMP_CUTBACK_17 0x04
  1398. #define SCB_TRANSFER_SIZE_1BYTE_LUN 0x30
  1399. #define PKT_OVERRUN_BUFSIZE 0x200
  1400. #define MAX_OFFSET 0xfe
  1401. #define HOST_MSG 0xff
  1402. #define BUS_16_BIT 0x01
  1403. /* Downloaded Constant Definitions */
  1404. #define SG_SIZEOF 0x04
  1405. #define SG_PREFETCH_ALIGN_MASK 0x02
  1406. #define SG_PREFETCH_CNT_LIMIT 0x01
  1407. #define CACHELINE_MASK 0x07
  1408. #define SCB_TRANSFER_SIZE 0x06
  1409. #define PKT_OVERRUN_BUFOFFSET 0x05
  1410. #define SG_PREFETCH_ADDR_MASK 0x03
  1411. #define SG_PREFETCH_CNT 0x00
  1412. #define DOWNLOAD_CONST_COUNT 0x08
  1413. /* Exported Labels */
  1414. #define LABEL_timer_isr 0x28b
  1415. #define LABEL_seq_isr 0x28f