aic79xx_core.c 292 KB

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  1. /*
  2. * Core routines and tables shareable across OS platforms.
  3. *
  4. * Copyright (c) 1994-2002 Justin T. Gibbs.
  5. * Copyright (c) 2000-2003 Adaptec Inc.
  6. * All rights reserved.
  7. *
  8. * Redistribution and use in source and binary forms, with or without
  9. * modification, are permitted provided that the following conditions
  10. * are met:
  11. * 1. Redistributions of source code must retain the above copyright
  12. * notice, this list of conditions, and the following disclaimer,
  13. * without modification.
  14. * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  15. * substantially similar to the "NO WARRANTY" disclaimer below
  16. * ("Disclaimer") and any redistribution must be conditioned upon
  17. * including a substantially similar Disclaimer requirement for further
  18. * binary redistribution.
  19. * 3. Neither the names of the above-listed copyright holders nor the names
  20. * of any contributors may be used to endorse or promote products derived
  21. * from this software without specific prior written permission.
  22. *
  23. * Alternatively, this software may be distributed under the terms of the
  24. * GNU General Public License ("GPL") version 2 as published by the Free
  25. * Software Foundation.
  26. *
  27. * NO WARRANTY
  28. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  31. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32. * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  33. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  34. * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  35. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  36. * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  37. * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  38. * POSSIBILITY OF SUCH DAMAGES.
  39. *
  40. * $Id: //depot/aic7xxx/aic7xxx/aic79xx.c#250 $
  41. */
  42. #ifdef __linux__
  43. #include "aic79xx_osm.h"
  44. #include "aic79xx_inline.h"
  45. #include "aicasm/aicasm_insformat.h"
  46. #else
  47. #include <dev/aic7xxx/aic79xx_osm.h>
  48. #include <dev/aic7xxx/aic79xx_inline.h>
  49. #include <dev/aic7xxx/aicasm/aicasm_insformat.h>
  50. #endif
  51. /***************************** Lookup Tables **********************************/
  52. static const char *const ahd_chip_names[] =
  53. {
  54. "NONE",
  55. "aic7901",
  56. "aic7902",
  57. "aic7901A"
  58. };
  59. static const u_int num_chip_names = ARRAY_SIZE(ahd_chip_names);
  60. /*
  61. * Hardware error codes.
  62. */
  63. struct ahd_hard_error_entry {
  64. uint8_t errno;
  65. const char *errmesg;
  66. };
  67. static const struct ahd_hard_error_entry ahd_hard_errors[] = {
  68. { DSCTMOUT, "Discard Timer has timed out" },
  69. { ILLOPCODE, "Illegal Opcode in sequencer program" },
  70. { SQPARERR, "Sequencer Parity Error" },
  71. { DPARERR, "Data-path Parity Error" },
  72. { MPARERR, "Scratch or SCB Memory Parity Error" },
  73. { CIOPARERR, "CIOBUS Parity Error" },
  74. };
  75. static const u_int num_errors = ARRAY_SIZE(ahd_hard_errors);
  76. static const struct ahd_phase_table_entry ahd_phase_table[] =
  77. {
  78. { P_DATAOUT, MSG_NOOP, "in Data-out phase" },
  79. { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" },
  80. { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" },
  81. { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" },
  82. { P_COMMAND, MSG_NOOP, "in Command phase" },
  83. { P_MESGOUT, MSG_NOOP, "in Message-out phase" },
  84. { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" },
  85. { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" },
  86. { P_BUSFREE, MSG_NOOP, "while idle" },
  87. { 0, MSG_NOOP, "in unknown phase" }
  88. };
  89. /*
  90. * In most cases we only wish to itterate over real phases, so
  91. * exclude the last element from the count.
  92. */
  93. static const u_int num_phases = ARRAY_SIZE(ahd_phase_table) - 1;
  94. /* Our Sequencer Program */
  95. #include "aic79xx_seq.h"
  96. /**************************** Function Declarations ***************************/
  97. static void ahd_handle_transmission_error(struct ahd_softc *ahd);
  98. static void ahd_handle_lqiphase_error(struct ahd_softc *ahd,
  99. u_int lqistat1);
  100. static int ahd_handle_pkt_busfree(struct ahd_softc *ahd,
  101. u_int busfreetime);
  102. static int ahd_handle_nonpkt_busfree(struct ahd_softc *ahd);
  103. static void ahd_handle_proto_violation(struct ahd_softc *ahd);
  104. static void ahd_force_renegotiation(struct ahd_softc *ahd,
  105. struct ahd_devinfo *devinfo);
  106. static struct ahd_tmode_tstate*
  107. ahd_alloc_tstate(struct ahd_softc *ahd,
  108. u_int scsi_id, char channel);
  109. #ifdef AHD_TARGET_MODE
  110. static void ahd_free_tstate(struct ahd_softc *ahd,
  111. u_int scsi_id, char channel, int force);
  112. #endif
  113. static void ahd_devlimited_syncrate(struct ahd_softc *ahd,
  114. struct ahd_initiator_tinfo *,
  115. u_int *period,
  116. u_int *ppr_options,
  117. role_t role);
  118. static void ahd_update_neg_table(struct ahd_softc *ahd,
  119. struct ahd_devinfo *devinfo,
  120. struct ahd_transinfo *tinfo);
  121. static void ahd_update_pending_scbs(struct ahd_softc *ahd);
  122. static void ahd_fetch_devinfo(struct ahd_softc *ahd,
  123. struct ahd_devinfo *devinfo);
  124. static void ahd_scb_devinfo(struct ahd_softc *ahd,
  125. struct ahd_devinfo *devinfo,
  126. struct scb *scb);
  127. static void ahd_setup_initiator_msgout(struct ahd_softc *ahd,
  128. struct ahd_devinfo *devinfo,
  129. struct scb *scb);
  130. static void ahd_build_transfer_msg(struct ahd_softc *ahd,
  131. struct ahd_devinfo *devinfo);
  132. static void ahd_construct_sdtr(struct ahd_softc *ahd,
  133. struct ahd_devinfo *devinfo,
  134. u_int period, u_int offset);
  135. static void ahd_construct_wdtr(struct ahd_softc *ahd,
  136. struct ahd_devinfo *devinfo,
  137. u_int bus_width);
  138. static void ahd_construct_ppr(struct ahd_softc *ahd,
  139. struct ahd_devinfo *devinfo,
  140. u_int period, u_int offset,
  141. u_int bus_width, u_int ppr_options);
  142. static void ahd_clear_msg_state(struct ahd_softc *ahd);
  143. static void ahd_handle_message_phase(struct ahd_softc *ahd);
  144. typedef enum {
  145. AHDMSG_1B,
  146. AHDMSG_2B,
  147. AHDMSG_EXT
  148. } ahd_msgtype;
  149. static int ahd_sent_msg(struct ahd_softc *ahd, ahd_msgtype type,
  150. u_int msgval, int full);
  151. static int ahd_parse_msg(struct ahd_softc *ahd,
  152. struct ahd_devinfo *devinfo);
  153. static int ahd_handle_msg_reject(struct ahd_softc *ahd,
  154. struct ahd_devinfo *devinfo);
  155. static void ahd_handle_ign_wide_residue(struct ahd_softc *ahd,
  156. struct ahd_devinfo *devinfo);
  157. static void ahd_reinitialize_dataptrs(struct ahd_softc *ahd);
  158. static void ahd_handle_devreset(struct ahd_softc *ahd,
  159. struct ahd_devinfo *devinfo,
  160. u_int lun, cam_status status,
  161. char *message, int verbose_level);
  162. #ifdef AHD_TARGET_MODE
  163. static void ahd_setup_target_msgin(struct ahd_softc *ahd,
  164. struct ahd_devinfo *devinfo,
  165. struct scb *scb);
  166. #endif
  167. static u_int ahd_sglist_size(struct ahd_softc *ahd);
  168. static u_int ahd_sglist_allocsize(struct ahd_softc *ahd);
  169. static bus_dmamap_callback_t
  170. ahd_dmamap_cb;
  171. static void ahd_initialize_hscbs(struct ahd_softc *ahd);
  172. static int ahd_init_scbdata(struct ahd_softc *ahd);
  173. static void ahd_fini_scbdata(struct ahd_softc *ahd);
  174. static void ahd_setup_iocell_workaround(struct ahd_softc *ahd);
  175. static void ahd_iocell_first_selection(struct ahd_softc *ahd);
  176. static void ahd_add_col_list(struct ahd_softc *ahd,
  177. struct scb *scb, u_int col_idx);
  178. static void ahd_rem_col_list(struct ahd_softc *ahd,
  179. struct scb *scb);
  180. static void ahd_chip_init(struct ahd_softc *ahd);
  181. static void ahd_qinfifo_requeue(struct ahd_softc *ahd,
  182. struct scb *prev_scb,
  183. struct scb *scb);
  184. static int ahd_qinfifo_count(struct ahd_softc *ahd);
  185. static int ahd_search_scb_list(struct ahd_softc *ahd, int target,
  186. char channel, int lun, u_int tag,
  187. role_t role, uint32_t status,
  188. ahd_search_action action,
  189. u_int *list_head, u_int *list_tail,
  190. u_int tid);
  191. static void ahd_stitch_tid_list(struct ahd_softc *ahd,
  192. u_int tid_prev, u_int tid_cur,
  193. u_int tid_next);
  194. static void ahd_add_scb_to_free_list(struct ahd_softc *ahd,
  195. u_int scbid);
  196. static u_int ahd_rem_wscb(struct ahd_softc *ahd, u_int scbid,
  197. u_int prev, u_int next, u_int tid);
  198. static void ahd_reset_current_bus(struct ahd_softc *ahd);
  199. static void ahd_stat_timer(struct timer_list *t);
  200. #ifdef AHD_DUMP_SEQ
  201. static void ahd_dumpseq(struct ahd_softc *ahd);
  202. #endif
  203. static void ahd_loadseq(struct ahd_softc *ahd);
  204. static int ahd_check_patch(struct ahd_softc *ahd,
  205. const struct patch **start_patch,
  206. u_int start_instr, u_int *skip_addr);
  207. static u_int ahd_resolve_seqaddr(struct ahd_softc *ahd,
  208. u_int address);
  209. static void ahd_download_instr(struct ahd_softc *ahd,
  210. u_int instrptr, uint8_t *dconsts);
  211. static int ahd_probe_stack_size(struct ahd_softc *ahd);
  212. static int ahd_scb_active_in_fifo(struct ahd_softc *ahd,
  213. struct scb *scb);
  214. static void ahd_run_data_fifo(struct ahd_softc *ahd,
  215. struct scb *scb);
  216. #ifdef AHD_TARGET_MODE
  217. static void ahd_queue_lstate_event(struct ahd_softc *ahd,
  218. struct ahd_tmode_lstate *lstate,
  219. u_int initiator_id,
  220. u_int event_type,
  221. u_int event_arg);
  222. static void ahd_update_scsiid(struct ahd_softc *ahd,
  223. u_int targid_mask);
  224. static int ahd_handle_target_cmd(struct ahd_softc *ahd,
  225. struct target_cmd *cmd);
  226. #endif
  227. static int ahd_abort_scbs(struct ahd_softc *ahd, int target,
  228. char channel, int lun, u_int tag,
  229. role_t role, uint32_t status);
  230. static void ahd_alloc_scbs(struct ahd_softc *ahd);
  231. static void ahd_busy_tcl(struct ahd_softc *ahd, u_int tcl,
  232. u_int scbid);
  233. static void ahd_calc_residual(struct ahd_softc *ahd,
  234. struct scb *scb);
  235. static void ahd_clear_critical_section(struct ahd_softc *ahd);
  236. static void ahd_clear_intstat(struct ahd_softc *ahd);
  237. static void ahd_enable_coalescing(struct ahd_softc *ahd,
  238. int enable);
  239. static u_int ahd_find_busy_tcl(struct ahd_softc *ahd, u_int tcl);
  240. static void ahd_freeze_devq(struct ahd_softc *ahd,
  241. struct scb *scb);
  242. static void ahd_handle_scb_status(struct ahd_softc *ahd,
  243. struct scb *scb);
  244. static const struct ahd_phase_table_entry* ahd_lookup_phase_entry(int phase);
  245. static void ahd_shutdown(void *arg);
  246. static void ahd_update_coalescing_values(struct ahd_softc *ahd,
  247. u_int timer,
  248. u_int maxcmds,
  249. u_int mincmds);
  250. static int ahd_verify_vpd_cksum(struct vpd_config *vpd);
  251. static int ahd_wait_seeprom(struct ahd_softc *ahd);
  252. static int ahd_match_scb(struct ahd_softc *ahd, struct scb *scb,
  253. int target, char channel, int lun,
  254. u_int tag, role_t role);
  255. static void ahd_reset_cmds_pending(struct ahd_softc *ahd);
  256. /*************************** Interrupt Services *******************************/
  257. static void ahd_run_qoutfifo(struct ahd_softc *ahd);
  258. #ifdef AHD_TARGET_MODE
  259. static void ahd_run_tqinfifo(struct ahd_softc *ahd, int paused);
  260. #endif
  261. static void ahd_handle_hwerrint(struct ahd_softc *ahd);
  262. static void ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat);
  263. static void ahd_handle_scsiint(struct ahd_softc *ahd,
  264. u_int intstat);
  265. /************************ Sequencer Execution Control *************************/
  266. void
  267. ahd_set_modes(struct ahd_softc *ahd, ahd_mode src, ahd_mode dst)
  268. {
  269. if (ahd->src_mode == src && ahd->dst_mode == dst)
  270. return;
  271. #ifdef AHD_DEBUG
  272. if (ahd->src_mode == AHD_MODE_UNKNOWN
  273. || ahd->dst_mode == AHD_MODE_UNKNOWN)
  274. panic("Setting mode prior to saving it.\n");
  275. if ((ahd_debug & AHD_SHOW_MODEPTR) != 0)
  276. printk("%s: Setting mode 0x%x\n", ahd_name(ahd),
  277. ahd_build_mode_state(ahd, src, dst));
  278. #endif
  279. ahd_outb(ahd, MODE_PTR, ahd_build_mode_state(ahd, src, dst));
  280. ahd->src_mode = src;
  281. ahd->dst_mode = dst;
  282. }
  283. static void
  284. ahd_update_modes(struct ahd_softc *ahd)
  285. {
  286. ahd_mode_state mode_ptr;
  287. ahd_mode src;
  288. ahd_mode dst;
  289. mode_ptr = ahd_inb(ahd, MODE_PTR);
  290. #ifdef AHD_DEBUG
  291. if ((ahd_debug & AHD_SHOW_MODEPTR) != 0)
  292. printk("Reading mode 0x%x\n", mode_ptr);
  293. #endif
  294. ahd_extract_mode_state(ahd, mode_ptr, &src, &dst);
  295. ahd_known_modes(ahd, src, dst);
  296. }
  297. static void
  298. ahd_assert_modes(struct ahd_softc *ahd, ahd_mode srcmode,
  299. ahd_mode dstmode, const char *file, int line)
  300. {
  301. #ifdef AHD_DEBUG
  302. if ((srcmode & AHD_MK_MSK(ahd->src_mode)) == 0
  303. || (dstmode & AHD_MK_MSK(ahd->dst_mode)) == 0) {
  304. panic("%s:%s:%d: Mode assertion failed.\n",
  305. ahd_name(ahd), file, line);
  306. }
  307. #endif
  308. }
  309. #define AHD_ASSERT_MODES(ahd, source, dest) \
  310. ahd_assert_modes(ahd, source, dest, __FILE__, __LINE__);
  311. ahd_mode_state
  312. ahd_save_modes(struct ahd_softc *ahd)
  313. {
  314. if (ahd->src_mode == AHD_MODE_UNKNOWN
  315. || ahd->dst_mode == AHD_MODE_UNKNOWN)
  316. ahd_update_modes(ahd);
  317. return (ahd_build_mode_state(ahd, ahd->src_mode, ahd->dst_mode));
  318. }
  319. void
  320. ahd_restore_modes(struct ahd_softc *ahd, ahd_mode_state state)
  321. {
  322. ahd_mode src;
  323. ahd_mode dst;
  324. ahd_extract_mode_state(ahd, state, &src, &dst);
  325. ahd_set_modes(ahd, src, dst);
  326. }
  327. /*
  328. * Determine whether the sequencer has halted code execution.
  329. * Returns non-zero status if the sequencer is stopped.
  330. */
  331. int
  332. ahd_is_paused(struct ahd_softc *ahd)
  333. {
  334. return ((ahd_inb(ahd, HCNTRL) & PAUSE) != 0);
  335. }
  336. /*
  337. * Request that the sequencer stop and wait, indefinitely, for it
  338. * to stop. The sequencer will only acknowledge that it is paused
  339. * once it has reached an instruction boundary and PAUSEDIS is
  340. * cleared in the SEQCTL register. The sequencer may use PAUSEDIS
  341. * for critical sections.
  342. */
  343. void
  344. ahd_pause(struct ahd_softc *ahd)
  345. {
  346. ahd_outb(ahd, HCNTRL, ahd->pause);
  347. /*
  348. * Since the sequencer can disable pausing in a critical section, we
  349. * must loop until it actually stops.
  350. */
  351. while (ahd_is_paused(ahd) == 0)
  352. ;
  353. }
  354. /*
  355. * Allow the sequencer to continue program execution.
  356. * We check here to ensure that no additional interrupt
  357. * sources that would cause the sequencer to halt have been
  358. * asserted. If, for example, a SCSI bus reset is detected
  359. * while we are fielding a different, pausing, interrupt type,
  360. * we don't want to release the sequencer before going back
  361. * into our interrupt handler and dealing with this new
  362. * condition.
  363. */
  364. void
  365. ahd_unpause(struct ahd_softc *ahd)
  366. {
  367. /*
  368. * Automatically restore our modes to those saved
  369. * prior to the first change of the mode.
  370. */
  371. if (ahd->saved_src_mode != AHD_MODE_UNKNOWN
  372. && ahd->saved_dst_mode != AHD_MODE_UNKNOWN) {
  373. if ((ahd->flags & AHD_UPDATE_PEND_CMDS) != 0)
  374. ahd_reset_cmds_pending(ahd);
  375. ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode);
  376. }
  377. if ((ahd_inb(ahd, INTSTAT) & ~CMDCMPLT) == 0)
  378. ahd_outb(ahd, HCNTRL, ahd->unpause);
  379. ahd_known_modes(ahd, AHD_MODE_UNKNOWN, AHD_MODE_UNKNOWN);
  380. }
  381. /*********************** Scatter Gather List Handling *************************/
  382. void *
  383. ahd_sg_setup(struct ahd_softc *ahd, struct scb *scb,
  384. void *sgptr, dma_addr_t addr, bus_size_t len, int last)
  385. {
  386. scb->sg_count++;
  387. if (sizeof(dma_addr_t) > 4
  388. && (ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
  389. struct ahd_dma64_seg *sg;
  390. sg = (struct ahd_dma64_seg *)sgptr;
  391. sg->addr = ahd_htole64(addr);
  392. sg->len = ahd_htole32(len | (last ? AHD_DMA_LAST_SEG : 0));
  393. return (sg + 1);
  394. } else {
  395. struct ahd_dma_seg *sg;
  396. sg = (struct ahd_dma_seg *)sgptr;
  397. sg->addr = ahd_htole32(addr & 0xFFFFFFFF);
  398. sg->len = ahd_htole32(len | ((addr >> 8) & 0x7F000000)
  399. | (last ? AHD_DMA_LAST_SEG : 0));
  400. return (sg + 1);
  401. }
  402. }
  403. static void
  404. ahd_setup_scb_common(struct ahd_softc *ahd, struct scb *scb)
  405. {
  406. /* XXX Handle target mode SCBs. */
  407. scb->crc_retry_count = 0;
  408. if ((scb->flags & SCB_PACKETIZED) != 0) {
  409. /* XXX what about ACA?? It is type 4, but TAG_TYPE == 0x3. */
  410. scb->hscb->task_attribute = scb->hscb->control & SCB_TAG_TYPE;
  411. } else {
  412. if (ahd_get_transfer_length(scb) & 0x01)
  413. scb->hscb->task_attribute = SCB_XFERLEN_ODD;
  414. else
  415. scb->hscb->task_attribute = 0;
  416. }
  417. if (scb->hscb->cdb_len <= MAX_CDB_LEN_WITH_SENSE_ADDR
  418. || (scb->hscb->cdb_len & SCB_CDB_LEN_PTR) != 0)
  419. scb->hscb->shared_data.idata.cdb_plus_saddr.sense_addr =
  420. ahd_htole32(scb->sense_busaddr);
  421. }
  422. static void
  423. ahd_setup_data_scb(struct ahd_softc *ahd, struct scb *scb)
  424. {
  425. /*
  426. * Copy the first SG into the "current" data ponter area.
  427. */
  428. if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
  429. struct ahd_dma64_seg *sg;
  430. sg = (struct ahd_dma64_seg *)scb->sg_list;
  431. scb->hscb->dataptr = sg->addr;
  432. scb->hscb->datacnt = sg->len;
  433. } else {
  434. struct ahd_dma_seg *sg;
  435. uint32_t *dataptr_words;
  436. sg = (struct ahd_dma_seg *)scb->sg_list;
  437. dataptr_words = (uint32_t*)&scb->hscb->dataptr;
  438. dataptr_words[0] = sg->addr;
  439. dataptr_words[1] = 0;
  440. if ((ahd->flags & AHD_39BIT_ADDRESSING) != 0) {
  441. uint64_t high_addr;
  442. high_addr = ahd_le32toh(sg->len) & 0x7F000000;
  443. scb->hscb->dataptr |= ahd_htole64(high_addr << 8);
  444. }
  445. scb->hscb->datacnt = sg->len;
  446. }
  447. /*
  448. * Note where to find the SG entries in bus space.
  449. * We also set the full residual flag which the
  450. * sequencer will clear as soon as a data transfer
  451. * occurs.
  452. */
  453. scb->hscb->sgptr = ahd_htole32(scb->sg_list_busaddr|SG_FULL_RESID);
  454. }
  455. static void
  456. ahd_setup_noxfer_scb(struct ahd_softc *ahd, struct scb *scb)
  457. {
  458. scb->hscb->sgptr = ahd_htole32(SG_LIST_NULL);
  459. scb->hscb->dataptr = 0;
  460. scb->hscb->datacnt = 0;
  461. }
  462. /************************** Memory mapping routines ***************************/
  463. static void *
  464. ahd_sg_bus_to_virt(struct ahd_softc *ahd, struct scb *scb, uint32_t sg_busaddr)
  465. {
  466. dma_addr_t sg_offset;
  467. /* sg_list_phys points to entry 1, not 0 */
  468. sg_offset = sg_busaddr - (scb->sg_list_busaddr - ahd_sg_size(ahd));
  469. return ((uint8_t *)scb->sg_list + sg_offset);
  470. }
  471. static uint32_t
  472. ahd_sg_virt_to_bus(struct ahd_softc *ahd, struct scb *scb, void *sg)
  473. {
  474. dma_addr_t sg_offset;
  475. /* sg_list_phys points to entry 1, not 0 */
  476. sg_offset = ((uint8_t *)sg - (uint8_t *)scb->sg_list)
  477. - ahd_sg_size(ahd);
  478. return (scb->sg_list_busaddr + sg_offset);
  479. }
  480. static void
  481. ahd_sync_scb(struct ahd_softc *ahd, struct scb *scb, int op)
  482. {
  483. ahd_dmamap_sync(ahd, ahd->scb_data.hscb_dmat,
  484. scb->hscb_map->dmamap,
  485. /*offset*/(uint8_t*)scb->hscb - scb->hscb_map->vaddr,
  486. /*len*/sizeof(*scb->hscb), op);
  487. }
  488. void
  489. ahd_sync_sglist(struct ahd_softc *ahd, struct scb *scb, int op)
  490. {
  491. if (scb->sg_count == 0)
  492. return;
  493. ahd_dmamap_sync(ahd, ahd->scb_data.sg_dmat,
  494. scb->sg_map->dmamap,
  495. /*offset*/scb->sg_list_busaddr - ahd_sg_size(ahd),
  496. /*len*/ahd_sg_size(ahd) * scb->sg_count, op);
  497. }
  498. static void
  499. ahd_sync_sense(struct ahd_softc *ahd, struct scb *scb, int op)
  500. {
  501. ahd_dmamap_sync(ahd, ahd->scb_data.sense_dmat,
  502. scb->sense_map->dmamap,
  503. /*offset*/scb->sense_busaddr,
  504. /*len*/AHD_SENSE_BUFSIZE, op);
  505. }
  506. #ifdef AHD_TARGET_MODE
  507. static uint32_t
  508. ahd_targetcmd_offset(struct ahd_softc *ahd, u_int index)
  509. {
  510. return (((uint8_t *)&ahd->targetcmds[index])
  511. - (uint8_t *)ahd->qoutfifo);
  512. }
  513. #endif
  514. /*********************** Miscellaneous Support Functions ***********************/
  515. /*
  516. * Return pointers to the transfer negotiation information
  517. * for the specified our_id/remote_id pair.
  518. */
  519. struct ahd_initiator_tinfo *
  520. ahd_fetch_transinfo(struct ahd_softc *ahd, char channel, u_int our_id,
  521. u_int remote_id, struct ahd_tmode_tstate **tstate)
  522. {
  523. /*
  524. * Transfer data structures are stored from the perspective
  525. * of the target role. Since the parameters for a connection
  526. * in the initiator role to a given target are the same as
  527. * when the roles are reversed, we pretend we are the target.
  528. */
  529. if (channel == 'B')
  530. our_id += 8;
  531. *tstate = ahd->enabled_targets[our_id];
  532. return (&(*tstate)->transinfo[remote_id]);
  533. }
  534. uint16_t
  535. ahd_inw(struct ahd_softc *ahd, u_int port)
  536. {
  537. /*
  538. * Read high byte first as some registers increment
  539. * or have other side effects when the low byte is
  540. * read.
  541. */
  542. uint16_t r = ahd_inb(ahd, port+1) << 8;
  543. return r | ahd_inb(ahd, port);
  544. }
  545. void
  546. ahd_outw(struct ahd_softc *ahd, u_int port, u_int value)
  547. {
  548. /*
  549. * Write low byte first to accommodate registers
  550. * such as PRGMCNT where the order maters.
  551. */
  552. ahd_outb(ahd, port, value & 0xFF);
  553. ahd_outb(ahd, port+1, (value >> 8) & 0xFF);
  554. }
  555. uint32_t
  556. ahd_inl(struct ahd_softc *ahd, u_int port)
  557. {
  558. return ((ahd_inb(ahd, port))
  559. | (ahd_inb(ahd, port+1) << 8)
  560. | (ahd_inb(ahd, port+2) << 16)
  561. | (ahd_inb(ahd, port+3) << 24));
  562. }
  563. void
  564. ahd_outl(struct ahd_softc *ahd, u_int port, uint32_t value)
  565. {
  566. ahd_outb(ahd, port, (value) & 0xFF);
  567. ahd_outb(ahd, port+1, ((value) >> 8) & 0xFF);
  568. ahd_outb(ahd, port+2, ((value) >> 16) & 0xFF);
  569. ahd_outb(ahd, port+3, ((value) >> 24) & 0xFF);
  570. }
  571. uint64_t
  572. ahd_inq(struct ahd_softc *ahd, u_int port)
  573. {
  574. return ((ahd_inb(ahd, port))
  575. | (ahd_inb(ahd, port+1) << 8)
  576. | (ahd_inb(ahd, port+2) << 16)
  577. | (ahd_inb(ahd, port+3) << 24)
  578. | (((uint64_t)ahd_inb(ahd, port+4)) << 32)
  579. | (((uint64_t)ahd_inb(ahd, port+5)) << 40)
  580. | (((uint64_t)ahd_inb(ahd, port+6)) << 48)
  581. | (((uint64_t)ahd_inb(ahd, port+7)) << 56));
  582. }
  583. void
  584. ahd_outq(struct ahd_softc *ahd, u_int port, uint64_t value)
  585. {
  586. ahd_outb(ahd, port, value & 0xFF);
  587. ahd_outb(ahd, port+1, (value >> 8) & 0xFF);
  588. ahd_outb(ahd, port+2, (value >> 16) & 0xFF);
  589. ahd_outb(ahd, port+3, (value >> 24) & 0xFF);
  590. ahd_outb(ahd, port+4, (value >> 32) & 0xFF);
  591. ahd_outb(ahd, port+5, (value >> 40) & 0xFF);
  592. ahd_outb(ahd, port+6, (value >> 48) & 0xFF);
  593. ahd_outb(ahd, port+7, (value >> 56) & 0xFF);
  594. }
  595. u_int
  596. ahd_get_scbptr(struct ahd_softc *ahd)
  597. {
  598. AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
  599. ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
  600. return (ahd_inb(ahd, SCBPTR) | (ahd_inb(ahd, SCBPTR + 1) << 8));
  601. }
  602. void
  603. ahd_set_scbptr(struct ahd_softc *ahd, u_int scbptr)
  604. {
  605. AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
  606. ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
  607. ahd_outb(ahd, SCBPTR, scbptr & 0xFF);
  608. ahd_outb(ahd, SCBPTR+1, (scbptr >> 8) & 0xFF);
  609. }
  610. #if 0 /* unused */
  611. static u_int
  612. ahd_get_hnscb_qoff(struct ahd_softc *ahd)
  613. {
  614. return (ahd_inw_atomic(ahd, HNSCB_QOFF));
  615. }
  616. #endif
  617. static void
  618. ahd_set_hnscb_qoff(struct ahd_softc *ahd, u_int value)
  619. {
  620. ahd_outw_atomic(ahd, HNSCB_QOFF, value);
  621. }
  622. #if 0 /* unused */
  623. static u_int
  624. ahd_get_hescb_qoff(struct ahd_softc *ahd)
  625. {
  626. return (ahd_inb(ahd, HESCB_QOFF));
  627. }
  628. #endif
  629. static void
  630. ahd_set_hescb_qoff(struct ahd_softc *ahd, u_int value)
  631. {
  632. ahd_outb(ahd, HESCB_QOFF, value);
  633. }
  634. static u_int
  635. ahd_get_snscb_qoff(struct ahd_softc *ahd)
  636. {
  637. u_int oldvalue;
  638. AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
  639. oldvalue = ahd_inw(ahd, SNSCB_QOFF);
  640. ahd_outw(ahd, SNSCB_QOFF, oldvalue);
  641. return (oldvalue);
  642. }
  643. static void
  644. ahd_set_snscb_qoff(struct ahd_softc *ahd, u_int value)
  645. {
  646. AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
  647. ahd_outw(ahd, SNSCB_QOFF, value);
  648. }
  649. #if 0 /* unused */
  650. static u_int
  651. ahd_get_sescb_qoff(struct ahd_softc *ahd)
  652. {
  653. AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
  654. return (ahd_inb(ahd, SESCB_QOFF));
  655. }
  656. #endif
  657. static void
  658. ahd_set_sescb_qoff(struct ahd_softc *ahd, u_int value)
  659. {
  660. AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
  661. ahd_outb(ahd, SESCB_QOFF, value);
  662. }
  663. #if 0 /* unused */
  664. static u_int
  665. ahd_get_sdscb_qoff(struct ahd_softc *ahd)
  666. {
  667. AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
  668. return (ahd_inb(ahd, SDSCB_QOFF) | (ahd_inb(ahd, SDSCB_QOFF + 1) << 8));
  669. }
  670. #endif
  671. static void
  672. ahd_set_sdscb_qoff(struct ahd_softc *ahd, u_int value)
  673. {
  674. AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
  675. ahd_outb(ahd, SDSCB_QOFF, value & 0xFF);
  676. ahd_outb(ahd, SDSCB_QOFF+1, (value >> 8) & 0xFF);
  677. }
  678. u_int
  679. ahd_inb_scbram(struct ahd_softc *ahd, u_int offset)
  680. {
  681. u_int value;
  682. /*
  683. * Workaround PCI-X Rev A. hardware bug.
  684. * After a host read of SCB memory, the chip
  685. * may become confused into thinking prefetch
  686. * was required. This starts the discard timer
  687. * running and can cause an unexpected discard
  688. * timer interrupt. The work around is to read
  689. * a normal register prior to the exhaustion of
  690. * the discard timer. The mode pointer register
  691. * has no side effects and so serves well for
  692. * this purpose.
  693. *
  694. * Razor #528
  695. */
  696. value = ahd_inb(ahd, offset);
  697. if ((ahd->bugs & AHD_PCIX_SCBRAM_RD_BUG) != 0)
  698. ahd_inb(ahd, MODE_PTR);
  699. return (value);
  700. }
  701. u_int
  702. ahd_inw_scbram(struct ahd_softc *ahd, u_int offset)
  703. {
  704. return (ahd_inb_scbram(ahd, offset)
  705. | (ahd_inb_scbram(ahd, offset+1) << 8));
  706. }
  707. static uint32_t
  708. ahd_inl_scbram(struct ahd_softc *ahd, u_int offset)
  709. {
  710. return (ahd_inw_scbram(ahd, offset)
  711. | (ahd_inw_scbram(ahd, offset+2) << 16));
  712. }
  713. static uint64_t
  714. ahd_inq_scbram(struct ahd_softc *ahd, u_int offset)
  715. {
  716. return (ahd_inl_scbram(ahd, offset)
  717. | ((uint64_t)ahd_inl_scbram(ahd, offset+4)) << 32);
  718. }
  719. struct scb *
  720. ahd_lookup_scb(struct ahd_softc *ahd, u_int tag)
  721. {
  722. struct scb* scb;
  723. if (tag >= AHD_SCB_MAX)
  724. return (NULL);
  725. scb = ahd->scb_data.scbindex[tag];
  726. if (scb != NULL)
  727. ahd_sync_scb(ahd, scb,
  728. BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
  729. return (scb);
  730. }
  731. static void
  732. ahd_swap_with_next_hscb(struct ahd_softc *ahd, struct scb *scb)
  733. {
  734. struct hardware_scb *q_hscb;
  735. struct map_node *q_hscb_map;
  736. uint32_t saved_hscb_busaddr;
  737. /*
  738. * Our queuing method is a bit tricky. The card
  739. * knows in advance which HSCB (by address) to download,
  740. * and we can't disappoint it. To achieve this, the next
  741. * HSCB to download is saved off in ahd->next_queued_hscb.
  742. * When we are called to queue "an arbitrary scb",
  743. * we copy the contents of the incoming HSCB to the one
  744. * the sequencer knows about, swap HSCB pointers and
  745. * finally assign the SCB to the tag indexed location
  746. * in the scb_array. This makes sure that we can still
  747. * locate the correct SCB by SCB_TAG.
  748. */
  749. q_hscb = ahd->next_queued_hscb;
  750. q_hscb_map = ahd->next_queued_hscb_map;
  751. saved_hscb_busaddr = q_hscb->hscb_busaddr;
  752. memcpy(q_hscb, scb->hscb, sizeof(*scb->hscb));
  753. q_hscb->hscb_busaddr = saved_hscb_busaddr;
  754. q_hscb->next_hscb_busaddr = scb->hscb->hscb_busaddr;
  755. /* Now swap HSCB pointers. */
  756. ahd->next_queued_hscb = scb->hscb;
  757. ahd->next_queued_hscb_map = scb->hscb_map;
  758. scb->hscb = q_hscb;
  759. scb->hscb_map = q_hscb_map;
  760. /* Now define the mapping from tag to SCB in the scbindex */
  761. ahd->scb_data.scbindex[SCB_GET_TAG(scb)] = scb;
  762. }
  763. /*
  764. * Tell the sequencer about a new transaction to execute.
  765. */
  766. void
  767. ahd_queue_scb(struct ahd_softc *ahd, struct scb *scb)
  768. {
  769. ahd_swap_with_next_hscb(ahd, scb);
  770. if (SCBID_IS_NULL(SCB_GET_TAG(scb)))
  771. panic("Attempt to queue invalid SCB tag %x\n",
  772. SCB_GET_TAG(scb));
  773. /*
  774. * Keep a history of SCBs we've downloaded in the qinfifo.
  775. */
  776. ahd->qinfifo[AHD_QIN_WRAP(ahd->qinfifonext)] = SCB_GET_TAG(scb);
  777. ahd->qinfifonext++;
  778. if (scb->sg_count != 0)
  779. ahd_setup_data_scb(ahd, scb);
  780. else
  781. ahd_setup_noxfer_scb(ahd, scb);
  782. ahd_setup_scb_common(ahd, scb);
  783. /*
  784. * Make sure our data is consistent from the
  785. * perspective of the adapter.
  786. */
  787. ahd_sync_scb(ahd, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
  788. #ifdef AHD_DEBUG
  789. if ((ahd_debug & AHD_SHOW_QUEUE) != 0) {
  790. uint64_t host_dataptr;
  791. host_dataptr = ahd_le64toh(scb->hscb->dataptr);
  792. printk("%s: Queueing SCB %d:0x%x bus addr 0x%x - 0x%x%x/0x%x\n",
  793. ahd_name(ahd),
  794. SCB_GET_TAG(scb), scb->hscb->scsiid,
  795. ahd_le32toh(scb->hscb->hscb_busaddr),
  796. (u_int)((host_dataptr >> 32) & 0xFFFFFFFF),
  797. (u_int)(host_dataptr & 0xFFFFFFFF),
  798. ahd_le32toh(scb->hscb->datacnt));
  799. }
  800. #endif
  801. /* Tell the adapter about the newly queued SCB */
  802. ahd_set_hnscb_qoff(ahd, ahd->qinfifonext);
  803. }
  804. /************************** Interrupt Processing ******************************/
  805. static void
  806. ahd_sync_qoutfifo(struct ahd_softc *ahd, int op)
  807. {
  808. ahd_dmamap_sync(ahd, ahd->shared_data_dmat, ahd->shared_data_map.dmamap,
  809. /*offset*/0,
  810. /*len*/AHD_SCB_MAX * sizeof(struct ahd_completion), op);
  811. }
  812. static void
  813. ahd_sync_tqinfifo(struct ahd_softc *ahd, int op)
  814. {
  815. #ifdef AHD_TARGET_MODE
  816. if ((ahd->flags & AHD_TARGETROLE) != 0) {
  817. ahd_dmamap_sync(ahd, ahd->shared_data_dmat,
  818. ahd->shared_data_map.dmamap,
  819. ahd_targetcmd_offset(ahd, 0),
  820. sizeof(struct target_cmd) * AHD_TMODE_CMDS,
  821. op);
  822. }
  823. #endif
  824. }
  825. /*
  826. * See if the firmware has posted any completed commands
  827. * into our in-core command complete fifos.
  828. */
  829. #define AHD_RUN_QOUTFIFO 0x1
  830. #define AHD_RUN_TQINFIFO 0x2
  831. static u_int
  832. ahd_check_cmdcmpltqueues(struct ahd_softc *ahd)
  833. {
  834. u_int retval;
  835. retval = 0;
  836. ahd_dmamap_sync(ahd, ahd->shared_data_dmat, ahd->shared_data_map.dmamap,
  837. /*offset*/ahd->qoutfifonext * sizeof(*ahd->qoutfifo),
  838. /*len*/sizeof(*ahd->qoutfifo), BUS_DMASYNC_POSTREAD);
  839. if (ahd->qoutfifo[ahd->qoutfifonext].valid_tag
  840. == ahd->qoutfifonext_valid_tag)
  841. retval |= AHD_RUN_QOUTFIFO;
  842. #ifdef AHD_TARGET_MODE
  843. if ((ahd->flags & AHD_TARGETROLE) != 0
  844. && (ahd->flags & AHD_TQINFIFO_BLOCKED) == 0) {
  845. ahd_dmamap_sync(ahd, ahd->shared_data_dmat,
  846. ahd->shared_data_map.dmamap,
  847. ahd_targetcmd_offset(ahd, ahd->tqinfifofnext),
  848. /*len*/sizeof(struct target_cmd),
  849. BUS_DMASYNC_POSTREAD);
  850. if (ahd->targetcmds[ahd->tqinfifonext].cmd_valid != 0)
  851. retval |= AHD_RUN_TQINFIFO;
  852. }
  853. #endif
  854. return (retval);
  855. }
  856. /*
  857. * Catch an interrupt from the adapter
  858. */
  859. int
  860. ahd_intr(struct ahd_softc *ahd)
  861. {
  862. u_int intstat;
  863. if ((ahd->pause & INTEN) == 0) {
  864. /*
  865. * Our interrupt is not enabled on the chip
  866. * and may be disabled for re-entrancy reasons,
  867. * so just return. This is likely just a shared
  868. * interrupt.
  869. */
  870. return (0);
  871. }
  872. /*
  873. * Instead of directly reading the interrupt status register,
  874. * infer the cause of the interrupt by checking our in-core
  875. * completion queues. This avoids a costly PCI bus read in
  876. * most cases.
  877. */
  878. if ((ahd->flags & AHD_ALL_INTERRUPTS) == 0
  879. && (ahd_check_cmdcmpltqueues(ahd) != 0))
  880. intstat = CMDCMPLT;
  881. else
  882. intstat = ahd_inb(ahd, INTSTAT);
  883. if ((intstat & INT_PEND) == 0)
  884. return (0);
  885. if (intstat & CMDCMPLT) {
  886. ahd_outb(ahd, CLRINT, CLRCMDINT);
  887. /*
  888. * Ensure that the chip sees that we've cleared
  889. * this interrupt before we walk the output fifo.
  890. * Otherwise, we may, due to posted bus writes,
  891. * clear the interrupt after we finish the scan,
  892. * and after the sequencer has added new entries
  893. * and asserted the interrupt again.
  894. */
  895. if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) {
  896. if (ahd_is_paused(ahd)) {
  897. /*
  898. * Potentially lost SEQINT.
  899. * If SEQINTCODE is non-zero,
  900. * simulate the SEQINT.
  901. */
  902. if (ahd_inb(ahd, SEQINTCODE) != NO_SEQINT)
  903. intstat |= SEQINT;
  904. }
  905. } else {
  906. ahd_flush_device_writes(ahd);
  907. }
  908. ahd_run_qoutfifo(ahd);
  909. ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket]++;
  910. ahd->cmdcmplt_total++;
  911. #ifdef AHD_TARGET_MODE
  912. if ((ahd->flags & AHD_TARGETROLE) != 0)
  913. ahd_run_tqinfifo(ahd, /*paused*/FALSE);
  914. #endif
  915. }
  916. /*
  917. * Handle statuses that may invalidate our cached
  918. * copy of INTSTAT separately.
  919. */
  920. if (intstat == 0xFF && (ahd->features & AHD_REMOVABLE) != 0) {
  921. /* Hot eject. Do nothing */
  922. } else if (intstat & HWERRINT) {
  923. ahd_handle_hwerrint(ahd);
  924. } else if ((intstat & (PCIINT|SPLTINT)) != 0) {
  925. ahd->bus_intr(ahd);
  926. } else {
  927. if ((intstat & SEQINT) != 0)
  928. ahd_handle_seqint(ahd, intstat);
  929. if ((intstat & SCSIINT) != 0)
  930. ahd_handle_scsiint(ahd, intstat);
  931. }
  932. return (1);
  933. }
  934. /******************************** Private Inlines *****************************/
  935. static inline void
  936. ahd_assert_atn(struct ahd_softc *ahd)
  937. {
  938. ahd_outb(ahd, SCSISIGO, ATNO);
  939. }
  940. /*
  941. * Determine if the current connection has a packetized
  942. * agreement. This does not necessarily mean that we
  943. * are currently in a packetized transfer. We could
  944. * just as easily be sending or receiving a message.
  945. */
  946. static int
  947. ahd_currently_packetized(struct ahd_softc *ahd)
  948. {
  949. ahd_mode_state saved_modes;
  950. int packetized;
  951. saved_modes = ahd_save_modes(ahd);
  952. if ((ahd->bugs & AHD_PKTIZED_STATUS_BUG) != 0) {
  953. /*
  954. * The packetized bit refers to the last
  955. * connection, not the current one. Check
  956. * for non-zero LQISTATE instead.
  957. */
  958. ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
  959. packetized = ahd_inb(ahd, LQISTATE) != 0;
  960. } else {
  961. ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
  962. packetized = ahd_inb(ahd, LQISTAT2) & PACKETIZED;
  963. }
  964. ahd_restore_modes(ahd, saved_modes);
  965. return (packetized);
  966. }
  967. static inline int
  968. ahd_set_active_fifo(struct ahd_softc *ahd)
  969. {
  970. u_int active_fifo;
  971. AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
  972. active_fifo = ahd_inb(ahd, DFFSTAT) & CURRFIFO;
  973. switch (active_fifo) {
  974. case 0:
  975. case 1:
  976. ahd_set_modes(ahd, active_fifo, active_fifo);
  977. return (1);
  978. default:
  979. return (0);
  980. }
  981. }
  982. static inline void
  983. ahd_unbusy_tcl(struct ahd_softc *ahd, u_int tcl)
  984. {
  985. ahd_busy_tcl(ahd, tcl, SCB_LIST_NULL);
  986. }
  987. /*
  988. * Determine whether the sequencer reported a residual
  989. * for this SCB/transaction.
  990. */
  991. static inline void
  992. ahd_update_residual(struct ahd_softc *ahd, struct scb *scb)
  993. {
  994. uint32_t sgptr;
  995. sgptr = ahd_le32toh(scb->hscb->sgptr);
  996. if ((sgptr & SG_STATUS_VALID) != 0)
  997. ahd_calc_residual(ahd, scb);
  998. }
  999. static inline void
  1000. ahd_complete_scb(struct ahd_softc *ahd, struct scb *scb)
  1001. {
  1002. uint32_t sgptr;
  1003. sgptr = ahd_le32toh(scb->hscb->sgptr);
  1004. if ((sgptr & SG_STATUS_VALID) != 0)
  1005. ahd_handle_scb_status(ahd, scb);
  1006. else
  1007. ahd_done(ahd, scb);
  1008. }
  1009. /************************* Sequencer Execution Control ************************/
  1010. /*
  1011. * Restart the sequencer program from address zero
  1012. */
  1013. static void
  1014. ahd_restart(struct ahd_softc *ahd)
  1015. {
  1016. ahd_pause(ahd);
  1017. ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
  1018. /* No more pending messages */
  1019. ahd_clear_msg_state(ahd);
  1020. ahd_outb(ahd, SCSISIGO, 0); /* De-assert BSY */
  1021. ahd_outb(ahd, MSG_OUT, MSG_NOOP); /* No message to send */
  1022. ahd_outb(ahd, SXFRCTL1, ahd_inb(ahd, SXFRCTL1) & ~BITBUCKET);
  1023. ahd_outb(ahd, SEQINTCTL, 0);
  1024. ahd_outb(ahd, LASTPHASE, P_BUSFREE);
  1025. ahd_outb(ahd, SEQ_FLAGS, 0);
  1026. ahd_outb(ahd, SAVED_SCSIID, 0xFF);
  1027. ahd_outb(ahd, SAVED_LUN, 0xFF);
  1028. /*
  1029. * Ensure that the sequencer's idea of TQINPOS
  1030. * matches our own. The sequencer increments TQINPOS
  1031. * only after it sees a DMA complete and a reset could
  1032. * occur before the increment leaving the kernel to believe
  1033. * the command arrived but the sequencer to not.
  1034. */
  1035. ahd_outb(ahd, TQINPOS, ahd->tqinfifonext);
  1036. /* Always allow reselection */
  1037. ahd_outb(ahd, SCSISEQ1,
  1038. ahd_inb(ahd, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP));
  1039. ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
  1040. /*
  1041. * Clear any pending sequencer interrupt. It is no
  1042. * longer relevant since we're resetting the Program
  1043. * Counter.
  1044. */
  1045. ahd_outb(ahd, CLRINT, CLRSEQINT);
  1046. ahd_outb(ahd, SEQCTL0, FASTMODE|SEQRESET);
  1047. ahd_unpause(ahd);
  1048. }
  1049. static void
  1050. ahd_clear_fifo(struct ahd_softc *ahd, u_int fifo)
  1051. {
  1052. ahd_mode_state saved_modes;
  1053. #ifdef AHD_DEBUG
  1054. if ((ahd_debug & AHD_SHOW_FIFOS) != 0)
  1055. printk("%s: Clearing FIFO %d\n", ahd_name(ahd), fifo);
  1056. #endif
  1057. saved_modes = ahd_save_modes(ahd);
  1058. ahd_set_modes(ahd, fifo, fifo);
  1059. ahd_outb(ahd, DFFSXFRCTL, RSTCHN|CLRSHCNT);
  1060. if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0)
  1061. ahd_outb(ahd, CCSGCTL, CCSGRESET);
  1062. ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR);
  1063. ahd_outb(ahd, SG_STATE, 0);
  1064. ahd_restore_modes(ahd, saved_modes);
  1065. }
  1066. /************************* Input/Output Queues ********************************/
  1067. /*
  1068. * Flush and completed commands that are sitting in the command
  1069. * complete queues down on the chip but have yet to be dma'ed back up.
  1070. */
  1071. static void
  1072. ahd_flush_qoutfifo(struct ahd_softc *ahd)
  1073. {
  1074. struct scb *scb;
  1075. ahd_mode_state saved_modes;
  1076. u_int saved_scbptr;
  1077. u_int ccscbctl;
  1078. u_int scbid;
  1079. u_int next_scbid;
  1080. saved_modes = ahd_save_modes(ahd);
  1081. /*
  1082. * Flush the good status FIFO for completed packetized commands.
  1083. */
  1084. ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
  1085. saved_scbptr = ahd_get_scbptr(ahd);
  1086. while ((ahd_inb(ahd, LQISTAT2) & LQIGSAVAIL) != 0) {
  1087. u_int fifo_mode;
  1088. u_int i;
  1089. scbid = ahd_inw(ahd, GSFIFO);
  1090. scb = ahd_lookup_scb(ahd, scbid);
  1091. if (scb == NULL) {
  1092. printk("%s: Warning - GSFIFO SCB %d invalid\n",
  1093. ahd_name(ahd), scbid);
  1094. continue;
  1095. }
  1096. /*
  1097. * Determine if this transaction is still active in
  1098. * any FIFO. If it is, we must flush that FIFO to
  1099. * the host before completing the command.
  1100. */
  1101. fifo_mode = 0;
  1102. rescan_fifos:
  1103. for (i = 0; i < 2; i++) {
  1104. /* Toggle to the other mode. */
  1105. fifo_mode ^= 1;
  1106. ahd_set_modes(ahd, fifo_mode, fifo_mode);
  1107. if (ahd_scb_active_in_fifo(ahd, scb) == 0)
  1108. continue;
  1109. ahd_run_data_fifo(ahd, scb);
  1110. /*
  1111. * Running this FIFO may cause a CFG4DATA for
  1112. * this same transaction to assert in the other
  1113. * FIFO or a new snapshot SAVEPTRS interrupt
  1114. * in this FIFO. Even running a FIFO may not
  1115. * clear the transaction if we are still waiting
  1116. * for data to drain to the host. We must loop
  1117. * until the transaction is not active in either
  1118. * FIFO just to be sure. Reset our loop counter
  1119. * so we will visit both FIFOs again before
  1120. * declaring this transaction finished. We
  1121. * also delay a bit so that status has a chance
  1122. * to change before we look at this FIFO again.
  1123. */
  1124. ahd_delay(200);
  1125. goto rescan_fifos;
  1126. }
  1127. ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
  1128. ahd_set_scbptr(ahd, scbid);
  1129. if ((ahd_inb_scbram(ahd, SCB_SGPTR) & SG_LIST_NULL) == 0
  1130. && ((ahd_inb_scbram(ahd, SCB_SGPTR) & SG_FULL_RESID) != 0
  1131. || (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR)
  1132. & SG_LIST_NULL) != 0)) {
  1133. u_int comp_head;
  1134. /*
  1135. * The transfer completed with a residual.
  1136. * Place this SCB on the complete DMA list
  1137. * so that we update our in-core copy of the
  1138. * SCB before completing the command.
  1139. */
  1140. ahd_outb(ahd, SCB_SCSI_STATUS, 0);
  1141. ahd_outb(ahd, SCB_SGPTR,
  1142. ahd_inb_scbram(ahd, SCB_SGPTR)
  1143. | SG_STATUS_VALID);
  1144. ahd_outw(ahd, SCB_TAG, scbid);
  1145. ahd_outw(ahd, SCB_NEXT_COMPLETE, SCB_LIST_NULL);
  1146. comp_head = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD);
  1147. if (SCBID_IS_NULL(comp_head)) {
  1148. ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, scbid);
  1149. ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, scbid);
  1150. } else {
  1151. u_int tail;
  1152. tail = ahd_inw(ahd, COMPLETE_DMA_SCB_TAIL);
  1153. ahd_set_scbptr(ahd, tail);
  1154. ahd_outw(ahd, SCB_NEXT_COMPLETE, scbid);
  1155. ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, scbid);
  1156. ahd_set_scbptr(ahd, scbid);
  1157. }
  1158. } else
  1159. ahd_complete_scb(ahd, scb);
  1160. }
  1161. ahd_set_scbptr(ahd, saved_scbptr);
  1162. /*
  1163. * Setup for command channel portion of flush.
  1164. */
  1165. ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
  1166. /*
  1167. * Wait for any inprogress DMA to complete and clear DMA state
  1168. * if this is for an SCB in the qinfifo.
  1169. */
  1170. while (((ccscbctl = ahd_inb(ahd, CCSCBCTL)) & (CCARREN|CCSCBEN)) != 0) {
  1171. if ((ccscbctl & (CCSCBDIR|CCARREN)) == (CCSCBDIR|CCARREN)) {
  1172. if ((ccscbctl & ARRDONE) != 0)
  1173. break;
  1174. } else if ((ccscbctl & CCSCBDONE) != 0)
  1175. break;
  1176. ahd_delay(200);
  1177. }
  1178. /*
  1179. * We leave the sequencer to cleanup in the case of DMA's to
  1180. * update the qoutfifo. In all other cases (DMA's to the
  1181. * chip or a push of an SCB from the COMPLETE_DMA_SCB list),
  1182. * we disable the DMA engine so that the sequencer will not
  1183. * attempt to handle the DMA completion.
  1184. */
  1185. if ((ccscbctl & CCSCBDIR) != 0 || (ccscbctl & ARRDONE) != 0)
  1186. ahd_outb(ahd, CCSCBCTL, ccscbctl & ~(CCARREN|CCSCBEN));
  1187. /*
  1188. * Complete any SCBs that just finished
  1189. * being DMA'ed into the qoutfifo.
  1190. */
  1191. ahd_run_qoutfifo(ahd);
  1192. saved_scbptr = ahd_get_scbptr(ahd);
  1193. /*
  1194. * Manually update/complete any completed SCBs that are waiting to be
  1195. * DMA'ed back up to the host.
  1196. */
  1197. scbid = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD);
  1198. while (!SCBID_IS_NULL(scbid)) {
  1199. uint8_t *hscb_ptr;
  1200. u_int i;
  1201. ahd_set_scbptr(ahd, scbid);
  1202. next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
  1203. scb = ahd_lookup_scb(ahd, scbid);
  1204. if (scb == NULL) {
  1205. printk("%s: Warning - DMA-up and complete "
  1206. "SCB %d invalid\n", ahd_name(ahd), scbid);
  1207. continue;
  1208. }
  1209. hscb_ptr = (uint8_t *)scb->hscb;
  1210. for (i = 0; i < sizeof(struct hardware_scb); i++)
  1211. *hscb_ptr++ = ahd_inb_scbram(ahd, SCB_BASE + i);
  1212. ahd_complete_scb(ahd, scb);
  1213. scbid = next_scbid;
  1214. }
  1215. ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, SCB_LIST_NULL);
  1216. ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, SCB_LIST_NULL);
  1217. scbid = ahd_inw(ahd, COMPLETE_ON_QFREEZE_HEAD);
  1218. while (!SCBID_IS_NULL(scbid)) {
  1219. ahd_set_scbptr(ahd, scbid);
  1220. next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
  1221. scb = ahd_lookup_scb(ahd, scbid);
  1222. if (scb == NULL) {
  1223. printk("%s: Warning - Complete Qfrz SCB %d invalid\n",
  1224. ahd_name(ahd), scbid);
  1225. continue;
  1226. }
  1227. ahd_complete_scb(ahd, scb);
  1228. scbid = next_scbid;
  1229. }
  1230. ahd_outw(ahd, COMPLETE_ON_QFREEZE_HEAD, SCB_LIST_NULL);
  1231. scbid = ahd_inw(ahd, COMPLETE_SCB_HEAD);
  1232. while (!SCBID_IS_NULL(scbid)) {
  1233. ahd_set_scbptr(ahd, scbid);
  1234. next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
  1235. scb = ahd_lookup_scb(ahd, scbid);
  1236. if (scb == NULL) {
  1237. printk("%s: Warning - Complete SCB %d invalid\n",
  1238. ahd_name(ahd), scbid);
  1239. continue;
  1240. }
  1241. ahd_complete_scb(ahd, scb);
  1242. scbid = next_scbid;
  1243. }
  1244. ahd_outw(ahd, COMPLETE_SCB_HEAD, SCB_LIST_NULL);
  1245. /*
  1246. * Restore state.
  1247. */
  1248. ahd_set_scbptr(ahd, saved_scbptr);
  1249. ahd_restore_modes(ahd, saved_modes);
  1250. ahd->flags |= AHD_UPDATE_PEND_CMDS;
  1251. }
  1252. /*
  1253. * Determine if an SCB for a packetized transaction
  1254. * is active in a FIFO.
  1255. */
  1256. static int
  1257. ahd_scb_active_in_fifo(struct ahd_softc *ahd, struct scb *scb)
  1258. {
  1259. /*
  1260. * The FIFO is only active for our transaction if
  1261. * the SCBPTR matches the SCB's ID and the firmware
  1262. * has installed a handler for the FIFO or we have
  1263. * a pending SAVEPTRS or CFG4DATA interrupt.
  1264. */
  1265. if (ahd_get_scbptr(ahd) != SCB_GET_TAG(scb)
  1266. || ((ahd_inb(ahd, LONGJMP_ADDR+1) & INVALID_ADDR) != 0
  1267. && (ahd_inb(ahd, SEQINTSRC) & (CFG4DATA|SAVEPTRS)) == 0))
  1268. return (0);
  1269. return (1);
  1270. }
  1271. /*
  1272. * Run a data fifo to completion for a transaction we know
  1273. * has completed across the SCSI bus (good status has been
  1274. * received). We are already set to the correct FIFO mode
  1275. * on entry to this routine.
  1276. *
  1277. * This function attempts to operate exactly as the firmware
  1278. * would when running this FIFO. Care must be taken to update
  1279. * this routine any time the firmware's FIFO algorithm is
  1280. * changed.
  1281. */
  1282. static void
  1283. ahd_run_data_fifo(struct ahd_softc *ahd, struct scb *scb)
  1284. {
  1285. u_int seqintsrc;
  1286. seqintsrc = ahd_inb(ahd, SEQINTSRC);
  1287. if ((seqintsrc & CFG4DATA) != 0) {
  1288. uint32_t datacnt;
  1289. uint32_t sgptr;
  1290. /*
  1291. * Clear full residual flag.
  1292. */
  1293. sgptr = ahd_inl_scbram(ahd, SCB_SGPTR) & ~SG_FULL_RESID;
  1294. ahd_outb(ahd, SCB_SGPTR, sgptr);
  1295. /*
  1296. * Load datacnt and address.
  1297. */
  1298. datacnt = ahd_inl_scbram(ahd, SCB_DATACNT);
  1299. if ((datacnt & AHD_DMA_LAST_SEG) != 0) {
  1300. sgptr |= LAST_SEG;
  1301. ahd_outb(ahd, SG_STATE, 0);
  1302. } else
  1303. ahd_outb(ahd, SG_STATE, LOADING_NEEDED);
  1304. ahd_outq(ahd, HADDR, ahd_inq_scbram(ahd, SCB_DATAPTR));
  1305. ahd_outl(ahd, HCNT, datacnt & AHD_SG_LEN_MASK);
  1306. ahd_outb(ahd, SG_CACHE_PRE, sgptr);
  1307. ahd_outb(ahd, DFCNTRL, PRELOADEN|SCSIEN|HDMAEN);
  1308. /*
  1309. * Initialize Residual Fields.
  1310. */
  1311. ahd_outb(ahd, SCB_RESIDUAL_DATACNT+3, datacnt >> 24);
  1312. ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr & SG_PTR_MASK);
  1313. /*
  1314. * Mark the SCB as having a FIFO in use.
  1315. */
  1316. ahd_outb(ahd, SCB_FIFO_USE_COUNT,
  1317. ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT) + 1);
  1318. /*
  1319. * Install a "fake" handler for this FIFO.
  1320. */
  1321. ahd_outw(ahd, LONGJMP_ADDR, 0);
  1322. /*
  1323. * Notify the hardware that we have satisfied
  1324. * this sequencer interrupt.
  1325. */
  1326. ahd_outb(ahd, CLRSEQINTSRC, CLRCFG4DATA);
  1327. } else if ((seqintsrc & SAVEPTRS) != 0) {
  1328. uint32_t sgptr;
  1329. uint32_t resid;
  1330. if ((ahd_inb(ahd, LONGJMP_ADDR+1)&INVALID_ADDR) != 0) {
  1331. /*
  1332. * Snapshot Save Pointers. All that
  1333. * is necessary to clear the snapshot
  1334. * is a CLRCHN.
  1335. */
  1336. goto clrchn;
  1337. }
  1338. /*
  1339. * Disable S/G fetch so the DMA engine
  1340. * is available to future users.
  1341. */
  1342. if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0)
  1343. ahd_outb(ahd, CCSGCTL, 0);
  1344. ahd_outb(ahd, SG_STATE, 0);
  1345. /*
  1346. * Flush the data FIFO. Strickly only
  1347. * necessary for Rev A parts.
  1348. */
  1349. ahd_outb(ahd, DFCNTRL, ahd_inb(ahd, DFCNTRL) | FIFOFLUSH);
  1350. /*
  1351. * Calculate residual.
  1352. */
  1353. sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR);
  1354. resid = ahd_inl(ahd, SHCNT);
  1355. resid |= ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT+3) << 24;
  1356. ahd_outl(ahd, SCB_RESIDUAL_DATACNT, resid);
  1357. if ((ahd_inb(ahd, SG_CACHE_SHADOW) & LAST_SEG) == 0) {
  1358. /*
  1359. * Must back up to the correct S/G element.
  1360. * Typically this just means resetting our
  1361. * low byte to the offset in the SG_CACHE,
  1362. * but if we wrapped, we have to correct
  1363. * the other bytes of the sgptr too.
  1364. */
  1365. if ((ahd_inb(ahd, SG_CACHE_SHADOW) & 0x80) != 0
  1366. && (sgptr & 0x80) == 0)
  1367. sgptr -= 0x100;
  1368. sgptr &= ~0xFF;
  1369. sgptr |= ahd_inb(ahd, SG_CACHE_SHADOW)
  1370. & SG_ADDR_MASK;
  1371. ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr);
  1372. ahd_outb(ahd, SCB_RESIDUAL_DATACNT + 3, 0);
  1373. } else if ((resid & AHD_SG_LEN_MASK) == 0) {
  1374. ahd_outb(ahd, SCB_RESIDUAL_SGPTR,
  1375. sgptr | SG_LIST_NULL);
  1376. }
  1377. /*
  1378. * Save Pointers.
  1379. */
  1380. ahd_outq(ahd, SCB_DATAPTR, ahd_inq(ahd, SHADDR));
  1381. ahd_outl(ahd, SCB_DATACNT, resid);
  1382. ahd_outl(ahd, SCB_SGPTR, sgptr);
  1383. ahd_outb(ahd, CLRSEQINTSRC, CLRSAVEPTRS);
  1384. ahd_outb(ahd, SEQIMODE,
  1385. ahd_inb(ahd, SEQIMODE) | ENSAVEPTRS);
  1386. /*
  1387. * If the data is to the SCSI bus, we are
  1388. * done, otherwise wait for FIFOEMP.
  1389. */
  1390. if ((ahd_inb(ahd, DFCNTRL) & DIRECTION) != 0)
  1391. goto clrchn;
  1392. } else if ((ahd_inb(ahd, SG_STATE) & LOADING_NEEDED) != 0) {
  1393. uint32_t sgptr;
  1394. uint64_t data_addr;
  1395. uint32_t data_len;
  1396. u_int dfcntrl;
  1397. /*
  1398. * Disable S/G fetch so the DMA engine
  1399. * is available to future users. We won't
  1400. * be using the DMA engine to load segments.
  1401. */
  1402. if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0) {
  1403. ahd_outb(ahd, CCSGCTL, 0);
  1404. ahd_outb(ahd, SG_STATE, LOADING_NEEDED);
  1405. }
  1406. /*
  1407. * Wait for the DMA engine to notice that the
  1408. * host transfer is enabled and that there is
  1409. * space in the S/G FIFO for new segments before
  1410. * loading more segments.
  1411. */
  1412. if ((ahd_inb(ahd, DFSTATUS) & PRELOAD_AVAIL) != 0
  1413. && (ahd_inb(ahd, DFCNTRL) & HDMAENACK) != 0) {
  1414. /*
  1415. * Determine the offset of the next S/G
  1416. * element to load.
  1417. */
  1418. sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR);
  1419. sgptr &= SG_PTR_MASK;
  1420. if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
  1421. struct ahd_dma64_seg *sg;
  1422. sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
  1423. data_addr = sg->addr;
  1424. data_len = sg->len;
  1425. sgptr += sizeof(*sg);
  1426. } else {
  1427. struct ahd_dma_seg *sg;
  1428. sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
  1429. data_addr = sg->len & AHD_SG_HIGH_ADDR_MASK;
  1430. data_addr <<= 8;
  1431. data_addr |= sg->addr;
  1432. data_len = sg->len;
  1433. sgptr += sizeof(*sg);
  1434. }
  1435. /*
  1436. * Update residual information.
  1437. */
  1438. ahd_outb(ahd, SCB_RESIDUAL_DATACNT+3, data_len >> 24);
  1439. ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr);
  1440. /*
  1441. * Load the S/G.
  1442. */
  1443. if (data_len & AHD_DMA_LAST_SEG) {
  1444. sgptr |= LAST_SEG;
  1445. ahd_outb(ahd, SG_STATE, 0);
  1446. }
  1447. ahd_outq(ahd, HADDR, data_addr);
  1448. ahd_outl(ahd, HCNT, data_len & AHD_SG_LEN_MASK);
  1449. ahd_outb(ahd, SG_CACHE_PRE, sgptr & 0xFF);
  1450. /*
  1451. * Advertise the segment to the hardware.
  1452. */
  1453. dfcntrl = ahd_inb(ahd, DFCNTRL)|PRELOADEN|HDMAEN;
  1454. if ((ahd->features & AHD_NEW_DFCNTRL_OPTS) != 0) {
  1455. /*
  1456. * Use SCSIENWRDIS so that SCSIEN
  1457. * is never modified by this
  1458. * operation.
  1459. */
  1460. dfcntrl |= SCSIENWRDIS;
  1461. }
  1462. ahd_outb(ahd, DFCNTRL, dfcntrl);
  1463. }
  1464. } else if ((ahd_inb(ahd, SG_CACHE_SHADOW) & LAST_SEG_DONE) != 0) {
  1465. /*
  1466. * Transfer completed to the end of SG list
  1467. * and has flushed to the host.
  1468. */
  1469. ahd_outb(ahd, SCB_SGPTR,
  1470. ahd_inb_scbram(ahd, SCB_SGPTR) | SG_LIST_NULL);
  1471. goto clrchn;
  1472. } else if ((ahd_inb(ahd, DFSTATUS) & FIFOEMP) != 0) {
  1473. clrchn:
  1474. /*
  1475. * Clear any handler for this FIFO, decrement
  1476. * the FIFO use count for the SCB, and release
  1477. * the FIFO.
  1478. */
  1479. ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR);
  1480. ahd_outb(ahd, SCB_FIFO_USE_COUNT,
  1481. ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT) - 1);
  1482. ahd_outb(ahd, DFFSXFRCTL, CLRCHN);
  1483. }
  1484. }
  1485. /*
  1486. * Look for entries in the QoutFIFO that have completed.
  1487. * The valid_tag completion field indicates the validity
  1488. * of the entry - the valid value toggles each time through
  1489. * the queue. We use the sg_status field in the completion
  1490. * entry to avoid referencing the hscb if the completion
  1491. * occurred with no errors and no residual. sg_status is
  1492. * a copy of the first byte (little endian) of the sgptr
  1493. * hscb field.
  1494. */
  1495. static void
  1496. ahd_run_qoutfifo(struct ahd_softc *ahd)
  1497. {
  1498. struct ahd_completion *completion;
  1499. struct scb *scb;
  1500. u_int scb_index;
  1501. if ((ahd->flags & AHD_RUNNING_QOUTFIFO) != 0)
  1502. panic("ahd_run_qoutfifo recursion");
  1503. ahd->flags |= AHD_RUNNING_QOUTFIFO;
  1504. ahd_sync_qoutfifo(ahd, BUS_DMASYNC_POSTREAD);
  1505. for (;;) {
  1506. completion = &ahd->qoutfifo[ahd->qoutfifonext];
  1507. if (completion->valid_tag != ahd->qoutfifonext_valid_tag)
  1508. break;
  1509. scb_index = ahd_le16toh(completion->tag);
  1510. scb = ahd_lookup_scb(ahd, scb_index);
  1511. if (scb == NULL) {
  1512. printk("%s: WARNING no command for scb %d "
  1513. "(cmdcmplt)\nQOUTPOS = %d\n",
  1514. ahd_name(ahd), scb_index,
  1515. ahd->qoutfifonext);
  1516. ahd_dump_card_state(ahd);
  1517. } else if ((completion->sg_status & SG_STATUS_VALID) != 0) {
  1518. ahd_handle_scb_status(ahd, scb);
  1519. } else {
  1520. ahd_done(ahd, scb);
  1521. }
  1522. ahd->qoutfifonext = (ahd->qoutfifonext+1) & (AHD_QOUT_SIZE-1);
  1523. if (ahd->qoutfifonext == 0)
  1524. ahd->qoutfifonext_valid_tag ^= QOUTFIFO_ENTRY_VALID;
  1525. }
  1526. ahd->flags &= ~AHD_RUNNING_QOUTFIFO;
  1527. }
  1528. /************************* Interrupt Handling *********************************/
  1529. static void
  1530. ahd_handle_hwerrint(struct ahd_softc *ahd)
  1531. {
  1532. /*
  1533. * Some catastrophic hardware error has occurred.
  1534. * Print it for the user and disable the controller.
  1535. */
  1536. int i;
  1537. int error;
  1538. error = ahd_inb(ahd, ERROR);
  1539. for (i = 0; i < num_errors; i++) {
  1540. if ((error & ahd_hard_errors[i].errno) != 0)
  1541. printk("%s: hwerrint, %s\n",
  1542. ahd_name(ahd), ahd_hard_errors[i].errmesg);
  1543. }
  1544. ahd_dump_card_state(ahd);
  1545. panic("BRKADRINT");
  1546. /* Tell everyone that this HBA is no longer available */
  1547. ahd_abort_scbs(ahd, CAM_TARGET_WILDCARD, ALL_CHANNELS,
  1548. CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN,
  1549. CAM_NO_HBA);
  1550. /* Tell the system that this controller has gone away. */
  1551. ahd_free(ahd);
  1552. }
  1553. #ifdef AHD_DEBUG
  1554. static void
  1555. ahd_dump_sglist(struct scb *scb)
  1556. {
  1557. int i;
  1558. if (scb->sg_count > 0) {
  1559. if ((scb->ahd_softc->flags & AHD_64BIT_ADDRESSING) != 0) {
  1560. struct ahd_dma64_seg *sg_list;
  1561. sg_list = (struct ahd_dma64_seg*)scb->sg_list;
  1562. for (i = 0; i < scb->sg_count; i++) {
  1563. uint64_t addr;
  1564. uint32_t len;
  1565. addr = ahd_le64toh(sg_list[i].addr);
  1566. len = ahd_le32toh(sg_list[i].len);
  1567. printk("sg[%d] - Addr 0x%x%x : Length %d%s\n",
  1568. i,
  1569. (uint32_t)((addr >> 32) & 0xFFFFFFFF),
  1570. (uint32_t)(addr & 0xFFFFFFFF),
  1571. sg_list[i].len & AHD_SG_LEN_MASK,
  1572. (sg_list[i].len & AHD_DMA_LAST_SEG)
  1573. ? " Last" : "");
  1574. }
  1575. } else {
  1576. struct ahd_dma_seg *sg_list;
  1577. sg_list = (struct ahd_dma_seg*)scb->sg_list;
  1578. for (i = 0; i < scb->sg_count; i++) {
  1579. uint32_t len;
  1580. len = ahd_le32toh(sg_list[i].len);
  1581. printk("sg[%d] - Addr 0x%x%x : Length %d%s\n",
  1582. i,
  1583. (len & AHD_SG_HIGH_ADDR_MASK) >> 24,
  1584. ahd_le32toh(sg_list[i].addr),
  1585. len & AHD_SG_LEN_MASK,
  1586. len & AHD_DMA_LAST_SEG ? " Last" : "");
  1587. }
  1588. }
  1589. }
  1590. }
  1591. #endif /* AHD_DEBUG */
  1592. static void
  1593. ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat)
  1594. {
  1595. u_int seqintcode;
  1596. /*
  1597. * Save the sequencer interrupt code and clear the SEQINT
  1598. * bit. We will unpause the sequencer, if appropriate,
  1599. * after servicing the request.
  1600. */
  1601. seqintcode = ahd_inb(ahd, SEQINTCODE);
  1602. ahd_outb(ahd, CLRINT, CLRSEQINT);
  1603. if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) {
  1604. /*
  1605. * Unpause the sequencer and let it clear
  1606. * SEQINT by writing NO_SEQINT to it. This
  1607. * will cause the sequencer to be paused again,
  1608. * which is the expected state of this routine.
  1609. */
  1610. ahd_unpause(ahd);
  1611. while (!ahd_is_paused(ahd))
  1612. ;
  1613. ahd_outb(ahd, CLRINT, CLRSEQINT);
  1614. }
  1615. ahd_update_modes(ahd);
  1616. #ifdef AHD_DEBUG
  1617. if ((ahd_debug & AHD_SHOW_MISC) != 0)
  1618. printk("%s: Handle Seqint Called for code %d\n",
  1619. ahd_name(ahd), seqintcode);
  1620. #endif
  1621. switch (seqintcode) {
  1622. case ENTERING_NONPACK:
  1623. {
  1624. struct scb *scb;
  1625. u_int scbid;
  1626. AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
  1627. ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
  1628. scbid = ahd_get_scbptr(ahd);
  1629. scb = ahd_lookup_scb(ahd, scbid);
  1630. if (scb == NULL) {
  1631. /*
  1632. * Somehow need to know if this
  1633. * is from a selection or reselection.
  1634. * From that, we can determine target
  1635. * ID so we at least have an I_T nexus.
  1636. */
  1637. } else {
  1638. ahd_outb(ahd, SAVED_SCSIID, scb->hscb->scsiid);
  1639. ahd_outb(ahd, SAVED_LUN, scb->hscb->lun);
  1640. ahd_outb(ahd, SEQ_FLAGS, 0x0);
  1641. }
  1642. if ((ahd_inb(ahd, LQISTAT2) & LQIPHASE_OUTPKT) != 0
  1643. && (ahd_inb(ahd, SCSISIGO) & ATNO) != 0) {
  1644. /*
  1645. * Phase change after read stream with
  1646. * CRC error with P0 asserted on last
  1647. * packet.
  1648. */
  1649. #ifdef AHD_DEBUG
  1650. if ((ahd_debug & AHD_SHOW_RECOVERY) != 0)
  1651. printk("%s: Assuming LQIPHASE_NLQ with "
  1652. "P0 assertion\n", ahd_name(ahd));
  1653. #endif
  1654. }
  1655. #ifdef AHD_DEBUG
  1656. if ((ahd_debug & AHD_SHOW_RECOVERY) != 0)
  1657. printk("%s: Entering NONPACK\n", ahd_name(ahd));
  1658. #endif
  1659. break;
  1660. }
  1661. case INVALID_SEQINT:
  1662. printk("%s: Invalid Sequencer interrupt occurred, "
  1663. "resetting channel.\n",
  1664. ahd_name(ahd));
  1665. #ifdef AHD_DEBUG
  1666. if ((ahd_debug & AHD_SHOW_RECOVERY) != 0)
  1667. ahd_dump_card_state(ahd);
  1668. #endif
  1669. ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
  1670. break;
  1671. case STATUS_OVERRUN:
  1672. {
  1673. struct scb *scb;
  1674. u_int scbid;
  1675. scbid = ahd_get_scbptr(ahd);
  1676. scb = ahd_lookup_scb(ahd, scbid);
  1677. if (scb != NULL)
  1678. ahd_print_path(ahd, scb);
  1679. else
  1680. printk("%s: ", ahd_name(ahd));
  1681. printk("SCB %d Packetized Status Overrun", scbid);
  1682. ahd_dump_card_state(ahd);
  1683. ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
  1684. break;
  1685. }
  1686. case CFG4ISTAT_INTR:
  1687. {
  1688. struct scb *scb;
  1689. u_int scbid;
  1690. scbid = ahd_get_scbptr(ahd);
  1691. scb = ahd_lookup_scb(ahd, scbid);
  1692. if (scb == NULL) {
  1693. ahd_dump_card_state(ahd);
  1694. printk("CFG4ISTAT: Free SCB %d referenced", scbid);
  1695. panic("For safety");
  1696. }
  1697. ahd_outq(ahd, HADDR, scb->sense_busaddr);
  1698. ahd_outw(ahd, HCNT, AHD_SENSE_BUFSIZE);
  1699. ahd_outb(ahd, HCNT + 2, 0);
  1700. ahd_outb(ahd, SG_CACHE_PRE, SG_LAST_SEG);
  1701. ahd_outb(ahd, DFCNTRL, PRELOADEN|SCSIEN|HDMAEN);
  1702. break;
  1703. }
  1704. case ILLEGAL_PHASE:
  1705. {
  1706. u_int bus_phase;
  1707. bus_phase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK;
  1708. printk("%s: ILLEGAL_PHASE 0x%x\n",
  1709. ahd_name(ahd), bus_phase);
  1710. switch (bus_phase) {
  1711. case P_DATAOUT:
  1712. case P_DATAIN:
  1713. case P_DATAOUT_DT:
  1714. case P_DATAIN_DT:
  1715. case P_MESGOUT:
  1716. case P_STATUS:
  1717. case P_MESGIN:
  1718. ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
  1719. printk("%s: Issued Bus Reset.\n", ahd_name(ahd));
  1720. break;
  1721. case P_COMMAND:
  1722. {
  1723. struct ahd_devinfo devinfo;
  1724. struct scb *scb;
  1725. struct ahd_initiator_tinfo *targ_info;
  1726. struct ahd_tmode_tstate *tstate;
  1727. struct ahd_transinfo *tinfo;
  1728. u_int scbid;
  1729. /*
  1730. * If a target takes us into the command phase
  1731. * assume that it has been externally reset and
  1732. * has thus lost our previous packetized negotiation
  1733. * agreement. Since we have not sent an identify
  1734. * message and may not have fully qualified the
  1735. * connection, we change our command to TUR, assert
  1736. * ATN and ABORT the task when we go to message in
  1737. * phase. The OSM will see the REQUEUE_REQUEST
  1738. * status and retry the command.
  1739. */
  1740. scbid = ahd_get_scbptr(ahd);
  1741. scb = ahd_lookup_scb(ahd, scbid);
  1742. if (scb == NULL) {
  1743. printk("Invalid phase with no valid SCB. "
  1744. "Resetting bus.\n");
  1745. ahd_reset_channel(ahd, 'A',
  1746. /*Initiate Reset*/TRUE);
  1747. break;
  1748. }
  1749. ahd_compile_devinfo(&devinfo, SCB_GET_OUR_ID(scb),
  1750. SCB_GET_TARGET(ahd, scb),
  1751. SCB_GET_LUN(scb),
  1752. SCB_GET_CHANNEL(ahd, scb),
  1753. ROLE_INITIATOR);
  1754. targ_info = ahd_fetch_transinfo(ahd,
  1755. devinfo.channel,
  1756. devinfo.our_scsiid,
  1757. devinfo.target,
  1758. &tstate);
  1759. tinfo = &targ_info->curr;
  1760. ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
  1761. AHD_TRANS_ACTIVE, /*paused*/TRUE);
  1762. ahd_set_syncrate(ahd, &devinfo, /*period*/0,
  1763. /*offset*/0, /*ppr_options*/0,
  1764. AHD_TRANS_ACTIVE, /*paused*/TRUE);
  1765. /* Hand-craft TUR command */
  1766. ahd_outb(ahd, SCB_CDB_STORE, 0);
  1767. ahd_outb(ahd, SCB_CDB_STORE+1, 0);
  1768. ahd_outb(ahd, SCB_CDB_STORE+2, 0);
  1769. ahd_outb(ahd, SCB_CDB_STORE+3, 0);
  1770. ahd_outb(ahd, SCB_CDB_STORE+4, 0);
  1771. ahd_outb(ahd, SCB_CDB_STORE+5, 0);
  1772. ahd_outb(ahd, SCB_CDB_LEN, 6);
  1773. scb->hscb->control &= ~(TAG_ENB|SCB_TAG_TYPE);
  1774. scb->hscb->control |= MK_MESSAGE;
  1775. ahd_outb(ahd, SCB_CONTROL, scb->hscb->control);
  1776. ahd_outb(ahd, MSG_OUT, HOST_MSG);
  1777. ahd_outb(ahd, SAVED_SCSIID, scb->hscb->scsiid);
  1778. /*
  1779. * The lun is 0, regardless of the SCB's lun
  1780. * as we have not sent an identify message.
  1781. */
  1782. ahd_outb(ahd, SAVED_LUN, 0);
  1783. ahd_outb(ahd, SEQ_FLAGS, 0);
  1784. ahd_assert_atn(ahd);
  1785. scb->flags &= ~SCB_PACKETIZED;
  1786. scb->flags |= SCB_ABORT|SCB_EXTERNAL_RESET;
  1787. ahd_freeze_devq(ahd, scb);
  1788. ahd_set_transaction_status(scb, CAM_REQUEUE_REQ);
  1789. ahd_freeze_scb(scb);
  1790. /* Notify XPT */
  1791. ahd_send_async(ahd, devinfo.channel, devinfo.target,
  1792. CAM_LUN_WILDCARD, AC_SENT_BDR);
  1793. /*
  1794. * Allow the sequencer to continue with
  1795. * non-pack processing.
  1796. */
  1797. ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
  1798. ahd_outb(ahd, CLRLQOINT1, CLRLQOPHACHGINPKT);
  1799. if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) {
  1800. ahd_outb(ahd, CLRLQOINT1, 0);
  1801. }
  1802. #ifdef AHD_DEBUG
  1803. if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) {
  1804. ahd_print_path(ahd, scb);
  1805. printk("Unexpected command phase from "
  1806. "packetized target\n");
  1807. }
  1808. #endif
  1809. break;
  1810. }
  1811. }
  1812. break;
  1813. }
  1814. case CFG4OVERRUN:
  1815. {
  1816. struct scb *scb;
  1817. u_int scb_index;
  1818. #ifdef AHD_DEBUG
  1819. if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) {
  1820. printk("%s: CFG4OVERRUN mode = %x\n", ahd_name(ahd),
  1821. ahd_inb(ahd, MODE_PTR));
  1822. }
  1823. #endif
  1824. scb_index = ahd_get_scbptr(ahd);
  1825. scb = ahd_lookup_scb(ahd, scb_index);
  1826. if (scb == NULL) {
  1827. /*
  1828. * Attempt to transfer to an SCB that is
  1829. * not outstanding.
  1830. */
  1831. ahd_assert_atn(ahd);
  1832. ahd_outb(ahd, MSG_OUT, HOST_MSG);
  1833. ahd->msgout_buf[0] = MSG_ABORT_TASK;
  1834. ahd->msgout_len = 1;
  1835. ahd->msgout_index = 0;
  1836. ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
  1837. /*
  1838. * Clear status received flag to prevent any
  1839. * attempt to complete this bogus SCB.
  1840. */
  1841. ahd_outb(ahd, SCB_CONTROL,
  1842. ahd_inb_scbram(ahd, SCB_CONTROL)
  1843. & ~STATUS_RCVD);
  1844. }
  1845. break;
  1846. }
  1847. case DUMP_CARD_STATE:
  1848. {
  1849. ahd_dump_card_state(ahd);
  1850. break;
  1851. }
  1852. case PDATA_REINIT:
  1853. {
  1854. #ifdef AHD_DEBUG
  1855. if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) {
  1856. printk("%s: PDATA_REINIT - DFCNTRL = 0x%x "
  1857. "SG_CACHE_SHADOW = 0x%x\n",
  1858. ahd_name(ahd), ahd_inb(ahd, DFCNTRL),
  1859. ahd_inb(ahd, SG_CACHE_SHADOW));
  1860. }
  1861. #endif
  1862. ahd_reinitialize_dataptrs(ahd);
  1863. break;
  1864. }
  1865. case HOST_MSG_LOOP:
  1866. {
  1867. struct ahd_devinfo devinfo;
  1868. /*
  1869. * The sequencer has encountered a message phase
  1870. * that requires host assistance for completion.
  1871. * While handling the message phase(s), we will be
  1872. * notified by the sequencer after each byte is
  1873. * transferred so we can track bus phase changes.
  1874. *
  1875. * If this is the first time we've seen a HOST_MSG_LOOP
  1876. * interrupt, initialize the state of the host message
  1877. * loop.
  1878. */
  1879. ahd_fetch_devinfo(ahd, &devinfo);
  1880. if (ahd->msg_type == MSG_TYPE_NONE) {
  1881. struct scb *scb;
  1882. u_int scb_index;
  1883. u_int bus_phase;
  1884. bus_phase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK;
  1885. if (bus_phase != P_MESGIN
  1886. && bus_phase != P_MESGOUT) {
  1887. printk("ahd_intr: HOST_MSG_LOOP bad "
  1888. "phase 0x%x\n", bus_phase);
  1889. /*
  1890. * Probably transitioned to bus free before
  1891. * we got here. Just punt the message.
  1892. */
  1893. ahd_dump_card_state(ahd);
  1894. ahd_clear_intstat(ahd);
  1895. ahd_restart(ahd);
  1896. return;
  1897. }
  1898. scb_index = ahd_get_scbptr(ahd);
  1899. scb = ahd_lookup_scb(ahd, scb_index);
  1900. if (devinfo.role == ROLE_INITIATOR) {
  1901. if (bus_phase == P_MESGOUT)
  1902. ahd_setup_initiator_msgout(ahd,
  1903. &devinfo,
  1904. scb);
  1905. else {
  1906. ahd->msg_type =
  1907. MSG_TYPE_INITIATOR_MSGIN;
  1908. ahd->msgin_index = 0;
  1909. }
  1910. }
  1911. #ifdef AHD_TARGET_MODE
  1912. else {
  1913. if (bus_phase == P_MESGOUT) {
  1914. ahd->msg_type =
  1915. MSG_TYPE_TARGET_MSGOUT;
  1916. ahd->msgin_index = 0;
  1917. }
  1918. else
  1919. ahd_setup_target_msgin(ahd,
  1920. &devinfo,
  1921. scb);
  1922. }
  1923. #endif
  1924. }
  1925. ahd_handle_message_phase(ahd);
  1926. break;
  1927. }
  1928. case NO_MATCH:
  1929. {
  1930. /* Ensure we don't leave the selection hardware on */
  1931. AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
  1932. ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO);
  1933. printk("%s:%c:%d: no active SCB for reconnecting "
  1934. "target - issuing BUS DEVICE RESET\n",
  1935. ahd_name(ahd), 'A', ahd_inb(ahd, SELID) >> 4);
  1936. printk("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
  1937. "REG0 == 0x%x ACCUM = 0x%x\n",
  1938. ahd_inb(ahd, SAVED_SCSIID), ahd_inb(ahd, SAVED_LUN),
  1939. ahd_inw(ahd, REG0), ahd_inb(ahd, ACCUM));
  1940. printk("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
  1941. "SINDEX == 0x%x\n",
  1942. ahd_inb(ahd, SEQ_FLAGS), ahd_get_scbptr(ahd),
  1943. ahd_find_busy_tcl(ahd,
  1944. BUILD_TCL(ahd_inb(ahd, SAVED_SCSIID),
  1945. ahd_inb(ahd, SAVED_LUN))),
  1946. ahd_inw(ahd, SINDEX));
  1947. printk("SELID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
  1948. "SCB_CONTROL == 0x%x\n",
  1949. ahd_inb(ahd, SELID), ahd_inb_scbram(ahd, SCB_SCSIID),
  1950. ahd_inb_scbram(ahd, SCB_LUN),
  1951. ahd_inb_scbram(ahd, SCB_CONTROL));
  1952. printk("SCSIBUS[0] == 0x%x, SCSISIGI == 0x%x\n",
  1953. ahd_inb(ahd, SCSIBUS), ahd_inb(ahd, SCSISIGI));
  1954. printk("SXFRCTL0 == 0x%x\n", ahd_inb(ahd, SXFRCTL0));
  1955. printk("SEQCTL0 == 0x%x\n", ahd_inb(ahd, SEQCTL0));
  1956. ahd_dump_card_state(ahd);
  1957. ahd->msgout_buf[0] = MSG_BUS_DEV_RESET;
  1958. ahd->msgout_len = 1;
  1959. ahd->msgout_index = 0;
  1960. ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
  1961. ahd_outb(ahd, MSG_OUT, HOST_MSG);
  1962. ahd_assert_atn(ahd);
  1963. break;
  1964. }
  1965. case PROTO_VIOLATION:
  1966. {
  1967. ahd_handle_proto_violation(ahd);
  1968. break;
  1969. }
  1970. case IGN_WIDE_RES:
  1971. {
  1972. struct ahd_devinfo devinfo;
  1973. ahd_fetch_devinfo(ahd, &devinfo);
  1974. ahd_handle_ign_wide_residue(ahd, &devinfo);
  1975. break;
  1976. }
  1977. case BAD_PHASE:
  1978. {
  1979. u_int lastphase;
  1980. lastphase = ahd_inb(ahd, LASTPHASE);
  1981. printk("%s:%c:%d: unknown scsi bus phase %x, "
  1982. "lastphase = 0x%x. Attempting to continue\n",
  1983. ahd_name(ahd), 'A',
  1984. SCSIID_TARGET(ahd, ahd_inb(ahd, SAVED_SCSIID)),
  1985. lastphase, ahd_inb(ahd, SCSISIGI));
  1986. break;
  1987. }
  1988. case MISSED_BUSFREE:
  1989. {
  1990. u_int lastphase;
  1991. lastphase = ahd_inb(ahd, LASTPHASE);
  1992. printk("%s:%c:%d: Missed busfree. "
  1993. "Lastphase = 0x%x, Curphase = 0x%x\n",
  1994. ahd_name(ahd), 'A',
  1995. SCSIID_TARGET(ahd, ahd_inb(ahd, SAVED_SCSIID)),
  1996. lastphase, ahd_inb(ahd, SCSISIGI));
  1997. ahd_restart(ahd);
  1998. return;
  1999. }
  2000. case DATA_OVERRUN:
  2001. {
  2002. /*
  2003. * When the sequencer detects an overrun, it
  2004. * places the controller in "BITBUCKET" mode
  2005. * and allows the target to complete its transfer.
  2006. * Unfortunately, none of the counters get updated
  2007. * when the controller is in this mode, so we have
  2008. * no way of knowing how large the overrun was.
  2009. */
  2010. struct scb *scb;
  2011. u_int scbindex;
  2012. #ifdef AHD_DEBUG
  2013. u_int lastphase;
  2014. #endif
  2015. scbindex = ahd_get_scbptr(ahd);
  2016. scb = ahd_lookup_scb(ahd, scbindex);
  2017. #ifdef AHD_DEBUG
  2018. lastphase = ahd_inb(ahd, LASTPHASE);
  2019. if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) {
  2020. ahd_print_path(ahd, scb);
  2021. printk("data overrun detected %s. Tag == 0x%x.\n",
  2022. ahd_lookup_phase_entry(lastphase)->phasemsg,
  2023. SCB_GET_TAG(scb));
  2024. ahd_print_path(ahd, scb);
  2025. printk("%s seen Data Phase. Length = %ld. "
  2026. "NumSGs = %d.\n",
  2027. ahd_inb(ahd, SEQ_FLAGS) & DPHASE
  2028. ? "Have" : "Haven't",
  2029. ahd_get_transfer_length(scb), scb->sg_count);
  2030. ahd_dump_sglist(scb);
  2031. }
  2032. #endif
  2033. /*
  2034. * Set this and it will take effect when the
  2035. * target does a command complete.
  2036. */
  2037. ahd_freeze_devq(ahd, scb);
  2038. ahd_set_transaction_status(scb, CAM_DATA_RUN_ERR);
  2039. ahd_freeze_scb(scb);
  2040. break;
  2041. }
  2042. case MKMSG_FAILED:
  2043. {
  2044. struct ahd_devinfo devinfo;
  2045. struct scb *scb;
  2046. u_int scbid;
  2047. ahd_fetch_devinfo(ahd, &devinfo);
  2048. printk("%s:%c:%d:%d: Attempt to issue message failed\n",
  2049. ahd_name(ahd), devinfo.channel, devinfo.target,
  2050. devinfo.lun);
  2051. scbid = ahd_get_scbptr(ahd);
  2052. scb = ahd_lookup_scb(ahd, scbid);
  2053. if (scb != NULL
  2054. && (scb->flags & SCB_RECOVERY_SCB) != 0)
  2055. /*
  2056. * Ensure that we didn't put a second instance of this
  2057. * SCB into the QINFIFO.
  2058. */
  2059. ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb),
  2060. SCB_GET_CHANNEL(ahd, scb),
  2061. SCB_GET_LUN(scb), SCB_GET_TAG(scb),
  2062. ROLE_INITIATOR, /*status*/0,
  2063. SEARCH_REMOVE);
  2064. ahd_outb(ahd, SCB_CONTROL,
  2065. ahd_inb_scbram(ahd, SCB_CONTROL) & ~MK_MESSAGE);
  2066. break;
  2067. }
  2068. case TASKMGMT_FUNC_COMPLETE:
  2069. {
  2070. u_int scbid;
  2071. struct scb *scb;
  2072. scbid = ahd_get_scbptr(ahd);
  2073. scb = ahd_lookup_scb(ahd, scbid);
  2074. if (scb != NULL) {
  2075. u_int lun;
  2076. u_int tag;
  2077. cam_status error;
  2078. ahd_print_path(ahd, scb);
  2079. printk("Task Management Func 0x%x Complete\n",
  2080. scb->hscb->task_management);
  2081. lun = CAM_LUN_WILDCARD;
  2082. tag = SCB_LIST_NULL;
  2083. switch (scb->hscb->task_management) {
  2084. case SIU_TASKMGMT_ABORT_TASK:
  2085. tag = SCB_GET_TAG(scb);
  2086. case SIU_TASKMGMT_ABORT_TASK_SET:
  2087. case SIU_TASKMGMT_CLEAR_TASK_SET:
  2088. lun = scb->hscb->lun;
  2089. error = CAM_REQ_ABORTED;
  2090. ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb),
  2091. 'A', lun, tag, ROLE_INITIATOR,
  2092. error);
  2093. break;
  2094. case SIU_TASKMGMT_LUN_RESET:
  2095. lun = scb->hscb->lun;
  2096. case SIU_TASKMGMT_TARGET_RESET:
  2097. {
  2098. struct ahd_devinfo devinfo;
  2099. ahd_scb_devinfo(ahd, &devinfo, scb);
  2100. error = CAM_BDR_SENT;
  2101. ahd_handle_devreset(ahd, &devinfo, lun,
  2102. CAM_BDR_SENT,
  2103. lun != CAM_LUN_WILDCARD
  2104. ? "Lun Reset"
  2105. : "Target Reset",
  2106. /*verbose_level*/0);
  2107. break;
  2108. }
  2109. default:
  2110. panic("Unexpected TaskMgmt Func\n");
  2111. break;
  2112. }
  2113. }
  2114. break;
  2115. }
  2116. case TASKMGMT_CMD_CMPLT_OKAY:
  2117. {
  2118. u_int scbid;
  2119. struct scb *scb;
  2120. /*
  2121. * An ABORT TASK TMF failed to be delivered before
  2122. * the targeted command completed normally.
  2123. */
  2124. scbid = ahd_get_scbptr(ahd);
  2125. scb = ahd_lookup_scb(ahd, scbid);
  2126. if (scb != NULL) {
  2127. /*
  2128. * Remove the second instance of this SCB from
  2129. * the QINFIFO if it is still there.
  2130. */
  2131. ahd_print_path(ahd, scb);
  2132. printk("SCB completes before TMF\n");
  2133. /*
  2134. * Handle losing the race. Wait until any
  2135. * current selection completes. We will then
  2136. * set the TMF back to zero in this SCB so that
  2137. * the sequencer doesn't bother to issue another
  2138. * sequencer interrupt for its completion.
  2139. */
  2140. while ((ahd_inb(ahd, SCSISEQ0) & ENSELO) != 0
  2141. && (ahd_inb(ahd, SSTAT0) & SELDO) == 0
  2142. && (ahd_inb(ahd, SSTAT1) & SELTO) == 0)
  2143. ;
  2144. ahd_outb(ahd, SCB_TASK_MANAGEMENT, 0);
  2145. ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb),
  2146. SCB_GET_CHANNEL(ahd, scb),
  2147. SCB_GET_LUN(scb), SCB_GET_TAG(scb),
  2148. ROLE_INITIATOR, /*status*/0,
  2149. SEARCH_REMOVE);
  2150. }
  2151. break;
  2152. }
  2153. case TRACEPOINT0:
  2154. case TRACEPOINT1:
  2155. case TRACEPOINT2:
  2156. case TRACEPOINT3:
  2157. printk("%s: Tracepoint %d\n", ahd_name(ahd),
  2158. seqintcode - TRACEPOINT0);
  2159. break;
  2160. case NO_SEQINT:
  2161. break;
  2162. case SAW_HWERR:
  2163. ahd_handle_hwerrint(ahd);
  2164. break;
  2165. default:
  2166. printk("%s: Unexpected SEQINTCODE %d\n", ahd_name(ahd),
  2167. seqintcode);
  2168. break;
  2169. }
  2170. /*
  2171. * The sequencer is paused immediately on
  2172. * a SEQINT, so we should restart it when
  2173. * we're done.
  2174. */
  2175. ahd_unpause(ahd);
  2176. }
  2177. static void
  2178. ahd_handle_scsiint(struct ahd_softc *ahd, u_int intstat)
  2179. {
  2180. struct scb *scb;
  2181. u_int status0;
  2182. u_int status3;
  2183. u_int status;
  2184. u_int lqistat1;
  2185. u_int lqostat0;
  2186. u_int scbid;
  2187. u_int busfreetime;
  2188. ahd_update_modes(ahd);
  2189. ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
  2190. status3 = ahd_inb(ahd, SSTAT3) & (NTRAMPERR|OSRAMPERR);
  2191. status0 = ahd_inb(ahd, SSTAT0) & (IOERR|OVERRUN|SELDI|SELDO);
  2192. status = ahd_inb(ahd, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
  2193. lqistat1 = ahd_inb(ahd, LQISTAT1);
  2194. lqostat0 = ahd_inb(ahd, LQOSTAT0);
  2195. busfreetime = ahd_inb(ahd, SSTAT2) & BUSFREETIME;
  2196. /*
  2197. * Ignore external resets after a bus reset.
  2198. */
  2199. if (((status & SCSIRSTI) != 0) && (ahd->flags & AHD_BUS_RESET_ACTIVE)) {
  2200. ahd_outb(ahd, CLRSINT1, CLRSCSIRSTI);
  2201. return;
  2202. }
  2203. /*
  2204. * Clear bus reset flag
  2205. */
  2206. ahd->flags &= ~AHD_BUS_RESET_ACTIVE;
  2207. if ((status0 & (SELDI|SELDO)) != 0) {
  2208. u_int simode0;
  2209. ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
  2210. simode0 = ahd_inb(ahd, SIMODE0);
  2211. status0 &= simode0 & (IOERR|OVERRUN|SELDI|SELDO);
  2212. ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
  2213. }
  2214. scbid = ahd_get_scbptr(ahd);
  2215. scb = ahd_lookup_scb(ahd, scbid);
  2216. if (scb != NULL
  2217. && (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) != 0)
  2218. scb = NULL;
  2219. if ((status0 & IOERR) != 0) {
  2220. u_int now_lvd;
  2221. now_lvd = ahd_inb(ahd, SBLKCTL) & ENAB40;
  2222. printk("%s: Transceiver State Has Changed to %s mode\n",
  2223. ahd_name(ahd), now_lvd ? "LVD" : "SE");
  2224. ahd_outb(ahd, CLRSINT0, CLRIOERR);
  2225. /*
  2226. * A change in I/O mode is equivalent to a bus reset.
  2227. */
  2228. ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
  2229. ahd_pause(ahd);
  2230. ahd_setup_iocell_workaround(ahd);
  2231. ahd_unpause(ahd);
  2232. } else if ((status0 & OVERRUN) != 0) {
  2233. printk("%s: SCSI offset overrun detected. Resetting bus.\n",
  2234. ahd_name(ahd));
  2235. ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
  2236. } else if ((status & SCSIRSTI) != 0) {
  2237. printk("%s: Someone reset channel A\n", ahd_name(ahd));
  2238. ahd_reset_channel(ahd, 'A', /*Initiate Reset*/FALSE);
  2239. } else if ((status & SCSIPERR) != 0) {
  2240. /* Make sure the sequencer is in a safe location. */
  2241. ahd_clear_critical_section(ahd);
  2242. ahd_handle_transmission_error(ahd);
  2243. } else if (lqostat0 != 0) {
  2244. printk("%s: lqostat0 == 0x%x!\n", ahd_name(ahd), lqostat0);
  2245. ahd_outb(ahd, CLRLQOINT0, lqostat0);
  2246. if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0)
  2247. ahd_outb(ahd, CLRLQOINT1, 0);
  2248. } else if ((status & SELTO) != 0) {
  2249. /* Stop the selection */
  2250. ahd_outb(ahd, SCSISEQ0, 0);
  2251. /* Make sure the sequencer is in a safe location. */
  2252. ahd_clear_critical_section(ahd);
  2253. /* No more pending messages */
  2254. ahd_clear_msg_state(ahd);
  2255. /* Clear interrupt state */
  2256. ahd_outb(ahd, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR);
  2257. /*
  2258. * Although the driver does not care about the
  2259. * 'Selection in Progress' status bit, the busy
  2260. * LED does. SELINGO is only cleared by a successful
  2261. * selection, so we must manually clear it to insure
  2262. * the LED turns off just incase no future successful
  2263. * selections occur (e.g. no devices on the bus).
  2264. */
  2265. ahd_outb(ahd, CLRSINT0, CLRSELINGO);
  2266. scbid = ahd_inw(ahd, WAITING_TID_HEAD);
  2267. scb = ahd_lookup_scb(ahd, scbid);
  2268. if (scb == NULL) {
  2269. printk("%s: ahd_intr - referenced scb not "
  2270. "valid during SELTO scb(0x%x)\n",
  2271. ahd_name(ahd), scbid);
  2272. ahd_dump_card_state(ahd);
  2273. } else {
  2274. struct ahd_devinfo devinfo;
  2275. #ifdef AHD_DEBUG
  2276. if ((ahd_debug & AHD_SHOW_SELTO) != 0) {
  2277. ahd_print_path(ahd, scb);
  2278. printk("Saw Selection Timeout for SCB 0x%x\n",
  2279. scbid);
  2280. }
  2281. #endif
  2282. ahd_scb_devinfo(ahd, &devinfo, scb);
  2283. ahd_set_transaction_status(scb, CAM_SEL_TIMEOUT);
  2284. ahd_freeze_devq(ahd, scb);
  2285. /*
  2286. * Cancel any pending transactions on the device
  2287. * now that it seems to be missing. This will
  2288. * also revert us to async/narrow transfers until
  2289. * we can renegotiate with the device.
  2290. */
  2291. ahd_handle_devreset(ahd, &devinfo,
  2292. CAM_LUN_WILDCARD,
  2293. CAM_SEL_TIMEOUT,
  2294. "Selection Timeout",
  2295. /*verbose_level*/1);
  2296. }
  2297. ahd_outb(ahd, CLRINT, CLRSCSIINT);
  2298. ahd_iocell_first_selection(ahd);
  2299. ahd_unpause(ahd);
  2300. } else if ((status0 & (SELDI|SELDO)) != 0) {
  2301. ahd_iocell_first_selection(ahd);
  2302. ahd_unpause(ahd);
  2303. } else if (status3 != 0) {
  2304. printk("%s: SCSI Cell parity error SSTAT3 == 0x%x\n",
  2305. ahd_name(ahd), status3);
  2306. ahd_outb(ahd, CLRSINT3, status3);
  2307. } else if ((lqistat1 & (LQIPHASE_LQ|LQIPHASE_NLQ)) != 0) {
  2308. /* Make sure the sequencer is in a safe location. */
  2309. ahd_clear_critical_section(ahd);
  2310. ahd_handle_lqiphase_error(ahd, lqistat1);
  2311. } else if ((lqistat1 & LQICRCI_NLQ) != 0) {
  2312. /*
  2313. * This status can be delayed during some
  2314. * streaming operations. The SCSIPHASE
  2315. * handler has already dealt with this case
  2316. * so just clear the error.
  2317. */
  2318. ahd_outb(ahd, CLRLQIINT1, CLRLQICRCI_NLQ);
  2319. } else if ((status & BUSFREE) != 0
  2320. || (lqistat1 & LQOBUSFREE) != 0) {
  2321. u_int lqostat1;
  2322. int restart;
  2323. int clear_fifo;
  2324. int packetized;
  2325. u_int mode;
  2326. /*
  2327. * Clear our selection hardware as soon as possible.
  2328. * We may have an entry in the waiting Q for this target,
  2329. * that is affected by this busfree and we don't want to
  2330. * go about selecting the target while we handle the event.
  2331. */
  2332. ahd_outb(ahd, SCSISEQ0, 0);
  2333. /* Make sure the sequencer is in a safe location. */
  2334. ahd_clear_critical_section(ahd);
  2335. /*
  2336. * Determine what we were up to at the time of
  2337. * the busfree.
  2338. */
  2339. mode = AHD_MODE_SCSI;
  2340. busfreetime = ahd_inb(ahd, SSTAT2) & BUSFREETIME;
  2341. lqostat1 = ahd_inb(ahd, LQOSTAT1);
  2342. switch (busfreetime) {
  2343. case BUSFREE_DFF0:
  2344. case BUSFREE_DFF1:
  2345. {
  2346. mode = busfreetime == BUSFREE_DFF0
  2347. ? AHD_MODE_DFF0 : AHD_MODE_DFF1;
  2348. ahd_set_modes(ahd, mode, mode);
  2349. scbid = ahd_get_scbptr(ahd);
  2350. scb = ahd_lookup_scb(ahd, scbid);
  2351. if (scb == NULL) {
  2352. printk("%s: Invalid SCB %d in DFF%d "
  2353. "during unexpected busfree\n",
  2354. ahd_name(ahd), scbid, mode);
  2355. packetized = 0;
  2356. } else
  2357. packetized = (scb->flags & SCB_PACKETIZED) != 0;
  2358. clear_fifo = 1;
  2359. break;
  2360. }
  2361. case BUSFREE_LQO:
  2362. clear_fifo = 0;
  2363. packetized = 1;
  2364. break;
  2365. default:
  2366. clear_fifo = 0;
  2367. packetized = (lqostat1 & LQOBUSFREE) != 0;
  2368. if (!packetized
  2369. && ahd_inb(ahd, LASTPHASE) == P_BUSFREE
  2370. && (ahd_inb(ahd, SSTAT0) & SELDI) == 0
  2371. && ((ahd_inb(ahd, SSTAT0) & SELDO) == 0
  2372. || (ahd_inb(ahd, SCSISEQ0) & ENSELO) == 0))
  2373. /*
  2374. * Assume packetized if we are not
  2375. * on the bus in a non-packetized
  2376. * capacity and any pending selection
  2377. * was a packetized selection.
  2378. */
  2379. packetized = 1;
  2380. break;
  2381. }
  2382. #ifdef AHD_DEBUG
  2383. if ((ahd_debug & AHD_SHOW_MISC) != 0)
  2384. printk("Saw Busfree. Busfreetime = 0x%x.\n",
  2385. busfreetime);
  2386. #endif
  2387. /*
  2388. * Busfrees that occur in non-packetized phases are
  2389. * handled by the nonpkt_busfree handler.
  2390. */
  2391. if (packetized && ahd_inb(ahd, LASTPHASE) == P_BUSFREE) {
  2392. restart = ahd_handle_pkt_busfree(ahd, busfreetime);
  2393. } else {
  2394. packetized = 0;
  2395. restart = ahd_handle_nonpkt_busfree(ahd);
  2396. }
  2397. /*
  2398. * Clear the busfree interrupt status. The setting of
  2399. * the interrupt is a pulse, so in a perfect world, we
  2400. * would not need to muck with the ENBUSFREE logic. This
  2401. * would ensure that if the bus moves on to another
  2402. * connection, busfree protection is still in force. If
  2403. * BUSFREEREV is broken, however, we must manually clear
  2404. * the ENBUSFREE if the busfree occurred during a non-pack
  2405. * connection so that we don't get false positives during
  2406. * future, packetized, connections.
  2407. */
  2408. ahd_outb(ahd, CLRSINT1, CLRBUSFREE);
  2409. if (packetized == 0
  2410. && (ahd->bugs & AHD_BUSFREEREV_BUG) != 0)
  2411. ahd_outb(ahd, SIMODE1,
  2412. ahd_inb(ahd, SIMODE1) & ~ENBUSFREE);
  2413. if (clear_fifo)
  2414. ahd_clear_fifo(ahd, mode);
  2415. ahd_clear_msg_state(ahd);
  2416. ahd_outb(ahd, CLRINT, CLRSCSIINT);
  2417. if (restart) {
  2418. ahd_restart(ahd);
  2419. } else {
  2420. ahd_unpause(ahd);
  2421. }
  2422. } else {
  2423. printk("%s: Missing case in ahd_handle_scsiint. status = %x\n",
  2424. ahd_name(ahd), status);
  2425. ahd_dump_card_state(ahd);
  2426. ahd_clear_intstat(ahd);
  2427. ahd_unpause(ahd);
  2428. }
  2429. }
  2430. static void
  2431. ahd_handle_transmission_error(struct ahd_softc *ahd)
  2432. {
  2433. struct scb *scb;
  2434. u_int scbid;
  2435. u_int lqistat1;
  2436. u_int lqistat2;
  2437. u_int msg_out;
  2438. u_int curphase;
  2439. u_int lastphase;
  2440. u_int perrdiag;
  2441. u_int cur_col;
  2442. int silent;
  2443. scb = NULL;
  2444. ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
  2445. lqistat1 = ahd_inb(ahd, LQISTAT1) & ~(LQIPHASE_LQ|LQIPHASE_NLQ);
  2446. lqistat2 = ahd_inb(ahd, LQISTAT2);
  2447. if ((lqistat1 & (LQICRCI_NLQ|LQICRCI_LQ)) == 0
  2448. && (ahd->bugs & AHD_NLQICRC_DELAYED_BUG) != 0) {
  2449. u_int lqistate;
  2450. ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
  2451. lqistate = ahd_inb(ahd, LQISTATE);
  2452. if ((lqistate >= 0x1E && lqistate <= 0x24)
  2453. || (lqistate == 0x29)) {
  2454. #ifdef AHD_DEBUG
  2455. if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) {
  2456. printk("%s: NLQCRC found via LQISTATE\n",
  2457. ahd_name(ahd));
  2458. }
  2459. #endif
  2460. lqistat1 |= LQICRCI_NLQ;
  2461. }
  2462. ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
  2463. }
  2464. ahd_outb(ahd, CLRLQIINT1, lqistat1);
  2465. lastphase = ahd_inb(ahd, LASTPHASE);
  2466. curphase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK;
  2467. perrdiag = ahd_inb(ahd, PERRDIAG);
  2468. msg_out = MSG_INITIATOR_DET_ERR;
  2469. ahd_outb(ahd, CLRSINT1, CLRSCSIPERR);
  2470. /*
  2471. * Try to find the SCB associated with this error.
  2472. */
  2473. silent = FALSE;
  2474. if (lqistat1 == 0
  2475. || (lqistat1 & LQICRCI_NLQ) != 0) {
  2476. if ((lqistat1 & (LQICRCI_NLQ|LQIOVERI_NLQ)) != 0)
  2477. ahd_set_active_fifo(ahd);
  2478. scbid = ahd_get_scbptr(ahd);
  2479. scb = ahd_lookup_scb(ahd, scbid);
  2480. if (scb != NULL && SCB_IS_SILENT(scb))
  2481. silent = TRUE;
  2482. }
  2483. cur_col = 0;
  2484. if (silent == FALSE) {
  2485. printk("%s: Transmission error detected\n", ahd_name(ahd));
  2486. ahd_lqistat1_print(lqistat1, &cur_col, 50);
  2487. ahd_lastphase_print(lastphase, &cur_col, 50);
  2488. ahd_scsisigi_print(curphase, &cur_col, 50);
  2489. ahd_perrdiag_print(perrdiag, &cur_col, 50);
  2490. printk("\n");
  2491. ahd_dump_card_state(ahd);
  2492. }
  2493. if ((lqistat1 & (LQIOVERI_LQ|LQIOVERI_NLQ)) != 0) {
  2494. if (silent == FALSE) {
  2495. printk("%s: Gross protocol error during incoming "
  2496. "packet. lqistat1 == 0x%x. Resetting bus.\n",
  2497. ahd_name(ahd), lqistat1);
  2498. }
  2499. ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
  2500. return;
  2501. } else if ((lqistat1 & LQICRCI_LQ) != 0) {
  2502. /*
  2503. * A CRC error has been detected on an incoming LQ.
  2504. * The bus is currently hung on the last ACK.
  2505. * Hit LQIRETRY to release the last ack, and
  2506. * wait for the sequencer to determine that ATNO
  2507. * is asserted while in message out to take us
  2508. * to our host message loop. No NONPACKREQ or
  2509. * LQIPHASE type errors will occur in this
  2510. * scenario. After this first LQIRETRY, the LQI
  2511. * manager will be in ISELO where it will
  2512. * happily sit until another packet phase begins.
  2513. * Unexpected bus free detection is enabled
  2514. * through any phases that occur after we release
  2515. * this last ack until the LQI manager sees a
  2516. * packet phase. This implies we may have to
  2517. * ignore a perfectly valid "unexected busfree"
  2518. * after our "initiator detected error" message is
  2519. * sent. A busfree is the expected response after
  2520. * we tell the target that it's L_Q was corrupted.
  2521. * (SPI4R09 10.7.3.3.3)
  2522. */
  2523. ahd_outb(ahd, LQCTL2, LQIRETRY);
  2524. printk("LQIRetry for LQICRCI_LQ to release ACK\n");
  2525. } else if ((lqistat1 & LQICRCI_NLQ) != 0) {
  2526. /*
  2527. * We detected a CRC error in a NON-LQ packet.
  2528. * The hardware has varying behavior in this situation
  2529. * depending on whether this packet was part of a
  2530. * stream or not.
  2531. *
  2532. * PKT by PKT mode:
  2533. * The hardware has already acked the complete packet.
  2534. * If the target honors our outstanding ATN condition,
  2535. * we should be (or soon will be) in MSGOUT phase.
  2536. * This will trigger the LQIPHASE_LQ status bit as the
  2537. * hardware was expecting another LQ. Unexpected
  2538. * busfree detection is enabled. Once LQIPHASE_LQ is
  2539. * true (first entry into host message loop is much
  2540. * the same), we must clear LQIPHASE_LQ and hit
  2541. * LQIRETRY so the hardware is ready to handle
  2542. * a future LQ. NONPACKREQ will not be asserted again
  2543. * once we hit LQIRETRY until another packet is
  2544. * processed. The target may either go busfree
  2545. * or start another packet in response to our message.
  2546. *
  2547. * Read Streaming P0 asserted:
  2548. * If we raise ATN and the target completes the entire
  2549. * stream (P0 asserted during the last packet), the
  2550. * hardware will ack all data and return to the ISTART
  2551. * state. When the target reponds to our ATN condition,
  2552. * LQIPHASE_LQ will be asserted. We should respond to
  2553. * this with an LQIRETRY to prepare for any future
  2554. * packets. NONPACKREQ will not be asserted again
  2555. * once we hit LQIRETRY until another packet is
  2556. * processed. The target may either go busfree or
  2557. * start another packet in response to our message.
  2558. * Busfree detection is enabled.
  2559. *
  2560. * Read Streaming P0 not asserted:
  2561. * If we raise ATN and the target transitions to
  2562. * MSGOUT in or after a packet where P0 is not
  2563. * asserted, the hardware will assert LQIPHASE_NLQ.
  2564. * We should respond to the LQIPHASE_NLQ with an
  2565. * LQIRETRY. Should the target stay in a non-pkt
  2566. * phase after we send our message, the hardware
  2567. * will assert LQIPHASE_LQ. Recovery is then just as
  2568. * listed above for the read streaming with P0 asserted.
  2569. * Busfree detection is enabled.
  2570. */
  2571. if (silent == FALSE)
  2572. printk("LQICRC_NLQ\n");
  2573. if (scb == NULL) {
  2574. printk("%s: No SCB valid for LQICRC_NLQ. "
  2575. "Resetting bus\n", ahd_name(ahd));
  2576. ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
  2577. return;
  2578. }
  2579. } else if ((lqistat1 & LQIBADLQI) != 0) {
  2580. printk("Need to handle BADLQI!\n");
  2581. ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
  2582. return;
  2583. } else if ((perrdiag & (PARITYERR|PREVPHASE)) == PARITYERR) {
  2584. if ((curphase & ~P_DATAIN_DT) != 0) {
  2585. /* Ack the byte. So we can continue. */
  2586. if (silent == FALSE)
  2587. printk("Acking %s to clear perror\n",
  2588. ahd_lookup_phase_entry(curphase)->phasemsg);
  2589. ahd_inb(ahd, SCSIDAT);
  2590. }
  2591. if (curphase == P_MESGIN)
  2592. msg_out = MSG_PARITY_ERROR;
  2593. }
  2594. /*
  2595. * We've set the hardware to assert ATN if we
  2596. * get a parity error on "in" phases, so all we
  2597. * need to do is stuff the message buffer with
  2598. * the appropriate message. "In" phases have set
  2599. * mesg_out to something other than MSG_NOP.
  2600. */
  2601. ahd->send_msg_perror = msg_out;
  2602. if (scb != NULL && msg_out == MSG_INITIATOR_DET_ERR)
  2603. scb->flags |= SCB_TRANSMISSION_ERROR;
  2604. ahd_outb(ahd, MSG_OUT, HOST_MSG);
  2605. ahd_outb(ahd, CLRINT, CLRSCSIINT);
  2606. ahd_unpause(ahd);
  2607. }
  2608. static void
  2609. ahd_handle_lqiphase_error(struct ahd_softc *ahd, u_int lqistat1)
  2610. {
  2611. /*
  2612. * Clear the sources of the interrupts.
  2613. */
  2614. ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
  2615. ahd_outb(ahd, CLRLQIINT1, lqistat1);
  2616. /*
  2617. * If the "illegal" phase changes were in response
  2618. * to our ATN to flag a CRC error, AND we ended up
  2619. * on packet boundaries, clear the error, restart the
  2620. * LQI manager as appropriate, and go on our merry
  2621. * way toward sending the message. Otherwise, reset
  2622. * the bus to clear the error.
  2623. */
  2624. ahd_set_active_fifo(ahd);
  2625. if ((ahd_inb(ahd, SCSISIGO) & ATNO) != 0
  2626. && (ahd_inb(ahd, MDFFSTAT) & DLZERO) != 0) {
  2627. if ((lqistat1 & LQIPHASE_LQ) != 0) {
  2628. printk("LQIRETRY for LQIPHASE_LQ\n");
  2629. ahd_outb(ahd, LQCTL2, LQIRETRY);
  2630. } else if ((lqistat1 & LQIPHASE_NLQ) != 0) {
  2631. printk("LQIRETRY for LQIPHASE_NLQ\n");
  2632. ahd_outb(ahd, LQCTL2, LQIRETRY);
  2633. } else
  2634. panic("ahd_handle_lqiphase_error: No phase errors\n");
  2635. ahd_dump_card_state(ahd);
  2636. ahd_outb(ahd, CLRINT, CLRSCSIINT);
  2637. ahd_unpause(ahd);
  2638. } else {
  2639. printk("Resetting Channel for LQI Phase error\n");
  2640. ahd_dump_card_state(ahd);
  2641. ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
  2642. }
  2643. }
  2644. /*
  2645. * Packetized unexpected or expected busfree.
  2646. * Entered in mode based on busfreetime.
  2647. */
  2648. static int
  2649. ahd_handle_pkt_busfree(struct ahd_softc *ahd, u_int busfreetime)
  2650. {
  2651. u_int lqostat1;
  2652. AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
  2653. ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
  2654. lqostat1 = ahd_inb(ahd, LQOSTAT1);
  2655. if ((lqostat1 & LQOBUSFREE) != 0) {
  2656. struct scb *scb;
  2657. u_int scbid;
  2658. u_int saved_scbptr;
  2659. u_int waiting_h;
  2660. u_int waiting_t;
  2661. u_int next;
  2662. /*
  2663. * The LQO manager detected an unexpected busfree
  2664. * either:
  2665. *
  2666. * 1) During an outgoing LQ.
  2667. * 2) After an outgoing LQ but before the first
  2668. * REQ of the command packet.
  2669. * 3) During an outgoing command packet.
  2670. *
  2671. * In all cases, CURRSCB is pointing to the
  2672. * SCB that encountered the failure. Clean
  2673. * up the queue, clear SELDO and LQOBUSFREE,
  2674. * and allow the sequencer to restart the select
  2675. * out at its lesure.
  2676. */
  2677. ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
  2678. scbid = ahd_inw(ahd, CURRSCB);
  2679. scb = ahd_lookup_scb(ahd, scbid);
  2680. if (scb == NULL)
  2681. panic("SCB not valid during LQOBUSFREE");
  2682. /*
  2683. * Clear the status.
  2684. */
  2685. ahd_outb(ahd, CLRLQOINT1, CLRLQOBUSFREE);
  2686. if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0)
  2687. ahd_outb(ahd, CLRLQOINT1, 0);
  2688. ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO);
  2689. ahd_flush_device_writes(ahd);
  2690. ahd_outb(ahd, CLRSINT0, CLRSELDO);
  2691. /*
  2692. * Return the LQO manager to its idle loop. It will
  2693. * not do this automatically if the busfree occurs
  2694. * after the first REQ of either the LQ or command
  2695. * packet or between the LQ and command packet.
  2696. */
  2697. ahd_outb(ahd, LQCTL2, ahd_inb(ahd, LQCTL2) | LQOTOIDLE);
  2698. /*
  2699. * Update the waiting for selection queue so
  2700. * we restart on the correct SCB.
  2701. */
  2702. waiting_h = ahd_inw(ahd, WAITING_TID_HEAD);
  2703. saved_scbptr = ahd_get_scbptr(ahd);
  2704. if (waiting_h != scbid) {
  2705. ahd_outw(ahd, WAITING_TID_HEAD, scbid);
  2706. waiting_t = ahd_inw(ahd, WAITING_TID_TAIL);
  2707. if (waiting_t == waiting_h) {
  2708. ahd_outw(ahd, WAITING_TID_TAIL, scbid);
  2709. next = SCB_LIST_NULL;
  2710. } else {
  2711. ahd_set_scbptr(ahd, waiting_h);
  2712. next = ahd_inw_scbram(ahd, SCB_NEXT2);
  2713. }
  2714. ahd_set_scbptr(ahd, scbid);
  2715. ahd_outw(ahd, SCB_NEXT2, next);
  2716. }
  2717. ahd_set_scbptr(ahd, saved_scbptr);
  2718. if (scb->crc_retry_count < AHD_MAX_LQ_CRC_ERRORS) {
  2719. if (SCB_IS_SILENT(scb) == FALSE) {
  2720. ahd_print_path(ahd, scb);
  2721. printk("Probable outgoing LQ CRC error. "
  2722. "Retrying command\n");
  2723. }
  2724. scb->crc_retry_count++;
  2725. } else {
  2726. ahd_set_transaction_status(scb, CAM_UNCOR_PARITY);
  2727. ahd_freeze_scb(scb);
  2728. ahd_freeze_devq(ahd, scb);
  2729. }
  2730. /* Return unpausing the sequencer. */
  2731. return (0);
  2732. } else if ((ahd_inb(ahd, PERRDIAG) & PARITYERR) != 0) {
  2733. /*
  2734. * Ignore what are really parity errors that
  2735. * occur on the last REQ of a free running
  2736. * clock prior to going busfree. Some drives
  2737. * do not properly active negate just before
  2738. * going busfree resulting in a parity glitch.
  2739. */
  2740. ahd_outb(ahd, CLRSINT1, CLRSCSIPERR|CLRBUSFREE);
  2741. #ifdef AHD_DEBUG
  2742. if ((ahd_debug & AHD_SHOW_MASKED_ERRORS) != 0)
  2743. printk("%s: Parity on last REQ detected "
  2744. "during busfree phase.\n",
  2745. ahd_name(ahd));
  2746. #endif
  2747. /* Return unpausing the sequencer. */
  2748. return (0);
  2749. }
  2750. if (ahd->src_mode != AHD_MODE_SCSI) {
  2751. u_int scbid;
  2752. struct scb *scb;
  2753. scbid = ahd_get_scbptr(ahd);
  2754. scb = ahd_lookup_scb(ahd, scbid);
  2755. ahd_print_path(ahd, scb);
  2756. printk("Unexpected PKT busfree condition\n");
  2757. ahd_dump_card_state(ahd);
  2758. ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb), 'A',
  2759. SCB_GET_LUN(scb), SCB_GET_TAG(scb),
  2760. ROLE_INITIATOR, CAM_UNEXP_BUSFREE);
  2761. /* Return restarting the sequencer. */
  2762. return (1);
  2763. }
  2764. printk("%s: Unexpected PKT busfree condition\n", ahd_name(ahd));
  2765. ahd_dump_card_state(ahd);
  2766. /* Restart the sequencer. */
  2767. return (1);
  2768. }
  2769. /*
  2770. * Non-packetized unexpected or expected busfree.
  2771. */
  2772. static int
  2773. ahd_handle_nonpkt_busfree(struct ahd_softc *ahd)
  2774. {
  2775. struct ahd_devinfo devinfo;
  2776. struct scb *scb;
  2777. u_int lastphase;
  2778. u_int saved_scsiid;
  2779. u_int saved_lun;
  2780. u_int target;
  2781. u_int initiator_role_id;
  2782. u_int scbid;
  2783. u_int ppr_busfree;
  2784. int printerror;
  2785. /*
  2786. * Look at what phase we were last in. If its message out,
  2787. * chances are pretty good that the busfree was in response
  2788. * to one of our abort requests.
  2789. */
  2790. lastphase = ahd_inb(ahd, LASTPHASE);
  2791. saved_scsiid = ahd_inb(ahd, SAVED_SCSIID);
  2792. saved_lun = ahd_inb(ahd, SAVED_LUN);
  2793. target = SCSIID_TARGET(ahd, saved_scsiid);
  2794. initiator_role_id = SCSIID_OUR_ID(saved_scsiid);
  2795. ahd_compile_devinfo(&devinfo, initiator_role_id,
  2796. target, saved_lun, 'A', ROLE_INITIATOR);
  2797. printerror = 1;
  2798. scbid = ahd_get_scbptr(ahd);
  2799. scb = ahd_lookup_scb(ahd, scbid);
  2800. if (scb != NULL
  2801. && (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) != 0)
  2802. scb = NULL;
  2803. ppr_busfree = (ahd->msg_flags & MSG_FLAG_EXPECT_PPR_BUSFREE) != 0;
  2804. if (lastphase == P_MESGOUT) {
  2805. u_int tag;
  2806. tag = SCB_LIST_NULL;
  2807. if (ahd_sent_msg(ahd, AHDMSG_1B, MSG_ABORT_TAG, TRUE)
  2808. || ahd_sent_msg(ahd, AHDMSG_1B, MSG_ABORT, TRUE)) {
  2809. int found;
  2810. int sent_msg;
  2811. if (scb == NULL) {
  2812. ahd_print_devinfo(ahd, &devinfo);
  2813. printk("Abort for unidentified "
  2814. "connection completed.\n");
  2815. /* restart the sequencer. */
  2816. return (1);
  2817. }
  2818. sent_msg = ahd->msgout_buf[ahd->msgout_index - 1];
  2819. ahd_print_path(ahd, scb);
  2820. printk("SCB %d - Abort%s Completed.\n",
  2821. SCB_GET_TAG(scb),
  2822. sent_msg == MSG_ABORT_TAG ? "" : " Tag");
  2823. if (sent_msg == MSG_ABORT_TAG)
  2824. tag = SCB_GET_TAG(scb);
  2825. if ((scb->flags & SCB_EXTERNAL_RESET) != 0) {
  2826. /*
  2827. * This abort is in response to an
  2828. * unexpected switch to command phase
  2829. * for a packetized connection. Since
  2830. * the identify message was never sent,
  2831. * "saved lun" is 0. We really want to
  2832. * abort only the SCB that encountered
  2833. * this error, which could have a different
  2834. * lun. The SCB will be retried so the OS
  2835. * will see the UA after renegotiating to
  2836. * packetized.
  2837. */
  2838. tag = SCB_GET_TAG(scb);
  2839. saved_lun = scb->hscb->lun;
  2840. }
  2841. found = ahd_abort_scbs(ahd, target, 'A', saved_lun,
  2842. tag, ROLE_INITIATOR,
  2843. CAM_REQ_ABORTED);
  2844. printk("found == 0x%x\n", found);
  2845. printerror = 0;
  2846. } else if (ahd_sent_msg(ahd, AHDMSG_1B,
  2847. MSG_BUS_DEV_RESET, TRUE)) {
  2848. #ifdef __FreeBSD__
  2849. /*
  2850. * Don't mark the user's request for this BDR
  2851. * as completing with CAM_BDR_SENT. CAM3
  2852. * specifies CAM_REQ_CMP.
  2853. */
  2854. if (scb != NULL
  2855. && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV
  2856. && ahd_match_scb(ahd, scb, target, 'A',
  2857. CAM_LUN_WILDCARD, SCB_LIST_NULL,
  2858. ROLE_INITIATOR))
  2859. ahd_set_transaction_status(scb, CAM_REQ_CMP);
  2860. #endif
  2861. ahd_handle_devreset(ahd, &devinfo, CAM_LUN_WILDCARD,
  2862. CAM_BDR_SENT, "Bus Device Reset",
  2863. /*verbose_level*/0);
  2864. printerror = 0;
  2865. } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, FALSE)
  2866. && ppr_busfree == 0) {
  2867. struct ahd_initiator_tinfo *tinfo;
  2868. struct ahd_tmode_tstate *tstate;
  2869. /*
  2870. * PPR Rejected.
  2871. *
  2872. * If the previous negotiation was packetized,
  2873. * this could be because the device has been
  2874. * reset without our knowledge. Force our
  2875. * current negotiation to async and retry the
  2876. * negotiation. Otherwise retry the command
  2877. * with non-ppr negotiation.
  2878. */
  2879. #ifdef AHD_DEBUG
  2880. if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
  2881. printk("PPR negotiation rejected busfree.\n");
  2882. #endif
  2883. tinfo = ahd_fetch_transinfo(ahd, devinfo.channel,
  2884. devinfo.our_scsiid,
  2885. devinfo.target, &tstate);
  2886. if ((tinfo->curr.ppr_options & MSG_EXT_PPR_IU_REQ)!=0) {
  2887. ahd_set_width(ahd, &devinfo,
  2888. MSG_EXT_WDTR_BUS_8_BIT,
  2889. AHD_TRANS_CUR,
  2890. /*paused*/TRUE);
  2891. ahd_set_syncrate(ahd, &devinfo,
  2892. /*period*/0, /*offset*/0,
  2893. /*ppr_options*/0,
  2894. AHD_TRANS_CUR,
  2895. /*paused*/TRUE);
  2896. /*
  2897. * The expect PPR busfree handler below
  2898. * will effect the retry and necessary
  2899. * abort.
  2900. */
  2901. } else {
  2902. tinfo->curr.transport_version = 2;
  2903. tinfo->goal.transport_version = 2;
  2904. tinfo->goal.ppr_options = 0;
  2905. if (scb != NULL) {
  2906. /*
  2907. * Remove any SCBs in the waiting
  2908. * for selection queue that may
  2909. * also be for this target so that
  2910. * command ordering is preserved.
  2911. */
  2912. ahd_freeze_devq(ahd, scb);
  2913. ahd_qinfifo_requeue_tail(ahd, scb);
  2914. }
  2915. printerror = 0;
  2916. }
  2917. } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, FALSE)
  2918. && ppr_busfree == 0) {
  2919. /*
  2920. * Negotiation Rejected. Go-narrow and
  2921. * retry command.
  2922. */
  2923. #ifdef AHD_DEBUG
  2924. if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
  2925. printk("WDTR negotiation rejected busfree.\n");
  2926. #endif
  2927. ahd_set_width(ahd, &devinfo,
  2928. MSG_EXT_WDTR_BUS_8_BIT,
  2929. AHD_TRANS_CUR|AHD_TRANS_GOAL,
  2930. /*paused*/TRUE);
  2931. if (scb != NULL) {
  2932. /*
  2933. * Remove any SCBs in the waiting for
  2934. * selection queue that may also be for
  2935. * this target so that command ordering
  2936. * is preserved.
  2937. */
  2938. ahd_freeze_devq(ahd, scb);
  2939. ahd_qinfifo_requeue_tail(ahd, scb);
  2940. }
  2941. printerror = 0;
  2942. } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, FALSE)
  2943. && ppr_busfree == 0) {
  2944. /*
  2945. * Negotiation Rejected. Go-async and
  2946. * retry command.
  2947. */
  2948. #ifdef AHD_DEBUG
  2949. if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
  2950. printk("SDTR negotiation rejected busfree.\n");
  2951. #endif
  2952. ahd_set_syncrate(ahd, &devinfo,
  2953. /*period*/0, /*offset*/0,
  2954. /*ppr_options*/0,
  2955. AHD_TRANS_CUR|AHD_TRANS_GOAL,
  2956. /*paused*/TRUE);
  2957. if (scb != NULL) {
  2958. /*
  2959. * Remove any SCBs in the waiting for
  2960. * selection queue that may also be for
  2961. * this target so that command ordering
  2962. * is preserved.
  2963. */
  2964. ahd_freeze_devq(ahd, scb);
  2965. ahd_qinfifo_requeue_tail(ahd, scb);
  2966. }
  2967. printerror = 0;
  2968. } else if ((ahd->msg_flags & MSG_FLAG_EXPECT_IDE_BUSFREE) != 0
  2969. && ahd_sent_msg(ahd, AHDMSG_1B,
  2970. MSG_INITIATOR_DET_ERR, TRUE)) {
  2971. #ifdef AHD_DEBUG
  2972. if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
  2973. printk("Expected IDE Busfree\n");
  2974. #endif
  2975. printerror = 0;
  2976. } else if ((ahd->msg_flags & MSG_FLAG_EXPECT_QASREJ_BUSFREE)
  2977. && ahd_sent_msg(ahd, AHDMSG_1B,
  2978. MSG_MESSAGE_REJECT, TRUE)) {
  2979. #ifdef AHD_DEBUG
  2980. if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
  2981. printk("Expected QAS Reject Busfree\n");
  2982. #endif
  2983. printerror = 0;
  2984. }
  2985. }
  2986. /*
  2987. * The busfree required flag is honored at the end of
  2988. * the message phases. We check it last in case we
  2989. * had to send some other message that caused a busfree.
  2990. */
  2991. if (scb != NULL && printerror != 0
  2992. && (lastphase == P_MESGIN || lastphase == P_MESGOUT)
  2993. && ((ahd->msg_flags & MSG_FLAG_EXPECT_PPR_BUSFREE) != 0)) {
  2994. ahd_freeze_devq(ahd, scb);
  2995. ahd_set_transaction_status(scb, CAM_REQUEUE_REQ);
  2996. ahd_freeze_scb(scb);
  2997. if ((ahd->msg_flags & MSG_FLAG_IU_REQ_CHANGED) != 0) {
  2998. ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb),
  2999. SCB_GET_CHANNEL(ahd, scb),
  3000. SCB_GET_LUN(scb), SCB_LIST_NULL,
  3001. ROLE_INITIATOR, CAM_REQ_ABORTED);
  3002. } else {
  3003. #ifdef AHD_DEBUG
  3004. if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
  3005. printk("PPR Negotiation Busfree.\n");
  3006. #endif
  3007. ahd_done(ahd, scb);
  3008. }
  3009. printerror = 0;
  3010. }
  3011. if (printerror != 0) {
  3012. int aborted;
  3013. aborted = 0;
  3014. if (scb != NULL) {
  3015. u_int tag;
  3016. if ((scb->hscb->control & TAG_ENB) != 0)
  3017. tag = SCB_GET_TAG(scb);
  3018. else
  3019. tag = SCB_LIST_NULL;
  3020. ahd_print_path(ahd, scb);
  3021. aborted = ahd_abort_scbs(ahd, target, 'A',
  3022. SCB_GET_LUN(scb), tag,
  3023. ROLE_INITIATOR,
  3024. CAM_UNEXP_BUSFREE);
  3025. } else {
  3026. /*
  3027. * We had not fully identified this connection,
  3028. * so we cannot abort anything.
  3029. */
  3030. printk("%s: ", ahd_name(ahd));
  3031. }
  3032. printk("Unexpected busfree %s, %d SCBs aborted, "
  3033. "PRGMCNT == 0x%x\n",
  3034. ahd_lookup_phase_entry(lastphase)->phasemsg,
  3035. aborted,
  3036. ahd_inw(ahd, PRGMCNT));
  3037. ahd_dump_card_state(ahd);
  3038. if (lastphase != P_BUSFREE)
  3039. ahd_force_renegotiation(ahd, &devinfo);
  3040. }
  3041. /* Always restart the sequencer. */
  3042. return (1);
  3043. }
  3044. static void
  3045. ahd_handle_proto_violation(struct ahd_softc *ahd)
  3046. {
  3047. struct ahd_devinfo devinfo;
  3048. struct scb *scb;
  3049. u_int scbid;
  3050. u_int seq_flags;
  3051. u_int curphase;
  3052. u_int lastphase;
  3053. int found;
  3054. ahd_fetch_devinfo(ahd, &devinfo);
  3055. scbid = ahd_get_scbptr(ahd);
  3056. scb = ahd_lookup_scb(ahd, scbid);
  3057. seq_flags = ahd_inb(ahd, SEQ_FLAGS);
  3058. curphase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK;
  3059. lastphase = ahd_inb(ahd, LASTPHASE);
  3060. if ((seq_flags & NOT_IDENTIFIED) != 0) {
  3061. /*
  3062. * The reconnecting target either did not send an
  3063. * identify message, or did, but we didn't find an SCB
  3064. * to match.
  3065. */
  3066. ahd_print_devinfo(ahd, &devinfo);
  3067. printk("Target did not send an IDENTIFY message. "
  3068. "LASTPHASE = 0x%x.\n", lastphase);
  3069. scb = NULL;
  3070. } else if (scb == NULL) {
  3071. /*
  3072. * We don't seem to have an SCB active for this
  3073. * transaction. Print an error and reset the bus.
  3074. */
  3075. ahd_print_devinfo(ahd, &devinfo);
  3076. printk("No SCB found during protocol violation\n");
  3077. goto proto_violation_reset;
  3078. } else {
  3079. ahd_set_transaction_status(scb, CAM_SEQUENCE_FAIL);
  3080. if ((seq_flags & NO_CDB_SENT) != 0) {
  3081. ahd_print_path(ahd, scb);
  3082. printk("No or incomplete CDB sent to device.\n");
  3083. } else if ((ahd_inb_scbram(ahd, SCB_CONTROL)
  3084. & STATUS_RCVD) == 0) {
  3085. /*
  3086. * The target never bothered to provide status to
  3087. * us prior to completing the command. Since we don't
  3088. * know the disposition of this command, we must attempt
  3089. * to abort it. Assert ATN and prepare to send an abort
  3090. * message.
  3091. */
  3092. ahd_print_path(ahd, scb);
  3093. printk("Completed command without status.\n");
  3094. } else {
  3095. ahd_print_path(ahd, scb);
  3096. printk("Unknown protocol violation.\n");
  3097. ahd_dump_card_state(ahd);
  3098. }
  3099. }
  3100. if ((lastphase & ~P_DATAIN_DT) == 0
  3101. || lastphase == P_COMMAND) {
  3102. proto_violation_reset:
  3103. /*
  3104. * Target either went directly to data
  3105. * phase or didn't respond to our ATN.
  3106. * The only safe thing to do is to blow
  3107. * it away with a bus reset.
  3108. */
  3109. found = ahd_reset_channel(ahd, 'A', TRUE);
  3110. printk("%s: Issued Channel %c Bus Reset. "
  3111. "%d SCBs aborted\n", ahd_name(ahd), 'A', found);
  3112. } else {
  3113. /*
  3114. * Leave the selection hardware off in case
  3115. * this abort attempt will affect yet to
  3116. * be sent commands.
  3117. */
  3118. ahd_outb(ahd, SCSISEQ0,
  3119. ahd_inb(ahd, SCSISEQ0) & ~ENSELO);
  3120. ahd_assert_atn(ahd);
  3121. ahd_outb(ahd, MSG_OUT, HOST_MSG);
  3122. if (scb == NULL) {
  3123. ahd_print_devinfo(ahd, &devinfo);
  3124. ahd->msgout_buf[0] = MSG_ABORT_TASK;
  3125. ahd->msgout_len = 1;
  3126. ahd->msgout_index = 0;
  3127. ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
  3128. } else {
  3129. ahd_print_path(ahd, scb);
  3130. scb->flags |= SCB_ABORT;
  3131. }
  3132. printk("Protocol violation %s. Attempting to abort.\n",
  3133. ahd_lookup_phase_entry(curphase)->phasemsg);
  3134. }
  3135. }
  3136. /*
  3137. * Force renegotiation to occur the next time we initiate
  3138. * a command to the current device.
  3139. */
  3140. static void
  3141. ahd_force_renegotiation(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
  3142. {
  3143. struct ahd_initiator_tinfo *targ_info;
  3144. struct ahd_tmode_tstate *tstate;
  3145. #ifdef AHD_DEBUG
  3146. if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
  3147. ahd_print_devinfo(ahd, devinfo);
  3148. printk("Forcing renegotiation\n");
  3149. }
  3150. #endif
  3151. targ_info = ahd_fetch_transinfo(ahd,
  3152. devinfo->channel,
  3153. devinfo->our_scsiid,
  3154. devinfo->target,
  3155. &tstate);
  3156. ahd_update_neg_request(ahd, devinfo, tstate,
  3157. targ_info, AHD_NEG_IF_NON_ASYNC);
  3158. }
  3159. #define AHD_MAX_STEPS 2000
  3160. static void
  3161. ahd_clear_critical_section(struct ahd_softc *ahd)
  3162. {
  3163. ahd_mode_state saved_modes;
  3164. int stepping;
  3165. int steps;
  3166. int first_instr;
  3167. u_int simode0;
  3168. u_int simode1;
  3169. u_int simode3;
  3170. u_int lqimode0;
  3171. u_int lqimode1;
  3172. u_int lqomode0;
  3173. u_int lqomode1;
  3174. if (ahd->num_critical_sections == 0)
  3175. return;
  3176. stepping = FALSE;
  3177. steps = 0;
  3178. first_instr = 0;
  3179. simode0 = 0;
  3180. simode1 = 0;
  3181. simode3 = 0;
  3182. lqimode0 = 0;
  3183. lqimode1 = 0;
  3184. lqomode0 = 0;
  3185. lqomode1 = 0;
  3186. saved_modes = ahd_save_modes(ahd);
  3187. for (;;) {
  3188. struct cs *cs;
  3189. u_int seqaddr;
  3190. u_int i;
  3191. ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
  3192. seqaddr = ahd_inw(ahd, CURADDR);
  3193. cs = ahd->critical_sections;
  3194. for (i = 0; i < ahd->num_critical_sections; i++, cs++) {
  3195. if (cs->begin < seqaddr && cs->end >= seqaddr)
  3196. break;
  3197. }
  3198. if (i == ahd->num_critical_sections)
  3199. break;
  3200. if (steps > AHD_MAX_STEPS) {
  3201. printk("%s: Infinite loop in critical section\n"
  3202. "%s: First Instruction 0x%x now 0x%x\n",
  3203. ahd_name(ahd), ahd_name(ahd), first_instr,
  3204. seqaddr);
  3205. ahd_dump_card_state(ahd);
  3206. panic("critical section loop");
  3207. }
  3208. steps++;
  3209. #ifdef AHD_DEBUG
  3210. if ((ahd_debug & AHD_SHOW_MISC) != 0)
  3211. printk("%s: Single stepping at 0x%x\n", ahd_name(ahd),
  3212. seqaddr);
  3213. #endif
  3214. if (stepping == FALSE) {
  3215. first_instr = seqaddr;
  3216. ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
  3217. simode0 = ahd_inb(ahd, SIMODE0);
  3218. simode3 = ahd_inb(ahd, SIMODE3);
  3219. lqimode0 = ahd_inb(ahd, LQIMODE0);
  3220. lqimode1 = ahd_inb(ahd, LQIMODE1);
  3221. lqomode0 = ahd_inb(ahd, LQOMODE0);
  3222. lqomode1 = ahd_inb(ahd, LQOMODE1);
  3223. ahd_outb(ahd, SIMODE0, 0);
  3224. ahd_outb(ahd, SIMODE3, 0);
  3225. ahd_outb(ahd, LQIMODE0, 0);
  3226. ahd_outb(ahd, LQIMODE1, 0);
  3227. ahd_outb(ahd, LQOMODE0, 0);
  3228. ahd_outb(ahd, LQOMODE1, 0);
  3229. ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
  3230. simode1 = ahd_inb(ahd, SIMODE1);
  3231. /*
  3232. * We don't clear ENBUSFREE. Unfortunately
  3233. * we cannot re-enable busfree detection within
  3234. * the current connection, so we must leave it
  3235. * on while single stepping.
  3236. */
  3237. ahd_outb(ahd, SIMODE1, simode1 & ENBUSFREE);
  3238. ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) | STEP);
  3239. stepping = TRUE;
  3240. }
  3241. ahd_outb(ahd, CLRSINT1, CLRBUSFREE);
  3242. ahd_outb(ahd, CLRINT, CLRSCSIINT);
  3243. ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode);
  3244. ahd_outb(ahd, HCNTRL, ahd->unpause);
  3245. while (!ahd_is_paused(ahd))
  3246. ahd_delay(200);
  3247. ahd_update_modes(ahd);
  3248. }
  3249. if (stepping) {
  3250. ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
  3251. ahd_outb(ahd, SIMODE0, simode0);
  3252. ahd_outb(ahd, SIMODE3, simode3);
  3253. ahd_outb(ahd, LQIMODE0, lqimode0);
  3254. ahd_outb(ahd, LQIMODE1, lqimode1);
  3255. ahd_outb(ahd, LQOMODE0, lqomode0);
  3256. ahd_outb(ahd, LQOMODE1, lqomode1);
  3257. ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
  3258. ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) & ~STEP);
  3259. ahd_outb(ahd, SIMODE1, simode1);
  3260. /*
  3261. * SCSIINT seems to glitch occasionally when
  3262. * the interrupt masks are restored. Clear SCSIINT
  3263. * one more time so that only persistent errors
  3264. * are seen as a real interrupt.
  3265. */
  3266. ahd_outb(ahd, CLRINT, CLRSCSIINT);
  3267. }
  3268. ahd_restore_modes(ahd, saved_modes);
  3269. }
  3270. /*
  3271. * Clear any pending interrupt status.
  3272. */
  3273. static void
  3274. ahd_clear_intstat(struct ahd_softc *ahd)
  3275. {
  3276. AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
  3277. ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
  3278. /* Clear any interrupt conditions this may have caused */
  3279. ahd_outb(ahd, CLRLQIINT0, CLRLQIATNQAS|CLRLQICRCT1|CLRLQICRCT2
  3280. |CLRLQIBADLQT|CLRLQIATNLQ|CLRLQIATNCMD);
  3281. ahd_outb(ahd, CLRLQIINT1, CLRLQIPHASE_LQ|CLRLQIPHASE_NLQ|CLRLIQABORT
  3282. |CLRLQICRCI_LQ|CLRLQICRCI_NLQ|CLRLQIBADLQI
  3283. |CLRLQIOVERI_LQ|CLRLQIOVERI_NLQ|CLRNONPACKREQ);
  3284. ahd_outb(ahd, CLRLQOINT0, CLRLQOTARGSCBPERR|CLRLQOSTOPT2|CLRLQOATNLQ
  3285. |CLRLQOATNPKT|CLRLQOTCRC);
  3286. ahd_outb(ahd, CLRLQOINT1, CLRLQOINITSCBPERR|CLRLQOSTOPI2|CLRLQOBADQAS
  3287. |CLRLQOBUSFREE|CLRLQOPHACHGINPKT);
  3288. if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) {
  3289. ahd_outb(ahd, CLRLQOINT0, 0);
  3290. ahd_outb(ahd, CLRLQOINT1, 0);
  3291. }
  3292. ahd_outb(ahd, CLRSINT3, CLRNTRAMPERR|CLROSRAMPERR);
  3293. ahd_outb(ahd, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI
  3294. |CLRBUSFREE|CLRSCSIPERR|CLRREQINIT);
  3295. ahd_outb(ahd, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO
  3296. |CLRIOERR|CLROVERRUN);
  3297. ahd_outb(ahd, CLRINT, CLRSCSIINT);
  3298. }
  3299. /**************************** Debugging Routines ******************************/
  3300. #ifdef AHD_DEBUG
  3301. uint32_t ahd_debug = AHD_DEBUG_OPTS;
  3302. #endif
  3303. #if 0
  3304. void
  3305. ahd_print_scb(struct scb *scb)
  3306. {
  3307. struct hardware_scb *hscb;
  3308. int i;
  3309. hscb = scb->hscb;
  3310. printk("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n",
  3311. (void *)scb,
  3312. hscb->control,
  3313. hscb->scsiid,
  3314. hscb->lun,
  3315. hscb->cdb_len);
  3316. printk("Shared Data: ");
  3317. for (i = 0; i < sizeof(hscb->shared_data.idata.cdb); i++)
  3318. printk("%#02x", hscb->shared_data.idata.cdb[i]);
  3319. printk(" dataptr:%#x%x datacnt:%#x sgptr:%#x tag:%#x\n",
  3320. (uint32_t)((ahd_le64toh(hscb->dataptr) >> 32) & 0xFFFFFFFF),
  3321. (uint32_t)(ahd_le64toh(hscb->dataptr) & 0xFFFFFFFF),
  3322. ahd_le32toh(hscb->datacnt),
  3323. ahd_le32toh(hscb->sgptr),
  3324. SCB_GET_TAG(scb));
  3325. ahd_dump_sglist(scb);
  3326. }
  3327. #endif /* 0 */
  3328. /************************* Transfer Negotiation *******************************/
  3329. /*
  3330. * Allocate per target mode instance (ID we respond to as a target)
  3331. * transfer negotiation data structures.
  3332. */
  3333. static struct ahd_tmode_tstate *
  3334. ahd_alloc_tstate(struct ahd_softc *ahd, u_int scsi_id, char channel)
  3335. {
  3336. struct ahd_tmode_tstate *master_tstate;
  3337. struct ahd_tmode_tstate *tstate;
  3338. int i;
  3339. master_tstate = ahd->enabled_targets[ahd->our_id];
  3340. if (ahd->enabled_targets[scsi_id] != NULL
  3341. && ahd->enabled_targets[scsi_id] != master_tstate)
  3342. panic("%s: ahd_alloc_tstate - Target already allocated",
  3343. ahd_name(ahd));
  3344. tstate = kmalloc(sizeof(*tstate), GFP_ATOMIC);
  3345. if (tstate == NULL)
  3346. return (NULL);
  3347. /*
  3348. * If we have allocated a master tstate, copy user settings from
  3349. * the master tstate (taken from SRAM or the EEPROM) for this
  3350. * channel, but reset our current and goal settings to async/narrow
  3351. * until an initiator talks to us.
  3352. */
  3353. if (master_tstate != NULL) {
  3354. memcpy(tstate, master_tstate, sizeof(*tstate));
  3355. memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns));
  3356. for (i = 0; i < 16; i++) {
  3357. memset(&tstate->transinfo[i].curr, 0,
  3358. sizeof(tstate->transinfo[i].curr));
  3359. memset(&tstate->transinfo[i].goal, 0,
  3360. sizeof(tstate->transinfo[i].goal));
  3361. }
  3362. } else
  3363. memset(tstate, 0, sizeof(*tstate));
  3364. ahd->enabled_targets[scsi_id] = tstate;
  3365. return (tstate);
  3366. }
  3367. #ifdef AHD_TARGET_MODE
  3368. /*
  3369. * Free per target mode instance (ID we respond to as a target)
  3370. * transfer negotiation data structures.
  3371. */
  3372. static void
  3373. ahd_free_tstate(struct ahd_softc *ahd, u_int scsi_id, char channel, int force)
  3374. {
  3375. struct ahd_tmode_tstate *tstate;
  3376. /*
  3377. * Don't clean up our "master" tstate.
  3378. * It has our default user settings.
  3379. */
  3380. if (scsi_id == ahd->our_id
  3381. && force == FALSE)
  3382. return;
  3383. tstate = ahd->enabled_targets[scsi_id];
  3384. if (tstate != NULL)
  3385. kfree(tstate);
  3386. ahd->enabled_targets[scsi_id] = NULL;
  3387. }
  3388. #endif
  3389. /*
  3390. * Called when we have an active connection to a target on the bus,
  3391. * this function finds the nearest period to the input period limited
  3392. * by the capabilities of the bus connectivity of and sync settings for
  3393. * the target.
  3394. */
  3395. static void
  3396. ahd_devlimited_syncrate(struct ahd_softc *ahd,
  3397. struct ahd_initiator_tinfo *tinfo,
  3398. u_int *period, u_int *ppr_options, role_t role)
  3399. {
  3400. struct ahd_transinfo *transinfo;
  3401. u_int maxsync;
  3402. if ((ahd_inb(ahd, SBLKCTL) & ENAB40) != 0
  3403. && (ahd_inb(ahd, SSTAT2) & EXP_ACTIVE) == 0) {
  3404. maxsync = AHD_SYNCRATE_PACED;
  3405. } else {
  3406. maxsync = AHD_SYNCRATE_ULTRA;
  3407. /* Can't do DT related options on an SE bus */
  3408. *ppr_options &= MSG_EXT_PPR_QAS_REQ;
  3409. }
  3410. /*
  3411. * Never allow a value higher than our current goal
  3412. * period otherwise we may allow a target initiated
  3413. * negotiation to go above the limit as set by the
  3414. * user. In the case of an initiator initiated
  3415. * sync negotiation, we limit based on the user
  3416. * setting. This allows the system to still accept
  3417. * incoming negotiations even if target initiated
  3418. * negotiation is not performed.
  3419. */
  3420. if (role == ROLE_TARGET)
  3421. transinfo = &tinfo->user;
  3422. else
  3423. transinfo = &tinfo->goal;
  3424. *ppr_options &= (transinfo->ppr_options|MSG_EXT_PPR_PCOMP_EN);
  3425. if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) {
  3426. maxsync = max(maxsync, (u_int)AHD_SYNCRATE_ULTRA2);
  3427. *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
  3428. }
  3429. if (transinfo->period == 0) {
  3430. *period = 0;
  3431. *ppr_options = 0;
  3432. } else {
  3433. *period = max(*period, (u_int)transinfo->period);
  3434. ahd_find_syncrate(ahd, period, ppr_options, maxsync);
  3435. }
  3436. }
  3437. /*
  3438. * Look up the valid period to SCSIRATE conversion in our table.
  3439. * Return the period and offset that should be sent to the target
  3440. * if this was the beginning of an SDTR.
  3441. */
  3442. void
  3443. ahd_find_syncrate(struct ahd_softc *ahd, u_int *period,
  3444. u_int *ppr_options, u_int maxsync)
  3445. {
  3446. if (*period < maxsync)
  3447. *period = maxsync;
  3448. if ((*ppr_options & MSG_EXT_PPR_DT_REQ) != 0
  3449. && *period > AHD_SYNCRATE_MIN_DT)
  3450. *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
  3451. if (*period > AHD_SYNCRATE_MIN)
  3452. *period = 0;
  3453. /* Honor PPR option conformance rules. */
  3454. if (*period > AHD_SYNCRATE_PACED)
  3455. *ppr_options &= ~MSG_EXT_PPR_RTI;
  3456. if ((*ppr_options & MSG_EXT_PPR_IU_REQ) == 0)
  3457. *ppr_options &= (MSG_EXT_PPR_DT_REQ|MSG_EXT_PPR_QAS_REQ);
  3458. if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0)
  3459. *ppr_options &= MSG_EXT_PPR_QAS_REQ;
  3460. /* Skip all PACED only entries if IU is not available */
  3461. if ((*ppr_options & MSG_EXT_PPR_IU_REQ) == 0
  3462. && *period < AHD_SYNCRATE_DT)
  3463. *period = AHD_SYNCRATE_DT;
  3464. /* Skip all DT only entries if DT is not available */
  3465. if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0
  3466. && *period < AHD_SYNCRATE_ULTRA2)
  3467. *period = AHD_SYNCRATE_ULTRA2;
  3468. }
  3469. /*
  3470. * Truncate the given synchronous offset to a value the
  3471. * current adapter type and syncrate are capable of.
  3472. */
  3473. static void
  3474. ahd_validate_offset(struct ahd_softc *ahd,
  3475. struct ahd_initiator_tinfo *tinfo,
  3476. u_int period, u_int *offset, int wide,
  3477. role_t role)
  3478. {
  3479. u_int maxoffset;
  3480. /* Limit offset to what we can do */
  3481. if (period == 0)
  3482. maxoffset = 0;
  3483. else if (period <= AHD_SYNCRATE_PACED) {
  3484. if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0)
  3485. maxoffset = MAX_OFFSET_PACED_BUG;
  3486. else
  3487. maxoffset = MAX_OFFSET_PACED;
  3488. } else
  3489. maxoffset = MAX_OFFSET_NON_PACED;
  3490. *offset = min(*offset, maxoffset);
  3491. if (tinfo != NULL) {
  3492. if (role == ROLE_TARGET)
  3493. *offset = min(*offset, (u_int)tinfo->user.offset);
  3494. else
  3495. *offset = min(*offset, (u_int)tinfo->goal.offset);
  3496. }
  3497. }
  3498. /*
  3499. * Truncate the given transfer width parameter to a value the
  3500. * current adapter type is capable of.
  3501. */
  3502. static void
  3503. ahd_validate_width(struct ahd_softc *ahd, struct ahd_initiator_tinfo *tinfo,
  3504. u_int *bus_width, role_t role)
  3505. {
  3506. switch (*bus_width) {
  3507. default:
  3508. if (ahd->features & AHD_WIDE) {
  3509. /* Respond Wide */
  3510. *bus_width = MSG_EXT_WDTR_BUS_16_BIT;
  3511. break;
  3512. }
  3513. /* FALLTHROUGH */
  3514. case MSG_EXT_WDTR_BUS_8_BIT:
  3515. *bus_width = MSG_EXT_WDTR_BUS_8_BIT;
  3516. break;
  3517. }
  3518. if (tinfo != NULL) {
  3519. if (role == ROLE_TARGET)
  3520. *bus_width = min((u_int)tinfo->user.width, *bus_width);
  3521. else
  3522. *bus_width = min((u_int)tinfo->goal.width, *bus_width);
  3523. }
  3524. }
  3525. /*
  3526. * Update the bitmask of targets for which the controller should
  3527. * negotiate with at the next convenient opportunity. This currently
  3528. * means the next time we send the initial identify messages for
  3529. * a new transaction.
  3530. */
  3531. int
  3532. ahd_update_neg_request(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
  3533. struct ahd_tmode_tstate *tstate,
  3534. struct ahd_initiator_tinfo *tinfo, ahd_neg_type neg_type)
  3535. {
  3536. u_int auto_negotiate_orig;
  3537. auto_negotiate_orig = tstate->auto_negotiate;
  3538. if (neg_type == AHD_NEG_ALWAYS) {
  3539. /*
  3540. * Force our "current" settings to be
  3541. * unknown so that unless a bus reset
  3542. * occurs the need to renegotiate is
  3543. * recorded persistently.
  3544. */
  3545. if ((ahd->features & AHD_WIDE) != 0)
  3546. tinfo->curr.width = AHD_WIDTH_UNKNOWN;
  3547. tinfo->curr.period = AHD_PERIOD_UNKNOWN;
  3548. tinfo->curr.offset = AHD_OFFSET_UNKNOWN;
  3549. }
  3550. if (tinfo->curr.period != tinfo->goal.period
  3551. || tinfo->curr.width != tinfo->goal.width
  3552. || tinfo->curr.offset != tinfo->goal.offset
  3553. || tinfo->curr.ppr_options != tinfo->goal.ppr_options
  3554. || (neg_type == AHD_NEG_IF_NON_ASYNC
  3555. && (tinfo->goal.offset != 0
  3556. || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT
  3557. || tinfo->goal.ppr_options != 0)))
  3558. tstate->auto_negotiate |= devinfo->target_mask;
  3559. else
  3560. tstate->auto_negotiate &= ~devinfo->target_mask;
  3561. return (auto_negotiate_orig != tstate->auto_negotiate);
  3562. }
  3563. /*
  3564. * Update the user/goal/curr tables of synchronous negotiation
  3565. * parameters as well as, in the case of a current or active update,
  3566. * any data structures on the host controller. In the case of an
  3567. * active update, the specified target is currently talking to us on
  3568. * the bus, so the transfer parameter update must take effect
  3569. * immediately.
  3570. */
  3571. void
  3572. ahd_set_syncrate(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
  3573. u_int period, u_int offset, u_int ppr_options,
  3574. u_int type, int paused)
  3575. {
  3576. struct ahd_initiator_tinfo *tinfo;
  3577. struct ahd_tmode_tstate *tstate;
  3578. u_int old_period;
  3579. u_int old_offset;
  3580. u_int old_ppr;
  3581. int active;
  3582. int update_needed;
  3583. active = (type & AHD_TRANS_ACTIVE) == AHD_TRANS_ACTIVE;
  3584. update_needed = 0;
  3585. if (period == 0 || offset == 0) {
  3586. period = 0;
  3587. offset = 0;
  3588. }
  3589. tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid,
  3590. devinfo->target, &tstate);
  3591. if ((type & AHD_TRANS_USER) != 0) {
  3592. tinfo->user.period = period;
  3593. tinfo->user.offset = offset;
  3594. tinfo->user.ppr_options = ppr_options;
  3595. }
  3596. if ((type & AHD_TRANS_GOAL) != 0) {
  3597. tinfo->goal.period = period;
  3598. tinfo->goal.offset = offset;
  3599. tinfo->goal.ppr_options = ppr_options;
  3600. }
  3601. old_period = tinfo->curr.period;
  3602. old_offset = tinfo->curr.offset;
  3603. old_ppr = tinfo->curr.ppr_options;
  3604. if ((type & AHD_TRANS_CUR) != 0
  3605. && (old_period != period
  3606. || old_offset != offset
  3607. || old_ppr != ppr_options)) {
  3608. update_needed++;
  3609. tinfo->curr.period = period;
  3610. tinfo->curr.offset = offset;
  3611. tinfo->curr.ppr_options = ppr_options;
  3612. ahd_send_async(ahd, devinfo->channel, devinfo->target,
  3613. CAM_LUN_WILDCARD, AC_TRANSFER_NEG);
  3614. if (bootverbose) {
  3615. if (offset != 0) {
  3616. int options;
  3617. printk("%s: target %d synchronous with "
  3618. "period = 0x%x, offset = 0x%x",
  3619. ahd_name(ahd), devinfo->target,
  3620. period, offset);
  3621. options = 0;
  3622. if ((ppr_options & MSG_EXT_PPR_RD_STRM) != 0) {
  3623. printk("(RDSTRM");
  3624. options++;
  3625. }
  3626. if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0) {
  3627. printk("%s", options ? "|DT" : "(DT");
  3628. options++;
  3629. }
  3630. if ((ppr_options & MSG_EXT_PPR_IU_REQ) != 0) {
  3631. printk("%s", options ? "|IU" : "(IU");
  3632. options++;
  3633. }
  3634. if ((ppr_options & MSG_EXT_PPR_RTI) != 0) {
  3635. printk("%s", options ? "|RTI" : "(RTI");
  3636. options++;
  3637. }
  3638. if ((ppr_options & MSG_EXT_PPR_QAS_REQ) != 0) {
  3639. printk("%s", options ? "|QAS" : "(QAS");
  3640. options++;
  3641. }
  3642. if (options != 0)
  3643. printk(")\n");
  3644. else
  3645. printk("\n");
  3646. } else {
  3647. printk("%s: target %d using "
  3648. "asynchronous transfers%s\n",
  3649. ahd_name(ahd), devinfo->target,
  3650. (ppr_options & MSG_EXT_PPR_QAS_REQ) != 0
  3651. ? "(QAS)" : "");
  3652. }
  3653. }
  3654. }
  3655. /*
  3656. * Always refresh the neg-table to handle the case of the
  3657. * sequencer setting the ENATNO bit for a MK_MESSAGE request.
  3658. * We will always renegotiate in that case if this is a
  3659. * packetized request. Also manage the busfree expected flag
  3660. * from this common routine so that we catch changes due to
  3661. * WDTR or SDTR messages.
  3662. */
  3663. if ((type & AHD_TRANS_CUR) != 0) {
  3664. if (!paused)
  3665. ahd_pause(ahd);
  3666. ahd_update_neg_table(ahd, devinfo, &tinfo->curr);
  3667. if (!paused)
  3668. ahd_unpause(ahd);
  3669. if (ahd->msg_type != MSG_TYPE_NONE) {
  3670. if ((old_ppr & MSG_EXT_PPR_IU_REQ)
  3671. != (ppr_options & MSG_EXT_PPR_IU_REQ)) {
  3672. #ifdef AHD_DEBUG
  3673. if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
  3674. ahd_print_devinfo(ahd, devinfo);
  3675. printk("Expecting IU Change busfree\n");
  3676. }
  3677. #endif
  3678. ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE
  3679. | MSG_FLAG_IU_REQ_CHANGED;
  3680. }
  3681. if ((old_ppr & MSG_EXT_PPR_IU_REQ) != 0) {
  3682. #ifdef AHD_DEBUG
  3683. if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
  3684. printk("PPR with IU_REQ outstanding\n");
  3685. #endif
  3686. ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE;
  3687. }
  3688. }
  3689. }
  3690. update_needed += ahd_update_neg_request(ahd, devinfo, tstate,
  3691. tinfo, AHD_NEG_TO_GOAL);
  3692. if (update_needed && active)
  3693. ahd_update_pending_scbs(ahd);
  3694. }
  3695. /*
  3696. * Update the user/goal/curr tables of wide negotiation
  3697. * parameters as well as, in the case of a current or active update,
  3698. * any data structures on the host controller. In the case of an
  3699. * active update, the specified target is currently talking to us on
  3700. * the bus, so the transfer parameter update must take effect
  3701. * immediately.
  3702. */
  3703. void
  3704. ahd_set_width(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
  3705. u_int width, u_int type, int paused)
  3706. {
  3707. struct ahd_initiator_tinfo *tinfo;
  3708. struct ahd_tmode_tstate *tstate;
  3709. u_int oldwidth;
  3710. int active;
  3711. int update_needed;
  3712. active = (type & AHD_TRANS_ACTIVE) == AHD_TRANS_ACTIVE;
  3713. update_needed = 0;
  3714. tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid,
  3715. devinfo->target, &tstate);
  3716. if ((type & AHD_TRANS_USER) != 0)
  3717. tinfo->user.width = width;
  3718. if ((type & AHD_TRANS_GOAL) != 0)
  3719. tinfo->goal.width = width;
  3720. oldwidth = tinfo->curr.width;
  3721. if ((type & AHD_TRANS_CUR) != 0 && oldwidth != width) {
  3722. update_needed++;
  3723. tinfo->curr.width = width;
  3724. ahd_send_async(ahd, devinfo->channel, devinfo->target,
  3725. CAM_LUN_WILDCARD, AC_TRANSFER_NEG);
  3726. if (bootverbose) {
  3727. printk("%s: target %d using %dbit transfers\n",
  3728. ahd_name(ahd), devinfo->target,
  3729. 8 * (0x01 << width));
  3730. }
  3731. }
  3732. if ((type & AHD_TRANS_CUR) != 0) {
  3733. if (!paused)
  3734. ahd_pause(ahd);
  3735. ahd_update_neg_table(ahd, devinfo, &tinfo->curr);
  3736. if (!paused)
  3737. ahd_unpause(ahd);
  3738. }
  3739. update_needed += ahd_update_neg_request(ahd, devinfo, tstate,
  3740. tinfo, AHD_NEG_TO_GOAL);
  3741. if (update_needed && active)
  3742. ahd_update_pending_scbs(ahd);
  3743. }
  3744. /*
  3745. * Update the current state of tagged queuing for a given target.
  3746. */
  3747. static void
  3748. ahd_set_tags(struct ahd_softc *ahd, struct scsi_cmnd *cmd,
  3749. struct ahd_devinfo *devinfo, ahd_queue_alg alg)
  3750. {
  3751. struct scsi_device *sdev = cmd->device;
  3752. ahd_platform_set_tags(ahd, sdev, devinfo, alg);
  3753. ahd_send_async(ahd, devinfo->channel, devinfo->target,
  3754. devinfo->lun, AC_TRANSFER_NEG);
  3755. }
  3756. static void
  3757. ahd_update_neg_table(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
  3758. struct ahd_transinfo *tinfo)
  3759. {
  3760. ahd_mode_state saved_modes;
  3761. u_int period;
  3762. u_int ppr_opts;
  3763. u_int con_opts;
  3764. u_int offset;
  3765. u_int saved_negoaddr;
  3766. uint8_t iocell_opts[sizeof(ahd->iocell_opts)];
  3767. saved_modes = ahd_save_modes(ahd);
  3768. ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
  3769. saved_negoaddr = ahd_inb(ahd, NEGOADDR);
  3770. ahd_outb(ahd, NEGOADDR, devinfo->target);
  3771. period = tinfo->period;
  3772. offset = tinfo->offset;
  3773. memcpy(iocell_opts, ahd->iocell_opts, sizeof(ahd->iocell_opts));
  3774. ppr_opts = tinfo->ppr_options & (MSG_EXT_PPR_QAS_REQ|MSG_EXT_PPR_DT_REQ
  3775. |MSG_EXT_PPR_IU_REQ|MSG_EXT_PPR_RTI);
  3776. con_opts = 0;
  3777. if (period == 0)
  3778. period = AHD_SYNCRATE_ASYNC;
  3779. if (period == AHD_SYNCRATE_160) {
  3780. if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0) {
  3781. /*
  3782. * When the SPI4 spec was finalized, PACE transfers
  3783. * was not made a configurable option in the PPR
  3784. * message. Instead it is assumed to be enabled for
  3785. * any syncrate faster than 80MHz. Nevertheless,
  3786. * Harpoon2A4 allows this to be configurable.
  3787. *
  3788. * Harpoon2A4 also assumes at most 2 data bytes per
  3789. * negotiated REQ/ACK offset. Paced transfers take
  3790. * 4, so we must adjust our offset.
  3791. */
  3792. ppr_opts |= PPROPT_PACE;
  3793. offset *= 2;
  3794. /*
  3795. * Harpoon2A assumed that there would be a
  3796. * fallback rate between 160MHz and 80MHz,
  3797. * so 7 is used as the period factor rather
  3798. * than 8 for 160MHz.
  3799. */
  3800. period = AHD_SYNCRATE_REVA_160;
  3801. }
  3802. if ((tinfo->ppr_options & MSG_EXT_PPR_PCOMP_EN) == 0)
  3803. iocell_opts[AHD_PRECOMP_SLEW_INDEX] &=
  3804. ~AHD_PRECOMP_MASK;
  3805. } else {
  3806. /*
  3807. * Precomp should be disabled for non-paced transfers.
  3808. */
  3809. iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_PRECOMP_MASK;
  3810. if ((ahd->features & AHD_NEW_IOCELL_OPTS) != 0
  3811. && (ppr_opts & MSG_EXT_PPR_DT_REQ) != 0
  3812. && (ppr_opts & MSG_EXT_PPR_IU_REQ) == 0) {
  3813. /*
  3814. * Slow down our CRC interval to be
  3815. * compatible with non-packetized
  3816. * U160 devices that can't handle a
  3817. * CRC at full speed.
  3818. */
  3819. con_opts |= ENSLOWCRC;
  3820. }
  3821. if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0) {
  3822. /*
  3823. * On H2A4, revert to a slower slewrate
  3824. * on non-paced transfers.
  3825. */
  3826. iocell_opts[AHD_PRECOMP_SLEW_INDEX] &=
  3827. ~AHD_SLEWRATE_MASK;
  3828. }
  3829. }
  3830. ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_PRECOMP_SLEW);
  3831. ahd_outb(ahd, ANNEXDAT, iocell_opts[AHD_PRECOMP_SLEW_INDEX]);
  3832. ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_AMPLITUDE);
  3833. ahd_outb(ahd, ANNEXDAT, iocell_opts[AHD_AMPLITUDE_INDEX]);
  3834. ahd_outb(ahd, NEGPERIOD, period);
  3835. ahd_outb(ahd, NEGPPROPTS, ppr_opts);
  3836. ahd_outb(ahd, NEGOFFSET, offset);
  3837. if (tinfo->width == MSG_EXT_WDTR_BUS_16_BIT)
  3838. con_opts |= WIDEXFER;
  3839. /*
  3840. * Slow down our CRC interval to be
  3841. * compatible with packetized U320 devices
  3842. * that can't handle a CRC at full speed
  3843. */
  3844. if (ahd->features & AHD_AIC79XXB_SLOWCRC) {
  3845. con_opts |= ENSLOWCRC;
  3846. }
  3847. /*
  3848. * During packetized transfers, the target will
  3849. * give us the opportunity to send command packets
  3850. * without us asserting attention.
  3851. */
  3852. if ((tinfo->ppr_options & MSG_EXT_PPR_IU_REQ) == 0)
  3853. con_opts |= ENAUTOATNO;
  3854. ahd_outb(ahd, NEGCONOPTS, con_opts);
  3855. ahd_outb(ahd, NEGOADDR, saved_negoaddr);
  3856. ahd_restore_modes(ahd, saved_modes);
  3857. }
  3858. /*
  3859. * When the transfer settings for a connection change, setup for
  3860. * negotiation in pending SCBs to effect the change as quickly as
  3861. * possible. We also cancel any negotiations that are scheduled
  3862. * for inflight SCBs that have not been started yet.
  3863. */
  3864. static void
  3865. ahd_update_pending_scbs(struct ahd_softc *ahd)
  3866. {
  3867. struct scb *pending_scb;
  3868. int pending_scb_count;
  3869. int paused;
  3870. u_int saved_scbptr;
  3871. ahd_mode_state saved_modes;
  3872. /*
  3873. * Traverse the pending SCB list and ensure that all of the
  3874. * SCBs there have the proper settings. We can only safely
  3875. * clear the negotiation required flag (setting requires the
  3876. * execution queue to be modified) and this is only possible
  3877. * if we are not already attempting to select out for this
  3878. * SCB. For this reason, all callers only call this routine
  3879. * if we are changing the negotiation settings for the currently
  3880. * active transaction on the bus.
  3881. */
  3882. pending_scb_count = 0;
  3883. LIST_FOREACH(pending_scb, &ahd->pending_scbs, pending_links) {
  3884. struct ahd_devinfo devinfo;
  3885. struct ahd_initiator_tinfo *tinfo;
  3886. struct ahd_tmode_tstate *tstate;
  3887. ahd_scb_devinfo(ahd, &devinfo, pending_scb);
  3888. tinfo = ahd_fetch_transinfo(ahd, devinfo.channel,
  3889. devinfo.our_scsiid,
  3890. devinfo.target, &tstate);
  3891. if ((tstate->auto_negotiate & devinfo.target_mask) == 0
  3892. && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) {
  3893. pending_scb->flags &= ~SCB_AUTO_NEGOTIATE;
  3894. pending_scb->hscb->control &= ~MK_MESSAGE;
  3895. }
  3896. ahd_sync_scb(ahd, pending_scb,
  3897. BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
  3898. pending_scb_count++;
  3899. }
  3900. if (pending_scb_count == 0)
  3901. return;
  3902. if (ahd_is_paused(ahd)) {
  3903. paused = 1;
  3904. } else {
  3905. paused = 0;
  3906. ahd_pause(ahd);
  3907. }
  3908. /*
  3909. * Force the sequencer to reinitialize the selection for
  3910. * the command at the head of the execution queue if it
  3911. * has already been setup. The negotiation changes may
  3912. * effect whether we select-out with ATN. It is only
  3913. * safe to clear ENSELO when the bus is not free and no
  3914. * selection is in progres or completed.
  3915. */
  3916. saved_modes = ahd_save_modes(ahd);
  3917. ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
  3918. if ((ahd_inb(ahd, SCSISIGI) & BSYI) != 0
  3919. && (ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) == 0)
  3920. ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO);
  3921. saved_scbptr = ahd_get_scbptr(ahd);
  3922. /* Ensure that the hscbs down on the card match the new information */
  3923. LIST_FOREACH(pending_scb, &ahd->pending_scbs, pending_links) {
  3924. u_int scb_tag;
  3925. u_int control;
  3926. scb_tag = SCB_GET_TAG(pending_scb);
  3927. ahd_set_scbptr(ahd, scb_tag);
  3928. control = ahd_inb_scbram(ahd, SCB_CONTROL);
  3929. control &= ~MK_MESSAGE;
  3930. control |= pending_scb->hscb->control & MK_MESSAGE;
  3931. ahd_outb(ahd, SCB_CONTROL, control);
  3932. }
  3933. ahd_set_scbptr(ahd, saved_scbptr);
  3934. ahd_restore_modes(ahd, saved_modes);
  3935. if (paused == 0)
  3936. ahd_unpause(ahd);
  3937. }
  3938. /**************************** Pathing Information *****************************/
  3939. static void
  3940. ahd_fetch_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
  3941. {
  3942. ahd_mode_state saved_modes;
  3943. u_int saved_scsiid;
  3944. role_t role;
  3945. int our_id;
  3946. saved_modes = ahd_save_modes(ahd);
  3947. ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
  3948. if (ahd_inb(ahd, SSTAT0) & TARGET)
  3949. role = ROLE_TARGET;
  3950. else
  3951. role = ROLE_INITIATOR;
  3952. if (role == ROLE_TARGET
  3953. && (ahd_inb(ahd, SEQ_FLAGS) & CMDPHASE_PENDING) != 0) {
  3954. /* We were selected, so pull our id from TARGIDIN */
  3955. our_id = ahd_inb(ahd, TARGIDIN) & OID;
  3956. } else if (role == ROLE_TARGET)
  3957. our_id = ahd_inb(ahd, TOWNID);
  3958. else
  3959. our_id = ahd_inb(ahd, IOWNID);
  3960. saved_scsiid = ahd_inb(ahd, SAVED_SCSIID);
  3961. ahd_compile_devinfo(devinfo,
  3962. our_id,
  3963. SCSIID_TARGET(ahd, saved_scsiid),
  3964. ahd_inb(ahd, SAVED_LUN),
  3965. SCSIID_CHANNEL(ahd, saved_scsiid),
  3966. role);
  3967. ahd_restore_modes(ahd, saved_modes);
  3968. }
  3969. void
  3970. ahd_print_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
  3971. {
  3972. printk("%s:%c:%d:%d: ", ahd_name(ahd), 'A',
  3973. devinfo->target, devinfo->lun);
  3974. }
  3975. static const struct ahd_phase_table_entry*
  3976. ahd_lookup_phase_entry(int phase)
  3977. {
  3978. const struct ahd_phase_table_entry *entry;
  3979. const struct ahd_phase_table_entry *last_entry;
  3980. /*
  3981. * num_phases doesn't include the default entry which
  3982. * will be returned if the phase doesn't match.
  3983. */
  3984. last_entry = &ahd_phase_table[num_phases];
  3985. for (entry = ahd_phase_table; entry < last_entry; entry++) {
  3986. if (phase == entry->phase)
  3987. break;
  3988. }
  3989. return (entry);
  3990. }
  3991. void
  3992. ahd_compile_devinfo(struct ahd_devinfo *devinfo, u_int our_id, u_int target,
  3993. u_int lun, char channel, role_t role)
  3994. {
  3995. devinfo->our_scsiid = our_id;
  3996. devinfo->target = target;
  3997. devinfo->lun = lun;
  3998. devinfo->target_offset = target;
  3999. devinfo->channel = channel;
  4000. devinfo->role = role;
  4001. if (channel == 'B')
  4002. devinfo->target_offset += 8;
  4003. devinfo->target_mask = (0x01 << devinfo->target_offset);
  4004. }
  4005. static void
  4006. ahd_scb_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
  4007. struct scb *scb)
  4008. {
  4009. role_t role;
  4010. int our_id;
  4011. our_id = SCSIID_OUR_ID(scb->hscb->scsiid);
  4012. role = ROLE_INITIATOR;
  4013. if ((scb->hscb->control & TARGET_SCB) != 0)
  4014. role = ROLE_TARGET;
  4015. ahd_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahd, scb),
  4016. SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahd, scb), role);
  4017. }
  4018. /************************ Message Phase Processing ****************************/
  4019. /*
  4020. * When an initiator transaction with the MK_MESSAGE flag either reconnects
  4021. * or enters the initial message out phase, we are interrupted. Fill our
  4022. * outgoing message buffer with the appropriate message and beging handing
  4023. * the message phase(s) manually.
  4024. */
  4025. static void
  4026. ahd_setup_initiator_msgout(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
  4027. struct scb *scb)
  4028. {
  4029. /*
  4030. * To facilitate adding multiple messages together,
  4031. * each routine should increment the index and len
  4032. * variables instead of setting them explicitly.
  4033. */
  4034. ahd->msgout_index = 0;
  4035. ahd->msgout_len = 0;
  4036. if (ahd_currently_packetized(ahd))
  4037. ahd->msg_flags |= MSG_FLAG_PACKETIZED;
  4038. if (ahd->send_msg_perror
  4039. && ahd_inb(ahd, MSG_OUT) == HOST_MSG) {
  4040. ahd->msgout_buf[ahd->msgout_index++] = ahd->send_msg_perror;
  4041. ahd->msgout_len++;
  4042. ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
  4043. #ifdef AHD_DEBUG
  4044. if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
  4045. printk("Setting up for Parity Error delivery\n");
  4046. #endif
  4047. return;
  4048. } else if (scb == NULL) {
  4049. printk("%s: WARNING. No pending message for "
  4050. "I_T msgin. Issuing NO-OP\n", ahd_name(ahd));
  4051. ahd->msgout_buf[ahd->msgout_index++] = MSG_NOOP;
  4052. ahd->msgout_len++;
  4053. ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
  4054. return;
  4055. }
  4056. if ((scb->flags & SCB_DEVICE_RESET) == 0
  4057. && (scb->flags & SCB_PACKETIZED) == 0
  4058. && ahd_inb(ahd, MSG_OUT) == MSG_IDENTIFYFLAG) {
  4059. u_int identify_msg;
  4060. identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb);
  4061. if ((scb->hscb->control & DISCENB) != 0)
  4062. identify_msg |= MSG_IDENTIFY_DISCFLAG;
  4063. ahd->msgout_buf[ahd->msgout_index++] = identify_msg;
  4064. ahd->msgout_len++;
  4065. if ((scb->hscb->control & TAG_ENB) != 0) {
  4066. ahd->msgout_buf[ahd->msgout_index++] =
  4067. scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE);
  4068. ahd->msgout_buf[ahd->msgout_index++] = SCB_GET_TAG(scb);
  4069. ahd->msgout_len += 2;
  4070. }
  4071. }
  4072. if (scb->flags & SCB_DEVICE_RESET) {
  4073. ahd->msgout_buf[ahd->msgout_index++] = MSG_BUS_DEV_RESET;
  4074. ahd->msgout_len++;
  4075. ahd_print_path(ahd, scb);
  4076. printk("Bus Device Reset Message Sent\n");
  4077. /*
  4078. * Clear our selection hardware in advance of
  4079. * the busfree. We may have an entry in the waiting
  4080. * Q for this target, and we don't want to go about
  4081. * selecting while we handle the busfree and blow it
  4082. * away.
  4083. */
  4084. ahd_outb(ahd, SCSISEQ0, 0);
  4085. } else if ((scb->flags & SCB_ABORT) != 0) {
  4086. if ((scb->hscb->control & TAG_ENB) != 0) {
  4087. ahd->msgout_buf[ahd->msgout_index++] = MSG_ABORT_TAG;
  4088. } else {
  4089. ahd->msgout_buf[ahd->msgout_index++] = MSG_ABORT;
  4090. }
  4091. ahd->msgout_len++;
  4092. ahd_print_path(ahd, scb);
  4093. printk("Abort%s Message Sent\n",
  4094. (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : "");
  4095. /*
  4096. * Clear our selection hardware in advance of
  4097. * the busfree. We may have an entry in the waiting
  4098. * Q for this target, and we don't want to go about
  4099. * selecting while we handle the busfree and blow it
  4100. * away.
  4101. */
  4102. ahd_outb(ahd, SCSISEQ0, 0);
  4103. } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) {
  4104. ahd_build_transfer_msg(ahd, devinfo);
  4105. /*
  4106. * Clear our selection hardware in advance of potential
  4107. * PPR IU status change busfree. We may have an entry in
  4108. * the waiting Q for this target, and we don't want to go
  4109. * about selecting while we handle the busfree and blow
  4110. * it away.
  4111. */
  4112. ahd_outb(ahd, SCSISEQ0, 0);
  4113. } else {
  4114. printk("ahd_intr: AWAITING_MSG for an SCB that "
  4115. "does not have a waiting message\n");
  4116. printk("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid,
  4117. devinfo->target_mask);
  4118. panic("SCB = %d, SCB Control = %x:%x, MSG_OUT = %x "
  4119. "SCB flags = %x", SCB_GET_TAG(scb), scb->hscb->control,
  4120. ahd_inb_scbram(ahd, SCB_CONTROL), ahd_inb(ahd, MSG_OUT),
  4121. scb->flags);
  4122. }
  4123. /*
  4124. * Clear the MK_MESSAGE flag from the SCB so we aren't
  4125. * asked to send this message again.
  4126. */
  4127. ahd_outb(ahd, SCB_CONTROL,
  4128. ahd_inb_scbram(ahd, SCB_CONTROL) & ~MK_MESSAGE);
  4129. scb->hscb->control &= ~MK_MESSAGE;
  4130. ahd->msgout_index = 0;
  4131. ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
  4132. }
  4133. /*
  4134. * Build an appropriate transfer negotiation message for the
  4135. * currently active target.
  4136. */
  4137. static void
  4138. ahd_build_transfer_msg(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
  4139. {
  4140. /*
  4141. * We need to initiate transfer negotiations.
  4142. * If our current and goal settings are identical,
  4143. * we want to renegotiate due to a check condition.
  4144. */
  4145. struct ahd_initiator_tinfo *tinfo;
  4146. struct ahd_tmode_tstate *tstate;
  4147. int dowide;
  4148. int dosync;
  4149. int doppr;
  4150. u_int period;
  4151. u_int ppr_options;
  4152. u_int offset;
  4153. tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid,
  4154. devinfo->target, &tstate);
  4155. /*
  4156. * Filter our period based on the current connection.
  4157. * If we can't perform DT transfers on this segment (not in LVD
  4158. * mode for instance), then our decision to issue a PPR message
  4159. * may change.
  4160. */
  4161. period = tinfo->goal.period;
  4162. offset = tinfo->goal.offset;
  4163. ppr_options = tinfo->goal.ppr_options;
  4164. /* Target initiated PPR is not allowed in the SCSI spec */
  4165. if (devinfo->role == ROLE_TARGET)
  4166. ppr_options = 0;
  4167. ahd_devlimited_syncrate(ahd, tinfo, &period,
  4168. &ppr_options, devinfo->role);
  4169. dowide = tinfo->curr.width != tinfo->goal.width;
  4170. dosync = tinfo->curr.offset != offset || tinfo->curr.period != period;
  4171. /*
  4172. * Only use PPR if we have options that need it, even if the device
  4173. * claims to support it. There might be an expander in the way
  4174. * that doesn't.
  4175. */
  4176. doppr = ppr_options != 0;
  4177. if (!dowide && !dosync && !doppr) {
  4178. dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT;
  4179. dosync = tinfo->goal.offset != 0;
  4180. }
  4181. if (!dowide && !dosync && !doppr) {
  4182. /*
  4183. * Force async with a WDTR message if we have a wide bus,
  4184. * or just issue an SDTR with a 0 offset.
  4185. */
  4186. if ((ahd->features & AHD_WIDE) != 0)
  4187. dowide = 1;
  4188. else
  4189. dosync = 1;
  4190. if (bootverbose) {
  4191. ahd_print_devinfo(ahd, devinfo);
  4192. printk("Ensuring async\n");
  4193. }
  4194. }
  4195. /* Target initiated PPR is not allowed in the SCSI spec */
  4196. if (devinfo->role == ROLE_TARGET)
  4197. doppr = 0;
  4198. /*
  4199. * Both the PPR message and SDTR message require the
  4200. * goal syncrate to be limited to what the target device
  4201. * is capable of handling (based on whether an LVD->SE
  4202. * expander is on the bus), so combine these two cases.
  4203. * Regardless, guarantee that if we are using WDTR and SDTR
  4204. * messages that WDTR comes first.
  4205. */
  4206. if (doppr || (dosync && !dowide)) {
  4207. offset = tinfo->goal.offset;
  4208. ahd_validate_offset(ahd, tinfo, period, &offset,
  4209. doppr ? tinfo->goal.width
  4210. : tinfo->curr.width,
  4211. devinfo->role);
  4212. if (doppr) {
  4213. ahd_construct_ppr(ahd, devinfo, period, offset,
  4214. tinfo->goal.width, ppr_options);
  4215. } else {
  4216. ahd_construct_sdtr(ahd, devinfo, period, offset);
  4217. }
  4218. } else {
  4219. ahd_construct_wdtr(ahd, devinfo, tinfo->goal.width);
  4220. }
  4221. }
  4222. /*
  4223. * Build a synchronous negotiation message in our message
  4224. * buffer based on the input parameters.
  4225. */
  4226. static void
  4227. ahd_construct_sdtr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
  4228. u_int period, u_int offset)
  4229. {
  4230. if (offset == 0)
  4231. period = AHD_ASYNC_XFER_PERIOD;
  4232. ahd->msgout_index += spi_populate_sync_msg(
  4233. ahd->msgout_buf + ahd->msgout_index, period, offset);
  4234. ahd->msgout_len += 5;
  4235. if (bootverbose) {
  4236. printk("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n",
  4237. ahd_name(ahd), devinfo->channel, devinfo->target,
  4238. devinfo->lun, period, offset);
  4239. }
  4240. }
  4241. /*
  4242. * Build a wide negotiateion message in our message
  4243. * buffer based on the input parameters.
  4244. */
  4245. static void
  4246. ahd_construct_wdtr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
  4247. u_int bus_width)
  4248. {
  4249. ahd->msgout_index += spi_populate_width_msg(
  4250. ahd->msgout_buf + ahd->msgout_index, bus_width);
  4251. ahd->msgout_len += 4;
  4252. if (bootverbose) {
  4253. printk("(%s:%c:%d:%d): Sending WDTR %x\n",
  4254. ahd_name(ahd), devinfo->channel, devinfo->target,
  4255. devinfo->lun, bus_width);
  4256. }
  4257. }
  4258. /*
  4259. * Build a parallel protocol request message in our message
  4260. * buffer based on the input parameters.
  4261. */
  4262. static void
  4263. ahd_construct_ppr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
  4264. u_int period, u_int offset, u_int bus_width,
  4265. u_int ppr_options)
  4266. {
  4267. /*
  4268. * Always request precompensation from
  4269. * the other target if we are running
  4270. * at paced syncrates.
  4271. */
  4272. if (period <= AHD_SYNCRATE_PACED)
  4273. ppr_options |= MSG_EXT_PPR_PCOMP_EN;
  4274. if (offset == 0)
  4275. period = AHD_ASYNC_XFER_PERIOD;
  4276. ahd->msgout_index += spi_populate_ppr_msg(
  4277. ahd->msgout_buf + ahd->msgout_index, period, offset,
  4278. bus_width, ppr_options);
  4279. ahd->msgout_len += 8;
  4280. if (bootverbose) {
  4281. printk("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, "
  4282. "offset %x, ppr_options %x\n", ahd_name(ahd),
  4283. devinfo->channel, devinfo->target, devinfo->lun,
  4284. bus_width, period, offset, ppr_options);
  4285. }
  4286. }
  4287. /*
  4288. * Clear any active message state.
  4289. */
  4290. static void
  4291. ahd_clear_msg_state(struct ahd_softc *ahd)
  4292. {
  4293. ahd_mode_state saved_modes;
  4294. saved_modes = ahd_save_modes(ahd);
  4295. ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
  4296. ahd->send_msg_perror = 0;
  4297. ahd->msg_flags = MSG_FLAG_NONE;
  4298. ahd->msgout_len = 0;
  4299. ahd->msgin_index = 0;
  4300. ahd->msg_type = MSG_TYPE_NONE;
  4301. if ((ahd_inb(ahd, SCSISIGO) & ATNO) != 0) {
  4302. /*
  4303. * The target didn't care to respond to our
  4304. * message request, so clear ATN.
  4305. */
  4306. ahd_outb(ahd, CLRSINT1, CLRATNO);
  4307. }
  4308. ahd_outb(ahd, MSG_OUT, MSG_NOOP);
  4309. ahd_outb(ahd, SEQ_FLAGS2,
  4310. ahd_inb(ahd, SEQ_FLAGS2) & ~TARGET_MSG_PENDING);
  4311. ahd_restore_modes(ahd, saved_modes);
  4312. }
  4313. /*
  4314. * Manual message loop handler.
  4315. */
  4316. static void
  4317. ahd_handle_message_phase(struct ahd_softc *ahd)
  4318. {
  4319. struct ahd_devinfo devinfo;
  4320. u_int bus_phase;
  4321. int end_session;
  4322. ahd_fetch_devinfo(ahd, &devinfo);
  4323. end_session = FALSE;
  4324. bus_phase = ahd_inb(ahd, LASTPHASE);
  4325. if ((ahd_inb(ahd, LQISTAT2) & LQIPHASE_OUTPKT) != 0) {
  4326. printk("LQIRETRY for LQIPHASE_OUTPKT\n");
  4327. ahd_outb(ahd, LQCTL2, LQIRETRY);
  4328. }
  4329. reswitch:
  4330. switch (ahd->msg_type) {
  4331. case MSG_TYPE_INITIATOR_MSGOUT:
  4332. {
  4333. int lastbyte;
  4334. int phasemis;
  4335. int msgdone;
  4336. if (ahd->msgout_len == 0 && ahd->send_msg_perror == 0)
  4337. panic("HOST_MSG_LOOP interrupt with no active message");
  4338. #ifdef AHD_DEBUG
  4339. if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
  4340. ahd_print_devinfo(ahd, &devinfo);
  4341. printk("INITIATOR_MSG_OUT");
  4342. }
  4343. #endif
  4344. phasemis = bus_phase != P_MESGOUT;
  4345. if (phasemis) {
  4346. #ifdef AHD_DEBUG
  4347. if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
  4348. printk(" PHASEMIS %s\n",
  4349. ahd_lookup_phase_entry(bus_phase)
  4350. ->phasemsg);
  4351. }
  4352. #endif
  4353. if (bus_phase == P_MESGIN) {
  4354. /*
  4355. * Change gears and see if
  4356. * this messages is of interest to
  4357. * us or should be passed back to
  4358. * the sequencer.
  4359. */
  4360. ahd_outb(ahd, CLRSINT1, CLRATNO);
  4361. ahd->send_msg_perror = 0;
  4362. ahd->msg_type = MSG_TYPE_INITIATOR_MSGIN;
  4363. ahd->msgin_index = 0;
  4364. goto reswitch;
  4365. }
  4366. end_session = TRUE;
  4367. break;
  4368. }
  4369. if (ahd->send_msg_perror) {
  4370. ahd_outb(ahd, CLRSINT1, CLRATNO);
  4371. ahd_outb(ahd, CLRSINT1, CLRREQINIT);
  4372. #ifdef AHD_DEBUG
  4373. if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
  4374. printk(" byte 0x%x\n", ahd->send_msg_perror);
  4375. #endif
  4376. /*
  4377. * If we are notifying the target of a CRC error
  4378. * during packetized operations, the target is
  4379. * within its rights to acknowledge our message
  4380. * with a busfree.
  4381. */
  4382. if ((ahd->msg_flags & MSG_FLAG_PACKETIZED) != 0
  4383. && ahd->send_msg_perror == MSG_INITIATOR_DET_ERR)
  4384. ahd->msg_flags |= MSG_FLAG_EXPECT_IDE_BUSFREE;
  4385. ahd_outb(ahd, RETURN_2, ahd->send_msg_perror);
  4386. ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_WRITE);
  4387. break;
  4388. }
  4389. msgdone = ahd->msgout_index == ahd->msgout_len;
  4390. if (msgdone) {
  4391. /*
  4392. * The target has requested a retry.
  4393. * Re-assert ATN, reset our message index to
  4394. * 0, and try again.
  4395. */
  4396. ahd->msgout_index = 0;
  4397. ahd_assert_atn(ahd);
  4398. }
  4399. lastbyte = ahd->msgout_index == (ahd->msgout_len - 1);
  4400. if (lastbyte) {
  4401. /* Last byte is signified by dropping ATN */
  4402. ahd_outb(ahd, CLRSINT1, CLRATNO);
  4403. }
  4404. /*
  4405. * Clear our interrupt status and present
  4406. * the next byte on the bus.
  4407. */
  4408. ahd_outb(ahd, CLRSINT1, CLRREQINIT);
  4409. #ifdef AHD_DEBUG
  4410. if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
  4411. printk(" byte 0x%x\n",
  4412. ahd->msgout_buf[ahd->msgout_index]);
  4413. #endif
  4414. ahd_outb(ahd, RETURN_2, ahd->msgout_buf[ahd->msgout_index++]);
  4415. ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_WRITE);
  4416. break;
  4417. }
  4418. case MSG_TYPE_INITIATOR_MSGIN:
  4419. {
  4420. int phasemis;
  4421. int message_done;
  4422. #ifdef AHD_DEBUG
  4423. if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
  4424. ahd_print_devinfo(ahd, &devinfo);
  4425. printk("INITIATOR_MSG_IN");
  4426. }
  4427. #endif
  4428. phasemis = bus_phase != P_MESGIN;
  4429. if (phasemis) {
  4430. #ifdef AHD_DEBUG
  4431. if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
  4432. printk(" PHASEMIS %s\n",
  4433. ahd_lookup_phase_entry(bus_phase)
  4434. ->phasemsg);
  4435. }
  4436. #endif
  4437. ahd->msgin_index = 0;
  4438. if (bus_phase == P_MESGOUT
  4439. && (ahd->send_msg_perror != 0
  4440. || (ahd->msgout_len != 0
  4441. && ahd->msgout_index == 0))) {
  4442. ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
  4443. goto reswitch;
  4444. }
  4445. end_session = TRUE;
  4446. break;
  4447. }
  4448. /* Pull the byte in without acking it */
  4449. ahd->msgin_buf[ahd->msgin_index] = ahd_inb(ahd, SCSIBUS);
  4450. #ifdef AHD_DEBUG
  4451. if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
  4452. printk(" byte 0x%x\n",
  4453. ahd->msgin_buf[ahd->msgin_index]);
  4454. #endif
  4455. message_done = ahd_parse_msg(ahd, &devinfo);
  4456. if (message_done) {
  4457. /*
  4458. * Clear our incoming message buffer in case there
  4459. * is another message following this one.
  4460. */
  4461. ahd->msgin_index = 0;
  4462. /*
  4463. * If this message illicited a response,
  4464. * assert ATN so the target takes us to the
  4465. * message out phase.
  4466. */
  4467. if (ahd->msgout_len != 0) {
  4468. #ifdef AHD_DEBUG
  4469. if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
  4470. ahd_print_devinfo(ahd, &devinfo);
  4471. printk("Asserting ATN for response\n");
  4472. }
  4473. #endif
  4474. ahd_assert_atn(ahd);
  4475. }
  4476. } else
  4477. ahd->msgin_index++;
  4478. if (message_done == MSGLOOP_TERMINATED) {
  4479. end_session = TRUE;
  4480. } else {
  4481. /* Ack the byte */
  4482. ahd_outb(ahd, CLRSINT1, CLRREQINIT);
  4483. ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_READ);
  4484. }
  4485. break;
  4486. }
  4487. case MSG_TYPE_TARGET_MSGIN:
  4488. {
  4489. int msgdone;
  4490. int msgout_request;
  4491. /*
  4492. * By default, the message loop will continue.
  4493. */
  4494. ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_TARG);
  4495. if (ahd->msgout_len == 0)
  4496. panic("Target MSGIN with no active message");
  4497. /*
  4498. * If we interrupted a mesgout session, the initiator
  4499. * will not know this until our first REQ. So, we
  4500. * only honor mesgout requests after we've sent our
  4501. * first byte.
  4502. */
  4503. if ((ahd_inb(ahd, SCSISIGI) & ATNI) != 0
  4504. && ahd->msgout_index > 0)
  4505. msgout_request = TRUE;
  4506. else
  4507. msgout_request = FALSE;
  4508. if (msgout_request) {
  4509. /*
  4510. * Change gears and see if
  4511. * this messages is of interest to
  4512. * us or should be passed back to
  4513. * the sequencer.
  4514. */
  4515. ahd->msg_type = MSG_TYPE_TARGET_MSGOUT;
  4516. ahd_outb(ahd, SCSISIGO, P_MESGOUT | BSYO);
  4517. ahd->msgin_index = 0;
  4518. /* Dummy read to REQ for first byte */
  4519. ahd_inb(ahd, SCSIDAT);
  4520. ahd_outb(ahd, SXFRCTL0,
  4521. ahd_inb(ahd, SXFRCTL0) | SPIOEN);
  4522. break;
  4523. }
  4524. msgdone = ahd->msgout_index == ahd->msgout_len;
  4525. if (msgdone) {
  4526. ahd_outb(ahd, SXFRCTL0,
  4527. ahd_inb(ahd, SXFRCTL0) & ~SPIOEN);
  4528. end_session = TRUE;
  4529. break;
  4530. }
  4531. /*
  4532. * Present the next byte on the bus.
  4533. */
  4534. ahd_outb(ahd, SXFRCTL0, ahd_inb(ahd, SXFRCTL0) | SPIOEN);
  4535. ahd_outb(ahd, SCSIDAT, ahd->msgout_buf[ahd->msgout_index++]);
  4536. break;
  4537. }
  4538. case MSG_TYPE_TARGET_MSGOUT:
  4539. {
  4540. int lastbyte;
  4541. int msgdone;
  4542. /*
  4543. * By default, the message loop will continue.
  4544. */
  4545. ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_TARG);
  4546. /*
  4547. * The initiator signals that this is
  4548. * the last byte by dropping ATN.
  4549. */
  4550. lastbyte = (ahd_inb(ahd, SCSISIGI) & ATNI) == 0;
  4551. /*
  4552. * Read the latched byte, but turn off SPIOEN first
  4553. * so that we don't inadvertently cause a REQ for the
  4554. * next byte.
  4555. */
  4556. ahd_outb(ahd, SXFRCTL0, ahd_inb(ahd, SXFRCTL0) & ~SPIOEN);
  4557. ahd->msgin_buf[ahd->msgin_index] = ahd_inb(ahd, SCSIDAT);
  4558. msgdone = ahd_parse_msg(ahd, &devinfo);
  4559. if (msgdone == MSGLOOP_TERMINATED) {
  4560. /*
  4561. * The message is *really* done in that it caused
  4562. * us to go to bus free. The sequencer has already
  4563. * been reset at this point, so pull the ejection
  4564. * handle.
  4565. */
  4566. return;
  4567. }
  4568. ahd->msgin_index++;
  4569. /*
  4570. * XXX Read spec about initiator dropping ATN too soon
  4571. * and use msgdone to detect it.
  4572. */
  4573. if (msgdone == MSGLOOP_MSGCOMPLETE) {
  4574. ahd->msgin_index = 0;
  4575. /*
  4576. * If this message illicited a response, transition
  4577. * to the Message in phase and send it.
  4578. */
  4579. if (ahd->msgout_len != 0) {
  4580. ahd_outb(ahd, SCSISIGO, P_MESGIN | BSYO);
  4581. ahd_outb(ahd, SXFRCTL0,
  4582. ahd_inb(ahd, SXFRCTL0) | SPIOEN);
  4583. ahd->msg_type = MSG_TYPE_TARGET_MSGIN;
  4584. ahd->msgin_index = 0;
  4585. break;
  4586. }
  4587. }
  4588. if (lastbyte)
  4589. end_session = TRUE;
  4590. else {
  4591. /* Ask for the next byte. */
  4592. ahd_outb(ahd, SXFRCTL0,
  4593. ahd_inb(ahd, SXFRCTL0) | SPIOEN);
  4594. }
  4595. break;
  4596. }
  4597. default:
  4598. panic("Unknown REQINIT message type");
  4599. }
  4600. if (end_session) {
  4601. if ((ahd->msg_flags & MSG_FLAG_PACKETIZED) != 0) {
  4602. printk("%s: Returning to Idle Loop\n",
  4603. ahd_name(ahd));
  4604. ahd_clear_msg_state(ahd);
  4605. /*
  4606. * Perform the equivalent of a clear_target_state.
  4607. */
  4608. ahd_outb(ahd, LASTPHASE, P_BUSFREE);
  4609. ahd_outb(ahd, SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT);
  4610. ahd_outb(ahd, SEQCTL0, FASTMODE|SEQRESET);
  4611. } else {
  4612. ahd_clear_msg_state(ahd);
  4613. ahd_outb(ahd, RETURN_1, EXIT_MSG_LOOP);
  4614. }
  4615. }
  4616. }
  4617. /*
  4618. * See if we sent a particular extended message to the target.
  4619. * If "full" is true, return true only if the target saw the full
  4620. * message. If "full" is false, return true if the target saw at
  4621. * least the first byte of the message.
  4622. */
  4623. static int
  4624. ahd_sent_msg(struct ahd_softc *ahd, ahd_msgtype type, u_int msgval, int full)
  4625. {
  4626. int found;
  4627. u_int index;
  4628. found = FALSE;
  4629. index = 0;
  4630. while (index < ahd->msgout_len) {
  4631. if (ahd->msgout_buf[index] == MSG_EXTENDED) {
  4632. u_int end_index;
  4633. end_index = index + 1 + ahd->msgout_buf[index + 1];
  4634. if (ahd->msgout_buf[index+2] == msgval
  4635. && type == AHDMSG_EXT) {
  4636. if (full) {
  4637. if (ahd->msgout_index > end_index)
  4638. found = TRUE;
  4639. } else if (ahd->msgout_index > index)
  4640. found = TRUE;
  4641. }
  4642. index = end_index;
  4643. } else if (ahd->msgout_buf[index] >= MSG_SIMPLE_TASK
  4644. && ahd->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) {
  4645. /* Skip tag type and tag id or residue param*/
  4646. index += 2;
  4647. } else {
  4648. /* Single byte message */
  4649. if (type == AHDMSG_1B
  4650. && ahd->msgout_index > index
  4651. && (ahd->msgout_buf[index] == msgval
  4652. || ((ahd->msgout_buf[index] & MSG_IDENTIFYFLAG) != 0
  4653. && msgval == MSG_IDENTIFYFLAG)))
  4654. found = TRUE;
  4655. index++;
  4656. }
  4657. if (found)
  4658. break;
  4659. }
  4660. return (found);
  4661. }
  4662. /*
  4663. * Wait for a complete incoming message, parse it, and respond accordingly.
  4664. */
  4665. static int
  4666. ahd_parse_msg(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
  4667. {
  4668. struct ahd_initiator_tinfo *tinfo;
  4669. struct ahd_tmode_tstate *tstate;
  4670. int reject;
  4671. int done;
  4672. int response;
  4673. done = MSGLOOP_IN_PROG;
  4674. response = FALSE;
  4675. reject = FALSE;
  4676. tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid,
  4677. devinfo->target, &tstate);
  4678. /*
  4679. * Parse as much of the message as is available,
  4680. * rejecting it if we don't support it. When
  4681. * the entire message is available and has been
  4682. * handled, return MSGLOOP_MSGCOMPLETE, indicating
  4683. * that we have parsed an entire message.
  4684. *
  4685. * In the case of extended messages, we accept the length
  4686. * byte outright and perform more checking once we know the
  4687. * extended message type.
  4688. */
  4689. switch (ahd->msgin_buf[0]) {
  4690. case MSG_DISCONNECT:
  4691. case MSG_SAVEDATAPOINTER:
  4692. case MSG_CMDCOMPLETE:
  4693. case MSG_RESTOREPOINTERS:
  4694. case MSG_IGN_WIDE_RESIDUE:
  4695. /*
  4696. * End our message loop as these are messages
  4697. * the sequencer handles on its own.
  4698. */
  4699. done = MSGLOOP_TERMINATED;
  4700. break;
  4701. case MSG_MESSAGE_REJECT:
  4702. response = ahd_handle_msg_reject(ahd, devinfo);
  4703. /* FALLTHROUGH */
  4704. case MSG_NOOP:
  4705. done = MSGLOOP_MSGCOMPLETE;
  4706. break;
  4707. case MSG_EXTENDED:
  4708. {
  4709. /* Wait for enough of the message to begin validation */
  4710. if (ahd->msgin_index < 2)
  4711. break;
  4712. switch (ahd->msgin_buf[2]) {
  4713. case MSG_EXT_SDTR:
  4714. {
  4715. u_int period;
  4716. u_int ppr_options;
  4717. u_int offset;
  4718. u_int saved_offset;
  4719. if (ahd->msgin_buf[1] != MSG_EXT_SDTR_LEN) {
  4720. reject = TRUE;
  4721. break;
  4722. }
  4723. /*
  4724. * Wait until we have both args before validating
  4725. * and acting on this message.
  4726. *
  4727. * Add one to MSG_EXT_SDTR_LEN to account for
  4728. * the extended message preamble.
  4729. */
  4730. if (ahd->msgin_index < (MSG_EXT_SDTR_LEN + 1))
  4731. break;
  4732. period = ahd->msgin_buf[3];
  4733. ppr_options = 0;
  4734. saved_offset = offset = ahd->msgin_buf[4];
  4735. ahd_devlimited_syncrate(ahd, tinfo, &period,
  4736. &ppr_options, devinfo->role);
  4737. ahd_validate_offset(ahd, tinfo, period, &offset,
  4738. tinfo->curr.width, devinfo->role);
  4739. if (bootverbose) {
  4740. printk("(%s:%c:%d:%d): Received "
  4741. "SDTR period %x, offset %x\n\t"
  4742. "Filtered to period %x, offset %x\n",
  4743. ahd_name(ahd), devinfo->channel,
  4744. devinfo->target, devinfo->lun,
  4745. ahd->msgin_buf[3], saved_offset,
  4746. period, offset);
  4747. }
  4748. ahd_set_syncrate(ahd, devinfo, period,
  4749. offset, ppr_options,
  4750. AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
  4751. /*paused*/TRUE);
  4752. /*
  4753. * See if we initiated Sync Negotiation
  4754. * and didn't have to fall down to async
  4755. * transfers.
  4756. */
  4757. if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, TRUE)) {
  4758. /* We started it */
  4759. if (saved_offset != offset) {
  4760. /* Went too low - force async */
  4761. reject = TRUE;
  4762. }
  4763. } else {
  4764. /*
  4765. * Send our own SDTR in reply
  4766. */
  4767. if (bootverbose
  4768. && devinfo->role == ROLE_INITIATOR) {
  4769. printk("(%s:%c:%d:%d): Target "
  4770. "Initiated SDTR\n",
  4771. ahd_name(ahd), devinfo->channel,
  4772. devinfo->target, devinfo->lun);
  4773. }
  4774. ahd->msgout_index = 0;
  4775. ahd->msgout_len = 0;
  4776. ahd_construct_sdtr(ahd, devinfo,
  4777. period, offset);
  4778. ahd->msgout_index = 0;
  4779. response = TRUE;
  4780. }
  4781. done = MSGLOOP_MSGCOMPLETE;
  4782. break;
  4783. }
  4784. case MSG_EXT_WDTR:
  4785. {
  4786. u_int bus_width;
  4787. u_int saved_width;
  4788. u_int sending_reply;
  4789. sending_reply = FALSE;
  4790. if (ahd->msgin_buf[1] != MSG_EXT_WDTR_LEN) {
  4791. reject = TRUE;
  4792. break;
  4793. }
  4794. /*
  4795. * Wait until we have our arg before validating
  4796. * and acting on this message.
  4797. *
  4798. * Add one to MSG_EXT_WDTR_LEN to account for
  4799. * the extended message preamble.
  4800. */
  4801. if (ahd->msgin_index < (MSG_EXT_WDTR_LEN + 1))
  4802. break;
  4803. bus_width = ahd->msgin_buf[3];
  4804. saved_width = bus_width;
  4805. ahd_validate_width(ahd, tinfo, &bus_width,
  4806. devinfo->role);
  4807. if (bootverbose) {
  4808. printk("(%s:%c:%d:%d): Received WDTR "
  4809. "%x filtered to %x\n",
  4810. ahd_name(ahd), devinfo->channel,
  4811. devinfo->target, devinfo->lun,
  4812. saved_width, bus_width);
  4813. }
  4814. if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, TRUE)) {
  4815. /*
  4816. * Don't send a WDTR back to the
  4817. * target, since we asked first.
  4818. * If the width went higher than our
  4819. * request, reject it.
  4820. */
  4821. if (saved_width > bus_width) {
  4822. reject = TRUE;
  4823. printk("(%s:%c:%d:%d): requested %dBit "
  4824. "transfers. Rejecting...\n",
  4825. ahd_name(ahd), devinfo->channel,
  4826. devinfo->target, devinfo->lun,
  4827. 8 * (0x01 << bus_width));
  4828. bus_width = 0;
  4829. }
  4830. } else {
  4831. /*
  4832. * Send our own WDTR in reply
  4833. */
  4834. if (bootverbose
  4835. && devinfo->role == ROLE_INITIATOR) {
  4836. printk("(%s:%c:%d:%d): Target "
  4837. "Initiated WDTR\n",
  4838. ahd_name(ahd), devinfo->channel,
  4839. devinfo->target, devinfo->lun);
  4840. }
  4841. ahd->msgout_index = 0;
  4842. ahd->msgout_len = 0;
  4843. ahd_construct_wdtr(ahd, devinfo, bus_width);
  4844. ahd->msgout_index = 0;
  4845. response = TRUE;
  4846. sending_reply = TRUE;
  4847. }
  4848. /*
  4849. * After a wide message, we are async, but
  4850. * some devices don't seem to honor this portion
  4851. * of the spec. Force a renegotiation of the
  4852. * sync component of our transfer agreement even
  4853. * if our goal is async. By updating our width
  4854. * after forcing the negotiation, we avoid
  4855. * renegotiating for width.
  4856. */
  4857. ahd_update_neg_request(ahd, devinfo, tstate,
  4858. tinfo, AHD_NEG_ALWAYS);
  4859. ahd_set_width(ahd, devinfo, bus_width,
  4860. AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
  4861. /*paused*/TRUE);
  4862. if (sending_reply == FALSE && reject == FALSE) {
  4863. /*
  4864. * We will always have an SDTR to send.
  4865. */
  4866. ahd->msgout_index = 0;
  4867. ahd->msgout_len = 0;
  4868. ahd_build_transfer_msg(ahd, devinfo);
  4869. ahd->msgout_index = 0;
  4870. response = TRUE;
  4871. }
  4872. done = MSGLOOP_MSGCOMPLETE;
  4873. break;
  4874. }
  4875. case MSG_EXT_PPR:
  4876. {
  4877. u_int period;
  4878. u_int offset;
  4879. u_int bus_width;
  4880. u_int ppr_options;
  4881. u_int saved_width;
  4882. u_int saved_offset;
  4883. u_int saved_ppr_options;
  4884. if (ahd->msgin_buf[1] != MSG_EXT_PPR_LEN) {
  4885. reject = TRUE;
  4886. break;
  4887. }
  4888. /*
  4889. * Wait until we have all args before validating
  4890. * and acting on this message.
  4891. *
  4892. * Add one to MSG_EXT_PPR_LEN to account for
  4893. * the extended message preamble.
  4894. */
  4895. if (ahd->msgin_index < (MSG_EXT_PPR_LEN + 1))
  4896. break;
  4897. period = ahd->msgin_buf[3];
  4898. offset = ahd->msgin_buf[5];
  4899. bus_width = ahd->msgin_buf[6];
  4900. saved_width = bus_width;
  4901. ppr_options = ahd->msgin_buf[7];
  4902. /*
  4903. * According to the spec, a DT only
  4904. * period factor with no DT option
  4905. * set implies async.
  4906. */
  4907. if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0
  4908. && period <= 9)
  4909. offset = 0;
  4910. saved_ppr_options = ppr_options;
  4911. saved_offset = offset;
  4912. /*
  4913. * Transfer options are only available if we
  4914. * are negotiating wide.
  4915. */
  4916. if (bus_width == 0)
  4917. ppr_options &= MSG_EXT_PPR_QAS_REQ;
  4918. ahd_validate_width(ahd, tinfo, &bus_width,
  4919. devinfo->role);
  4920. ahd_devlimited_syncrate(ahd, tinfo, &period,
  4921. &ppr_options, devinfo->role);
  4922. ahd_validate_offset(ahd, tinfo, period, &offset,
  4923. bus_width, devinfo->role);
  4924. if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, TRUE)) {
  4925. /*
  4926. * If we are unable to do any of the
  4927. * requested options (we went too low),
  4928. * then we'll have to reject the message.
  4929. */
  4930. if (saved_width > bus_width
  4931. || saved_offset != offset
  4932. || saved_ppr_options != ppr_options) {
  4933. reject = TRUE;
  4934. period = 0;
  4935. offset = 0;
  4936. bus_width = 0;
  4937. ppr_options = 0;
  4938. }
  4939. } else {
  4940. if (devinfo->role != ROLE_TARGET)
  4941. printk("(%s:%c:%d:%d): Target "
  4942. "Initiated PPR\n",
  4943. ahd_name(ahd), devinfo->channel,
  4944. devinfo->target, devinfo->lun);
  4945. else
  4946. printk("(%s:%c:%d:%d): Initiator "
  4947. "Initiated PPR\n",
  4948. ahd_name(ahd), devinfo->channel,
  4949. devinfo->target, devinfo->lun);
  4950. ahd->msgout_index = 0;
  4951. ahd->msgout_len = 0;
  4952. ahd_construct_ppr(ahd, devinfo, period, offset,
  4953. bus_width, ppr_options);
  4954. ahd->msgout_index = 0;
  4955. response = TRUE;
  4956. }
  4957. if (bootverbose) {
  4958. printk("(%s:%c:%d:%d): Received PPR width %x, "
  4959. "period %x, offset %x,options %x\n"
  4960. "\tFiltered to width %x, period %x, "
  4961. "offset %x, options %x\n",
  4962. ahd_name(ahd), devinfo->channel,
  4963. devinfo->target, devinfo->lun,
  4964. saved_width, ahd->msgin_buf[3],
  4965. saved_offset, saved_ppr_options,
  4966. bus_width, period, offset, ppr_options);
  4967. }
  4968. ahd_set_width(ahd, devinfo, bus_width,
  4969. AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
  4970. /*paused*/TRUE);
  4971. ahd_set_syncrate(ahd, devinfo, period,
  4972. offset, ppr_options,
  4973. AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
  4974. /*paused*/TRUE);
  4975. done = MSGLOOP_MSGCOMPLETE;
  4976. break;
  4977. }
  4978. default:
  4979. /* Unknown extended message. Reject it. */
  4980. reject = TRUE;
  4981. break;
  4982. }
  4983. break;
  4984. }
  4985. #ifdef AHD_TARGET_MODE
  4986. case MSG_BUS_DEV_RESET:
  4987. ahd_handle_devreset(ahd, devinfo, CAM_LUN_WILDCARD,
  4988. CAM_BDR_SENT,
  4989. "Bus Device Reset Received",
  4990. /*verbose_level*/0);
  4991. ahd_restart(ahd);
  4992. done = MSGLOOP_TERMINATED;
  4993. break;
  4994. case MSG_ABORT_TAG:
  4995. case MSG_ABORT:
  4996. case MSG_CLEAR_QUEUE:
  4997. {
  4998. int tag;
  4999. /* Target mode messages */
  5000. if (devinfo->role != ROLE_TARGET) {
  5001. reject = TRUE;
  5002. break;
  5003. }
  5004. tag = SCB_LIST_NULL;
  5005. if (ahd->msgin_buf[0] == MSG_ABORT_TAG)
  5006. tag = ahd_inb(ahd, INITIATOR_TAG);
  5007. ahd_abort_scbs(ahd, devinfo->target, devinfo->channel,
  5008. devinfo->lun, tag, ROLE_TARGET,
  5009. CAM_REQ_ABORTED);
  5010. tstate = ahd->enabled_targets[devinfo->our_scsiid];
  5011. if (tstate != NULL) {
  5012. struct ahd_tmode_lstate* lstate;
  5013. lstate = tstate->enabled_luns[devinfo->lun];
  5014. if (lstate != NULL) {
  5015. ahd_queue_lstate_event(ahd, lstate,
  5016. devinfo->our_scsiid,
  5017. ahd->msgin_buf[0],
  5018. /*arg*/tag);
  5019. ahd_send_lstate_events(ahd, lstate);
  5020. }
  5021. }
  5022. ahd_restart(ahd);
  5023. done = MSGLOOP_TERMINATED;
  5024. break;
  5025. }
  5026. #endif
  5027. case MSG_QAS_REQUEST:
  5028. #ifdef AHD_DEBUG
  5029. if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
  5030. printk("%s: QAS request. SCSISIGI == 0x%x\n",
  5031. ahd_name(ahd), ahd_inb(ahd, SCSISIGI));
  5032. #endif
  5033. ahd->msg_flags |= MSG_FLAG_EXPECT_QASREJ_BUSFREE;
  5034. /* FALLTHROUGH */
  5035. case MSG_TERM_IO_PROC:
  5036. default:
  5037. reject = TRUE;
  5038. break;
  5039. }
  5040. if (reject) {
  5041. /*
  5042. * Setup to reject the message.
  5043. */
  5044. ahd->msgout_index = 0;
  5045. ahd->msgout_len = 1;
  5046. ahd->msgout_buf[0] = MSG_MESSAGE_REJECT;
  5047. done = MSGLOOP_MSGCOMPLETE;
  5048. response = TRUE;
  5049. }
  5050. if (done != MSGLOOP_IN_PROG && !response)
  5051. /* Clear the outgoing message buffer */
  5052. ahd->msgout_len = 0;
  5053. return (done);
  5054. }
  5055. /*
  5056. * Process a message reject message.
  5057. */
  5058. static int
  5059. ahd_handle_msg_reject(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
  5060. {
  5061. /*
  5062. * What we care about here is if we had an
  5063. * outstanding SDTR or WDTR message for this
  5064. * target. If we did, this is a signal that
  5065. * the target is refusing negotiation.
  5066. */
  5067. struct scb *scb;
  5068. struct ahd_initiator_tinfo *tinfo;
  5069. struct ahd_tmode_tstate *tstate;
  5070. u_int scb_index;
  5071. u_int last_msg;
  5072. int response = 0;
  5073. scb_index = ahd_get_scbptr(ahd);
  5074. scb = ahd_lookup_scb(ahd, scb_index);
  5075. tinfo = ahd_fetch_transinfo(ahd, devinfo->channel,
  5076. devinfo->our_scsiid,
  5077. devinfo->target, &tstate);
  5078. /* Might be necessary */
  5079. last_msg = ahd_inb(ahd, LAST_MSG);
  5080. if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) {
  5081. if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, /*full*/TRUE)
  5082. && tinfo->goal.period <= AHD_SYNCRATE_PACED) {
  5083. /*
  5084. * Target may not like our SPI-4 PPR Options.
  5085. * Attempt to negotiate 80MHz which will turn
  5086. * off these options.
  5087. */
  5088. if (bootverbose) {
  5089. printk("(%s:%c:%d:%d): PPR Rejected. "
  5090. "Trying simple U160 PPR\n",
  5091. ahd_name(ahd), devinfo->channel,
  5092. devinfo->target, devinfo->lun);
  5093. }
  5094. tinfo->goal.period = AHD_SYNCRATE_DT;
  5095. tinfo->goal.ppr_options &= MSG_EXT_PPR_IU_REQ
  5096. | MSG_EXT_PPR_QAS_REQ
  5097. | MSG_EXT_PPR_DT_REQ;
  5098. } else {
  5099. /*
  5100. * Target does not support the PPR message.
  5101. * Attempt to negotiate SPI-2 style.
  5102. */
  5103. if (bootverbose) {
  5104. printk("(%s:%c:%d:%d): PPR Rejected. "
  5105. "Trying WDTR/SDTR\n",
  5106. ahd_name(ahd), devinfo->channel,
  5107. devinfo->target, devinfo->lun);
  5108. }
  5109. tinfo->goal.ppr_options = 0;
  5110. tinfo->curr.transport_version = 2;
  5111. tinfo->goal.transport_version = 2;
  5112. }
  5113. ahd->msgout_index = 0;
  5114. ahd->msgout_len = 0;
  5115. ahd_build_transfer_msg(ahd, devinfo);
  5116. ahd->msgout_index = 0;
  5117. response = 1;
  5118. } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) {
  5119. /* note 8bit xfers */
  5120. printk("(%s:%c:%d:%d): refuses WIDE negotiation. Using "
  5121. "8bit transfers\n", ahd_name(ahd),
  5122. devinfo->channel, devinfo->target, devinfo->lun);
  5123. ahd_set_width(ahd, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
  5124. AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
  5125. /*paused*/TRUE);
  5126. /*
  5127. * No need to clear the sync rate. If the target
  5128. * did not accept the command, our syncrate is
  5129. * unaffected. If the target started the negotiation,
  5130. * but rejected our response, we already cleared the
  5131. * sync rate before sending our WDTR.
  5132. */
  5133. if (tinfo->goal.offset != tinfo->curr.offset) {
  5134. /* Start the sync negotiation */
  5135. ahd->msgout_index = 0;
  5136. ahd->msgout_len = 0;
  5137. ahd_build_transfer_msg(ahd, devinfo);
  5138. ahd->msgout_index = 0;
  5139. response = 1;
  5140. }
  5141. } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) {
  5142. /* note asynch xfers and clear flag */
  5143. ahd_set_syncrate(ahd, devinfo, /*period*/0,
  5144. /*offset*/0, /*ppr_options*/0,
  5145. AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
  5146. /*paused*/TRUE);
  5147. printk("(%s:%c:%d:%d): refuses synchronous negotiation. "
  5148. "Using asynchronous transfers\n",
  5149. ahd_name(ahd), devinfo->channel,
  5150. devinfo->target, devinfo->lun);
  5151. } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) {
  5152. int tag_type;
  5153. int mask;
  5154. tag_type = (scb->hscb->control & MSG_SIMPLE_TASK);
  5155. if (tag_type == MSG_SIMPLE_TASK) {
  5156. printk("(%s:%c:%d:%d): refuses tagged commands. "
  5157. "Performing non-tagged I/O\n", ahd_name(ahd),
  5158. devinfo->channel, devinfo->target, devinfo->lun);
  5159. ahd_set_tags(ahd, scb->io_ctx, devinfo, AHD_QUEUE_NONE);
  5160. mask = ~0x23;
  5161. } else {
  5162. printk("(%s:%c:%d:%d): refuses %s tagged commands. "
  5163. "Performing simple queue tagged I/O only\n",
  5164. ahd_name(ahd), devinfo->channel, devinfo->target,
  5165. devinfo->lun, tag_type == MSG_ORDERED_TASK
  5166. ? "ordered" : "head of queue");
  5167. ahd_set_tags(ahd, scb->io_ctx, devinfo, AHD_QUEUE_BASIC);
  5168. mask = ~0x03;
  5169. }
  5170. /*
  5171. * Resend the identify for this CCB as the target
  5172. * may believe that the selection is invalid otherwise.
  5173. */
  5174. ahd_outb(ahd, SCB_CONTROL,
  5175. ahd_inb_scbram(ahd, SCB_CONTROL) & mask);
  5176. scb->hscb->control &= mask;
  5177. ahd_set_transaction_tag(scb, /*enabled*/FALSE,
  5178. /*type*/MSG_SIMPLE_TASK);
  5179. ahd_outb(ahd, MSG_OUT, MSG_IDENTIFYFLAG);
  5180. ahd_assert_atn(ahd);
  5181. ahd_busy_tcl(ahd, BUILD_TCL(scb->hscb->scsiid, devinfo->lun),
  5182. SCB_GET_TAG(scb));
  5183. /*
  5184. * Requeue all tagged commands for this target
  5185. * currently in our possession so they can be
  5186. * converted to untagged commands.
  5187. */
  5188. ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb),
  5189. SCB_GET_CHANNEL(ahd, scb),
  5190. SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL,
  5191. ROLE_INITIATOR, CAM_REQUEUE_REQ,
  5192. SEARCH_COMPLETE);
  5193. } else if (ahd_sent_msg(ahd, AHDMSG_1B, MSG_IDENTIFYFLAG, TRUE)) {
  5194. /*
  5195. * Most likely the device believes that we had
  5196. * previously negotiated packetized.
  5197. */
  5198. ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE
  5199. | MSG_FLAG_IU_REQ_CHANGED;
  5200. ahd_force_renegotiation(ahd, devinfo);
  5201. ahd->msgout_index = 0;
  5202. ahd->msgout_len = 0;
  5203. ahd_build_transfer_msg(ahd, devinfo);
  5204. ahd->msgout_index = 0;
  5205. response = 1;
  5206. } else {
  5207. /*
  5208. * Otherwise, we ignore it.
  5209. */
  5210. printk("%s:%c:%d: Message reject for %x -- ignored\n",
  5211. ahd_name(ahd), devinfo->channel, devinfo->target,
  5212. last_msg);
  5213. }
  5214. return (response);
  5215. }
  5216. /*
  5217. * Process an ingnore wide residue message.
  5218. */
  5219. static void
  5220. ahd_handle_ign_wide_residue(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
  5221. {
  5222. u_int scb_index;
  5223. struct scb *scb;
  5224. scb_index = ahd_get_scbptr(ahd);
  5225. scb = ahd_lookup_scb(ahd, scb_index);
  5226. /*
  5227. * XXX Actually check data direction in the sequencer?
  5228. * Perhaps add datadir to some spare bits in the hscb?
  5229. */
  5230. if ((ahd_inb(ahd, SEQ_FLAGS) & DPHASE) == 0
  5231. || ahd_get_transfer_dir(scb) != CAM_DIR_IN) {
  5232. /*
  5233. * Ignore the message if we haven't
  5234. * seen an appropriate data phase yet.
  5235. */
  5236. } else {
  5237. /*
  5238. * If the residual occurred on the last
  5239. * transfer and the transfer request was
  5240. * expected to end on an odd count, do
  5241. * nothing. Otherwise, subtract a byte
  5242. * and update the residual count accordingly.
  5243. */
  5244. uint32_t sgptr;
  5245. sgptr = ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR);
  5246. if ((sgptr & SG_LIST_NULL) != 0
  5247. && (ahd_inb_scbram(ahd, SCB_TASK_ATTRIBUTE)
  5248. & SCB_XFERLEN_ODD) != 0) {
  5249. /*
  5250. * If the residual occurred on the last
  5251. * transfer and the transfer request was
  5252. * expected to end on an odd count, do
  5253. * nothing.
  5254. */
  5255. } else {
  5256. uint32_t data_cnt;
  5257. uint64_t data_addr;
  5258. uint32_t sglen;
  5259. /* Pull in the rest of the sgptr */
  5260. sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR);
  5261. data_cnt = ahd_inl_scbram(ahd, SCB_RESIDUAL_DATACNT);
  5262. if ((sgptr & SG_LIST_NULL) != 0) {
  5263. /*
  5264. * The residual data count is not updated
  5265. * for the command run to completion case.
  5266. * Explicitly zero the count.
  5267. */
  5268. data_cnt &= ~AHD_SG_LEN_MASK;
  5269. }
  5270. data_addr = ahd_inq(ahd, SHADDR);
  5271. data_cnt += 1;
  5272. data_addr -= 1;
  5273. sgptr &= SG_PTR_MASK;
  5274. if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
  5275. struct ahd_dma64_seg *sg;
  5276. sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
  5277. /*
  5278. * The residual sg ptr points to the next S/G
  5279. * to load so we must go back one.
  5280. */
  5281. sg--;
  5282. sglen = ahd_le32toh(sg->len) & AHD_SG_LEN_MASK;
  5283. if (sg != scb->sg_list
  5284. && sglen < (data_cnt & AHD_SG_LEN_MASK)) {
  5285. sg--;
  5286. sglen = ahd_le32toh(sg->len);
  5287. /*
  5288. * Preserve High Address and SG_LIST
  5289. * bits while setting the count to 1.
  5290. */
  5291. data_cnt = 1|(sglen&(~AHD_SG_LEN_MASK));
  5292. data_addr = ahd_le64toh(sg->addr)
  5293. + (sglen & AHD_SG_LEN_MASK)
  5294. - 1;
  5295. /*
  5296. * Increment sg so it points to the
  5297. * "next" sg.
  5298. */
  5299. sg++;
  5300. sgptr = ahd_sg_virt_to_bus(ahd, scb,
  5301. sg);
  5302. }
  5303. } else {
  5304. struct ahd_dma_seg *sg;
  5305. sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
  5306. /*
  5307. * The residual sg ptr points to the next S/G
  5308. * to load so we must go back one.
  5309. */
  5310. sg--;
  5311. sglen = ahd_le32toh(sg->len) & AHD_SG_LEN_MASK;
  5312. if (sg != scb->sg_list
  5313. && sglen < (data_cnt & AHD_SG_LEN_MASK)) {
  5314. sg--;
  5315. sglen = ahd_le32toh(sg->len);
  5316. /*
  5317. * Preserve High Address and SG_LIST
  5318. * bits while setting the count to 1.
  5319. */
  5320. data_cnt = 1|(sglen&(~AHD_SG_LEN_MASK));
  5321. data_addr = ahd_le32toh(sg->addr)
  5322. + (sglen & AHD_SG_LEN_MASK)
  5323. - 1;
  5324. /*
  5325. * Increment sg so it points to the
  5326. * "next" sg.
  5327. */
  5328. sg++;
  5329. sgptr = ahd_sg_virt_to_bus(ahd, scb,
  5330. sg);
  5331. }
  5332. }
  5333. /*
  5334. * Toggle the "oddness" of the transfer length
  5335. * to handle this mid-transfer ignore wide
  5336. * residue. This ensures that the oddness is
  5337. * correct for subsequent data transfers.
  5338. */
  5339. ahd_outb(ahd, SCB_TASK_ATTRIBUTE,
  5340. ahd_inb_scbram(ahd, SCB_TASK_ATTRIBUTE)
  5341. ^ SCB_XFERLEN_ODD);
  5342. ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr);
  5343. ahd_outl(ahd, SCB_RESIDUAL_DATACNT, data_cnt);
  5344. /*
  5345. * The FIFO's pointers will be updated if/when the
  5346. * sequencer re-enters a data phase.
  5347. */
  5348. }
  5349. }
  5350. }
  5351. /*
  5352. * Reinitialize the data pointers for the active transfer
  5353. * based on its current residual.
  5354. */
  5355. static void
  5356. ahd_reinitialize_dataptrs(struct ahd_softc *ahd)
  5357. {
  5358. struct scb *scb;
  5359. ahd_mode_state saved_modes;
  5360. u_int scb_index;
  5361. u_int wait;
  5362. uint32_t sgptr;
  5363. uint32_t resid;
  5364. uint64_t dataptr;
  5365. AHD_ASSERT_MODES(ahd, AHD_MODE_DFF0_MSK|AHD_MODE_DFF1_MSK,
  5366. AHD_MODE_DFF0_MSK|AHD_MODE_DFF1_MSK);
  5367. scb_index = ahd_get_scbptr(ahd);
  5368. scb = ahd_lookup_scb(ahd, scb_index);
  5369. /*
  5370. * Release and reacquire the FIFO so we
  5371. * have a clean slate.
  5372. */
  5373. ahd_outb(ahd, DFFSXFRCTL, CLRCHN);
  5374. wait = 1000;
  5375. while (--wait && !(ahd_inb(ahd, MDFFSTAT) & FIFOFREE))
  5376. ahd_delay(100);
  5377. if (wait == 0) {
  5378. ahd_print_path(ahd, scb);
  5379. printk("ahd_reinitialize_dataptrs: Forcing FIFO free.\n");
  5380. ahd_outb(ahd, DFFSXFRCTL, RSTCHN|CLRSHCNT);
  5381. }
  5382. saved_modes = ahd_save_modes(ahd);
  5383. ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
  5384. ahd_outb(ahd, DFFSTAT,
  5385. ahd_inb(ahd, DFFSTAT)
  5386. | (saved_modes == 0x11 ? CURRFIFO_1 : CURRFIFO_0));
  5387. /*
  5388. * Determine initial values for data_addr and data_cnt
  5389. * for resuming the data phase.
  5390. */
  5391. sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR);
  5392. sgptr &= SG_PTR_MASK;
  5393. resid = (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT + 2) << 16)
  5394. | (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT + 1) << 8)
  5395. | ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT);
  5396. if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
  5397. struct ahd_dma64_seg *sg;
  5398. sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
  5399. /* The residual sg_ptr always points to the next sg */
  5400. sg--;
  5401. dataptr = ahd_le64toh(sg->addr)
  5402. + (ahd_le32toh(sg->len) & AHD_SG_LEN_MASK)
  5403. - resid;
  5404. ahd_outl(ahd, HADDR + 4, dataptr >> 32);
  5405. } else {
  5406. struct ahd_dma_seg *sg;
  5407. sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
  5408. /* The residual sg_ptr always points to the next sg */
  5409. sg--;
  5410. dataptr = ahd_le32toh(sg->addr)
  5411. + (ahd_le32toh(sg->len) & AHD_SG_LEN_MASK)
  5412. - resid;
  5413. ahd_outb(ahd, HADDR + 4,
  5414. (ahd_le32toh(sg->len) & ~AHD_SG_LEN_MASK) >> 24);
  5415. }
  5416. ahd_outl(ahd, HADDR, dataptr);
  5417. ahd_outb(ahd, HCNT + 2, resid >> 16);
  5418. ahd_outb(ahd, HCNT + 1, resid >> 8);
  5419. ahd_outb(ahd, HCNT, resid);
  5420. }
  5421. /*
  5422. * Handle the effects of issuing a bus device reset message.
  5423. */
  5424. static void
  5425. ahd_handle_devreset(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
  5426. u_int lun, cam_status status, char *message,
  5427. int verbose_level)
  5428. {
  5429. #ifdef AHD_TARGET_MODE
  5430. struct ahd_tmode_tstate* tstate;
  5431. #endif
  5432. int found;
  5433. found = ahd_abort_scbs(ahd, devinfo->target, devinfo->channel,
  5434. lun, SCB_LIST_NULL, devinfo->role,
  5435. status);
  5436. #ifdef AHD_TARGET_MODE
  5437. /*
  5438. * Send an immediate notify ccb to all target mord peripheral
  5439. * drivers affected by this action.
  5440. */
  5441. tstate = ahd->enabled_targets[devinfo->our_scsiid];
  5442. if (tstate != NULL) {
  5443. u_int cur_lun;
  5444. u_int max_lun;
  5445. if (lun != CAM_LUN_WILDCARD) {
  5446. cur_lun = 0;
  5447. max_lun = AHD_NUM_LUNS - 1;
  5448. } else {
  5449. cur_lun = lun;
  5450. max_lun = lun;
  5451. }
  5452. for (;cur_lun <= max_lun; cur_lun++) {
  5453. struct ahd_tmode_lstate* lstate;
  5454. lstate = tstate->enabled_luns[cur_lun];
  5455. if (lstate == NULL)
  5456. continue;
  5457. ahd_queue_lstate_event(ahd, lstate, devinfo->our_scsiid,
  5458. MSG_BUS_DEV_RESET, /*arg*/0);
  5459. ahd_send_lstate_events(ahd, lstate);
  5460. }
  5461. }
  5462. #endif
  5463. /*
  5464. * Go back to async/narrow transfers and renegotiate.
  5465. */
  5466. ahd_set_width(ahd, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
  5467. AHD_TRANS_CUR, /*paused*/TRUE);
  5468. ahd_set_syncrate(ahd, devinfo, /*period*/0, /*offset*/0,
  5469. /*ppr_options*/0, AHD_TRANS_CUR,
  5470. /*paused*/TRUE);
  5471. if (status != CAM_SEL_TIMEOUT)
  5472. ahd_send_async(ahd, devinfo->channel, devinfo->target,
  5473. CAM_LUN_WILDCARD, AC_SENT_BDR);
  5474. if (message != NULL && bootverbose)
  5475. printk("%s: %s on %c:%d. %d SCBs aborted\n", ahd_name(ahd),
  5476. message, devinfo->channel, devinfo->target, found);
  5477. }
  5478. #ifdef AHD_TARGET_MODE
  5479. static void
  5480. ahd_setup_target_msgin(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
  5481. struct scb *scb)
  5482. {
  5483. /*
  5484. * To facilitate adding multiple messages together,
  5485. * each routine should increment the index and len
  5486. * variables instead of setting them explicitly.
  5487. */
  5488. ahd->msgout_index = 0;
  5489. ahd->msgout_len = 0;
  5490. if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0)
  5491. ahd_build_transfer_msg(ahd, devinfo);
  5492. else
  5493. panic("ahd_intr: AWAITING target message with no message");
  5494. ahd->msgout_index = 0;
  5495. ahd->msg_type = MSG_TYPE_TARGET_MSGIN;
  5496. }
  5497. #endif
  5498. /**************************** Initialization **********************************/
  5499. static u_int
  5500. ahd_sglist_size(struct ahd_softc *ahd)
  5501. {
  5502. bus_size_t list_size;
  5503. list_size = sizeof(struct ahd_dma_seg) * AHD_NSEG;
  5504. if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0)
  5505. list_size = sizeof(struct ahd_dma64_seg) * AHD_NSEG;
  5506. return (list_size);
  5507. }
  5508. /*
  5509. * Calculate the optimum S/G List allocation size. S/G elements used
  5510. * for a given transaction must be physically contiguous. Assume the
  5511. * OS will allocate full pages to us, so it doesn't make sense to request
  5512. * less than a page.
  5513. */
  5514. static u_int
  5515. ahd_sglist_allocsize(struct ahd_softc *ahd)
  5516. {
  5517. bus_size_t sg_list_increment;
  5518. bus_size_t sg_list_size;
  5519. bus_size_t max_list_size;
  5520. bus_size_t best_list_size;
  5521. /* Start out with the minimum required for AHD_NSEG. */
  5522. sg_list_increment = ahd_sglist_size(ahd);
  5523. sg_list_size = sg_list_increment;
  5524. /* Get us as close as possible to a page in size. */
  5525. while ((sg_list_size + sg_list_increment) <= PAGE_SIZE)
  5526. sg_list_size += sg_list_increment;
  5527. /*
  5528. * Try to reduce the amount of wastage by allocating
  5529. * multiple pages.
  5530. */
  5531. best_list_size = sg_list_size;
  5532. max_list_size = roundup(sg_list_increment, PAGE_SIZE);
  5533. if (max_list_size < 4 * PAGE_SIZE)
  5534. max_list_size = 4 * PAGE_SIZE;
  5535. if (max_list_size > (AHD_SCB_MAX_ALLOC * sg_list_increment))
  5536. max_list_size = (AHD_SCB_MAX_ALLOC * sg_list_increment);
  5537. while ((sg_list_size + sg_list_increment) <= max_list_size
  5538. && (sg_list_size % PAGE_SIZE) != 0) {
  5539. bus_size_t new_mod;
  5540. bus_size_t best_mod;
  5541. sg_list_size += sg_list_increment;
  5542. new_mod = sg_list_size % PAGE_SIZE;
  5543. best_mod = best_list_size % PAGE_SIZE;
  5544. if (new_mod > best_mod || new_mod == 0) {
  5545. best_list_size = sg_list_size;
  5546. }
  5547. }
  5548. return (best_list_size);
  5549. }
  5550. /*
  5551. * Allocate a controller structure for a new device
  5552. * and perform initial initializion.
  5553. */
  5554. struct ahd_softc *
  5555. ahd_alloc(void *platform_arg, char *name)
  5556. {
  5557. struct ahd_softc *ahd;
  5558. #ifndef __FreeBSD__
  5559. ahd = kmalloc(sizeof(*ahd), GFP_ATOMIC);
  5560. if (!ahd) {
  5561. printk("aic7xxx: cannot malloc softc!\n");
  5562. kfree(name);
  5563. return NULL;
  5564. }
  5565. #else
  5566. ahd = device_get_softc((device_t)platform_arg);
  5567. #endif
  5568. memset(ahd, 0, sizeof(*ahd));
  5569. ahd->seep_config = kmalloc(sizeof(*ahd->seep_config), GFP_ATOMIC);
  5570. if (ahd->seep_config == NULL) {
  5571. #ifndef __FreeBSD__
  5572. kfree(ahd);
  5573. #endif
  5574. kfree(name);
  5575. return (NULL);
  5576. }
  5577. LIST_INIT(&ahd->pending_scbs);
  5578. /* We don't know our unit number until the OSM sets it */
  5579. ahd->name = name;
  5580. ahd->unit = -1;
  5581. ahd->description = NULL;
  5582. ahd->bus_description = NULL;
  5583. ahd->channel = 'A';
  5584. ahd->chip = AHD_NONE;
  5585. ahd->features = AHD_FENONE;
  5586. ahd->bugs = AHD_BUGNONE;
  5587. ahd->flags = AHD_SPCHK_ENB_A|AHD_RESET_BUS_A|AHD_TERM_ENB_A
  5588. | AHD_EXTENDED_TRANS_A|AHD_STPWLEVEL_A;
  5589. timer_setup(&ahd->stat_timer, ahd_stat_timer, 0);
  5590. ahd->int_coalescing_timer = AHD_INT_COALESCING_TIMER_DEFAULT;
  5591. ahd->int_coalescing_maxcmds = AHD_INT_COALESCING_MAXCMDS_DEFAULT;
  5592. ahd->int_coalescing_mincmds = AHD_INT_COALESCING_MINCMDS_DEFAULT;
  5593. ahd->int_coalescing_threshold = AHD_INT_COALESCING_THRESHOLD_DEFAULT;
  5594. ahd->int_coalescing_stop_threshold =
  5595. AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT;
  5596. #ifdef AHD_DEBUG
  5597. if ((ahd_debug & AHD_SHOW_MEMORY) != 0) {
  5598. printk("%s: scb size = 0x%x, hscb size = 0x%x\n",
  5599. ahd_name(ahd), (u_int)sizeof(struct scb),
  5600. (u_int)sizeof(struct hardware_scb));
  5601. }
  5602. #endif
  5603. if (ahd_platform_alloc(ahd, platform_arg) != 0) {
  5604. ahd_free(ahd);
  5605. ahd = NULL;
  5606. }
  5607. return (ahd);
  5608. }
  5609. int
  5610. ahd_softc_init(struct ahd_softc *ahd)
  5611. {
  5612. ahd->unpause = 0;
  5613. ahd->pause = PAUSE;
  5614. return (0);
  5615. }
  5616. void
  5617. ahd_set_unit(struct ahd_softc *ahd, int unit)
  5618. {
  5619. ahd->unit = unit;
  5620. }
  5621. void
  5622. ahd_set_name(struct ahd_softc *ahd, char *name)
  5623. {
  5624. if (ahd->name != NULL)
  5625. kfree(ahd->name);
  5626. ahd->name = name;
  5627. }
  5628. void
  5629. ahd_free(struct ahd_softc *ahd)
  5630. {
  5631. int i;
  5632. switch (ahd->init_level) {
  5633. default:
  5634. case 5:
  5635. ahd_shutdown(ahd);
  5636. /* FALLTHROUGH */
  5637. case 4:
  5638. ahd_dmamap_unload(ahd, ahd->shared_data_dmat,
  5639. ahd->shared_data_map.dmamap);
  5640. /* FALLTHROUGH */
  5641. case 3:
  5642. ahd_dmamem_free(ahd, ahd->shared_data_dmat, ahd->qoutfifo,
  5643. ahd->shared_data_map.dmamap);
  5644. ahd_dmamap_destroy(ahd, ahd->shared_data_dmat,
  5645. ahd->shared_data_map.dmamap);
  5646. /* FALLTHROUGH */
  5647. case 2:
  5648. ahd_dma_tag_destroy(ahd, ahd->shared_data_dmat);
  5649. case 1:
  5650. #ifndef __linux__
  5651. ahd_dma_tag_destroy(ahd, ahd->buffer_dmat);
  5652. #endif
  5653. break;
  5654. case 0:
  5655. break;
  5656. }
  5657. #ifndef __linux__
  5658. ahd_dma_tag_destroy(ahd, ahd->parent_dmat);
  5659. #endif
  5660. ahd_platform_free(ahd);
  5661. ahd_fini_scbdata(ahd);
  5662. for (i = 0; i < AHD_NUM_TARGETS; i++) {
  5663. struct ahd_tmode_tstate *tstate;
  5664. tstate = ahd->enabled_targets[i];
  5665. if (tstate != NULL) {
  5666. #ifdef AHD_TARGET_MODE
  5667. int j;
  5668. for (j = 0; j < AHD_NUM_LUNS; j++) {
  5669. struct ahd_tmode_lstate *lstate;
  5670. lstate = tstate->enabled_luns[j];
  5671. if (lstate != NULL) {
  5672. xpt_free_path(lstate->path);
  5673. kfree(lstate);
  5674. }
  5675. }
  5676. #endif
  5677. kfree(tstate);
  5678. }
  5679. }
  5680. #ifdef AHD_TARGET_MODE
  5681. if (ahd->black_hole != NULL) {
  5682. xpt_free_path(ahd->black_hole->path);
  5683. kfree(ahd->black_hole);
  5684. }
  5685. #endif
  5686. if (ahd->name != NULL)
  5687. kfree(ahd->name);
  5688. if (ahd->seep_config != NULL)
  5689. kfree(ahd->seep_config);
  5690. if (ahd->saved_stack != NULL)
  5691. kfree(ahd->saved_stack);
  5692. #ifndef __FreeBSD__
  5693. kfree(ahd);
  5694. #endif
  5695. return;
  5696. }
  5697. static void
  5698. ahd_shutdown(void *arg)
  5699. {
  5700. struct ahd_softc *ahd;
  5701. ahd = (struct ahd_softc *)arg;
  5702. /*
  5703. * Stop periodic timer callbacks.
  5704. */
  5705. del_timer_sync(&ahd->stat_timer);
  5706. /* This will reset most registers to 0, but not all */
  5707. ahd_reset(ahd, /*reinit*/FALSE);
  5708. }
  5709. /*
  5710. * Reset the controller and record some information about it
  5711. * that is only available just after a reset. If "reinit" is
  5712. * non-zero, this reset occurred after initial configuration
  5713. * and the caller requests that the chip be fully reinitialized
  5714. * to a runable state. Chip interrupts are *not* enabled after
  5715. * a reinitialization. The caller must enable interrupts via
  5716. * ahd_intr_enable().
  5717. */
  5718. int
  5719. ahd_reset(struct ahd_softc *ahd, int reinit)
  5720. {
  5721. u_int sxfrctl1;
  5722. int wait;
  5723. uint32_t cmd;
  5724. /*
  5725. * Preserve the value of the SXFRCTL1 register for all channels.
  5726. * It contains settings that affect termination and we don't want
  5727. * to disturb the integrity of the bus.
  5728. */
  5729. ahd_pause(ahd);
  5730. ahd_update_modes(ahd);
  5731. ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
  5732. sxfrctl1 = ahd_inb(ahd, SXFRCTL1);
  5733. cmd = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2);
  5734. if ((ahd->bugs & AHD_PCIX_CHIPRST_BUG) != 0) {
  5735. uint32_t mod_cmd;
  5736. /*
  5737. * A4 Razor #632
  5738. * During the assertion of CHIPRST, the chip
  5739. * does not disable its parity logic prior to
  5740. * the start of the reset. This may cause a
  5741. * parity error to be detected and thus a
  5742. * spurious SERR or PERR assertion. Disable
  5743. * PERR and SERR responses during the CHIPRST.
  5744. */
  5745. mod_cmd = cmd & ~(PCIM_CMD_PERRESPEN|PCIM_CMD_SERRESPEN);
  5746. ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
  5747. mod_cmd, /*bytes*/2);
  5748. }
  5749. ahd_outb(ahd, HCNTRL, CHIPRST | ahd->pause);
  5750. /*
  5751. * Ensure that the reset has finished. We delay 1000us
  5752. * prior to reading the register to make sure the chip
  5753. * has sufficiently completed its reset to handle register
  5754. * accesses.
  5755. */
  5756. wait = 1000;
  5757. do {
  5758. ahd_delay(1000);
  5759. } while (--wait && !(ahd_inb(ahd, HCNTRL) & CHIPRSTACK));
  5760. if (wait == 0) {
  5761. printk("%s: WARNING - Failed chip reset! "
  5762. "Trying to initialize anyway.\n", ahd_name(ahd));
  5763. }
  5764. ahd_outb(ahd, HCNTRL, ahd->pause);
  5765. if ((ahd->bugs & AHD_PCIX_CHIPRST_BUG) != 0) {
  5766. /*
  5767. * Clear any latched PCI error status and restore
  5768. * previous SERR and PERR response enables.
  5769. */
  5770. ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
  5771. 0xFF, /*bytes*/1);
  5772. ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
  5773. cmd, /*bytes*/2);
  5774. }
  5775. /*
  5776. * Mode should be SCSI after a chip reset, but lets
  5777. * set it just to be safe. We touch the MODE_PTR
  5778. * register directly so as to bypass the lazy update
  5779. * code in ahd_set_modes().
  5780. */
  5781. ahd_known_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
  5782. ahd_outb(ahd, MODE_PTR,
  5783. ahd_build_mode_state(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI));
  5784. /*
  5785. * Restore SXFRCTL1.
  5786. *
  5787. * We must always initialize STPWEN to 1 before we
  5788. * restore the saved values. STPWEN is initialized
  5789. * to a tri-state condition which can only be cleared
  5790. * by turning it on.
  5791. */
  5792. ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN);
  5793. ahd_outb(ahd, SXFRCTL1, sxfrctl1);
  5794. /* Determine chip configuration */
  5795. ahd->features &= ~AHD_WIDE;
  5796. if ((ahd_inb(ahd, SBLKCTL) & SELWIDE) != 0)
  5797. ahd->features |= AHD_WIDE;
  5798. /*
  5799. * If a recovery action has forced a chip reset,
  5800. * re-initialize the chip to our liking.
  5801. */
  5802. if (reinit != 0)
  5803. ahd_chip_init(ahd);
  5804. return (0);
  5805. }
  5806. /*
  5807. * Determine the number of SCBs available on the controller
  5808. */
  5809. static int
  5810. ahd_probe_scbs(struct ahd_softc *ahd) {
  5811. int i;
  5812. AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
  5813. ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
  5814. for (i = 0; i < AHD_SCB_MAX; i++) {
  5815. int j;
  5816. ahd_set_scbptr(ahd, i);
  5817. ahd_outw(ahd, SCB_BASE, i);
  5818. for (j = 2; j < 64; j++)
  5819. ahd_outb(ahd, SCB_BASE+j, 0);
  5820. /* Start out life as unallocated (needing an abort) */
  5821. ahd_outb(ahd, SCB_CONTROL, MK_MESSAGE);
  5822. if (ahd_inw_scbram(ahd, SCB_BASE) != i)
  5823. break;
  5824. ahd_set_scbptr(ahd, 0);
  5825. if (ahd_inw_scbram(ahd, SCB_BASE) != 0)
  5826. break;
  5827. }
  5828. return (i);
  5829. }
  5830. static void
  5831. ahd_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
  5832. {
  5833. dma_addr_t *baddr;
  5834. baddr = (dma_addr_t *)arg;
  5835. *baddr = segs->ds_addr;
  5836. }
  5837. static void
  5838. ahd_initialize_hscbs(struct ahd_softc *ahd)
  5839. {
  5840. int i;
  5841. for (i = 0; i < ahd->scb_data.maxhscbs; i++) {
  5842. ahd_set_scbptr(ahd, i);
  5843. /* Clear the control byte. */
  5844. ahd_outb(ahd, SCB_CONTROL, 0);
  5845. /* Set the next pointer */
  5846. ahd_outw(ahd, SCB_NEXT, SCB_LIST_NULL);
  5847. }
  5848. }
  5849. static int
  5850. ahd_init_scbdata(struct ahd_softc *ahd)
  5851. {
  5852. struct scb_data *scb_data;
  5853. int i;
  5854. scb_data = &ahd->scb_data;
  5855. TAILQ_INIT(&scb_data->free_scbs);
  5856. for (i = 0; i < AHD_NUM_TARGETS * AHD_NUM_LUNS_NONPKT; i++)
  5857. LIST_INIT(&scb_data->free_scb_lists[i]);
  5858. LIST_INIT(&scb_data->any_dev_free_scb_list);
  5859. SLIST_INIT(&scb_data->hscb_maps);
  5860. SLIST_INIT(&scb_data->sg_maps);
  5861. SLIST_INIT(&scb_data->sense_maps);
  5862. /* Determine the number of hardware SCBs and initialize them */
  5863. scb_data->maxhscbs = ahd_probe_scbs(ahd);
  5864. if (scb_data->maxhscbs == 0) {
  5865. printk("%s: No SCB space found\n", ahd_name(ahd));
  5866. return (ENXIO);
  5867. }
  5868. ahd_initialize_hscbs(ahd);
  5869. /*
  5870. * Create our DMA tags. These tags define the kinds of device
  5871. * accessible memory allocations and memory mappings we will
  5872. * need to perform during normal operation.
  5873. *
  5874. * Unless we need to further restrict the allocation, we rely
  5875. * on the restrictions of the parent dmat, hence the common
  5876. * use of MAXADDR and MAXSIZE.
  5877. */
  5878. /* DMA tag for our hardware scb structures */
  5879. if (ahd_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1,
  5880. /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
  5881. /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
  5882. /*highaddr*/BUS_SPACE_MAXADDR,
  5883. /*filter*/NULL, /*filterarg*/NULL,
  5884. PAGE_SIZE, /*nsegments*/1,
  5885. /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
  5886. /*flags*/0, &scb_data->hscb_dmat) != 0) {
  5887. goto error_exit;
  5888. }
  5889. scb_data->init_level++;
  5890. /* DMA tag for our S/G structures. */
  5891. if (ahd_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/8,
  5892. /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
  5893. /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
  5894. /*highaddr*/BUS_SPACE_MAXADDR,
  5895. /*filter*/NULL, /*filterarg*/NULL,
  5896. ahd_sglist_allocsize(ahd), /*nsegments*/1,
  5897. /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
  5898. /*flags*/0, &scb_data->sg_dmat) != 0) {
  5899. goto error_exit;
  5900. }
  5901. #ifdef AHD_DEBUG
  5902. if ((ahd_debug & AHD_SHOW_MEMORY) != 0)
  5903. printk("%s: ahd_sglist_allocsize = 0x%x\n", ahd_name(ahd),
  5904. ahd_sglist_allocsize(ahd));
  5905. #endif
  5906. scb_data->init_level++;
  5907. /* DMA tag for our sense buffers. We allocate in page sized chunks */
  5908. if (ahd_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1,
  5909. /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
  5910. /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
  5911. /*highaddr*/BUS_SPACE_MAXADDR,
  5912. /*filter*/NULL, /*filterarg*/NULL,
  5913. PAGE_SIZE, /*nsegments*/1,
  5914. /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
  5915. /*flags*/0, &scb_data->sense_dmat) != 0) {
  5916. goto error_exit;
  5917. }
  5918. scb_data->init_level++;
  5919. /* Perform initial CCB allocation */
  5920. ahd_alloc_scbs(ahd);
  5921. if (scb_data->numscbs == 0) {
  5922. printk("%s: ahd_init_scbdata - "
  5923. "Unable to allocate initial scbs\n",
  5924. ahd_name(ahd));
  5925. goto error_exit;
  5926. }
  5927. /*
  5928. * Note that we were successful
  5929. */
  5930. return (0);
  5931. error_exit:
  5932. return (ENOMEM);
  5933. }
  5934. static struct scb *
  5935. ahd_find_scb_by_tag(struct ahd_softc *ahd, u_int tag)
  5936. {
  5937. struct scb *scb;
  5938. /*
  5939. * Look on the pending list.
  5940. */
  5941. LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) {
  5942. if (SCB_GET_TAG(scb) == tag)
  5943. return (scb);
  5944. }
  5945. /*
  5946. * Then on all of the collision free lists.
  5947. */
  5948. TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) {
  5949. struct scb *list_scb;
  5950. list_scb = scb;
  5951. do {
  5952. if (SCB_GET_TAG(list_scb) == tag)
  5953. return (list_scb);
  5954. list_scb = LIST_NEXT(list_scb, collision_links);
  5955. } while (list_scb);
  5956. }
  5957. /*
  5958. * And finally on the generic free list.
  5959. */
  5960. LIST_FOREACH(scb, &ahd->scb_data.any_dev_free_scb_list, links.le) {
  5961. if (SCB_GET_TAG(scb) == tag)
  5962. return (scb);
  5963. }
  5964. return (NULL);
  5965. }
  5966. static void
  5967. ahd_fini_scbdata(struct ahd_softc *ahd)
  5968. {
  5969. struct scb_data *scb_data;
  5970. scb_data = &ahd->scb_data;
  5971. if (scb_data == NULL)
  5972. return;
  5973. switch (scb_data->init_level) {
  5974. default:
  5975. case 7:
  5976. {
  5977. struct map_node *sns_map;
  5978. while ((sns_map = SLIST_FIRST(&scb_data->sense_maps)) != NULL) {
  5979. SLIST_REMOVE_HEAD(&scb_data->sense_maps, links);
  5980. ahd_dmamap_unload(ahd, scb_data->sense_dmat,
  5981. sns_map->dmamap);
  5982. ahd_dmamem_free(ahd, scb_data->sense_dmat,
  5983. sns_map->vaddr, sns_map->dmamap);
  5984. kfree(sns_map);
  5985. }
  5986. ahd_dma_tag_destroy(ahd, scb_data->sense_dmat);
  5987. /* FALLTHROUGH */
  5988. }
  5989. case 6:
  5990. {
  5991. struct map_node *sg_map;
  5992. while ((sg_map = SLIST_FIRST(&scb_data->sg_maps)) != NULL) {
  5993. SLIST_REMOVE_HEAD(&scb_data->sg_maps, links);
  5994. ahd_dmamap_unload(ahd, scb_data->sg_dmat,
  5995. sg_map->dmamap);
  5996. ahd_dmamem_free(ahd, scb_data->sg_dmat,
  5997. sg_map->vaddr, sg_map->dmamap);
  5998. kfree(sg_map);
  5999. }
  6000. ahd_dma_tag_destroy(ahd, scb_data->sg_dmat);
  6001. /* FALLTHROUGH */
  6002. }
  6003. case 5:
  6004. {
  6005. struct map_node *hscb_map;
  6006. while ((hscb_map = SLIST_FIRST(&scb_data->hscb_maps)) != NULL) {
  6007. SLIST_REMOVE_HEAD(&scb_data->hscb_maps, links);
  6008. ahd_dmamap_unload(ahd, scb_data->hscb_dmat,
  6009. hscb_map->dmamap);
  6010. ahd_dmamem_free(ahd, scb_data->hscb_dmat,
  6011. hscb_map->vaddr, hscb_map->dmamap);
  6012. kfree(hscb_map);
  6013. }
  6014. ahd_dma_tag_destroy(ahd, scb_data->hscb_dmat);
  6015. /* FALLTHROUGH */
  6016. }
  6017. case 4:
  6018. case 3:
  6019. case 2:
  6020. case 1:
  6021. case 0:
  6022. break;
  6023. }
  6024. }
  6025. /*
  6026. * DSP filter Bypass must be enabled until the first selection
  6027. * after a change in bus mode (Razor #491 and #493).
  6028. */
  6029. static void
  6030. ahd_setup_iocell_workaround(struct ahd_softc *ahd)
  6031. {
  6032. ahd_mode_state saved_modes;
  6033. saved_modes = ahd_save_modes(ahd);
  6034. ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
  6035. ahd_outb(ahd, DSPDATACTL, ahd_inb(ahd, DSPDATACTL)
  6036. | BYPASSENAB | RCVROFFSTDIS | XMITOFFSTDIS);
  6037. ahd_outb(ahd, SIMODE0, ahd_inb(ahd, SIMODE0) | (ENSELDO|ENSELDI));
  6038. #ifdef AHD_DEBUG
  6039. if ((ahd_debug & AHD_SHOW_MISC) != 0)
  6040. printk("%s: Setting up iocell workaround\n", ahd_name(ahd));
  6041. #endif
  6042. ahd_restore_modes(ahd, saved_modes);
  6043. ahd->flags &= ~AHD_HAD_FIRST_SEL;
  6044. }
  6045. static void
  6046. ahd_iocell_first_selection(struct ahd_softc *ahd)
  6047. {
  6048. ahd_mode_state saved_modes;
  6049. u_int sblkctl;
  6050. if ((ahd->flags & AHD_HAD_FIRST_SEL) != 0)
  6051. return;
  6052. saved_modes = ahd_save_modes(ahd);
  6053. ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
  6054. sblkctl = ahd_inb(ahd, SBLKCTL);
  6055. ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
  6056. #ifdef AHD_DEBUG
  6057. if ((ahd_debug & AHD_SHOW_MISC) != 0)
  6058. printk("%s: iocell first selection\n", ahd_name(ahd));
  6059. #endif
  6060. if ((sblkctl & ENAB40) != 0) {
  6061. ahd_outb(ahd, DSPDATACTL,
  6062. ahd_inb(ahd, DSPDATACTL) & ~BYPASSENAB);
  6063. #ifdef AHD_DEBUG
  6064. if ((ahd_debug & AHD_SHOW_MISC) != 0)
  6065. printk("%s: BYPASS now disabled\n", ahd_name(ahd));
  6066. #endif
  6067. }
  6068. ahd_outb(ahd, SIMODE0, ahd_inb(ahd, SIMODE0) & ~(ENSELDO|ENSELDI));
  6069. ahd_outb(ahd, CLRINT, CLRSCSIINT);
  6070. ahd_restore_modes(ahd, saved_modes);
  6071. ahd->flags |= AHD_HAD_FIRST_SEL;
  6072. }
  6073. /*************************** SCB Management ***********************************/
  6074. static void
  6075. ahd_add_col_list(struct ahd_softc *ahd, struct scb *scb, u_int col_idx)
  6076. {
  6077. struct scb_list *free_list;
  6078. struct scb_tailq *free_tailq;
  6079. struct scb *first_scb;
  6080. scb->flags |= SCB_ON_COL_LIST;
  6081. AHD_SET_SCB_COL_IDX(scb, col_idx);
  6082. free_list = &ahd->scb_data.free_scb_lists[col_idx];
  6083. free_tailq = &ahd->scb_data.free_scbs;
  6084. first_scb = LIST_FIRST(free_list);
  6085. if (first_scb != NULL) {
  6086. LIST_INSERT_AFTER(first_scb, scb, collision_links);
  6087. } else {
  6088. LIST_INSERT_HEAD(free_list, scb, collision_links);
  6089. TAILQ_INSERT_TAIL(free_tailq, scb, links.tqe);
  6090. }
  6091. }
  6092. static void
  6093. ahd_rem_col_list(struct ahd_softc *ahd, struct scb *scb)
  6094. {
  6095. struct scb_list *free_list;
  6096. struct scb_tailq *free_tailq;
  6097. struct scb *first_scb;
  6098. u_int col_idx;
  6099. scb->flags &= ~SCB_ON_COL_LIST;
  6100. col_idx = AHD_GET_SCB_COL_IDX(ahd, scb);
  6101. free_list = &ahd->scb_data.free_scb_lists[col_idx];
  6102. free_tailq = &ahd->scb_data.free_scbs;
  6103. first_scb = LIST_FIRST(free_list);
  6104. if (first_scb == scb) {
  6105. struct scb *next_scb;
  6106. /*
  6107. * Maintain order in the collision free
  6108. * lists for fairness if this device has
  6109. * other colliding tags active.
  6110. */
  6111. next_scb = LIST_NEXT(scb, collision_links);
  6112. if (next_scb != NULL) {
  6113. TAILQ_INSERT_AFTER(free_tailq, scb,
  6114. next_scb, links.tqe);
  6115. }
  6116. TAILQ_REMOVE(free_tailq, scb, links.tqe);
  6117. }
  6118. LIST_REMOVE(scb, collision_links);
  6119. }
  6120. /*
  6121. * Get a free scb. If there are none, see if we can allocate a new SCB.
  6122. */
  6123. struct scb *
  6124. ahd_get_scb(struct ahd_softc *ahd, u_int col_idx)
  6125. {
  6126. struct scb *scb;
  6127. int tries;
  6128. tries = 0;
  6129. look_again:
  6130. TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) {
  6131. if (AHD_GET_SCB_COL_IDX(ahd, scb) != col_idx) {
  6132. ahd_rem_col_list(ahd, scb);
  6133. goto found;
  6134. }
  6135. }
  6136. if ((scb = LIST_FIRST(&ahd->scb_data.any_dev_free_scb_list)) == NULL) {
  6137. if (tries++ != 0)
  6138. return (NULL);
  6139. ahd_alloc_scbs(ahd);
  6140. goto look_again;
  6141. }
  6142. LIST_REMOVE(scb, links.le);
  6143. if (col_idx != AHD_NEVER_COL_IDX
  6144. && (scb->col_scb != NULL)
  6145. && (scb->col_scb->flags & SCB_ACTIVE) == 0) {
  6146. LIST_REMOVE(scb->col_scb, links.le);
  6147. ahd_add_col_list(ahd, scb->col_scb, col_idx);
  6148. }
  6149. found:
  6150. scb->flags |= SCB_ACTIVE;
  6151. return (scb);
  6152. }
  6153. /*
  6154. * Return an SCB resource to the free list.
  6155. */
  6156. void
  6157. ahd_free_scb(struct ahd_softc *ahd, struct scb *scb)
  6158. {
  6159. /* Clean up for the next user */
  6160. scb->flags = SCB_FLAG_NONE;
  6161. scb->hscb->control = 0;
  6162. ahd->scb_data.scbindex[SCB_GET_TAG(scb)] = NULL;
  6163. if (scb->col_scb == NULL) {
  6164. /*
  6165. * No collision possible. Just free normally.
  6166. */
  6167. LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list,
  6168. scb, links.le);
  6169. } else if ((scb->col_scb->flags & SCB_ON_COL_LIST) != 0) {
  6170. /*
  6171. * The SCB we might have collided with is on
  6172. * a free collision list. Put both SCBs on
  6173. * the generic list.
  6174. */
  6175. ahd_rem_col_list(ahd, scb->col_scb);
  6176. LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list,
  6177. scb, links.le);
  6178. LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list,
  6179. scb->col_scb, links.le);
  6180. } else if ((scb->col_scb->flags
  6181. & (SCB_PACKETIZED|SCB_ACTIVE)) == SCB_ACTIVE
  6182. && (scb->col_scb->hscb->control & TAG_ENB) != 0) {
  6183. /*
  6184. * The SCB we might collide with on the next allocation
  6185. * is still active in a non-packetized, tagged, context.
  6186. * Put us on the SCB collision list.
  6187. */
  6188. ahd_add_col_list(ahd, scb,
  6189. AHD_GET_SCB_COL_IDX(ahd, scb->col_scb));
  6190. } else {
  6191. /*
  6192. * The SCB we might collide with on the next allocation
  6193. * is either active in a packetized context, or free.
  6194. * Since we can't collide, put this SCB on the generic
  6195. * free list.
  6196. */
  6197. LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list,
  6198. scb, links.le);
  6199. }
  6200. ahd_platform_scb_free(ahd, scb);
  6201. }
  6202. static void
  6203. ahd_alloc_scbs(struct ahd_softc *ahd)
  6204. {
  6205. struct scb_data *scb_data;
  6206. struct scb *next_scb;
  6207. struct hardware_scb *hscb;
  6208. struct map_node *hscb_map;
  6209. struct map_node *sg_map;
  6210. struct map_node *sense_map;
  6211. uint8_t *segs;
  6212. uint8_t *sense_data;
  6213. dma_addr_t hscb_busaddr;
  6214. dma_addr_t sg_busaddr;
  6215. dma_addr_t sense_busaddr;
  6216. int newcount;
  6217. int i;
  6218. scb_data = &ahd->scb_data;
  6219. if (scb_data->numscbs >= AHD_SCB_MAX_ALLOC)
  6220. /* Can't allocate any more */
  6221. return;
  6222. if (scb_data->scbs_left != 0) {
  6223. int offset;
  6224. offset = (PAGE_SIZE / sizeof(*hscb)) - scb_data->scbs_left;
  6225. hscb_map = SLIST_FIRST(&scb_data->hscb_maps);
  6226. hscb = &((struct hardware_scb *)hscb_map->vaddr)[offset];
  6227. hscb_busaddr = hscb_map->physaddr + (offset * sizeof(*hscb));
  6228. } else {
  6229. hscb_map = kmalloc(sizeof(*hscb_map), GFP_ATOMIC);
  6230. if (hscb_map == NULL)
  6231. return;
  6232. /* Allocate the next batch of hardware SCBs */
  6233. if (ahd_dmamem_alloc(ahd, scb_data->hscb_dmat,
  6234. (void **)&hscb_map->vaddr,
  6235. BUS_DMA_NOWAIT, &hscb_map->dmamap) != 0) {
  6236. kfree(hscb_map);
  6237. return;
  6238. }
  6239. SLIST_INSERT_HEAD(&scb_data->hscb_maps, hscb_map, links);
  6240. ahd_dmamap_load(ahd, scb_data->hscb_dmat, hscb_map->dmamap,
  6241. hscb_map->vaddr, PAGE_SIZE, ahd_dmamap_cb,
  6242. &hscb_map->physaddr, /*flags*/0);
  6243. hscb = (struct hardware_scb *)hscb_map->vaddr;
  6244. hscb_busaddr = hscb_map->physaddr;
  6245. scb_data->scbs_left = PAGE_SIZE / sizeof(*hscb);
  6246. }
  6247. if (scb_data->sgs_left != 0) {
  6248. int offset;
  6249. offset = ((ahd_sglist_allocsize(ahd) / ahd_sglist_size(ahd))
  6250. - scb_data->sgs_left) * ahd_sglist_size(ahd);
  6251. sg_map = SLIST_FIRST(&scb_data->sg_maps);
  6252. segs = sg_map->vaddr + offset;
  6253. sg_busaddr = sg_map->physaddr + offset;
  6254. } else {
  6255. sg_map = kmalloc(sizeof(*sg_map), GFP_ATOMIC);
  6256. if (sg_map == NULL)
  6257. return;
  6258. /* Allocate the next batch of S/G lists */
  6259. if (ahd_dmamem_alloc(ahd, scb_data->sg_dmat,
  6260. (void **)&sg_map->vaddr,
  6261. BUS_DMA_NOWAIT, &sg_map->dmamap) != 0) {
  6262. kfree(sg_map);
  6263. return;
  6264. }
  6265. SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links);
  6266. ahd_dmamap_load(ahd, scb_data->sg_dmat, sg_map->dmamap,
  6267. sg_map->vaddr, ahd_sglist_allocsize(ahd),
  6268. ahd_dmamap_cb, &sg_map->physaddr, /*flags*/0);
  6269. segs = sg_map->vaddr;
  6270. sg_busaddr = sg_map->physaddr;
  6271. scb_data->sgs_left =
  6272. ahd_sglist_allocsize(ahd) / ahd_sglist_size(ahd);
  6273. #ifdef AHD_DEBUG
  6274. if (ahd_debug & AHD_SHOW_MEMORY)
  6275. printk("Mapped SG data\n");
  6276. #endif
  6277. }
  6278. if (scb_data->sense_left != 0) {
  6279. int offset;
  6280. offset = PAGE_SIZE - (AHD_SENSE_BUFSIZE * scb_data->sense_left);
  6281. sense_map = SLIST_FIRST(&scb_data->sense_maps);
  6282. sense_data = sense_map->vaddr + offset;
  6283. sense_busaddr = sense_map->physaddr + offset;
  6284. } else {
  6285. sense_map = kmalloc(sizeof(*sense_map), GFP_ATOMIC);
  6286. if (sense_map == NULL)
  6287. return;
  6288. /* Allocate the next batch of sense buffers */
  6289. if (ahd_dmamem_alloc(ahd, scb_data->sense_dmat,
  6290. (void **)&sense_map->vaddr,
  6291. BUS_DMA_NOWAIT, &sense_map->dmamap) != 0) {
  6292. kfree(sense_map);
  6293. return;
  6294. }
  6295. SLIST_INSERT_HEAD(&scb_data->sense_maps, sense_map, links);
  6296. ahd_dmamap_load(ahd, scb_data->sense_dmat, sense_map->dmamap,
  6297. sense_map->vaddr, PAGE_SIZE, ahd_dmamap_cb,
  6298. &sense_map->physaddr, /*flags*/0);
  6299. sense_data = sense_map->vaddr;
  6300. sense_busaddr = sense_map->physaddr;
  6301. scb_data->sense_left = PAGE_SIZE / AHD_SENSE_BUFSIZE;
  6302. #ifdef AHD_DEBUG
  6303. if (ahd_debug & AHD_SHOW_MEMORY)
  6304. printk("Mapped sense data\n");
  6305. #endif
  6306. }
  6307. newcount = min(scb_data->sense_left, scb_data->scbs_left);
  6308. newcount = min(newcount, scb_data->sgs_left);
  6309. newcount = min(newcount, (AHD_SCB_MAX_ALLOC - scb_data->numscbs));
  6310. for (i = 0; i < newcount; i++) {
  6311. struct scb_platform_data *pdata;
  6312. u_int col_tag;
  6313. #ifndef __linux__
  6314. int error;
  6315. #endif
  6316. next_scb = kmalloc(sizeof(*next_scb), GFP_ATOMIC);
  6317. if (next_scb == NULL)
  6318. break;
  6319. pdata = kmalloc(sizeof(*pdata), GFP_ATOMIC);
  6320. if (pdata == NULL) {
  6321. kfree(next_scb);
  6322. break;
  6323. }
  6324. next_scb->platform_data = pdata;
  6325. next_scb->hscb_map = hscb_map;
  6326. next_scb->sg_map = sg_map;
  6327. next_scb->sense_map = sense_map;
  6328. next_scb->sg_list = segs;
  6329. next_scb->sense_data = sense_data;
  6330. next_scb->sense_busaddr = sense_busaddr;
  6331. memset(hscb, 0, sizeof(*hscb));
  6332. next_scb->hscb = hscb;
  6333. hscb->hscb_busaddr = ahd_htole32(hscb_busaddr);
  6334. /*
  6335. * The sequencer always starts with the second entry.
  6336. * The first entry is embedded in the scb.
  6337. */
  6338. next_scb->sg_list_busaddr = sg_busaddr;
  6339. if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0)
  6340. next_scb->sg_list_busaddr
  6341. += sizeof(struct ahd_dma64_seg);
  6342. else
  6343. next_scb->sg_list_busaddr += sizeof(struct ahd_dma_seg);
  6344. next_scb->ahd_softc = ahd;
  6345. next_scb->flags = SCB_FLAG_NONE;
  6346. #ifndef __linux__
  6347. error = ahd_dmamap_create(ahd, ahd->buffer_dmat, /*flags*/0,
  6348. &next_scb->dmamap);
  6349. if (error != 0) {
  6350. kfree(next_scb);
  6351. kfree(pdata);
  6352. break;
  6353. }
  6354. #endif
  6355. next_scb->hscb->tag = ahd_htole16(scb_data->numscbs);
  6356. col_tag = scb_data->numscbs ^ 0x100;
  6357. next_scb->col_scb = ahd_find_scb_by_tag(ahd, col_tag);
  6358. if (next_scb->col_scb != NULL)
  6359. next_scb->col_scb->col_scb = next_scb;
  6360. ahd_free_scb(ahd, next_scb);
  6361. hscb++;
  6362. hscb_busaddr += sizeof(*hscb);
  6363. segs += ahd_sglist_size(ahd);
  6364. sg_busaddr += ahd_sglist_size(ahd);
  6365. sense_data += AHD_SENSE_BUFSIZE;
  6366. sense_busaddr += AHD_SENSE_BUFSIZE;
  6367. scb_data->numscbs++;
  6368. scb_data->sense_left--;
  6369. scb_data->scbs_left--;
  6370. scb_data->sgs_left--;
  6371. }
  6372. }
  6373. void
  6374. ahd_controller_info(struct ahd_softc *ahd, char *buf)
  6375. {
  6376. const char *speed;
  6377. const char *type;
  6378. int len;
  6379. len = sprintf(buf, "%s: ", ahd_chip_names[ahd->chip & AHD_CHIPID_MASK]);
  6380. buf += len;
  6381. speed = "Ultra320 ";
  6382. if ((ahd->features & AHD_WIDE) != 0) {
  6383. type = "Wide ";
  6384. } else {
  6385. type = "Single ";
  6386. }
  6387. len = sprintf(buf, "%s%sChannel %c, SCSI Id=%d, ",
  6388. speed, type, ahd->channel, ahd->our_id);
  6389. buf += len;
  6390. sprintf(buf, "%s, %d SCBs", ahd->bus_description,
  6391. ahd->scb_data.maxhscbs);
  6392. }
  6393. static const char *channel_strings[] = {
  6394. "Primary Low",
  6395. "Primary High",
  6396. "Secondary Low",
  6397. "Secondary High"
  6398. };
  6399. static const char *termstat_strings[] = {
  6400. "Terminated Correctly",
  6401. "Over Terminated",
  6402. "Under Terminated",
  6403. "Not Configured"
  6404. };
  6405. /***************************** Timer Facilities *******************************/
  6406. static void
  6407. ahd_timer_reset(struct timer_list *timer, int usec)
  6408. {
  6409. del_timer(timer);
  6410. timer->expires = jiffies + (usec * HZ)/1000000;
  6411. add_timer(timer);
  6412. }
  6413. /*
  6414. * Start the board, ready for normal operation
  6415. */
  6416. int
  6417. ahd_init(struct ahd_softc *ahd)
  6418. {
  6419. uint8_t *next_vaddr;
  6420. dma_addr_t next_baddr;
  6421. size_t driver_data_size;
  6422. int i;
  6423. int error;
  6424. u_int warn_user;
  6425. uint8_t current_sensing;
  6426. uint8_t fstat;
  6427. AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
  6428. ahd->stack_size = ahd_probe_stack_size(ahd);
  6429. ahd->saved_stack = kmalloc_array(ahd->stack_size, sizeof(uint16_t),
  6430. GFP_ATOMIC);
  6431. if (ahd->saved_stack == NULL)
  6432. return (ENOMEM);
  6433. /*
  6434. * Verify that the compiler hasn't over-aggressively
  6435. * padded important structures.
  6436. */
  6437. if (sizeof(struct hardware_scb) != 64)
  6438. panic("Hardware SCB size is incorrect");
  6439. #ifdef AHD_DEBUG
  6440. if ((ahd_debug & AHD_DEBUG_SEQUENCER) != 0)
  6441. ahd->flags |= AHD_SEQUENCER_DEBUG;
  6442. #endif
  6443. /*
  6444. * Default to allowing initiator operations.
  6445. */
  6446. ahd->flags |= AHD_INITIATORROLE;
  6447. /*
  6448. * Only allow target mode features if this unit has them enabled.
  6449. */
  6450. if ((AHD_TMODE_ENABLE & (0x1 << ahd->unit)) == 0)
  6451. ahd->features &= ~AHD_TARGETMODE;
  6452. #ifndef __linux__
  6453. /* DMA tag for mapping buffers into device visible space. */
  6454. if (ahd_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1,
  6455. /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
  6456. /*lowaddr*/ahd->flags & AHD_39BIT_ADDRESSING
  6457. ? (dma_addr_t)0x7FFFFFFFFFULL
  6458. : BUS_SPACE_MAXADDR_32BIT,
  6459. /*highaddr*/BUS_SPACE_MAXADDR,
  6460. /*filter*/NULL, /*filterarg*/NULL,
  6461. /*maxsize*/(AHD_NSEG - 1) * PAGE_SIZE,
  6462. /*nsegments*/AHD_NSEG,
  6463. /*maxsegsz*/AHD_MAXTRANSFER_SIZE,
  6464. /*flags*/BUS_DMA_ALLOCNOW,
  6465. &ahd->buffer_dmat) != 0) {
  6466. return (ENOMEM);
  6467. }
  6468. #endif
  6469. ahd->init_level++;
  6470. /*
  6471. * DMA tag for our command fifos and other data in system memory
  6472. * the card's sequencer must be able to access. For initiator
  6473. * roles, we need to allocate space for the qoutfifo. When providing
  6474. * for the target mode role, we must additionally provide space for
  6475. * the incoming target command fifo.
  6476. */
  6477. driver_data_size = AHD_SCB_MAX * sizeof(*ahd->qoutfifo)
  6478. + sizeof(struct hardware_scb);
  6479. if ((ahd->features & AHD_TARGETMODE) != 0)
  6480. driver_data_size += AHD_TMODE_CMDS * sizeof(struct target_cmd);
  6481. if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0)
  6482. driver_data_size += PKT_OVERRUN_BUFSIZE;
  6483. if (ahd_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1,
  6484. /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
  6485. /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
  6486. /*highaddr*/BUS_SPACE_MAXADDR,
  6487. /*filter*/NULL, /*filterarg*/NULL,
  6488. driver_data_size,
  6489. /*nsegments*/1,
  6490. /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
  6491. /*flags*/0, &ahd->shared_data_dmat) != 0) {
  6492. return (ENOMEM);
  6493. }
  6494. ahd->init_level++;
  6495. /* Allocation of driver data */
  6496. if (ahd_dmamem_alloc(ahd, ahd->shared_data_dmat,
  6497. (void **)&ahd->shared_data_map.vaddr,
  6498. BUS_DMA_NOWAIT,
  6499. &ahd->shared_data_map.dmamap) != 0) {
  6500. return (ENOMEM);
  6501. }
  6502. ahd->init_level++;
  6503. /* And permanently map it in */
  6504. ahd_dmamap_load(ahd, ahd->shared_data_dmat, ahd->shared_data_map.dmamap,
  6505. ahd->shared_data_map.vaddr, driver_data_size,
  6506. ahd_dmamap_cb, &ahd->shared_data_map.physaddr,
  6507. /*flags*/0);
  6508. ahd->qoutfifo = (struct ahd_completion *)ahd->shared_data_map.vaddr;
  6509. next_vaddr = (uint8_t *)&ahd->qoutfifo[AHD_QOUT_SIZE];
  6510. next_baddr = ahd->shared_data_map.physaddr
  6511. + AHD_QOUT_SIZE*sizeof(struct ahd_completion);
  6512. if ((ahd->features & AHD_TARGETMODE) != 0) {
  6513. ahd->targetcmds = (struct target_cmd *)next_vaddr;
  6514. next_vaddr += AHD_TMODE_CMDS * sizeof(struct target_cmd);
  6515. next_baddr += AHD_TMODE_CMDS * sizeof(struct target_cmd);
  6516. }
  6517. if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) {
  6518. ahd->overrun_buf = next_vaddr;
  6519. next_vaddr += PKT_OVERRUN_BUFSIZE;
  6520. next_baddr += PKT_OVERRUN_BUFSIZE;
  6521. }
  6522. /*
  6523. * We need one SCB to serve as the "next SCB". Since the
  6524. * tag identifier in this SCB will never be used, there is
  6525. * no point in using a valid HSCB tag from an SCB pulled from
  6526. * the standard free pool. So, we allocate this "sentinel"
  6527. * specially from the DMA safe memory chunk used for the QOUTFIFO.
  6528. */
  6529. ahd->next_queued_hscb = (struct hardware_scb *)next_vaddr;
  6530. ahd->next_queued_hscb_map = &ahd->shared_data_map;
  6531. ahd->next_queued_hscb->hscb_busaddr = ahd_htole32(next_baddr);
  6532. ahd->init_level++;
  6533. /* Allocate SCB data now that buffer_dmat is initialized */
  6534. if (ahd_init_scbdata(ahd) != 0)
  6535. return (ENOMEM);
  6536. if ((ahd->flags & AHD_INITIATORROLE) == 0)
  6537. ahd->flags &= ~AHD_RESET_BUS_A;
  6538. /*
  6539. * Before committing these settings to the chip, give
  6540. * the OSM one last chance to modify our configuration.
  6541. */
  6542. ahd_platform_init(ahd);
  6543. /* Bring up the chip. */
  6544. ahd_chip_init(ahd);
  6545. AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
  6546. if ((ahd->flags & AHD_CURRENT_SENSING) == 0)
  6547. goto init_done;
  6548. /*
  6549. * Verify termination based on current draw and
  6550. * warn user if the bus is over/under terminated.
  6551. */
  6552. error = ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL,
  6553. CURSENSE_ENB);
  6554. if (error != 0) {
  6555. printk("%s: current sensing timeout 1\n", ahd_name(ahd));
  6556. goto init_done;
  6557. }
  6558. for (i = 20, fstat = FLX_FSTAT_BUSY;
  6559. (fstat & FLX_FSTAT_BUSY) != 0 && i; i--) {
  6560. error = ahd_read_flexport(ahd, FLXADDR_FLEXSTAT, &fstat);
  6561. if (error != 0) {
  6562. printk("%s: current sensing timeout 2\n",
  6563. ahd_name(ahd));
  6564. goto init_done;
  6565. }
  6566. }
  6567. if (i == 0) {
  6568. printk("%s: Timedout during current-sensing test\n",
  6569. ahd_name(ahd));
  6570. goto init_done;
  6571. }
  6572. /* Latch Current Sensing status. */
  6573. error = ahd_read_flexport(ahd, FLXADDR_CURRENT_STAT, &current_sensing);
  6574. if (error != 0) {
  6575. printk("%s: current sensing timeout 3\n", ahd_name(ahd));
  6576. goto init_done;
  6577. }
  6578. /* Diable current sensing. */
  6579. ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0);
  6580. #ifdef AHD_DEBUG
  6581. if ((ahd_debug & AHD_SHOW_TERMCTL) != 0) {
  6582. printk("%s: current_sensing == 0x%x\n",
  6583. ahd_name(ahd), current_sensing);
  6584. }
  6585. #endif
  6586. warn_user = 0;
  6587. for (i = 0; i < 4; i++, current_sensing >>= FLX_CSTAT_SHIFT) {
  6588. u_int term_stat;
  6589. term_stat = (current_sensing & FLX_CSTAT_MASK);
  6590. switch (term_stat) {
  6591. case FLX_CSTAT_OVER:
  6592. case FLX_CSTAT_UNDER:
  6593. warn_user++;
  6594. case FLX_CSTAT_INVALID:
  6595. case FLX_CSTAT_OKAY:
  6596. if (warn_user == 0 && bootverbose == 0)
  6597. break;
  6598. printk("%s: %s Channel %s\n", ahd_name(ahd),
  6599. channel_strings[i], termstat_strings[term_stat]);
  6600. break;
  6601. }
  6602. }
  6603. if (warn_user) {
  6604. printk("%s: WARNING. Termination is not configured correctly.\n"
  6605. "%s: WARNING. SCSI bus operations may FAIL.\n",
  6606. ahd_name(ahd), ahd_name(ahd));
  6607. }
  6608. init_done:
  6609. ahd_restart(ahd);
  6610. ahd_timer_reset(&ahd->stat_timer, AHD_STAT_UPDATE_US);
  6611. return (0);
  6612. }
  6613. /*
  6614. * (Re)initialize chip state after a chip reset.
  6615. */
  6616. static void
  6617. ahd_chip_init(struct ahd_softc *ahd)
  6618. {
  6619. uint32_t busaddr;
  6620. u_int sxfrctl1;
  6621. u_int scsiseq_template;
  6622. u_int wait;
  6623. u_int i;
  6624. u_int target;
  6625. ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
  6626. /*
  6627. * Take the LED out of diagnostic mode
  6628. */
  6629. ahd_outb(ahd, SBLKCTL, ahd_inb(ahd, SBLKCTL) & ~(DIAGLEDEN|DIAGLEDON));
  6630. /*
  6631. * Return HS_MAILBOX to its default value.
  6632. */
  6633. ahd->hs_mailbox = 0;
  6634. ahd_outb(ahd, HS_MAILBOX, 0);
  6635. /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1. */
  6636. ahd_outb(ahd, IOWNID, ahd->our_id);
  6637. ahd_outb(ahd, TOWNID, ahd->our_id);
  6638. sxfrctl1 = (ahd->flags & AHD_TERM_ENB_A) != 0 ? STPWEN : 0;
  6639. sxfrctl1 |= (ahd->flags & AHD_SPCHK_ENB_A) != 0 ? ENSPCHK : 0;
  6640. if ((ahd->bugs & AHD_LONG_SETIMO_BUG)
  6641. && (ahd->seltime != STIMESEL_MIN)) {
  6642. /*
  6643. * The selection timer duration is twice as long
  6644. * as it should be. Halve it by adding "1" to
  6645. * the user specified setting.
  6646. */
  6647. sxfrctl1 |= ahd->seltime + STIMESEL_BUG_ADJ;
  6648. } else {
  6649. sxfrctl1 |= ahd->seltime;
  6650. }
  6651. ahd_outb(ahd, SXFRCTL0, DFON);
  6652. ahd_outb(ahd, SXFRCTL1, sxfrctl1|ahd->seltime|ENSTIMER|ACTNEGEN);
  6653. ahd_outb(ahd, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
  6654. /*
  6655. * Now that termination is set, wait for up
  6656. * to 500ms for our transceivers to settle. If
  6657. * the adapter does not have a cable attached,
  6658. * the transceivers may never settle, so don't
  6659. * complain if we fail here.
  6660. */
  6661. for (wait = 10000;
  6662. (ahd_inb(ahd, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait;
  6663. wait--)
  6664. ahd_delay(100);
  6665. /* Clear any false bus resets due to the transceivers settling */
  6666. ahd_outb(ahd, CLRSINT1, CLRSCSIRSTI);
  6667. ahd_outb(ahd, CLRINT, CLRSCSIINT);
  6668. /* Initialize mode specific S/G state. */
  6669. for (i = 0; i < 2; i++) {
  6670. ahd_set_modes(ahd, AHD_MODE_DFF0 + i, AHD_MODE_DFF0 + i);
  6671. ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR);
  6672. ahd_outb(ahd, SG_STATE, 0);
  6673. ahd_outb(ahd, CLRSEQINTSRC, 0xFF);
  6674. ahd_outb(ahd, SEQIMODE,
  6675. ENSAVEPTRS|ENCFG4DATA|ENCFG4ISTAT
  6676. |ENCFG4TSTAT|ENCFG4ICMD|ENCFG4TCMD);
  6677. }
  6678. ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
  6679. ahd_outb(ahd, DSCOMMAND0, ahd_inb(ahd, DSCOMMAND0)|MPARCKEN|CACHETHEN);
  6680. ahd_outb(ahd, DFF_THRSH, RD_DFTHRSH_75|WR_DFTHRSH_75);
  6681. ahd_outb(ahd, SIMODE0, ENIOERR|ENOVERRUN);
  6682. ahd_outb(ahd, SIMODE3, ENNTRAMPERR|ENOSRAMPERR);
  6683. if ((ahd->bugs & AHD_BUSFREEREV_BUG) != 0) {
  6684. ahd_outb(ahd, OPTIONMODE, AUTOACKEN|AUTO_MSGOUT_DE);
  6685. } else {
  6686. ahd_outb(ahd, OPTIONMODE, AUTOACKEN|BUSFREEREV|AUTO_MSGOUT_DE);
  6687. }
  6688. ahd_outb(ahd, SCSCHKN, CURRFIFODEF|WIDERESEN|SHVALIDSTDIS);
  6689. if ((ahd->chip & AHD_BUS_MASK) == AHD_PCIX)
  6690. /*
  6691. * Do not issue a target abort when a split completion
  6692. * error occurs. Let our PCIX interrupt handler deal
  6693. * with it instead. H2A4 Razor #625
  6694. */
  6695. ahd_outb(ahd, PCIXCTL, ahd_inb(ahd, PCIXCTL) | SPLTSTADIS);
  6696. if ((ahd->bugs & AHD_LQOOVERRUN_BUG) != 0)
  6697. ahd_outb(ahd, LQOSCSCTL, LQONOCHKOVER);
  6698. /*
  6699. * Tweak IOCELL settings.
  6700. */
  6701. if ((ahd->flags & AHD_HP_BOARD) != 0) {
  6702. for (i = 0; i < NUMDSPS; i++) {
  6703. ahd_outb(ahd, DSPSELECT, i);
  6704. ahd_outb(ahd, WRTBIASCTL, WRTBIASCTL_HP_DEFAULT);
  6705. }
  6706. #ifdef AHD_DEBUG
  6707. if ((ahd_debug & AHD_SHOW_MISC) != 0)
  6708. printk("%s: WRTBIASCTL now 0x%x\n", ahd_name(ahd),
  6709. WRTBIASCTL_HP_DEFAULT);
  6710. #endif
  6711. }
  6712. ahd_setup_iocell_workaround(ahd);
  6713. /*
  6714. * Enable LQI Manager interrupts.
  6715. */
  6716. ahd_outb(ahd, LQIMODE1, ENLQIPHASE_LQ|ENLQIPHASE_NLQ|ENLIQABORT
  6717. | ENLQICRCI_LQ|ENLQICRCI_NLQ|ENLQIBADLQI
  6718. | ENLQIOVERI_LQ|ENLQIOVERI_NLQ);
  6719. ahd_outb(ahd, LQOMODE0, ENLQOATNLQ|ENLQOATNPKT|ENLQOTCRC);
  6720. /*
  6721. * We choose to have the sequencer catch LQOPHCHGINPKT errors
  6722. * manually for the command phase at the start of a packetized
  6723. * selection case. ENLQOBUSFREE should be made redundant by
  6724. * the BUSFREE interrupt, but it seems that some LQOBUSFREE
  6725. * events fail to assert the BUSFREE interrupt so we must
  6726. * also enable LQOBUSFREE interrupts.
  6727. */
  6728. ahd_outb(ahd, LQOMODE1, ENLQOBUSFREE);
  6729. /*
  6730. * Setup sequencer interrupt handlers.
  6731. */
  6732. ahd_outw(ahd, INTVEC1_ADDR, ahd_resolve_seqaddr(ahd, LABEL_seq_isr));
  6733. ahd_outw(ahd, INTVEC2_ADDR, ahd_resolve_seqaddr(ahd, LABEL_timer_isr));
  6734. /*
  6735. * Setup SCB Offset registers.
  6736. */
  6737. if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) {
  6738. ahd_outb(ahd, LUNPTR, offsetof(struct hardware_scb,
  6739. pkt_long_lun));
  6740. } else {
  6741. ahd_outb(ahd, LUNPTR, offsetof(struct hardware_scb, lun));
  6742. }
  6743. ahd_outb(ahd, CMDLENPTR, offsetof(struct hardware_scb, cdb_len));
  6744. ahd_outb(ahd, ATTRPTR, offsetof(struct hardware_scb, task_attribute));
  6745. ahd_outb(ahd, FLAGPTR, offsetof(struct hardware_scb, task_management));
  6746. ahd_outb(ahd, CMDPTR, offsetof(struct hardware_scb,
  6747. shared_data.idata.cdb));
  6748. ahd_outb(ahd, QNEXTPTR,
  6749. offsetof(struct hardware_scb, next_hscb_busaddr));
  6750. ahd_outb(ahd, ABRTBITPTR, MK_MESSAGE_BIT_OFFSET);
  6751. ahd_outb(ahd, ABRTBYTEPTR, offsetof(struct hardware_scb, control));
  6752. if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) {
  6753. ahd_outb(ahd, LUNLEN,
  6754. sizeof(ahd->next_queued_hscb->pkt_long_lun) - 1);
  6755. } else {
  6756. ahd_outb(ahd, LUNLEN, LUNLEN_SINGLE_LEVEL_LUN);
  6757. }
  6758. ahd_outb(ahd, CDBLIMIT, SCB_CDB_LEN_PTR - 1);
  6759. ahd_outb(ahd, MAXCMD, 0xFF);
  6760. ahd_outb(ahd, SCBAUTOPTR,
  6761. AUSCBPTR_EN | offsetof(struct hardware_scb, tag));
  6762. /* We haven't been enabled for target mode yet. */
  6763. ahd_outb(ahd, MULTARGID, 0);
  6764. ahd_outb(ahd, MULTARGID + 1, 0);
  6765. ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
  6766. /* Initialize the negotiation table. */
  6767. if ((ahd->features & AHD_NEW_IOCELL_OPTS) == 0) {
  6768. /*
  6769. * Clear the spare bytes in the neg table to avoid
  6770. * spurious parity errors.
  6771. */
  6772. for (target = 0; target < AHD_NUM_TARGETS; target++) {
  6773. ahd_outb(ahd, NEGOADDR, target);
  6774. ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_PER_DEV0);
  6775. for (i = 0; i < AHD_NUM_PER_DEV_ANNEXCOLS; i++)
  6776. ahd_outb(ahd, ANNEXDAT, 0);
  6777. }
  6778. }
  6779. for (target = 0; target < AHD_NUM_TARGETS; target++) {
  6780. struct ahd_devinfo devinfo;
  6781. struct ahd_initiator_tinfo *tinfo;
  6782. struct ahd_tmode_tstate *tstate;
  6783. tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id,
  6784. target, &tstate);
  6785. ahd_compile_devinfo(&devinfo, ahd->our_id,
  6786. target, CAM_LUN_WILDCARD,
  6787. 'A', ROLE_INITIATOR);
  6788. ahd_update_neg_table(ahd, &devinfo, &tinfo->curr);
  6789. }
  6790. ahd_outb(ahd, CLRSINT3, NTRAMPERR|OSRAMPERR);
  6791. ahd_outb(ahd, CLRINT, CLRSCSIINT);
  6792. #ifdef NEEDS_MORE_TESTING
  6793. /*
  6794. * Always enable abort on incoming L_Qs if this feature is
  6795. * supported. We use this to catch invalid SCB references.
  6796. */
  6797. if ((ahd->bugs & AHD_ABORT_LQI_BUG) == 0)
  6798. ahd_outb(ahd, LQCTL1, ABORTPENDING);
  6799. else
  6800. #endif
  6801. ahd_outb(ahd, LQCTL1, 0);
  6802. /* All of our queues are empty */
  6803. ahd->qoutfifonext = 0;
  6804. ahd->qoutfifonext_valid_tag = QOUTFIFO_ENTRY_VALID;
  6805. ahd_outb(ahd, QOUTFIFO_ENTRY_VALID_TAG, QOUTFIFO_ENTRY_VALID);
  6806. for (i = 0; i < AHD_QOUT_SIZE; i++)
  6807. ahd->qoutfifo[i].valid_tag = 0;
  6808. ahd_sync_qoutfifo(ahd, BUS_DMASYNC_PREREAD);
  6809. ahd->qinfifonext = 0;
  6810. for (i = 0; i < AHD_QIN_SIZE; i++)
  6811. ahd->qinfifo[i] = SCB_LIST_NULL;
  6812. if ((ahd->features & AHD_TARGETMODE) != 0) {
  6813. /* All target command blocks start out invalid. */
  6814. for (i = 0; i < AHD_TMODE_CMDS; i++)
  6815. ahd->targetcmds[i].cmd_valid = 0;
  6816. ahd_sync_tqinfifo(ahd, BUS_DMASYNC_PREREAD);
  6817. ahd->tqinfifonext = 1;
  6818. ahd_outb(ahd, KERNEL_TQINPOS, ahd->tqinfifonext - 1);
  6819. ahd_outb(ahd, TQINPOS, ahd->tqinfifonext);
  6820. }
  6821. /* Initialize Scratch Ram. */
  6822. ahd_outb(ahd, SEQ_FLAGS, 0);
  6823. ahd_outb(ahd, SEQ_FLAGS2, 0);
  6824. /* We don't have any waiting selections */
  6825. ahd_outw(ahd, WAITING_TID_HEAD, SCB_LIST_NULL);
  6826. ahd_outw(ahd, WAITING_TID_TAIL, SCB_LIST_NULL);
  6827. ahd_outw(ahd, MK_MESSAGE_SCB, SCB_LIST_NULL);
  6828. ahd_outw(ahd, MK_MESSAGE_SCSIID, 0xFF);
  6829. for (i = 0; i < AHD_NUM_TARGETS; i++)
  6830. ahd_outw(ahd, WAITING_SCB_TAILS + (2 * i), SCB_LIST_NULL);
  6831. /*
  6832. * Nobody is waiting to be DMAed into the QOUTFIFO.
  6833. */
  6834. ahd_outw(ahd, COMPLETE_SCB_HEAD, SCB_LIST_NULL);
  6835. ahd_outw(ahd, COMPLETE_SCB_DMAINPROG_HEAD, SCB_LIST_NULL);
  6836. ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, SCB_LIST_NULL);
  6837. ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, SCB_LIST_NULL);
  6838. ahd_outw(ahd, COMPLETE_ON_QFREEZE_HEAD, SCB_LIST_NULL);
  6839. /*
  6840. * The Freeze Count is 0.
  6841. */
  6842. ahd->qfreeze_cnt = 0;
  6843. ahd_outw(ahd, QFREEZE_COUNT, 0);
  6844. ahd_outw(ahd, KERNEL_QFREEZE_COUNT, 0);
  6845. /*
  6846. * Tell the sequencer where it can find our arrays in memory.
  6847. */
  6848. busaddr = ahd->shared_data_map.physaddr;
  6849. ahd_outl(ahd, SHARED_DATA_ADDR, busaddr);
  6850. ahd_outl(ahd, QOUTFIFO_NEXT_ADDR, busaddr);
  6851. /*
  6852. * Setup the allowed SCSI Sequences based on operational mode.
  6853. * If we are a target, we'll enable select in operations once
  6854. * we've had a lun enabled.
  6855. */
  6856. scsiseq_template = ENAUTOATNP;
  6857. if ((ahd->flags & AHD_INITIATORROLE) != 0)
  6858. scsiseq_template |= ENRSELI;
  6859. ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq_template);
  6860. /* There are no busy SCBs yet. */
  6861. for (target = 0; target < AHD_NUM_TARGETS; target++) {
  6862. int lun;
  6863. for (lun = 0; lun < AHD_NUM_LUNS_NONPKT; lun++)
  6864. ahd_unbusy_tcl(ahd, BUILD_TCL_RAW(target, 'A', lun));
  6865. }
  6866. /*
  6867. * Initialize the group code to command length table.
  6868. * Vendor Unique codes are set to 0 so we only capture
  6869. * the first byte of the cdb. These can be overridden
  6870. * when target mode is enabled.
  6871. */
  6872. ahd_outb(ahd, CMDSIZE_TABLE, 5);
  6873. ahd_outb(ahd, CMDSIZE_TABLE + 1, 9);
  6874. ahd_outb(ahd, CMDSIZE_TABLE + 2, 9);
  6875. ahd_outb(ahd, CMDSIZE_TABLE + 3, 0);
  6876. ahd_outb(ahd, CMDSIZE_TABLE + 4, 15);
  6877. ahd_outb(ahd, CMDSIZE_TABLE + 5, 11);
  6878. ahd_outb(ahd, CMDSIZE_TABLE + 6, 0);
  6879. ahd_outb(ahd, CMDSIZE_TABLE + 7, 0);
  6880. /* Tell the sequencer of our initial queue positions */
  6881. ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
  6882. ahd_outb(ahd, QOFF_CTLSTA, SCB_QSIZE_512);
  6883. ahd->qinfifonext = 0;
  6884. ahd_set_hnscb_qoff(ahd, ahd->qinfifonext);
  6885. ahd_set_hescb_qoff(ahd, 0);
  6886. ahd_set_snscb_qoff(ahd, 0);
  6887. ahd_set_sescb_qoff(ahd, 0);
  6888. ahd_set_sdscb_qoff(ahd, 0);
  6889. /*
  6890. * Tell the sequencer which SCB will be the next one it receives.
  6891. */
  6892. busaddr = ahd_le32toh(ahd->next_queued_hscb->hscb_busaddr);
  6893. ahd_outl(ahd, NEXT_QUEUED_SCB_ADDR, busaddr);
  6894. /*
  6895. * Default to coalescing disabled.
  6896. */
  6897. ahd_outw(ahd, INT_COALESCING_CMDCOUNT, 0);
  6898. ahd_outw(ahd, CMDS_PENDING, 0);
  6899. ahd_update_coalescing_values(ahd, ahd->int_coalescing_timer,
  6900. ahd->int_coalescing_maxcmds,
  6901. ahd->int_coalescing_mincmds);
  6902. ahd_enable_coalescing(ahd, FALSE);
  6903. ahd_loadseq(ahd);
  6904. ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
  6905. if (ahd->features & AHD_AIC79XXB_SLOWCRC) {
  6906. u_int negodat3 = ahd_inb(ahd, NEGCONOPTS);
  6907. negodat3 |= ENSLOWCRC;
  6908. ahd_outb(ahd, NEGCONOPTS, negodat3);
  6909. negodat3 = ahd_inb(ahd, NEGCONOPTS);
  6910. if (!(negodat3 & ENSLOWCRC))
  6911. printk("aic79xx: failed to set the SLOWCRC bit\n");
  6912. else
  6913. printk("aic79xx: SLOWCRC bit set\n");
  6914. }
  6915. }
  6916. /*
  6917. * Setup default device and controller settings.
  6918. * This should only be called if our probe has
  6919. * determined that no configuration data is available.
  6920. */
  6921. int
  6922. ahd_default_config(struct ahd_softc *ahd)
  6923. {
  6924. int targ;
  6925. ahd->our_id = 7;
  6926. /*
  6927. * Allocate a tstate to house information for our
  6928. * initiator presence on the bus as well as the user
  6929. * data for any target mode initiator.
  6930. */
  6931. if (ahd_alloc_tstate(ahd, ahd->our_id, 'A') == NULL) {
  6932. printk("%s: unable to allocate ahd_tmode_tstate. "
  6933. "Failing attach\n", ahd_name(ahd));
  6934. return (ENOMEM);
  6935. }
  6936. for (targ = 0; targ < AHD_NUM_TARGETS; targ++) {
  6937. struct ahd_devinfo devinfo;
  6938. struct ahd_initiator_tinfo *tinfo;
  6939. struct ahd_tmode_tstate *tstate;
  6940. uint16_t target_mask;
  6941. tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id,
  6942. targ, &tstate);
  6943. /*
  6944. * We support SPC2 and SPI4.
  6945. */
  6946. tinfo->user.protocol_version = 4;
  6947. tinfo->user.transport_version = 4;
  6948. target_mask = 0x01 << targ;
  6949. ahd->user_discenable |= target_mask;
  6950. tstate->discenable |= target_mask;
  6951. ahd->user_tagenable |= target_mask;
  6952. #ifdef AHD_FORCE_160
  6953. tinfo->user.period = AHD_SYNCRATE_DT;
  6954. #else
  6955. tinfo->user.period = AHD_SYNCRATE_160;
  6956. #endif
  6957. tinfo->user.offset = MAX_OFFSET;
  6958. tinfo->user.ppr_options = MSG_EXT_PPR_RD_STRM
  6959. | MSG_EXT_PPR_WR_FLOW
  6960. | MSG_EXT_PPR_HOLD_MCS
  6961. | MSG_EXT_PPR_IU_REQ
  6962. | MSG_EXT_PPR_QAS_REQ
  6963. | MSG_EXT_PPR_DT_REQ;
  6964. if ((ahd->features & AHD_RTI) != 0)
  6965. tinfo->user.ppr_options |= MSG_EXT_PPR_RTI;
  6966. tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
  6967. /*
  6968. * Start out Async/Narrow/Untagged and with
  6969. * conservative protocol support.
  6970. */
  6971. tinfo->goal.protocol_version = 2;
  6972. tinfo->goal.transport_version = 2;
  6973. tinfo->curr.protocol_version = 2;
  6974. tinfo->curr.transport_version = 2;
  6975. ahd_compile_devinfo(&devinfo, ahd->our_id,
  6976. targ, CAM_LUN_WILDCARD,
  6977. 'A', ROLE_INITIATOR);
  6978. tstate->tagenable &= ~target_mask;
  6979. ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
  6980. AHD_TRANS_CUR|AHD_TRANS_GOAL, /*paused*/TRUE);
  6981. ahd_set_syncrate(ahd, &devinfo, /*period*/0, /*offset*/0,
  6982. /*ppr_options*/0, AHD_TRANS_CUR|AHD_TRANS_GOAL,
  6983. /*paused*/TRUE);
  6984. }
  6985. return (0);
  6986. }
  6987. /*
  6988. * Parse device configuration information.
  6989. */
  6990. int
  6991. ahd_parse_cfgdata(struct ahd_softc *ahd, struct seeprom_config *sc)
  6992. {
  6993. int targ;
  6994. int max_targ;
  6995. max_targ = sc->max_targets & CFMAXTARG;
  6996. ahd->our_id = sc->brtime_id & CFSCSIID;
  6997. /*
  6998. * Allocate a tstate to house information for our
  6999. * initiator presence on the bus as well as the user
  7000. * data for any target mode initiator.
  7001. */
  7002. if (ahd_alloc_tstate(ahd, ahd->our_id, 'A') == NULL) {
  7003. printk("%s: unable to allocate ahd_tmode_tstate. "
  7004. "Failing attach\n", ahd_name(ahd));
  7005. return (ENOMEM);
  7006. }
  7007. for (targ = 0; targ < max_targ; targ++) {
  7008. struct ahd_devinfo devinfo;
  7009. struct ahd_initiator_tinfo *tinfo;
  7010. struct ahd_transinfo *user_tinfo;
  7011. struct ahd_tmode_tstate *tstate;
  7012. uint16_t target_mask;
  7013. tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id,
  7014. targ, &tstate);
  7015. user_tinfo = &tinfo->user;
  7016. /*
  7017. * We support SPC2 and SPI4.
  7018. */
  7019. tinfo->user.protocol_version = 4;
  7020. tinfo->user.transport_version = 4;
  7021. target_mask = 0x01 << targ;
  7022. ahd->user_discenable &= ~target_mask;
  7023. tstate->discenable &= ~target_mask;
  7024. ahd->user_tagenable &= ~target_mask;
  7025. if (sc->device_flags[targ] & CFDISC) {
  7026. tstate->discenable |= target_mask;
  7027. ahd->user_discenable |= target_mask;
  7028. ahd->user_tagenable |= target_mask;
  7029. } else {
  7030. /*
  7031. * Cannot be packetized without disconnection.
  7032. */
  7033. sc->device_flags[targ] &= ~CFPACKETIZED;
  7034. }
  7035. user_tinfo->ppr_options = 0;
  7036. user_tinfo->period = (sc->device_flags[targ] & CFXFER);
  7037. if (user_tinfo->period < CFXFER_ASYNC) {
  7038. if (user_tinfo->period <= AHD_PERIOD_10MHz)
  7039. user_tinfo->ppr_options |= MSG_EXT_PPR_DT_REQ;
  7040. user_tinfo->offset = MAX_OFFSET;
  7041. } else {
  7042. user_tinfo->offset = 0;
  7043. user_tinfo->period = AHD_ASYNC_XFER_PERIOD;
  7044. }
  7045. #ifdef AHD_FORCE_160
  7046. if (user_tinfo->period <= AHD_SYNCRATE_160)
  7047. user_tinfo->period = AHD_SYNCRATE_DT;
  7048. #endif
  7049. if ((sc->device_flags[targ] & CFPACKETIZED) != 0) {
  7050. user_tinfo->ppr_options |= MSG_EXT_PPR_RD_STRM
  7051. | MSG_EXT_PPR_WR_FLOW
  7052. | MSG_EXT_PPR_HOLD_MCS
  7053. | MSG_EXT_PPR_IU_REQ;
  7054. if ((ahd->features & AHD_RTI) != 0)
  7055. user_tinfo->ppr_options |= MSG_EXT_PPR_RTI;
  7056. }
  7057. if ((sc->device_flags[targ] & CFQAS) != 0)
  7058. user_tinfo->ppr_options |= MSG_EXT_PPR_QAS_REQ;
  7059. if ((sc->device_flags[targ] & CFWIDEB) != 0)
  7060. user_tinfo->width = MSG_EXT_WDTR_BUS_16_BIT;
  7061. else
  7062. user_tinfo->width = MSG_EXT_WDTR_BUS_8_BIT;
  7063. #ifdef AHD_DEBUG
  7064. if ((ahd_debug & AHD_SHOW_MISC) != 0)
  7065. printk("(%d): %x:%x:%x:%x\n", targ, user_tinfo->width,
  7066. user_tinfo->period, user_tinfo->offset,
  7067. user_tinfo->ppr_options);
  7068. #endif
  7069. /*
  7070. * Start out Async/Narrow/Untagged and with
  7071. * conservative protocol support.
  7072. */
  7073. tstate->tagenable &= ~target_mask;
  7074. tinfo->goal.protocol_version = 2;
  7075. tinfo->goal.transport_version = 2;
  7076. tinfo->curr.protocol_version = 2;
  7077. tinfo->curr.transport_version = 2;
  7078. ahd_compile_devinfo(&devinfo, ahd->our_id,
  7079. targ, CAM_LUN_WILDCARD,
  7080. 'A', ROLE_INITIATOR);
  7081. ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
  7082. AHD_TRANS_CUR|AHD_TRANS_GOAL, /*paused*/TRUE);
  7083. ahd_set_syncrate(ahd, &devinfo, /*period*/0, /*offset*/0,
  7084. /*ppr_options*/0, AHD_TRANS_CUR|AHD_TRANS_GOAL,
  7085. /*paused*/TRUE);
  7086. }
  7087. ahd->flags &= ~AHD_SPCHK_ENB_A;
  7088. if (sc->bios_control & CFSPARITY)
  7089. ahd->flags |= AHD_SPCHK_ENB_A;
  7090. ahd->flags &= ~AHD_RESET_BUS_A;
  7091. if (sc->bios_control & CFRESETB)
  7092. ahd->flags |= AHD_RESET_BUS_A;
  7093. ahd->flags &= ~AHD_EXTENDED_TRANS_A;
  7094. if (sc->bios_control & CFEXTEND)
  7095. ahd->flags |= AHD_EXTENDED_TRANS_A;
  7096. ahd->flags &= ~AHD_BIOS_ENABLED;
  7097. if ((sc->bios_control & CFBIOSSTATE) == CFBS_ENABLED)
  7098. ahd->flags |= AHD_BIOS_ENABLED;
  7099. ahd->flags &= ~AHD_STPWLEVEL_A;
  7100. if ((sc->adapter_control & CFSTPWLEVEL) != 0)
  7101. ahd->flags |= AHD_STPWLEVEL_A;
  7102. return (0);
  7103. }
  7104. /*
  7105. * Parse device configuration information.
  7106. */
  7107. int
  7108. ahd_parse_vpddata(struct ahd_softc *ahd, struct vpd_config *vpd)
  7109. {
  7110. int error;
  7111. error = ahd_verify_vpd_cksum(vpd);
  7112. if (error == 0)
  7113. return (EINVAL);
  7114. if ((vpd->bios_flags & VPDBOOTHOST) != 0)
  7115. ahd->flags |= AHD_BOOT_CHANNEL;
  7116. return (0);
  7117. }
  7118. void
  7119. ahd_intr_enable(struct ahd_softc *ahd, int enable)
  7120. {
  7121. u_int hcntrl;
  7122. hcntrl = ahd_inb(ahd, HCNTRL);
  7123. hcntrl &= ~INTEN;
  7124. ahd->pause &= ~INTEN;
  7125. ahd->unpause &= ~INTEN;
  7126. if (enable) {
  7127. hcntrl |= INTEN;
  7128. ahd->pause |= INTEN;
  7129. ahd->unpause |= INTEN;
  7130. }
  7131. ahd_outb(ahd, HCNTRL, hcntrl);
  7132. }
  7133. static void
  7134. ahd_update_coalescing_values(struct ahd_softc *ahd, u_int timer, u_int maxcmds,
  7135. u_int mincmds)
  7136. {
  7137. if (timer > AHD_TIMER_MAX_US)
  7138. timer = AHD_TIMER_MAX_US;
  7139. ahd->int_coalescing_timer = timer;
  7140. if (maxcmds > AHD_INT_COALESCING_MAXCMDS_MAX)
  7141. maxcmds = AHD_INT_COALESCING_MAXCMDS_MAX;
  7142. if (mincmds > AHD_INT_COALESCING_MINCMDS_MAX)
  7143. mincmds = AHD_INT_COALESCING_MINCMDS_MAX;
  7144. ahd->int_coalescing_maxcmds = maxcmds;
  7145. ahd_outw(ahd, INT_COALESCING_TIMER, timer / AHD_TIMER_US_PER_TICK);
  7146. ahd_outb(ahd, INT_COALESCING_MAXCMDS, -maxcmds);
  7147. ahd_outb(ahd, INT_COALESCING_MINCMDS, -mincmds);
  7148. }
  7149. static void
  7150. ahd_enable_coalescing(struct ahd_softc *ahd, int enable)
  7151. {
  7152. ahd->hs_mailbox &= ~ENINT_COALESCE;
  7153. if (enable)
  7154. ahd->hs_mailbox |= ENINT_COALESCE;
  7155. ahd_outb(ahd, HS_MAILBOX, ahd->hs_mailbox);
  7156. ahd_flush_device_writes(ahd);
  7157. ahd_run_qoutfifo(ahd);
  7158. }
  7159. /*
  7160. * Ensure that the card is paused in a location
  7161. * outside of all critical sections and that all
  7162. * pending work is completed prior to returning.
  7163. * This routine should only be called from outside
  7164. * an interrupt context.
  7165. */
  7166. void
  7167. ahd_pause_and_flushwork(struct ahd_softc *ahd)
  7168. {
  7169. u_int intstat;
  7170. u_int maxloops;
  7171. maxloops = 1000;
  7172. ahd->flags |= AHD_ALL_INTERRUPTS;
  7173. ahd_pause(ahd);
  7174. /*
  7175. * Freeze the outgoing selections. We do this only
  7176. * until we are safely paused without further selections
  7177. * pending.
  7178. */
  7179. ahd->qfreeze_cnt--;
  7180. ahd_outw(ahd, KERNEL_QFREEZE_COUNT, ahd->qfreeze_cnt);
  7181. ahd_outb(ahd, SEQ_FLAGS2, ahd_inb(ahd, SEQ_FLAGS2) | SELECTOUT_QFROZEN);
  7182. do {
  7183. ahd_unpause(ahd);
  7184. /*
  7185. * Give the sequencer some time to service
  7186. * any active selections.
  7187. */
  7188. ahd_delay(500);
  7189. ahd_intr(ahd);
  7190. ahd_pause(ahd);
  7191. intstat = ahd_inb(ahd, INTSTAT);
  7192. if ((intstat & INT_PEND) == 0) {
  7193. ahd_clear_critical_section(ahd);
  7194. intstat = ahd_inb(ahd, INTSTAT);
  7195. }
  7196. } while (--maxloops
  7197. && (intstat != 0xFF || (ahd->features & AHD_REMOVABLE) == 0)
  7198. && ((intstat & INT_PEND) != 0
  7199. || (ahd_inb(ahd, SCSISEQ0) & ENSELO) != 0
  7200. || (ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) != 0));
  7201. if (maxloops == 0) {
  7202. printk("Infinite interrupt loop, INTSTAT = %x",
  7203. ahd_inb(ahd, INTSTAT));
  7204. }
  7205. ahd->qfreeze_cnt++;
  7206. ahd_outw(ahd, KERNEL_QFREEZE_COUNT, ahd->qfreeze_cnt);
  7207. ahd_flush_qoutfifo(ahd);
  7208. ahd->flags &= ~AHD_ALL_INTERRUPTS;
  7209. }
  7210. #ifdef CONFIG_PM
  7211. int
  7212. ahd_suspend(struct ahd_softc *ahd)
  7213. {
  7214. ahd_pause_and_flushwork(ahd);
  7215. if (LIST_FIRST(&ahd->pending_scbs) != NULL) {
  7216. ahd_unpause(ahd);
  7217. return (EBUSY);
  7218. }
  7219. ahd_shutdown(ahd);
  7220. return (0);
  7221. }
  7222. void
  7223. ahd_resume(struct ahd_softc *ahd)
  7224. {
  7225. ahd_reset(ahd, /*reinit*/TRUE);
  7226. ahd_intr_enable(ahd, TRUE);
  7227. ahd_restart(ahd);
  7228. }
  7229. #endif
  7230. /************************** Busy Target Table *********************************/
  7231. /*
  7232. * Set SCBPTR to the SCB that contains the busy
  7233. * table entry for TCL. Return the offset into
  7234. * the SCB that contains the entry for TCL.
  7235. * saved_scbid is dereferenced and set to the
  7236. * scbid that should be restored once manipualtion
  7237. * of the TCL entry is complete.
  7238. */
  7239. static inline u_int
  7240. ahd_index_busy_tcl(struct ahd_softc *ahd, u_int *saved_scbid, u_int tcl)
  7241. {
  7242. /*
  7243. * Index to the SCB that contains the busy entry.
  7244. */
  7245. AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
  7246. *saved_scbid = ahd_get_scbptr(ahd);
  7247. ahd_set_scbptr(ahd, TCL_LUN(tcl)
  7248. | ((TCL_TARGET_OFFSET(tcl) & 0xC) << 4));
  7249. /*
  7250. * And now calculate the SCB offset to the entry.
  7251. * Each entry is 2 bytes wide, hence the
  7252. * multiplication by 2.
  7253. */
  7254. return (((TCL_TARGET_OFFSET(tcl) & 0x3) << 1) + SCB_DISCONNECTED_LISTS);
  7255. }
  7256. /*
  7257. * Return the untagged transaction id for a given target/channel lun.
  7258. */
  7259. static u_int
  7260. ahd_find_busy_tcl(struct ahd_softc *ahd, u_int tcl)
  7261. {
  7262. u_int scbid;
  7263. u_int scb_offset;
  7264. u_int saved_scbptr;
  7265. scb_offset = ahd_index_busy_tcl(ahd, &saved_scbptr, tcl);
  7266. scbid = ahd_inw_scbram(ahd, scb_offset);
  7267. ahd_set_scbptr(ahd, saved_scbptr);
  7268. return (scbid);
  7269. }
  7270. static void
  7271. ahd_busy_tcl(struct ahd_softc *ahd, u_int tcl, u_int scbid)
  7272. {
  7273. u_int scb_offset;
  7274. u_int saved_scbptr;
  7275. scb_offset = ahd_index_busy_tcl(ahd, &saved_scbptr, tcl);
  7276. ahd_outw(ahd, scb_offset, scbid);
  7277. ahd_set_scbptr(ahd, saved_scbptr);
  7278. }
  7279. /************************** SCB and SCB queue management **********************/
  7280. static int
  7281. ahd_match_scb(struct ahd_softc *ahd, struct scb *scb, int target,
  7282. char channel, int lun, u_int tag, role_t role)
  7283. {
  7284. int targ = SCB_GET_TARGET(ahd, scb);
  7285. char chan = SCB_GET_CHANNEL(ahd, scb);
  7286. int slun = SCB_GET_LUN(scb);
  7287. int match;
  7288. match = ((chan == channel) || (channel == ALL_CHANNELS));
  7289. if (match != 0)
  7290. match = ((targ == target) || (target == CAM_TARGET_WILDCARD));
  7291. if (match != 0)
  7292. match = ((lun == slun) || (lun == CAM_LUN_WILDCARD));
  7293. if (match != 0) {
  7294. #ifdef AHD_TARGET_MODE
  7295. int group;
  7296. group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code);
  7297. if (role == ROLE_INITIATOR) {
  7298. match = (group != XPT_FC_GROUP_TMODE)
  7299. && ((tag == SCB_GET_TAG(scb))
  7300. || (tag == SCB_LIST_NULL));
  7301. } else if (role == ROLE_TARGET) {
  7302. match = (group == XPT_FC_GROUP_TMODE)
  7303. && ((tag == scb->io_ctx->csio.tag_id)
  7304. || (tag == SCB_LIST_NULL));
  7305. }
  7306. #else /* !AHD_TARGET_MODE */
  7307. match = ((tag == SCB_GET_TAG(scb)) || (tag == SCB_LIST_NULL));
  7308. #endif /* AHD_TARGET_MODE */
  7309. }
  7310. return match;
  7311. }
  7312. static void
  7313. ahd_freeze_devq(struct ahd_softc *ahd, struct scb *scb)
  7314. {
  7315. int target;
  7316. char channel;
  7317. int lun;
  7318. target = SCB_GET_TARGET(ahd, scb);
  7319. lun = SCB_GET_LUN(scb);
  7320. channel = SCB_GET_CHANNEL(ahd, scb);
  7321. ahd_search_qinfifo(ahd, target, channel, lun,
  7322. /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN,
  7323. CAM_REQUEUE_REQ, SEARCH_COMPLETE);
  7324. ahd_platform_freeze_devq(ahd, scb);
  7325. }
  7326. void
  7327. ahd_qinfifo_requeue_tail(struct ahd_softc *ahd, struct scb *scb)
  7328. {
  7329. struct scb *prev_scb;
  7330. ahd_mode_state saved_modes;
  7331. saved_modes = ahd_save_modes(ahd);
  7332. ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
  7333. prev_scb = NULL;
  7334. if (ahd_qinfifo_count(ahd) != 0) {
  7335. u_int prev_tag;
  7336. u_int prev_pos;
  7337. prev_pos = AHD_QIN_WRAP(ahd->qinfifonext - 1);
  7338. prev_tag = ahd->qinfifo[prev_pos];
  7339. prev_scb = ahd_lookup_scb(ahd, prev_tag);
  7340. }
  7341. ahd_qinfifo_requeue(ahd, prev_scb, scb);
  7342. ahd_set_hnscb_qoff(ahd, ahd->qinfifonext);
  7343. ahd_restore_modes(ahd, saved_modes);
  7344. }
  7345. static void
  7346. ahd_qinfifo_requeue(struct ahd_softc *ahd, struct scb *prev_scb,
  7347. struct scb *scb)
  7348. {
  7349. if (prev_scb == NULL) {
  7350. uint32_t busaddr;
  7351. busaddr = ahd_le32toh(scb->hscb->hscb_busaddr);
  7352. ahd_outl(ahd, NEXT_QUEUED_SCB_ADDR, busaddr);
  7353. } else {
  7354. prev_scb->hscb->next_hscb_busaddr = scb->hscb->hscb_busaddr;
  7355. ahd_sync_scb(ahd, prev_scb,
  7356. BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
  7357. }
  7358. ahd->qinfifo[AHD_QIN_WRAP(ahd->qinfifonext)] = SCB_GET_TAG(scb);
  7359. ahd->qinfifonext++;
  7360. scb->hscb->next_hscb_busaddr = ahd->next_queued_hscb->hscb_busaddr;
  7361. ahd_sync_scb(ahd, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
  7362. }
  7363. static int
  7364. ahd_qinfifo_count(struct ahd_softc *ahd)
  7365. {
  7366. u_int qinpos;
  7367. u_int wrap_qinpos;
  7368. u_int wrap_qinfifonext;
  7369. AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
  7370. qinpos = ahd_get_snscb_qoff(ahd);
  7371. wrap_qinpos = AHD_QIN_WRAP(qinpos);
  7372. wrap_qinfifonext = AHD_QIN_WRAP(ahd->qinfifonext);
  7373. if (wrap_qinfifonext >= wrap_qinpos)
  7374. return (wrap_qinfifonext - wrap_qinpos);
  7375. else
  7376. return (wrap_qinfifonext
  7377. + ARRAY_SIZE(ahd->qinfifo) - wrap_qinpos);
  7378. }
  7379. static void
  7380. ahd_reset_cmds_pending(struct ahd_softc *ahd)
  7381. {
  7382. struct scb *scb;
  7383. ahd_mode_state saved_modes;
  7384. u_int pending_cmds;
  7385. saved_modes = ahd_save_modes(ahd);
  7386. ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
  7387. /*
  7388. * Don't count any commands as outstanding that the
  7389. * sequencer has already marked for completion.
  7390. */
  7391. ahd_flush_qoutfifo(ahd);
  7392. pending_cmds = 0;
  7393. LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) {
  7394. pending_cmds++;
  7395. }
  7396. ahd_outw(ahd, CMDS_PENDING, pending_cmds - ahd_qinfifo_count(ahd));
  7397. ahd_restore_modes(ahd, saved_modes);
  7398. ahd->flags &= ~AHD_UPDATE_PEND_CMDS;
  7399. }
  7400. static void
  7401. ahd_done_with_status(struct ahd_softc *ahd, struct scb *scb, uint32_t status)
  7402. {
  7403. cam_status ostat;
  7404. cam_status cstat;
  7405. ostat = ahd_get_transaction_status(scb);
  7406. if (ostat == CAM_REQ_INPROG)
  7407. ahd_set_transaction_status(scb, status);
  7408. cstat = ahd_get_transaction_status(scb);
  7409. if (cstat != CAM_REQ_CMP)
  7410. ahd_freeze_scb(scb);
  7411. ahd_done(ahd, scb);
  7412. }
  7413. int
  7414. ahd_search_qinfifo(struct ahd_softc *ahd, int target, char channel,
  7415. int lun, u_int tag, role_t role, uint32_t status,
  7416. ahd_search_action action)
  7417. {
  7418. struct scb *scb;
  7419. struct scb *mk_msg_scb;
  7420. struct scb *prev_scb;
  7421. ahd_mode_state saved_modes;
  7422. u_int qinstart;
  7423. u_int qinpos;
  7424. u_int qintail;
  7425. u_int tid_next;
  7426. u_int tid_prev;
  7427. u_int scbid;
  7428. u_int seq_flags2;
  7429. u_int savedscbptr;
  7430. uint32_t busaddr;
  7431. int found;
  7432. int targets;
  7433. /* Must be in CCHAN mode */
  7434. saved_modes = ahd_save_modes(ahd);
  7435. ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
  7436. /*
  7437. * Halt any pending SCB DMA. The sequencer will reinitiate
  7438. * this dma if the qinfifo is not empty once we unpause.
  7439. */
  7440. if ((ahd_inb(ahd, CCSCBCTL) & (CCARREN|CCSCBEN|CCSCBDIR))
  7441. == (CCARREN|CCSCBEN|CCSCBDIR)) {
  7442. ahd_outb(ahd, CCSCBCTL,
  7443. ahd_inb(ahd, CCSCBCTL) & ~(CCARREN|CCSCBEN));
  7444. while ((ahd_inb(ahd, CCSCBCTL) & (CCARREN|CCSCBEN)) != 0)
  7445. ;
  7446. }
  7447. /* Determine sequencer's position in the qinfifo. */
  7448. qintail = AHD_QIN_WRAP(ahd->qinfifonext);
  7449. qinstart = ahd_get_snscb_qoff(ahd);
  7450. qinpos = AHD_QIN_WRAP(qinstart);
  7451. found = 0;
  7452. prev_scb = NULL;
  7453. if (action == SEARCH_PRINT) {
  7454. printk("qinstart = %d qinfifonext = %d\nQINFIFO:",
  7455. qinstart, ahd->qinfifonext);
  7456. }
  7457. /*
  7458. * Start with an empty queue. Entries that are not chosen
  7459. * for removal will be re-added to the queue as we go.
  7460. */
  7461. ahd->qinfifonext = qinstart;
  7462. busaddr = ahd_le32toh(ahd->next_queued_hscb->hscb_busaddr);
  7463. ahd_outl(ahd, NEXT_QUEUED_SCB_ADDR, busaddr);
  7464. while (qinpos != qintail) {
  7465. scb = ahd_lookup_scb(ahd, ahd->qinfifo[qinpos]);
  7466. if (scb == NULL) {
  7467. printk("qinpos = %d, SCB index = %d\n",
  7468. qinpos, ahd->qinfifo[qinpos]);
  7469. panic("Loop 1\n");
  7470. }
  7471. if (ahd_match_scb(ahd, scb, target, channel, lun, tag, role)) {
  7472. /*
  7473. * We found an scb that needs to be acted on.
  7474. */
  7475. found++;
  7476. switch (action) {
  7477. case SEARCH_COMPLETE:
  7478. if ((scb->flags & SCB_ACTIVE) == 0)
  7479. printk("Inactive SCB in qinfifo\n");
  7480. ahd_done_with_status(ahd, scb, status);
  7481. /* FALLTHROUGH */
  7482. case SEARCH_REMOVE:
  7483. break;
  7484. case SEARCH_PRINT:
  7485. printk(" 0x%x", ahd->qinfifo[qinpos]);
  7486. /* FALLTHROUGH */
  7487. case SEARCH_COUNT:
  7488. ahd_qinfifo_requeue(ahd, prev_scb, scb);
  7489. prev_scb = scb;
  7490. break;
  7491. }
  7492. } else {
  7493. ahd_qinfifo_requeue(ahd, prev_scb, scb);
  7494. prev_scb = scb;
  7495. }
  7496. qinpos = AHD_QIN_WRAP(qinpos+1);
  7497. }
  7498. ahd_set_hnscb_qoff(ahd, ahd->qinfifonext);
  7499. if (action == SEARCH_PRINT)
  7500. printk("\nWAITING_TID_QUEUES:\n");
  7501. /*
  7502. * Search waiting for selection lists. We traverse the
  7503. * list of "their ids" waiting for selection and, if
  7504. * appropriate, traverse the SCBs of each "their id"
  7505. * looking for matches.
  7506. */
  7507. ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
  7508. seq_flags2 = ahd_inb(ahd, SEQ_FLAGS2);
  7509. if ((seq_flags2 & PENDING_MK_MESSAGE) != 0) {
  7510. scbid = ahd_inw(ahd, MK_MESSAGE_SCB);
  7511. mk_msg_scb = ahd_lookup_scb(ahd, scbid);
  7512. } else
  7513. mk_msg_scb = NULL;
  7514. savedscbptr = ahd_get_scbptr(ahd);
  7515. tid_next = ahd_inw(ahd, WAITING_TID_HEAD);
  7516. tid_prev = SCB_LIST_NULL;
  7517. targets = 0;
  7518. for (scbid = tid_next; !SCBID_IS_NULL(scbid); scbid = tid_next) {
  7519. u_int tid_head;
  7520. u_int tid_tail;
  7521. targets++;
  7522. if (targets > AHD_NUM_TARGETS)
  7523. panic("TID LIST LOOP");
  7524. if (scbid >= ahd->scb_data.numscbs) {
  7525. printk("%s: Waiting TID List inconsistency. "
  7526. "SCB index == 0x%x, yet numscbs == 0x%x.",
  7527. ahd_name(ahd), scbid, ahd->scb_data.numscbs);
  7528. ahd_dump_card_state(ahd);
  7529. panic("for safety");
  7530. }
  7531. scb = ahd_lookup_scb(ahd, scbid);
  7532. if (scb == NULL) {
  7533. printk("%s: SCB = 0x%x Not Active!\n",
  7534. ahd_name(ahd), scbid);
  7535. panic("Waiting TID List traversal\n");
  7536. }
  7537. ahd_set_scbptr(ahd, scbid);
  7538. tid_next = ahd_inw_scbram(ahd, SCB_NEXT2);
  7539. if (ahd_match_scb(ahd, scb, target, channel, CAM_LUN_WILDCARD,
  7540. SCB_LIST_NULL, ROLE_UNKNOWN) == 0) {
  7541. tid_prev = scbid;
  7542. continue;
  7543. }
  7544. /*
  7545. * We found a list of scbs that needs to be searched.
  7546. */
  7547. if (action == SEARCH_PRINT)
  7548. printk(" %d ( ", SCB_GET_TARGET(ahd, scb));
  7549. tid_head = scbid;
  7550. found += ahd_search_scb_list(ahd, target, channel,
  7551. lun, tag, role, status,
  7552. action, &tid_head, &tid_tail,
  7553. SCB_GET_TARGET(ahd, scb));
  7554. /*
  7555. * Check any MK_MESSAGE SCB that is still waiting to
  7556. * enter this target's waiting for selection queue.
  7557. */
  7558. if (mk_msg_scb != NULL
  7559. && ahd_match_scb(ahd, mk_msg_scb, target, channel,
  7560. lun, tag, role)) {
  7561. /*
  7562. * We found an scb that needs to be acted on.
  7563. */
  7564. found++;
  7565. switch (action) {
  7566. case SEARCH_COMPLETE:
  7567. if ((mk_msg_scb->flags & SCB_ACTIVE) == 0)
  7568. printk("Inactive SCB pending MK_MSG\n");
  7569. ahd_done_with_status(ahd, mk_msg_scb, status);
  7570. /* FALLTHROUGH */
  7571. case SEARCH_REMOVE:
  7572. {
  7573. u_int tail_offset;
  7574. printk("Removing MK_MSG scb\n");
  7575. /*
  7576. * Reset our tail to the tail of the
  7577. * main per-target list.
  7578. */
  7579. tail_offset = WAITING_SCB_TAILS
  7580. + (2 * SCB_GET_TARGET(ahd, mk_msg_scb));
  7581. ahd_outw(ahd, tail_offset, tid_tail);
  7582. seq_flags2 &= ~PENDING_MK_MESSAGE;
  7583. ahd_outb(ahd, SEQ_FLAGS2, seq_flags2);
  7584. ahd_outw(ahd, CMDS_PENDING,
  7585. ahd_inw(ahd, CMDS_PENDING)-1);
  7586. mk_msg_scb = NULL;
  7587. break;
  7588. }
  7589. case SEARCH_PRINT:
  7590. printk(" 0x%x", SCB_GET_TAG(scb));
  7591. /* FALLTHROUGH */
  7592. case SEARCH_COUNT:
  7593. break;
  7594. }
  7595. }
  7596. if (mk_msg_scb != NULL
  7597. && SCBID_IS_NULL(tid_head)
  7598. && ahd_match_scb(ahd, scb, target, channel, CAM_LUN_WILDCARD,
  7599. SCB_LIST_NULL, ROLE_UNKNOWN)) {
  7600. /*
  7601. * When removing the last SCB for a target
  7602. * queue with a pending MK_MESSAGE scb, we
  7603. * must queue the MK_MESSAGE scb.
  7604. */
  7605. printk("Queueing mk_msg_scb\n");
  7606. tid_head = ahd_inw(ahd, MK_MESSAGE_SCB);
  7607. seq_flags2 &= ~PENDING_MK_MESSAGE;
  7608. ahd_outb(ahd, SEQ_FLAGS2, seq_flags2);
  7609. mk_msg_scb = NULL;
  7610. }
  7611. if (tid_head != scbid)
  7612. ahd_stitch_tid_list(ahd, tid_prev, tid_head, tid_next);
  7613. if (!SCBID_IS_NULL(tid_head))
  7614. tid_prev = tid_head;
  7615. if (action == SEARCH_PRINT)
  7616. printk(")\n");
  7617. }
  7618. /* Restore saved state. */
  7619. ahd_set_scbptr(ahd, savedscbptr);
  7620. ahd_restore_modes(ahd, saved_modes);
  7621. return (found);
  7622. }
  7623. static int
  7624. ahd_search_scb_list(struct ahd_softc *ahd, int target, char channel,
  7625. int lun, u_int tag, role_t role, uint32_t status,
  7626. ahd_search_action action, u_int *list_head,
  7627. u_int *list_tail, u_int tid)
  7628. {
  7629. struct scb *scb;
  7630. u_int scbid;
  7631. u_int next;
  7632. u_int prev;
  7633. int found;
  7634. AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
  7635. found = 0;
  7636. prev = SCB_LIST_NULL;
  7637. next = *list_head;
  7638. *list_tail = SCB_LIST_NULL;
  7639. for (scbid = next; !SCBID_IS_NULL(scbid); scbid = next) {
  7640. if (scbid >= ahd->scb_data.numscbs) {
  7641. printk("%s:SCB List inconsistency. "
  7642. "SCB == 0x%x, yet numscbs == 0x%x.",
  7643. ahd_name(ahd), scbid, ahd->scb_data.numscbs);
  7644. ahd_dump_card_state(ahd);
  7645. panic("for safety");
  7646. }
  7647. scb = ahd_lookup_scb(ahd, scbid);
  7648. if (scb == NULL) {
  7649. printk("%s: SCB = %d Not Active!\n",
  7650. ahd_name(ahd), scbid);
  7651. panic("Waiting List traversal\n");
  7652. }
  7653. ahd_set_scbptr(ahd, scbid);
  7654. *list_tail = scbid;
  7655. next = ahd_inw_scbram(ahd, SCB_NEXT);
  7656. if (ahd_match_scb(ahd, scb, target, channel,
  7657. lun, SCB_LIST_NULL, role) == 0) {
  7658. prev = scbid;
  7659. continue;
  7660. }
  7661. found++;
  7662. switch (action) {
  7663. case SEARCH_COMPLETE:
  7664. if ((scb->flags & SCB_ACTIVE) == 0)
  7665. printk("Inactive SCB in Waiting List\n");
  7666. ahd_done_with_status(ahd, scb, status);
  7667. /* FALLTHROUGH */
  7668. case SEARCH_REMOVE:
  7669. ahd_rem_wscb(ahd, scbid, prev, next, tid);
  7670. *list_tail = prev;
  7671. if (SCBID_IS_NULL(prev))
  7672. *list_head = next;
  7673. break;
  7674. case SEARCH_PRINT:
  7675. printk("0x%x ", scbid);
  7676. case SEARCH_COUNT:
  7677. prev = scbid;
  7678. break;
  7679. }
  7680. if (found > AHD_SCB_MAX)
  7681. panic("SCB LIST LOOP");
  7682. }
  7683. if (action == SEARCH_COMPLETE
  7684. || action == SEARCH_REMOVE)
  7685. ahd_outw(ahd, CMDS_PENDING, ahd_inw(ahd, CMDS_PENDING) - found);
  7686. return (found);
  7687. }
  7688. static void
  7689. ahd_stitch_tid_list(struct ahd_softc *ahd, u_int tid_prev,
  7690. u_int tid_cur, u_int tid_next)
  7691. {
  7692. AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
  7693. if (SCBID_IS_NULL(tid_cur)) {
  7694. /* Bypass current TID list */
  7695. if (SCBID_IS_NULL(tid_prev)) {
  7696. ahd_outw(ahd, WAITING_TID_HEAD, tid_next);
  7697. } else {
  7698. ahd_set_scbptr(ahd, tid_prev);
  7699. ahd_outw(ahd, SCB_NEXT2, tid_next);
  7700. }
  7701. if (SCBID_IS_NULL(tid_next))
  7702. ahd_outw(ahd, WAITING_TID_TAIL, tid_prev);
  7703. } else {
  7704. /* Stitch through tid_cur */
  7705. if (SCBID_IS_NULL(tid_prev)) {
  7706. ahd_outw(ahd, WAITING_TID_HEAD, tid_cur);
  7707. } else {
  7708. ahd_set_scbptr(ahd, tid_prev);
  7709. ahd_outw(ahd, SCB_NEXT2, tid_cur);
  7710. }
  7711. ahd_set_scbptr(ahd, tid_cur);
  7712. ahd_outw(ahd, SCB_NEXT2, tid_next);
  7713. if (SCBID_IS_NULL(tid_next))
  7714. ahd_outw(ahd, WAITING_TID_TAIL, tid_cur);
  7715. }
  7716. }
  7717. /*
  7718. * Manipulate the waiting for selection list and return the
  7719. * scb that follows the one that we remove.
  7720. */
  7721. static u_int
  7722. ahd_rem_wscb(struct ahd_softc *ahd, u_int scbid,
  7723. u_int prev, u_int next, u_int tid)
  7724. {
  7725. u_int tail_offset;
  7726. AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
  7727. if (!SCBID_IS_NULL(prev)) {
  7728. ahd_set_scbptr(ahd, prev);
  7729. ahd_outw(ahd, SCB_NEXT, next);
  7730. }
  7731. /*
  7732. * SCBs that have MK_MESSAGE set in them may
  7733. * cause the tail pointer to be updated without
  7734. * setting the next pointer of the previous tail.
  7735. * Only clear the tail if the removed SCB was
  7736. * the tail.
  7737. */
  7738. tail_offset = WAITING_SCB_TAILS + (2 * tid);
  7739. if (SCBID_IS_NULL(next)
  7740. && ahd_inw(ahd, tail_offset) == scbid)
  7741. ahd_outw(ahd, tail_offset, prev);
  7742. ahd_add_scb_to_free_list(ahd, scbid);
  7743. return (next);
  7744. }
  7745. /*
  7746. * Add the SCB as selected by SCBPTR onto the on chip list of
  7747. * free hardware SCBs. This list is empty/unused if we are not
  7748. * performing SCB paging.
  7749. */
  7750. static void
  7751. ahd_add_scb_to_free_list(struct ahd_softc *ahd, u_int scbid)
  7752. {
  7753. /* XXX Need some other mechanism to designate "free". */
  7754. /*
  7755. * Invalidate the tag so that our abort
  7756. * routines don't think it's active.
  7757. ahd_outb(ahd, SCB_TAG, SCB_LIST_NULL);
  7758. */
  7759. }
  7760. /******************************** Error Handling ******************************/
  7761. /*
  7762. * Abort all SCBs that match the given description (target/channel/lun/tag),
  7763. * setting their status to the passed in status if the status has not already
  7764. * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer
  7765. * is paused before it is called.
  7766. */
  7767. static int
  7768. ahd_abort_scbs(struct ahd_softc *ahd, int target, char channel,
  7769. int lun, u_int tag, role_t role, uint32_t status)
  7770. {
  7771. struct scb *scbp;
  7772. struct scb *scbp_next;
  7773. u_int i, j;
  7774. u_int maxtarget;
  7775. u_int minlun;
  7776. u_int maxlun;
  7777. int found;
  7778. ahd_mode_state saved_modes;
  7779. /* restore this when we're done */
  7780. saved_modes = ahd_save_modes(ahd);
  7781. ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
  7782. found = ahd_search_qinfifo(ahd, target, channel, lun, SCB_LIST_NULL,
  7783. role, CAM_REQUEUE_REQ, SEARCH_COMPLETE);
  7784. /*
  7785. * Clean out the busy target table for any untagged commands.
  7786. */
  7787. i = 0;
  7788. maxtarget = 16;
  7789. if (target != CAM_TARGET_WILDCARD) {
  7790. i = target;
  7791. if (channel == 'B')
  7792. i += 8;
  7793. maxtarget = i + 1;
  7794. }
  7795. if (lun == CAM_LUN_WILDCARD) {
  7796. minlun = 0;
  7797. maxlun = AHD_NUM_LUNS_NONPKT;
  7798. } else if (lun >= AHD_NUM_LUNS_NONPKT) {
  7799. minlun = maxlun = 0;
  7800. } else {
  7801. minlun = lun;
  7802. maxlun = lun + 1;
  7803. }
  7804. if (role != ROLE_TARGET) {
  7805. for (;i < maxtarget; i++) {
  7806. for (j = minlun;j < maxlun; j++) {
  7807. u_int scbid;
  7808. u_int tcl;
  7809. tcl = BUILD_TCL_RAW(i, 'A', j);
  7810. scbid = ahd_find_busy_tcl(ahd, tcl);
  7811. scbp = ahd_lookup_scb(ahd, scbid);
  7812. if (scbp == NULL
  7813. || ahd_match_scb(ahd, scbp, target, channel,
  7814. lun, tag, role) == 0)
  7815. continue;
  7816. ahd_unbusy_tcl(ahd, BUILD_TCL_RAW(i, 'A', j));
  7817. }
  7818. }
  7819. }
  7820. /*
  7821. * Don't abort commands that have already completed,
  7822. * but haven't quite made it up to the host yet.
  7823. */
  7824. ahd_flush_qoutfifo(ahd);
  7825. /*
  7826. * Go through the pending CCB list and look for
  7827. * commands for this target that are still active.
  7828. * These are other tagged commands that were
  7829. * disconnected when the reset occurred.
  7830. */
  7831. scbp_next = LIST_FIRST(&ahd->pending_scbs);
  7832. while (scbp_next != NULL) {
  7833. scbp = scbp_next;
  7834. scbp_next = LIST_NEXT(scbp, pending_links);
  7835. if (ahd_match_scb(ahd, scbp, target, channel, lun, tag, role)) {
  7836. cam_status ostat;
  7837. ostat = ahd_get_transaction_status(scbp);
  7838. if (ostat == CAM_REQ_INPROG)
  7839. ahd_set_transaction_status(scbp, status);
  7840. if (ahd_get_transaction_status(scbp) != CAM_REQ_CMP)
  7841. ahd_freeze_scb(scbp);
  7842. if ((scbp->flags & SCB_ACTIVE) == 0)
  7843. printk("Inactive SCB on pending list\n");
  7844. ahd_done(ahd, scbp);
  7845. found++;
  7846. }
  7847. }
  7848. ahd_restore_modes(ahd, saved_modes);
  7849. ahd_platform_abort_scbs(ahd, target, channel, lun, tag, role, status);
  7850. ahd->flags |= AHD_UPDATE_PEND_CMDS;
  7851. return found;
  7852. }
  7853. static void
  7854. ahd_reset_current_bus(struct ahd_softc *ahd)
  7855. {
  7856. uint8_t scsiseq;
  7857. AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
  7858. ahd_outb(ahd, SIMODE1, ahd_inb(ahd, SIMODE1) & ~ENSCSIRST);
  7859. scsiseq = ahd_inb(ahd, SCSISEQ0) & ~(ENSELO|ENARBO|SCSIRSTO);
  7860. ahd_outb(ahd, SCSISEQ0, scsiseq | SCSIRSTO);
  7861. ahd_flush_device_writes(ahd);
  7862. ahd_delay(AHD_BUSRESET_DELAY);
  7863. /* Turn off the bus reset */
  7864. ahd_outb(ahd, SCSISEQ0, scsiseq);
  7865. ahd_flush_device_writes(ahd);
  7866. ahd_delay(AHD_BUSRESET_DELAY);
  7867. if ((ahd->bugs & AHD_SCSIRST_BUG) != 0) {
  7868. /*
  7869. * 2A Razor #474
  7870. * Certain chip state is not cleared for
  7871. * SCSI bus resets that we initiate, so
  7872. * we must reset the chip.
  7873. */
  7874. ahd_reset(ahd, /*reinit*/TRUE);
  7875. ahd_intr_enable(ahd, /*enable*/TRUE);
  7876. AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
  7877. }
  7878. ahd_clear_intstat(ahd);
  7879. }
  7880. int
  7881. ahd_reset_channel(struct ahd_softc *ahd, char channel, int initiate_reset)
  7882. {
  7883. struct ahd_devinfo caminfo;
  7884. u_int initiator;
  7885. u_int target;
  7886. u_int max_scsiid;
  7887. int found;
  7888. u_int fifo;
  7889. u_int next_fifo;
  7890. uint8_t scsiseq;
  7891. /*
  7892. * Check if the last bus reset is cleared
  7893. */
  7894. if (ahd->flags & AHD_BUS_RESET_ACTIVE) {
  7895. printk("%s: bus reset still active\n",
  7896. ahd_name(ahd));
  7897. return 0;
  7898. }
  7899. ahd->flags |= AHD_BUS_RESET_ACTIVE;
  7900. ahd->pending_device = NULL;
  7901. ahd_compile_devinfo(&caminfo,
  7902. CAM_TARGET_WILDCARD,
  7903. CAM_TARGET_WILDCARD,
  7904. CAM_LUN_WILDCARD,
  7905. channel, ROLE_UNKNOWN);
  7906. ahd_pause(ahd);
  7907. /* Make sure the sequencer is in a safe location. */
  7908. ahd_clear_critical_section(ahd);
  7909. /*
  7910. * Run our command complete fifos to ensure that we perform
  7911. * completion processing on any commands that 'completed'
  7912. * before the reset occurred.
  7913. */
  7914. ahd_run_qoutfifo(ahd);
  7915. #ifdef AHD_TARGET_MODE
  7916. if ((ahd->flags & AHD_TARGETROLE) != 0) {
  7917. ahd_run_tqinfifo(ahd, /*paused*/TRUE);
  7918. }
  7919. #endif
  7920. ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
  7921. /*
  7922. * Disable selections so no automatic hardware
  7923. * functions will modify chip state.
  7924. */
  7925. ahd_outb(ahd, SCSISEQ0, 0);
  7926. ahd_outb(ahd, SCSISEQ1, 0);
  7927. /*
  7928. * Safely shut down our DMA engines. Always start with
  7929. * the FIFO that is not currently active (if any are
  7930. * actively connected).
  7931. */
  7932. next_fifo = fifo = ahd_inb(ahd, DFFSTAT) & CURRFIFO;
  7933. if (next_fifo > CURRFIFO_1)
  7934. /* If disconneced, arbitrarily start with FIFO1. */
  7935. next_fifo = fifo = 0;
  7936. do {
  7937. next_fifo ^= CURRFIFO_1;
  7938. ahd_set_modes(ahd, next_fifo, next_fifo);
  7939. ahd_outb(ahd, DFCNTRL,
  7940. ahd_inb(ahd, DFCNTRL) & ~(SCSIEN|HDMAEN));
  7941. while ((ahd_inb(ahd, DFCNTRL) & HDMAENACK) != 0)
  7942. ahd_delay(10);
  7943. /*
  7944. * Set CURRFIFO to the now inactive channel.
  7945. */
  7946. ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
  7947. ahd_outb(ahd, DFFSTAT, next_fifo);
  7948. } while (next_fifo != fifo);
  7949. /*
  7950. * Reset the bus if we are initiating this reset
  7951. */
  7952. ahd_clear_msg_state(ahd);
  7953. ahd_outb(ahd, SIMODE1,
  7954. ahd_inb(ahd, SIMODE1) & ~(ENBUSFREE|ENSCSIRST));
  7955. if (initiate_reset)
  7956. ahd_reset_current_bus(ahd);
  7957. ahd_clear_intstat(ahd);
  7958. /*
  7959. * Clean up all the state information for the
  7960. * pending transactions on this bus.
  7961. */
  7962. found = ahd_abort_scbs(ahd, CAM_TARGET_WILDCARD, channel,
  7963. CAM_LUN_WILDCARD, SCB_LIST_NULL,
  7964. ROLE_UNKNOWN, CAM_SCSI_BUS_RESET);
  7965. /*
  7966. * Cleanup anything left in the FIFOs.
  7967. */
  7968. ahd_clear_fifo(ahd, 0);
  7969. ahd_clear_fifo(ahd, 1);
  7970. /*
  7971. * Clear SCSI interrupt status
  7972. */
  7973. ahd_outb(ahd, CLRSINT1, CLRSCSIRSTI);
  7974. /*
  7975. * Reenable selections
  7976. */
  7977. ahd_outb(ahd, SIMODE1, ahd_inb(ahd, SIMODE1) | ENSCSIRST);
  7978. scsiseq = ahd_inb(ahd, SCSISEQ_TEMPLATE);
  7979. ahd_outb(ahd, SCSISEQ1, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP));
  7980. max_scsiid = (ahd->features & AHD_WIDE) ? 15 : 7;
  7981. #ifdef AHD_TARGET_MODE
  7982. /*
  7983. * Send an immediate notify ccb to all target more peripheral
  7984. * drivers affected by this action.
  7985. */
  7986. for (target = 0; target <= max_scsiid; target++) {
  7987. struct ahd_tmode_tstate* tstate;
  7988. u_int lun;
  7989. tstate = ahd->enabled_targets[target];
  7990. if (tstate == NULL)
  7991. continue;
  7992. for (lun = 0; lun < AHD_NUM_LUNS; lun++) {
  7993. struct ahd_tmode_lstate* lstate;
  7994. lstate = tstate->enabled_luns[lun];
  7995. if (lstate == NULL)
  7996. continue;
  7997. ahd_queue_lstate_event(ahd, lstate, CAM_TARGET_WILDCARD,
  7998. EVENT_TYPE_BUS_RESET, /*arg*/0);
  7999. ahd_send_lstate_events(ahd, lstate);
  8000. }
  8001. }
  8002. #endif
  8003. /*
  8004. * Revert to async/narrow transfers until we renegotiate.
  8005. */
  8006. for (target = 0; target <= max_scsiid; target++) {
  8007. if (ahd->enabled_targets[target] == NULL)
  8008. continue;
  8009. for (initiator = 0; initiator <= max_scsiid; initiator++) {
  8010. struct ahd_devinfo devinfo;
  8011. ahd_compile_devinfo(&devinfo, target, initiator,
  8012. CAM_LUN_WILDCARD,
  8013. 'A', ROLE_UNKNOWN);
  8014. ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
  8015. AHD_TRANS_CUR, /*paused*/TRUE);
  8016. ahd_set_syncrate(ahd, &devinfo, /*period*/0,
  8017. /*offset*/0, /*ppr_options*/0,
  8018. AHD_TRANS_CUR, /*paused*/TRUE);
  8019. }
  8020. }
  8021. /* Notify the XPT that a bus reset occurred */
  8022. ahd_send_async(ahd, caminfo.channel, CAM_TARGET_WILDCARD,
  8023. CAM_LUN_WILDCARD, AC_BUS_RESET);
  8024. ahd_restart(ahd);
  8025. return (found);
  8026. }
  8027. /**************************** Statistics Processing ***************************/
  8028. static void
  8029. ahd_stat_timer(struct timer_list *t)
  8030. {
  8031. struct ahd_softc *ahd = from_timer(ahd, t, stat_timer);
  8032. u_long s;
  8033. int enint_coal;
  8034. ahd_lock(ahd, &s);
  8035. enint_coal = ahd->hs_mailbox & ENINT_COALESCE;
  8036. if (ahd->cmdcmplt_total > ahd->int_coalescing_threshold)
  8037. enint_coal |= ENINT_COALESCE;
  8038. else if (ahd->cmdcmplt_total < ahd->int_coalescing_stop_threshold)
  8039. enint_coal &= ~ENINT_COALESCE;
  8040. if (enint_coal != (ahd->hs_mailbox & ENINT_COALESCE)) {
  8041. ahd_enable_coalescing(ahd, enint_coal);
  8042. #ifdef AHD_DEBUG
  8043. if ((ahd_debug & AHD_SHOW_INT_COALESCING) != 0)
  8044. printk("%s: Interrupt coalescing "
  8045. "now %sabled. Cmds %d\n",
  8046. ahd_name(ahd),
  8047. (enint_coal & ENINT_COALESCE) ? "en" : "dis",
  8048. ahd->cmdcmplt_total);
  8049. #endif
  8050. }
  8051. ahd->cmdcmplt_bucket = (ahd->cmdcmplt_bucket+1) & (AHD_STAT_BUCKETS-1);
  8052. ahd->cmdcmplt_total -= ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket];
  8053. ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket] = 0;
  8054. ahd_timer_reset(&ahd->stat_timer, AHD_STAT_UPDATE_US);
  8055. ahd_unlock(ahd, &s);
  8056. }
  8057. /****************************** Status Processing *****************************/
  8058. static void
  8059. ahd_handle_scsi_status(struct ahd_softc *ahd, struct scb *scb)
  8060. {
  8061. struct hardware_scb *hscb;
  8062. int paused;
  8063. /*
  8064. * The sequencer freezes its select-out queue
  8065. * anytime a SCSI status error occurs. We must
  8066. * handle the error and increment our qfreeze count
  8067. * to allow the sequencer to continue. We don't
  8068. * bother clearing critical sections here since all
  8069. * operations are on data structures that the sequencer
  8070. * is not touching once the queue is frozen.
  8071. */
  8072. hscb = scb->hscb;
  8073. if (ahd_is_paused(ahd)) {
  8074. paused = 1;
  8075. } else {
  8076. paused = 0;
  8077. ahd_pause(ahd);
  8078. }
  8079. /* Freeze the queue until the client sees the error. */
  8080. ahd_freeze_devq(ahd, scb);
  8081. ahd_freeze_scb(scb);
  8082. ahd->qfreeze_cnt++;
  8083. ahd_outw(ahd, KERNEL_QFREEZE_COUNT, ahd->qfreeze_cnt);
  8084. if (paused == 0)
  8085. ahd_unpause(ahd);
  8086. /* Don't want to clobber the original sense code */
  8087. if ((scb->flags & SCB_SENSE) != 0) {
  8088. /*
  8089. * Clear the SCB_SENSE Flag and perform
  8090. * a normal command completion.
  8091. */
  8092. scb->flags &= ~SCB_SENSE;
  8093. ahd_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
  8094. ahd_done(ahd, scb);
  8095. return;
  8096. }
  8097. ahd_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR);
  8098. ahd_set_scsi_status(scb, hscb->shared_data.istatus.scsi_status);
  8099. switch (hscb->shared_data.istatus.scsi_status) {
  8100. case STATUS_PKT_SENSE:
  8101. {
  8102. struct scsi_status_iu_header *siu;
  8103. ahd_sync_sense(ahd, scb, BUS_DMASYNC_POSTREAD);
  8104. siu = (struct scsi_status_iu_header *)scb->sense_data;
  8105. ahd_set_scsi_status(scb, siu->status);
  8106. #ifdef AHD_DEBUG
  8107. if ((ahd_debug & AHD_SHOW_SENSE) != 0) {
  8108. ahd_print_path(ahd, scb);
  8109. printk("SCB 0x%x Received PKT Status of 0x%x\n",
  8110. SCB_GET_TAG(scb), siu->status);
  8111. printk("\tflags = 0x%x, sense len = 0x%x, "
  8112. "pktfail = 0x%x\n",
  8113. siu->flags, scsi_4btoul(siu->sense_length),
  8114. scsi_4btoul(siu->pkt_failures_length));
  8115. }
  8116. #endif
  8117. if ((siu->flags & SIU_RSPVALID) != 0) {
  8118. ahd_print_path(ahd, scb);
  8119. if (scsi_4btoul(siu->pkt_failures_length) < 4) {
  8120. printk("Unable to parse pkt_failures\n");
  8121. } else {
  8122. switch (SIU_PKTFAIL_CODE(siu)) {
  8123. case SIU_PFC_NONE:
  8124. printk("No packet failure found\n");
  8125. break;
  8126. case SIU_PFC_CIU_FIELDS_INVALID:
  8127. printk("Invalid Command IU Field\n");
  8128. break;
  8129. case SIU_PFC_TMF_NOT_SUPPORTED:
  8130. printk("TMF not supported\n");
  8131. break;
  8132. case SIU_PFC_TMF_FAILED:
  8133. printk("TMF failed\n");
  8134. break;
  8135. case SIU_PFC_INVALID_TYPE_CODE:
  8136. printk("Invalid L_Q Type code\n");
  8137. break;
  8138. case SIU_PFC_ILLEGAL_REQUEST:
  8139. printk("Illegal request\n");
  8140. default:
  8141. break;
  8142. }
  8143. }
  8144. if (siu->status == SCSI_STATUS_OK)
  8145. ahd_set_transaction_status(scb,
  8146. CAM_REQ_CMP_ERR);
  8147. }
  8148. if ((siu->flags & SIU_SNSVALID) != 0) {
  8149. scb->flags |= SCB_PKT_SENSE;
  8150. #ifdef AHD_DEBUG
  8151. if ((ahd_debug & AHD_SHOW_SENSE) != 0)
  8152. printk("Sense data available\n");
  8153. #endif
  8154. }
  8155. ahd_done(ahd, scb);
  8156. break;
  8157. }
  8158. case SCSI_STATUS_CMD_TERMINATED:
  8159. case SCSI_STATUS_CHECK_COND:
  8160. {
  8161. struct ahd_devinfo devinfo;
  8162. struct ahd_dma_seg *sg;
  8163. struct scsi_sense *sc;
  8164. struct ahd_initiator_tinfo *targ_info;
  8165. struct ahd_tmode_tstate *tstate;
  8166. struct ahd_transinfo *tinfo;
  8167. #ifdef AHD_DEBUG
  8168. if (ahd_debug & AHD_SHOW_SENSE) {
  8169. ahd_print_path(ahd, scb);
  8170. printk("SCB %d: requests Check Status\n",
  8171. SCB_GET_TAG(scb));
  8172. }
  8173. #endif
  8174. if (ahd_perform_autosense(scb) == 0)
  8175. break;
  8176. ahd_compile_devinfo(&devinfo, SCB_GET_OUR_ID(scb),
  8177. SCB_GET_TARGET(ahd, scb),
  8178. SCB_GET_LUN(scb),
  8179. SCB_GET_CHANNEL(ahd, scb),
  8180. ROLE_INITIATOR);
  8181. targ_info = ahd_fetch_transinfo(ahd,
  8182. devinfo.channel,
  8183. devinfo.our_scsiid,
  8184. devinfo.target,
  8185. &tstate);
  8186. tinfo = &targ_info->curr;
  8187. sg = scb->sg_list;
  8188. sc = (struct scsi_sense *)hscb->shared_data.idata.cdb;
  8189. /*
  8190. * Save off the residual if there is one.
  8191. */
  8192. ahd_update_residual(ahd, scb);
  8193. #ifdef AHD_DEBUG
  8194. if (ahd_debug & AHD_SHOW_SENSE) {
  8195. ahd_print_path(ahd, scb);
  8196. printk("Sending Sense\n");
  8197. }
  8198. #endif
  8199. scb->sg_count = 0;
  8200. sg = ahd_sg_setup(ahd, scb, sg, ahd_get_sense_bufaddr(ahd, scb),
  8201. ahd_get_sense_bufsize(ahd, scb),
  8202. /*last*/TRUE);
  8203. sc->opcode = REQUEST_SENSE;
  8204. sc->byte2 = 0;
  8205. if (tinfo->protocol_version <= SCSI_REV_2
  8206. && SCB_GET_LUN(scb) < 8)
  8207. sc->byte2 = SCB_GET_LUN(scb) << 5;
  8208. sc->unused[0] = 0;
  8209. sc->unused[1] = 0;
  8210. sc->length = ahd_get_sense_bufsize(ahd, scb);
  8211. sc->control = 0;
  8212. /*
  8213. * We can't allow the target to disconnect.
  8214. * This will be an untagged transaction and
  8215. * having the target disconnect will make this
  8216. * transaction indestinguishable from outstanding
  8217. * tagged transactions.
  8218. */
  8219. hscb->control = 0;
  8220. /*
  8221. * This request sense could be because the
  8222. * the device lost power or in some other
  8223. * way has lost our transfer negotiations.
  8224. * Renegotiate if appropriate. Unit attention
  8225. * errors will be reported before any data
  8226. * phases occur.
  8227. */
  8228. if (ahd_get_residual(scb) == ahd_get_transfer_length(scb)) {
  8229. ahd_update_neg_request(ahd, &devinfo,
  8230. tstate, targ_info,
  8231. AHD_NEG_IF_NON_ASYNC);
  8232. }
  8233. if (tstate->auto_negotiate & devinfo.target_mask) {
  8234. hscb->control |= MK_MESSAGE;
  8235. scb->flags &=
  8236. ~(SCB_NEGOTIATE|SCB_ABORT|SCB_DEVICE_RESET);
  8237. scb->flags |= SCB_AUTO_NEGOTIATE;
  8238. }
  8239. hscb->cdb_len = sizeof(*sc);
  8240. ahd_setup_data_scb(ahd, scb);
  8241. scb->flags |= SCB_SENSE;
  8242. ahd_queue_scb(ahd, scb);
  8243. break;
  8244. }
  8245. case SCSI_STATUS_OK:
  8246. printk("%s: Interrupted for status of 0???\n",
  8247. ahd_name(ahd));
  8248. /* FALLTHROUGH */
  8249. default:
  8250. ahd_done(ahd, scb);
  8251. break;
  8252. }
  8253. }
  8254. static void
  8255. ahd_handle_scb_status(struct ahd_softc *ahd, struct scb *scb)
  8256. {
  8257. if (scb->hscb->shared_data.istatus.scsi_status != 0) {
  8258. ahd_handle_scsi_status(ahd, scb);
  8259. } else {
  8260. ahd_calc_residual(ahd, scb);
  8261. ahd_done(ahd, scb);
  8262. }
  8263. }
  8264. /*
  8265. * Calculate the residual for a just completed SCB.
  8266. */
  8267. static void
  8268. ahd_calc_residual(struct ahd_softc *ahd, struct scb *scb)
  8269. {
  8270. struct hardware_scb *hscb;
  8271. struct initiator_status *spkt;
  8272. uint32_t sgptr;
  8273. uint32_t resid_sgptr;
  8274. uint32_t resid;
  8275. /*
  8276. * 5 cases.
  8277. * 1) No residual.
  8278. * SG_STATUS_VALID clear in sgptr.
  8279. * 2) Transferless command
  8280. * 3) Never performed any transfers.
  8281. * sgptr has SG_FULL_RESID set.
  8282. * 4) No residual but target did not
  8283. * save data pointers after the
  8284. * last transfer, so sgptr was
  8285. * never updated.
  8286. * 5) We have a partial residual.
  8287. * Use residual_sgptr to determine
  8288. * where we are.
  8289. */
  8290. hscb = scb->hscb;
  8291. sgptr = ahd_le32toh(hscb->sgptr);
  8292. if ((sgptr & SG_STATUS_VALID) == 0)
  8293. /* Case 1 */
  8294. return;
  8295. sgptr &= ~SG_STATUS_VALID;
  8296. if ((sgptr & SG_LIST_NULL) != 0)
  8297. /* Case 2 */
  8298. return;
  8299. /*
  8300. * Residual fields are the same in both
  8301. * target and initiator status packets,
  8302. * so we can always use the initiator fields
  8303. * regardless of the role for this SCB.
  8304. */
  8305. spkt = &hscb->shared_data.istatus;
  8306. resid_sgptr = ahd_le32toh(spkt->residual_sgptr);
  8307. if ((sgptr & SG_FULL_RESID) != 0) {
  8308. /* Case 3 */
  8309. resid = ahd_get_transfer_length(scb);
  8310. } else if ((resid_sgptr & SG_LIST_NULL) != 0) {
  8311. /* Case 4 */
  8312. return;
  8313. } else if ((resid_sgptr & SG_OVERRUN_RESID) != 0) {
  8314. ahd_print_path(ahd, scb);
  8315. printk("data overrun detected Tag == 0x%x.\n",
  8316. SCB_GET_TAG(scb));
  8317. ahd_freeze_devq(ahd, scb);
  8318. ahd_set_transaction_status(scb, CAM_DATA_RUN_ERR);
  8319. ahd_freeze_scb(scb);
  8320. return;
  8321. } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) {
  8322. panic("Bogus resid sgptr value 0x%x\n", resid_sgptr);
  8323. /* NOTREACHED */
  8324. } else {
  8325. struct ahd_dma_seg *sg;
  8326. /*
  8327. * Remainder of the SG where the transfer
  8328. * stopped.
  8329. */
  8330. resid = ahd_le32toh(spkt->residual_datacnt) & AHD_SG_LEN_MASK;
  8331. sg = ahd_sg_bus_to_virt(ahd, scb, resid_sgptr & SG_PTR_MASK);
  8332. /* The residual sg_ptr always points to the next sg */
  8333. sg--;
  8334. /*
  8335. * Add up the contents of all residual
  8336. * SG segments that are after the SG where
  8337. * the transfer stopped.
  8338. */
  8339. while ((ahd_le32toh(sg->len) & AHD_DMA_LAST_SEG) == 0) {
  8340. sg++;
  8341. resid += ahd_le32toh(sg->len) & AHD_SG_LEN_MASK;
  8342. }
  8343. }
  8344. if ((scb->flags & SCB_SENSE) == 0)
  8345. ahd_set_residual(scb, resid);
  8346. else
  8347. ahd_set_sense_residual(scb, resid);
  8348. #ifdef AHD_DEBUG
  8349. if ((ahd_debug & AHD_SHOW_MISC) != 0) {
  8350. ahd_print_path(ahd, scb);
  8351. printk("Handled %sResidual of %d bytes\n",
  8352. (scb->flags & SCB_SENSE) ? "Sense " : "", resid);
  8353. }
  8354. #endif
  8355. }
  8356. /******************************* Target Mode **********************************/
  8357. #ifdef AHD_TARGET_MODE
  8358. /*
  8359. * Add a target mode event to this lun's queue
  8360. */
  8361. static void
  8362. ahd_queue_lstate_event(struct ahd_softc *ahd, struct ahd_tmode_lstate *lstate,
  8363. u_int initiator_id, u_int event_type, u_int event_arg)
  8364. {
  8365. struct ahd_tmode_event *event;
  8366. int pending;
  8367. xpt_freeze_devq(lstate->path, /*count*/1);
  8368. if (lstate->event_w_idx >= lstate->event_r_idx)
  8369. pending = lstate->event_w_idx - lstate->event_r_idx;
  8370. else
  8371. pending = AHD_TMODE_EVENT_BUFFER_SIZE + 1
  8372. - (lstate->event_r_idx - lstate->event_w_idx);
  8373. if (event_type == EVENT_TYPE_BUS_RESET
  8374. || event_type == MSG_BUS_DEV_RESET) {
  8375. /*
  8376. * Any earlier events are irrelevant, so reset our buffer.
  8377. * This has the effect of allowing us to deal with reset
  8378. * floods (an external device holding down the reset line)
  8379. * without losing the event that is really interesting.
  8380. */
  8381. lstate->event_r_idx = 0;
  8382. lstate->event_w_idx = 0;
  8383. xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE);
  8384. }
  8385. if (pending == AHD_TMODE_EVENT_BUFFER_SIZE) {
  8386. xpt_print_path(lstate->path);
  8387. printk("immediate event %x:%x lost\n",
  8388. lstate->event_buffer[lstate->event_r_idx].event_type,
  8389. lstate->event_buffer[lstate->event_r_idx].event_arg);
  8390. lstate->event_r_idx++;
  8391. if (lstate->event_r_idx == AHD_TMODE_EVENT_BUFFER_SIZE)
  8392. lstate->event_r_idx = 0;
  8393. xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE);
  8394. }
  8395. event = &lstate->event_buffer[lstate->event_w_idx];
  8396. event->initiator_id = initiator_id;
  8397. event->event_type = event_type;
  8398. event->event_arg = event_arg;
  8399. lstate->event_w_idx++;
  8400. if (lstate->event_w_idx == AHD_TMODE_EVENT_BUFFER_SIZE)
  8401. lstate->event_w_idx = 0;
  8402. }
  8403. /*
  8404. * Send any target mode events queued up waiting
  8405. * for immediate notify resources.
  8406. */
  8407. void
  8408. ahd_send_lstate_events(struct ahd_softc *ahd, struct ahd_tmode_lstate *lstate)
  8409. {
  8410. struct ccb_hdr *ccbh;
  8411. struct ccb_immed_notify *inot;
  8412. while (lstate->event_r_idx != lstate->event_w_idx
  8413. && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) {
  8414. struct ahd_tmode_event *event;
  8415. event = &lstate->event_buffer[lstate->event_r_idx];
  8416. SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle);
  8417. inot = (struct ccb_immed_notify *)ccbh;
  8418. switch (event->event_type) {
  8419. case EVENT_TYPE_BUS_RESET:
  8420. ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN;
  8421. break;
  8422. default:
  8423. ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN;
  8424. inot->message_args[0] = event->event_type;
  8425. inot->message_args[1] = event->event_arg;
  8426. break;
  8427. }
  8428. inot->initiator_id = event->initiator_id;
  8429. inot->sense_len = 0;
  8430. xpt_done((union ccb *)inot);
  8431. lstate->event_r_idx++;
  8432. if (lstate->event_r_idx == AHD_TMODE_EVENT_BUFFER_SIZE)
  8433. lstate->event_r_idx = 0;
  8434. }
  8435. }
  8436. #endif
  8437. /******************** Sequencer Program Patching/Download *********************/
  8438. #ifdef AHD_DUMP_SEQ
  8439. void
  8440. ahd_dumpseq(struct ahd_softc* ahd)
  8441. {
  8442. int i;
  8443. int max_prog;
  8444. max_prog = 2048;
  8445. ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
  8446. ahd_outw(ahd, PRGMCNT, 0);
  8447. for (i = 0; i < max_prog; i++) {
  8448. uint8_t ins_bytes[4];
  8449. ahd_insb(ahd, SEQRAM, ins_bytes, 4);
  8450. printk("0x%08x\n", ins_bytes[0] << 24
  8451. | ins_bytes[1] << 16
  8452. | ins_bytes[2] << 8
  8453. | ins_bytes[3]);
  8454. }
  8455. }
  8456. #endif
  8457. static void
  8458. ahd_loadseq(struct ahd_softc *ahd)
  8459. {
  8460. struct cs cs_table[NUM_CRITICAL_SECTIONS];
  8461. u_int begin_set[NUM_CRITICAL_SECTIONS];
  8462. u_int end_set[NUM_CRITICAL_SECTIONS];
  8463. const struct patch *cur_patch;
  8464. u_int cs_count;
  8465. u_int cur_cs;
  8466. u_int i;
  8467. int downloaded;
  8468. u_int skip_addr;
  8469. u_int sg_prefetch_cnt;
  8470. u_int sg_prefetch_cnt_limit;
  8471. u_int sg_prefetch_align;
  8472. u_int sg_size;
  8473. u_int cacheline_mask;
  8474. uint8_t download_consts[DOWNLOAD_CONST_COUNT];
  8475. if (bootverbose)
  8476. printk("%s: Downloading Sequencer Program...",
  8477. ahd_name(ahd));
  8478. #if DOWNLOAD_CONST_COUNT != 8
  8479. #error "Download Const Mismatch"
  8480. #endif
  8481. /*
  8482. * Start out with 0 critical sections
  8483. * that apply to this firmware load.
  8484. */
  8485. cs_count = 0;
  8486. cur_cs = 0;
  8487. memset(begin_set, 0, sizeof(begin_set));
  8488. memset(end_set, 0, sizeof(end_set));
  8489. /*
  8490. * Setup downloadable constant table.
  8491. *
  8492. * The computation for the S/G prefetch variables is
  8493. * a bit complicated. We would like to always fetch
  8494. * in terms of cachelined sized increments. However,
  8495. * if the cacheline is not an even multiple of the
  8496. * SG element size or is larger than our SG RAM, using
  8497. * just the cache size might leave us with only a portion
  8498. * of an SG element at the tail of a prefetch. If the
  8499. * cacheline is larger than our S/G prefetch buffer less
  8500. * the size of an SG element, we may round down to a cacheline
  8501. * that doesn't contain any or all of the S/G of interest
  8502. * within the bounds of our S/G ram. Provide variables to
  8503. * the sequencer that will allow it to handle these edge
  8504. * cases.
  8505. */
  8506. /* Start by aligning to the nearest cacheline. */
  8507. sg_prefetch_align = ahd->pci_cachesize;
  8508. if (sg_prefetch_align == 0)
  8509. sg_prefetch_align = 8;
  8510. /* Round down to the nearest power of 2. */
  8511. while (powerof2(sg_prefetch_align) == 0)
  8512. sg_prefetch_align--;
  8513. cacheline_mask = sg_prefetch_align - 1;
  8514. /*
  8515. * If the cacheline boundary is greater than half our prefetch RAM
  8516. * we risk not being able to fetch even a single complete S/G
  8517. * segment if we align to that boundary.
  8518. */
  8519. if (sg_prefetch_align > CCSGADDR_MAX/2)
  8520. sg_prefetch_align = CCSGADDR_MAX/2;
  8521. /* Start by fetching a single cacheline. */
  8522. sg_prefetch_cnt = sg_prefetch_align;
  8523. /*
  8524. * Increment the prefetch count by cachelines until
  8525. * at least one S/G element will fit.
  8526. */
  8527. sg_size = sizeof(struct ahd_dma_seg);
  8528. if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0)
  8529. sg_size = sizeof(struct ahd_dma64_seg);
  8530. while (sg_prefetch_cnt < sg_size)
  8531. sg_prefetch_cnt += sg_prefetch_align;
  8532. /*
  8533. * If the cacheline is not an even multiple of
  8534. * the S/G size, we may only get a partial S/G when
  8535. * we align. Add a cacheline if this is the case.
  8536. */
  8537. if ((sg_prefetch_align % sg_size) != 0
  8538. && (sg_prefetch_cnt < CCSGADDR_MAX))
  8539. sg_prefetch_cnt += sg_prefetch_align;
  8540. /*
  8541. * Lastly, compute a value that the sequencer can use
  8542. * to determine if the remainder of the CCSGRAM buffer
  8543. * has a full S/G element in it.
  8544. */
  8545. sg_prefetch_cnt_limit = -(sg_prefetch_cnt - sg_size + 1);
  8546. download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt;
  8547. download_consts[SG_PREFETCH_CNT_LIMIT] = sg_prefetch_cnt_limit;
  8548. download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_align - 1);
  8549. download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_align - 1);
  8550. download_consts[SG_SIZEOF] = sg_size;
  8551. download_consts[PKT_OVERRUN_BUFOFFSET] =
  8552. (ahd->overrun_buf - (uint8_t *)ahd->qoutfifo) / 256;
  8553. download_consts[SCB_TRANSFER_SIZE] = SCB_TRANSFER_SIZE_1BYTE_LUN;
  8554. download_consts[CACHELINE_MASK] = cacheline_mask;
  8555. cur_patch = patches;
  8556. downloaded = 0;
  8557. skip_addr = 0;
  8558. ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
  8559. ahd_outw(ahd, PRGMCNT, 0);
  8560. for (i = 0; i < sizeof(seqprog)/4; i++) {
  8561. if (ahd_check_patch(ahd, &cur_patch, i, &skip_addr) == 0) {
  8562. /*
  8563. * Don't download this instruction as it
  8564. * is in a patch that was removed.
  8565. */
  8566. continue;
  8567. }
  8568. /*
  8569. * Move through the CS table until we find a CS
  8570. * that might apply to this instruction.
  8571. */
  8572. for (; cur_cs < NUM_CRITICAL_SECTIONS; cur_cs++) {
  8573. if (critical_sections[cur_cs].end <= i) {
  8574. if (begin_set[cs_count] == TRUE
  8575. && end_set[cs_count] == FALSE) {
  8576. cs_table[cs_count].end = downloaded;
  8577. end_set[cs_count] = TRUE;
  8578. cs_count++;
  8579. }
  8580. continue;
  8581. }
  8582. if (critical_sections[cur_cs].begin <= i
  8583. && begin_set[cs_count] == FALSE) {
  8584. cs_table[cs_count].begin = downloaded;
  8585. begin_set[cs_count] = TRUE;
  8586. }
  8587. break;
  8588. }
  8589. ahd_download_instr(ahd, i, download_consts);
  8590. downloaded++;
  8591. }
  8592. ahd->num_critical_sections = cs_count;
  8593. if (cs_count != 0) {
  8594. cs_count *= sizeof(struct cs);
  8595. ahd->critical_sections = kmalloc(cs_count, GFP_ATOMIC);
  8596. if (ahd->critical_sections == NULL)
  8597. panic("ahd_loadseq: Could not malloc");
  8598. memcpy(ahd->critical_sections, cs_table, cs_count);
  8599. }
  8600. ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE);
  8601. if (bootverbose) {
  8602. printk(" %d instructions downloaded\n", downloaded);
  8603. printk("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n",
  8604. ahd_name(ahd), ahd->features, ahd->bugs, ahd->flags);
  8605. }
  8606. }
  8607. static int
  8608. ahd_check_patch(struct ahd_softc *ahd, const struct patch **start_patch,
  8609. u_int start_instr, u_int *skip_addr)
  8610. {
  8611. const struct patch *cur_patch;
  8612. const struct patch *last_patch;
  8613. u_int num_patches;
  8614. num_patches = ARRAY_SIZE(patches);
  8615. last_patch = &patches[num_patches];
  8616. cur_patch = *start_patch;
  8617. while (cur_patch < last_patch && start_instr == cur_patch->begin) {
  8618. if (cur_patch->patch_func(ahd) == 0) {
  8619. /* Start rejecting code */
  8620. *skip_addr = start_instr + cur_patch->skip_instr;
  8621. cur_patch += cur_patch->skip_patch;
  8622. } else {
  8623. /* Accepted this patch. Advance to the next
  8624. * one and wait for our intruction pointer to
  8625. * hit this point.
  8626. */
  8627. cur_patch++;
  8628. }
  8629. }
  8630. *start_patch = cur_patch;
  8631. if (start_instr < *skip_addr)
  8632. /* Still skipping */
  8633. return (0);
  8634. return (1);
  8635. }
  8636. static u_int
  8637. ahd_resolve_seqaddr(struct ahd_softc *ahd, u_int address)
  8638. {
  8639. const struct patch *cur_patch;
  8640. int address_offset;
  8641. u_int skip_addr;
  8642. u_int i;
  8643. address_offset = 0;
  8644. cur_patch = patches;
  8645. skip_addr = 0;
  8646. for (i = 0; i < address;) {
  8647. ahd_check_patch(ahd, &cur_patch, i, &skip_addr);
  8648. if (skip_addr > i) {
  8649. int end_addr;
  8650. end_addr = min(address, skip_addr);
  8651. address_offset += end_addr - i;
  8652. i = skip_addr;
  8653. } else {
  8654. i++;
  8655. }
  8656. }
  8657. return (address - address_offset);
  8658. }
  8659. static void
  8660. ahd_download_instr(struct ahd_softc *ahd, u_int instrptr, uint8_t *dconsts)
  8661. {
  8662. union ins_formats instr;
  8663. struct ins_format1 *fmt1_ins;
  8664. struct ins_format3 *fmt3_ins;
  8665. u_int opcode;
  8666. /*
  8667. * The firmware is always compiled into a little endian format.
  8668. */
  8669. instr.integer = ahd_le32toh(*(uint32_t*)&seqprog[instrptr * 4]);
  8670. fmt1_ins = &instr.format1;
  8671. fmt3_ins = NULL;
  8672. /* Pull the opcode */
  8673. opcode = instr.format1.opcode;
  8674. switch (opcode) {
  8675. case AIC_OP_JMP:
  8676. case AIC_OP_JC:
  8677. case AIC_OP_JNC:
  8678. case AIC_OP_CALL:
  8679. case AIC_OP_JNE:
  8680. case AIC_OP_JNZ:
  8681. case AIC_OP_JE:
  8682. case AIC_OP_JZ:
  8683. {
  8684. fmt3_ins = &instr.format3;
  8685. fmt3_ins->address = ahd_resolve_seqaddr(ahd, fmt3_ins->address);
  8686. /* FALLTHROUGH */
  8687. }
  8688. case AIC_OP_OR:
  8689. case AIC_OP_AND:
  8690. case AIC_OP_XOR:
  8691. case AIC_OP_ADD:
  8692. case AIC_OP_ADC:
  8693. case AIC_OP_BMOV:
  8694. if (fmt1_ins->parity != 0) {
  8695. fmt1_ins->immediate = dconsts[fmt1_ins->immediate];
  8696. }
  8697. fmt1_ins->parity = 0;
  8698. /* FALLTHROUGH */
  8699. case AIC_OP_ROL:
  8700. {
  8701. int i, count;
  8702. /* Calculate odd parity for the instruction */
  8703. for (i = 0, count = 0; i < 31; i++) {
  8704. uint32_t mask;
  8705. mask = 0x01 << i;
  8706. if ((instr.integer & mask) != 0)
  8707. count++;
  8708. }
  8709. if ((count & 0x01) == 0)
  8710. instr.format1.parity = 1;
  8711. /* The sequencer is a little endian cpu */
  8712. instr.integer = ahd_htole32(instr.integer);
  8713. ahd_outsb(ahd, SEQRAM, instr.bytes, 4);
  8714. break;
  8715. }
  8716. default:
  8717. panic("Unknown opcode encountered in seq program");
  8718. break;
  8719. }
  8720. }
  8721. static int
  8722. ahd_probe_stack_size(struct ahd_softc *ahd)
  8723. {
  8724. int last_probe;
  8725. last_probe = 0;
  8726. while (1) {
  8727. int i;
  8728. /*
  8729. * We avoid using 0 as a pattern to avoid
  8730. * confusion if the stack implementation
  8731. * "back-fills" with zeros when "poping'
  8732. * entries.
  8733. */
  8734. for (i = 1; i <= last_probe+1; i++) {
  8735. ahd_outb(ahd, STACK, i & 0xFF);
  8736. ahd_outb(ahd, STACK, (i >> 8) & 0xFF);
  8737. }
  8738. /* Verify */
  8739. for (i = last_probe+1; i > 0; i--) {
  8740. u_int stack_entry;
  8741. stack_entry = ahd_inb(ahd, STACK)
  8742. |(ahd_inb(ahd, STACK) << 8);
  8743. if (stack_entry != i)
  8744. goto sized;
  8745. }
  8746. last_probe++;
  8747. }
  8748. sized:
  8749. return (last_probe);
  8750. }
  8751. int
  8752. ahd_print_register(const ahd_reg_parse_entry_t *table, u_int num_entries,
  8753. const char *name, u_int address, u_int value,
  8754. u_int *cur_column, u_int wrap_point)
  8755. {
  8756. int printed;
  8757. u_int printed_mask;
  8758. if (cur_column != NULL && *cur_column >= wrap_point) {
  8759. printk("\n");
  8760. *cur_column = 0;
  8761. }
  8762. printed = printk("%s[0x%x]", name, value);
  8763. if (table == NULL) {
  8764. printed += printk(" ");
  8765. *cur_column += printed;
  8766. return (printed);
  8767. }
  8768. printed_mask = 0;
  8769. while (printed_mask != 0xFF) {
  8770. int entry;
  8771. for (entry = 0; entry < num_entries; entry++) {
  8772. if (((value & table[entry].mask)
  8773. != table[entry].value)
  8774. || ((printed_mask & table[entry].mask)
  8775. == table[entry].mask))
  8776. continue;
  8777. printed += printk("%s%s",
  8778. printed_mask == 0 ? ":(" : "|",
  8779. table[entry].name);
  8780. printed_mask |= table[entry].mask;
  8781. break;
  8782. }
  8783. if (entry >= num_entries)
  8784. break;
  8785. }
  8786. if (printed_mask != 0)
  8787. printed += printk(") ");
  8788. else
  8789. printed += printk(" ");
  8790. if (cur_column != NULL)
  8791. *cur_column += printed;
  8792. return (printed);
  8793. }
  8794. void
  8795. ahd_dump_card_state(struct ahd_softc *ahd)
  8796. {
  8797. struct scb *scb;
  8798. ahd_mode_state saved_modes;
  8799. u_int dffstat;
  8800. int paused;
  8801. u_int scb_index;
  8802. u_int saved_scb_index;
  8803. u_int cur_col;
  8804. int i;
  8805. if (ahd_is_paused(ahd)) {
  8806. paused = 1;
  8807. } else {
  8808. paused = 0;
  8809. ahd_pause(ahd);
  8810. }
  8811. saved_modes = ahd_save_modes(ahd);
  8812. ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
  8813. printk(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n"
  8814. "%s: Dumping Card State at program address 0x%x Mode 0x%x\n",
  8815. ahd_name(ahd),
  8816. ahd_inw(ahd, CURADDR),
  8817. ahd_build_mode_state(ahd, ahd->saved_src_mode,
  8818. ahd->saved_dst_mode));
  8819. if (paused)
  8820. printk("Card was paused\n");
  8821. if (ahd_check_cmdcmpltqueues(ahd))
  8822. printk("Completions are pending\n");
  8823. /*
  8824. * Mode independent registers.
  8825. */
  8826. cur_col = 0;
  8827. ahd_intstat_print(ahd_inb(ahd, INTSTAT), &cur_col, 50);
  8828. ahd_seloid_print(ahd_inb(ahd, SELOID), &cur_col, 50);
  8829. ahd_selid_print(ahd_inb(ahd, SELID), &cur_col, 50);
  8830. ahd_hs_mailbox_print(ahd_inb(ahd, LOCAL_HS_MAILBOX), &cur_col, 50);
  8831. ahd_intctl_print(ahd_inb(ahd, INTCTL), &cur_col, 50);
  8832. ahd_seqintstat_print(ahd_inb(ahd, SEQINTSTAT), &cur_col, 50);
  8833. ahd_saved_mode_print(ahd_inb(ahd, SAVED_MODE), &cur_col, 50);
  8834. ahd_dffstat_print(ahd_inb(ahd, DFFSTAT), &cur_col, 50);
  8835. ahd_scsisigi_print(ahd_inb(ahd, SCSISIGI), &cur_col, 50);
  8836. ahd_scsiphase_print(ahd_inb(ahd, SCSIPHASE), &cur_col, 50);
  8837. ahd_scsibus_print(ahd_inb(ahd, SCSIBUS), &cur_col, 50);
  8838. ahd_lastphase_print(ahd_inb(ahd, LASTPHASE), &cur_col, 50);
  8839. ahd_scsiseq0_print(ahd_inb(ahd, SCSISEQ0), &cur_col, 50);
  8840. ahd_scsiseq1_print(ahd_inb(ahd, SCSISEQ1), &cur_col, 50);
  8841. ahd_seqctl0_print(ahd_inb(ahd, SEQCTL0), &cur_col, 50);
  8842. ahd_seqintctl_print(ahd_inb(ahd, SEQINTCTL), &cur_col, 50);
  8843. ahd_seq_flags_print(ahd_inb(ahd, SEQ_FLAGS), &cur_col, 50);
  8844. ahd_seq_flags2_print(ahd_inb(ahd, SEQ_FLAGS2), &cur_col, 50);
  8845. ahd_qfreeze_count_print(ahd_inw(ahd, QFREEZE_COUNT), &cur_col, 50);
  8846. ahd_kernel_qfreeze_count_print(ahd_inw(ahd, KERNEL_QFREEZE_COUNT),
  8847. &cur_col, 50);
  8848. ahd_mk_message_scb_print(ahd_inw(ahd, MK_MESSAGE_SCB), &cur_col, 50);
  8849. ahd_mk_message_scsiid_print(ahd_inb(ahd, MK_MESSAGE_SCSIID),
  8850. &cur_col, 50);
  8851. ahd_sstat0_print(ahd_inb(ahd, SSTAT0), &cur_col, 50);
  8852. ahd_sstat1_print(ahd_inb(ahd, SSTAT1), &cur_col, 50);
  8853. ahd_sstat2_print(ahd_inb(ahd, SSTAT2), &cur_col, 50);
  8854. ahd_sstat3_print(ahd_inb(ahd, SSTAT3), &cur_col, 50);
  8855. ahd_perrdiag_print(ahd_inb(ahd, PERRDIAG), &cur_col, 50);
  8856. ahd_simode1_print(ahd_inb(ahd, SIMODE1), &cur_col, 50);
  8857. ahd_lqistat0_print(ahd_inb(ahd, LQISTAT0), &cur_col, 50);
  8858. ahd_lqistat1_print(ahd_inb(ahd, LQISTAT1), &cur_col, 50);
  8859. ahd_lqistat2_print(ahd_inb(ahd, LQISTAT2), &cur_col, 50);
  8860. ahd_lqostat0_print(ahd_inb(ahd, LQOSTAT0), &cur_col, 50);
  8861. ahd_lqostat1_print(ahd_inb(ahd, LQOSTAT1), &cur_col, 50);
  8862. ahd_lqostat2_print(ahd_inb(ahd, LQOSTAT2), &cur_col, 50);
  8863. printk("\n");
  8864. printk("\nSCB Count = %d CMDS_PENDING = %d LASTSCB 0x%x "
  8865. "CURRSCB 0x%x NEXTSCB 0x%x\n",
  8866. ahd->scb_data.numscbs, ahd_inw(ahd, CMDS_PENDING),
  8867. ahd_inw(ahd, LASTSCB), ahd_inw(ahd, CURRSCB),
  8868. ahd_inw(ahd, NEXTSCB));
  8869. cur_col = 0;
  8870. /* QINFIFO */
  8871. ahd_search_qinfifo(ahd, CAM_TARGET_WILDCARD, ALL_CHANNELS,
  8872. CAM_LUN_WILDCARD, SCB_LIST_NULL,
  8873. ROLE_UNKNOWN, /*status*/0, SEARCH_PRINT);
  8874. saved_scb_index = ahd_get_scbptr(ahd);
  8875. printk("Pending list:");
  8876. i = 0;
  8877. LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) {
  8878. if (i++ > AHD_SCB_MAX)
  8879. break;
  8880. cur_col = printk("\n%3d FIFO_USE[0x%x] ", SCB_GET_TAG(scb),
  8881. ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT));
  8882. ahd_set_scbptr(ahd, SCB_GET_TAG(scb));
  8883. ahd_scb_control_print(ahd_inb_scbram(ahd, SCB_CONTROL),
  8884. &cur_col, 60);
  8885. ahd_scb_scsiid_print(ahd_inb_scbram(ahd, SCB_SCSIID),
  8886. &cur_col, 60);
  8887. }
  8888. printk("\nTotal %d\n", i);
  8889. printk("Kernel Free SCB list: ");
  8890. i = 0;
  8891. TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) {
  8892. struct scb *list_scb;
  8893. list_scb = scb;
  8894. do {
  8895. printk("%d ", SCB_GET_TAG(list_scb));
  8896. list_scb = LIST_NEXT(list_scb, collision_links);
  8897. } while (list_scb && i++ < AHD_SCB_MAX);
  8898. }
  8899. LIST_FOREACH(scb, &ahd->scb_data.any_dev_free_scb_list, links.le) {
  8900. if (i++ > AHD_SCB_MAX)
  8901. break;
  8902. printk("%d ", SCB_GET_TAG(scb));
  8903. }
  8904. printk("\n");
  8905. printk("Sequencer Complete DMA-inprog list: ");
  8906. scb_index = ahd_inw(ahd, COMPLETE_SCB_DMAINPROG_HEAD);
  8907. i = 0;
  8908. while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) {
  8909. ahd_set_scbptr(ahd, scb_index);
  8910. printk("%d ", scb_index);
  8911. scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
  8912. }
  8913. printk("\n");
  8914. printk("Sequencer Complete list: ");
  8915. scb_index = ahd_inw(ahd, COMPLETE_SCB_HEAD);
  8916. i = 0;
  8917. while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) {
  8918. ahd_set_scbptr(ahd, scb_index);
  8919. printk("%d ", scb_index);
  8920. scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
  8921. }
  8922. printk("\n");
  8923. printk("Sequencer DMA-Up and Complete list: ");
  8924. scb_index = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD);
  8925. i = 0;
  8926. while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) {
  8927. ahd_set_scbptr(ahd, scb_index);
  8928. printk("%d ", scb_index);
  8929. scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
  8930. }
  8931. printk("\n");
  8932. printk("Sequencer On QFreeze and Complete list: ");
  8933. scb_index = ahd_inw(ahd, COMPLETE_ON_QFREEZE_HEAD);
  8934. i = 0;
  8935. while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) {
  8936. ahd_set_scbptr(ahd, scb_index);
  8937. printk("%d ", scb_index);
  8938. scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
  8939. }
  8940. printk("\n");
  8941. ahd_set_scbptr(ahd, saved_scb_index);
  8942. dffstat = ahd_inb(ahd, DFFSTAT);
  8943. for (i = 0; i < 2; i++) {
  8944. #ifdef AHD_DEBUG
  8945. struct scb *fifo_scb;
  8946. #endif
  8947. u_int fifo_scbptr;
  8948. ahd_set_modes(ahd, AHD_MODE_DFF0 + i, AHD_MODE_DFF0 + i);
  8949. fifo_scbptr = ahd_get_scbptr(ahd);
  8950. printk("\n\n%s: FIFO%d %s, LONGJMP == 0x%x, SCB 0x%x\n",
  8951. ahd_name(ahd), i,
  8952. (dffstat & (FIFO0FREE << i)) ? "Free" : "Active",
  8953. ahd_inw(ahd, LONGJMP_ADDR), fifo_scbptr);
  8954. cur_col = 0;
  8955. ahd_seqimode_print(ahd_inb(ahd, SEQIMODE), &cur_col, 50);
  8956. ahd_seqintsrc_print(ahd_inb(ahd, SEQINTSRC), &cur_col, 50);
  8957. ahd_dfcntrl_print(ahd_inb(ahd, DFCNTRL), &cur_col, 50);
  8958. ahd_dfstatus_print(ahd_inb(ahd, DFSTATUS), &cur_col, 50);
  8959. ahd_sg_cache_shadow_print(ahd_inb(ahd, SG_CACHE_SHADOW),
  8960. &cur_col, 50);
  8961. ahd_sg_state_print(ahd_inb(ahd, SG_STATE), &cur_col, 50);
  8962. ahd_dffsxfrctl_print(ahd_inb(ahd, DFFSXFRCTL), &cur_col, 50);
  8963. ahd_soffcnt_print(ahd_inb(ahd, SOFFCNT), &cur_col, 50);
  8964. ahd_mdffstat_print(ahd_inb(ahd, MDFFSTAT), &cur_col, 50);
  8965. if (cur_col > 50) {
  8966. printk("\n");
  8967. cur_col = 0;
  8968. }
  8969. cur_col += printk("SHADDR = 0x%x%x, SHCNT = 0x%x ",
  8970. ahd_inl(ahd, SHADDR+4),
  8971. ahd_inl(ahd, SHADDR),
  8972. (ahd_inb(ahd, SHCNT)
  8973. | (ahd_inb(ahd, SHCNT + 1) << 8)
  8974. | (ahd_inb(ahd, SHCNT + 2) << 16)));
  8975. if (cur_col > 50) {
  8976. printk("\n");
  8977. cur_col = 0;
  8978. }
  8979. cur_col += printk("HADDR = 0x%x%x, HCNT = 0x%x ",
  8980. ahd_inl(ahd, HADDR+4),
  8981. ahd_inl(ahd, HADDR),
  8982. (ahd_inb(ahd, HCNT)
  8983. | (ahd_inb(ahd, HCNT + 1) << 8)
  8984. | (ahd_inb(ahd, HCNT + 2) << 16)));
  8985. ahd_ccsgctl_print(ahd_inb(ahd, CCSGCTL), &cur_col, 50);
  8986. #ifdef AHD_DEBUG
  8987. if ((ahd_debug & AHD_SHOW_SG) != 0) {
  8988. fifo_scb = ahd_lookup_scb(ahd, fifo_scbptr);
  8989. if (fifo_scb != NULL)
  8990. ahd_dump_sglist(fifo_scb);
  8991. }
  8992. #endif
  8993. }
  8994. printk("\nLQIN: ");
  8995. for (i = 0; i < 20; i++)
  8996. printk("0x%x ", ahd_inb(ahd, LQIN + i));
  8997. printk("\n");
  8998. ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
  8999. printk("%s: LQISTATE = 0x%x, LQOSTATE = 0x%x, OPTIONMODE = 0x%x\n",
  9000. ahd_name(ahd), ahd_inb(ahd, LQISTATE), ahd_inb(ahd, LQOSTATE),
  9001. ahd_inb(ahd, OPTIONMODE));
  9002. printk("%s: OS_SPACE_CNT = 0x%x MAXCMDCNT = 0x%x\n",
  9003. ahd_name(ahd), ahd_inb(ahd, OS_SPACE_CNT),
  9004. ahd_inb(ahd, MAXCMDCNT));
  9005. printk("%s: SAVED_SCSIID = 0x%x SAVED_LUN = 0x%x\n",
  9006. ahd_name(ahd), ahd_inb(ahd, SAVED_SCSIID),
  9007. ahd_inb(ahd, SAVED_LUN));
  9008. ahd_simode0_print(ahd_inb(ahd, SIMODE0), &cur_col, 50);
  9009. printk("\n");
  9010. ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
  9011. cur_col = 0;
  9012. ahd_ccscbctl_print(ahd_inb(ahd, CCSCBCTL), &cur_col, 50);
  9013. printk("\n");
  9014. ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode);
  9015. printk("%s: REG0 == 0x%x, SINDEX = 0x%x, DINDEX = 0x%x\n",
  9016. ahd_name(ahd), ahd_inw(ahd, REG0), ahd_inw(ahd, SINDEX),
  9017. ahd_inw(ahd, DINDEX));
  9018. printk("%s: SCBPTR == 0x%x, SCB_NEXT == 0x%x, SCB_NEXT2 == 0x%x\n",
  9019. ahd_name(ahd), ahd_get_scbptr(ahd),
  9020. ahd_inw_scbram(ahd, SCB_NEXT),
  9021. ahd_inw_scbram(ahd, SCB_NEXT2));
  9022. printk("CDB %x %x %x %x %x %x\n",
  9023. ahd_inb_scbram(ahd, SCB_CDB_STORE),
  9024. ahd_inb_scbram(ahd, SCB_CDB_STORE+1),
  9025. ahd_inb_scbram(ahd, SCB_CDB_STORE+2),
  9026. ahd_inb_scbram(ahd, SCB_CDB_STORE+3),
  9027. ahd_inb_scbram(ahd, SCB_CDB_STORE+4),
  9028. ahd_inb_scbram(ahd, SCB_CDB_STORE+5));
  9029. printk("STACK:");
  9030. for (i = 0; i < ahd->stack_size; i++) {
  9031. ahd->saved_stack[i] =
  9032. ahd_inb(ahd, STACK)|(ahd_inb(ahd, STACK) << 8);
  9033. printk(" 0x%x", ahd->saved_stack[i]);
  9034. }
  9035. for (i = ahd->stack_size-1; i >= 0; i--) {
  9036. ahd_outb(ahd, STACK, ahd->saved_stack[i] & 0xFF);
  9037. ahd_outb(ahd, STACK, (ahd->saved_stack[i] >> 8) & 0xFF);
  9038. }
  9039. printk("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n");
  9040. ahd_restore_modes(ahd, saved_modes);
  9041. if (paused == 0)
  9042. ahd_unpause(ahd);
  9043. }
  9044. #if 0
  9045. void
  9046. ahd_dump_scbs(struct ahd_softc *ahd)
  9047. {
  9048. ahd_mode_state saved_modes;
  9049. u_int saved_scb_index;
  9050. int i;
  9051. saved_modes = ahd_save_modes(ahd);
  9052. ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
  9053. saved_scb_index = ahd_get_scbptr(ahd);
  9054. for (i = 0; i < AHD_SCB_MAX; i++) {
  9055. ahd_set_scbptr(ahd, i);
  9056. printk("%3d", i);
  9057. printk("(CTRL 0x%x ID 0x%x N 0x%x N2 0x%x SG 0x%x, RSG 0x%x)\n",
  9058. ahd_inb_scbram(ahd, SCB_CONTROL),
  9059. ahd_inb_scbram(ahd, SCB_SCSIID),
  9060. ahd_inw_scbram(ahd, SCB_NEXT),
  9061. ahd_inw_scbram(ahd, SCB_NEXT2),
  9062. ahd_inl_scbram(ahd, SCB_SGPTR),
  9063. ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR));
  9064. }
  9065. printk("\n");
  9066. ahd_set_scbptr(ahd, saved_scb_index);
  9067. ahd_restore_modes(ahd, saved_modes);
  9068. }
  9069. #endif /* 0 */
  9070. /**************************** Flexport Logic **********************************/
  9071. /*
  9072. * Read count 16bit words from 16bit word address start_addr from the
  9073. * SEEPROM attached to the controller, into buf, using the controller's
  9074. * SEEPROM reading state machine. Optionally treat the data as a byte
  9075. * stream in terms of byte order.
  9076. */
  9077. int
  9078. ahd_read_seeprom(struct ahd_softc *ahd, uint16_t *buf,
  9079. u_int start_addr, u_int count, int bytestream)
  9080. {
  9081. u_int cur_addr;
  9082. u_int end_addr;
  9083. int error;
  9084. /*
  9085. * If we never make it through the loop even once,
  9086. * we were passed invalid arguments.
  9087. */
  9088. error = EINVAL;
  9089. AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
  9090. end_addr = start_addr + count;
  9091. for (cur_addr = start_addr; cur_addr < end_addr; cur_addr++) {
  9092. ahd_outb(ahd, SEEADR, cur_addr);
  9093. ahd_outb(ahd, SEECTL, SEEOP_READ | SEESTART);
  9094. error = ahd_wait_seeprom(ahd);
  9095. if (error)
  9096. break;
  9097. if (bytestream != 0) {
  9098. uint8_t *bytestream_ptr;
  9099. bytestream_ptr = (uint8_t *)buf;
  9100. *bytestream_ptr++ = ahd_inb(ahd, SEEDAT);
  9101. *bytestream_ptr = ahd_inb(ahd, SEEDAT+1);
  9102. } else {
  9103. /*
  9104. * ahd_inw() already handles machine byte order.
  9105. */
  9106. *buf = ahd_inw(ahd, SEEDAT);
  9107. }
  9108. buf++;
  9109. }
  9110. return (error);
  9111. }
  9112. /*
  9113. * Write count 16bit words from buf, into SEEPROM attache to the
  9114. * controller starting at 16bit word address start_addr, using the
  9115. * controller's SEEPROM writing state machine.
  9116. */
  9117. int
  9118. ahd_write_seeprom(struct ahd_softc *ahd, uint16_t *buf,
  9119. u_int start_addr, u_int count)
  9120. {
  9121. u_int cur_addr;
  9122. u_int end_addr;
  9123. int error;
  9124. int retval;
  9125. AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
  9126. error = ENOENT;
  9127. /* Place the chip into write-enable mode */
  9128. ahd_outb(ahd, SEEADR, SEEOP_EWEN_ADDR);
  9129. ahd_outb(ahd, SEECTL, SEEOP_EWEN | SEESTART);
  9130. error = ahd_wait_seeprom(ahd);
  9131. if (error)
  9132. return (error);
  9133. /*
  9134. * Write the data. If we don't get through the loop at
  9135. * least once, the arguments were invalid.
  9136. */
  9137. retval = EINVAL;
  9138. end_addr = start_addr + count;
  9139. for (cur_addr = start_addr; cur_addr < end_addr; cur_addr++) {
  9140. ahd_outw(ahd, SEEDAT, *buf++);
  9141. ahd_outb(ahd, SEEADR, cur_addr);
  9142. ahd_outb(ahd, SEECTL, SEEOP_WRITE | SEESTART);
  9143. retval = ahd_wait_seeprom(ahd);
  9144. if (retval)
  9145. break;
  9146. }
  9147. /*
  9148. * Disable writes.
  9149. */
  9150. ahd_outb(ahd, SEEADR, SEEOP_EWDS_ADDR);
  9151. ahd_outb(ahd, SEECTL, SEEOP_EWDS | SEESTART);
  9152. error = ahd_wait_seeprom(ahd);
  9153. if (error)
  9154. return (error);
  9155. return (retval);
  9156. }
  9157. /*
  9158. * Wait ~100us for the serial eeprom to satisfy our request.
  9159. */
  9160. static int
  9161. ahd_wait_seeprom(struct ahd_softc *ahd)
  9162. {
  9163. int cnt;
  9164. cnt = 5000;
  9165. while ((ahd_inb(ahd, SEESTAT) & (SEEARBACK|SEEBUSY)) != 0 && --cnt)
  9166. ahd_delay(5);
  9167. if (cnt == 0)
  9168. return (ETIMEDOUT);
  9169. return (0);
  9170. }
  9171. /*
  9172. * Validate the two checksums in the per_channel
  9173. * vital product data struct.
  9174. */
  9175. static int
  9176. ahd_verify_vpd_cksum(struct vpd_config *vpd)
  9177. {
  9178. int i;
  9179. int maxaddr;
  9180. uint32_t checksum;
  9181. uint8_t *vpdarray;
  9182. vpdarray = (uint8_t *)vpd;
  9183. maxaddr = offsetof(struct vpd_config, vpd_checksum);
  9184. checksum = 0;
  9185. for (i = offsetof(struct vpd_config, resource_type); i < maxaddr; i++)
  9186. checksum = checksum + vpdarray[i];
  9187. if (checksum == 0
  9188. || (-checksum & 0xFF) != vpd->vpd_checksum)
  9189. return (0);
  9190. checksum = 0;
  9191. maxaddr = offsetof(struct vpd_config, checksum);
  9192. for (i = offsetof(struct vpd_config, default_target_flags);
  9193. i < maxaddr; i++)
  9194. checksum = checksum + vpdarray[i];
  9195. if (checksum == 0
  9196. || (-checksum & 0xFF) != vpd->checksum)
  9197. return (0);
  9198. return (1);
  9199. }
  9200. int
  9201. ahd_verify_cksum(struct seeprom_config *sc)
  9202. {
  9203. int i;
  9204. int maxaddr;
  9205. uint32_t checksum;
  9206. uint16_t *scarray;
  9207. maxaddr = (sizeof(*sc)/2) - 1;
  9208. checksum = 0;
  9209. scarray = (uint16_t *)sc;
  9210. for (i = 0; i < maxaddr; i++)
  9211. checksum = checksum + scarray[i];
  9212. if (checksum == 0
  9213. || (checksum & 0xFFFF) != sc->checksum) {
  9214. return (0);
  9215. } else {
  9216. return (1);
  9217. }
  9218. }
  9219. int
  9220. ahd_acquire_seeprom(struct ahd_softc *ahd)
  9221. {
  9222. /*
  9223. * We should be able to determine the SEEPROM type
  9224. * from the flexport logic, but unfortunately not
  9225. * all implementations have this logic and there is
  9226. * no programatic method for determining if the logic
  9227. * is present.
  9228. */
  9229. return (1);
  9230. #if 0
  9231. uint8_t seetype;
  9232. int error;
  9233. error = ahd_read_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, &seetype);
  9234. if (error != 0
  9235. || ((seetype & FLX_ROMSTAT_SEECFG) == FLX_ROMSTAT_SEE_NONE))
  9236. return (0);
  9237. return (1);
  9238. #endif
  9239. }
  9240. void
  9241. ahd_release_seeprom(struct ahd_softc *ahd)
  9242. {
  9243. /* Currently a no-op */
  9244. }
  9245. /*
  9246. * Wait at most 2 seconds for flexport arbitration to succeed.
  9247. */
  9248. static int
  9249. ahd_wait_flexport(struct ahd_softc *ahd)
  9250. {
  9251. int cnt;
  9252. AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
  9253. cnt = 1000000 * 2 / 5;
  9254. while ((ahd_inb(ahd, BRDCTL) & FLXARBACK) == 0 && --cnt)
  9255. ahd_delay(5);
  9256. if (cnt == 0)
  9257. return (ETIMEDOUT);
  9258. return (0);
  9259. }
  9260. int
  9261. ahd_write_flexport(struct ahd_softc *ahd, u_int addr, u_int value)
  9262. {
  9263. int error;
  9264. AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
  9265. if (addr > 7)
  9266. panic("ahd_write_flexport: address out of range");
  9267. ahd_outb(ahd, BRDCTL, BRDEN|(addr << 3));
  9268. error = ahd_wait_flexport(ahd);
  9269. if (error != 0)
  9270. return (error);
  9271. ahd_outb(ahd, BRDDAT, value);
  9272. ahd_flush_device_writes(ahd);
  9273. ahd_outb(ahd, BRDCTL, BRDSTB|BRDEN|(addr << 3));
  9274. ahd_flush_device_writes(ahd);
  9275. ahd_outb(ahd, BRDCTL, BRDEN|(addr << 3));
  9276. ahd_flush_device_writes(ahd);
  9277. ahd_outb(ahd, BRDCTL, 0);
  9278. ahd_flush_device_writes(ahd);
  9279. return (0);
  9280. }
  9281. int
  9282. ahd_read_flexport(struct ahd_softc *ahd, u_int addr, uint8_t *value)
  9283. {
  9284. int error;
  9285. AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
  9286. if (addr > 7)
  9287. panic("ahd_read_flexport: address out of range");
  9288. ahd_outb(ahd, BRDCTL, BRDRW|BRDEN|(addr << 3));
  9289. error = ahd_wait_flexport(ahd);
  9290. if (error != 0)
  9291. return (error);
  9292. *value = ahd_inb(ahd, BRDDAT);
  9293. ahd_outb(ahd, BRDCTL, 0);
  9294. ahd_flush_device_writes(ahd);
  9295. return (0);
  9296. }
  9297. /************************* Target Mode ****************************************/
  9298. #ifdef AHD_TARGET_MODE
  9299. cam_status
  9300. ahd_find_tmode_devs(struct ahd_softc *ahd, struct cam_sim *sim, union ccb *ccb,
  9301. struct ahd_tmode_tstate **tstate,
  9302. struct ahd_tmode_lstate **lstate,
  9303. int notfound_failure)
  9304. {
  9305. if ((ahd->features & AHD_TARGETMODE) == 0)
  9306. return (CAM_REQ_INVALID);
  9307. /*
  9308. * Handle the 'black hole' device that sucks up
  9309. * requests to unattached luns on enabled targets.
  9310. */
  9311. if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD
  9312. && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) {
  9313. *tstate = NULL;
  9314. *lstate = ahd->black_hole;
  9315. } else {
  9316. u_int max_id;
  9317. max_id = (ahd->features & AHD_WIDE) ? 16 : 8;
  9318. if (ccb->ccb_h.target_id >= max_id)
  9319. return (CAM_TID_INVALID);
  9320. if (ccb->ccb_h.target_lun >= AHD_NUM_LUNS)
  9321. return (CAM_LUN_INVALID);
  9322. *tstate = ahd->enabled_targets[ccb->ccb_h.target_id];
  9323. *lstate = NULL;
  9324. if (*tstate != NULL)
  9325. *lstate =
  9326. (*tstate)->enabled_luns[ccb->ccb_h.target_lun];
  9327. }
  9328. if (notfound_failure != 0 && *lstate == NULL)
  9329. return (CAM_PATH_INVALID);
  9330. return (CAM_REQ_CMP);
  9331. }
  9332. void
  9333. ahd_handle_en_lun(struct ahd_softc *ahd, struct cam_sim *sim, union ccb *ccb)
  9334. {
  9335. #if NOT_YET
  9336. struct ahd_tmode_tstate *tstate;
  9337. struct ahd_tmode_lstate *lstate;
  9338. struct ccb_en_lun *cel;
  9339. cam_status status;
  9340. u_int target;
  9341. u_int lun;
  9342. u_int target_mask;
  9343. u_long s;
  9344. char channel;
  9345. status = ahd_find_tmode_devs(ahd, sim, ccb, &tstate, &lstate,
  9346. /*notfound_failure*/FALSE);
  9347. if (status != CAM_REQ_CMP) {
  9348. ccb->ccb_h.status = status;
  9349. return;
  9350. }
  9351. if ((ahd->features & AHD_MULTIROLE) != 0) {
  9352. u_int our_id;
  9353. our_id = ahd->our_id;
  9354. if (ccb->ccb_h.target_id != our_id) {
  9355. if ((ahd->features & AHD_MULTI_TID) != 0
  9356. && (ahd->flags & AHD_INITIATORROLE) != 0) {
  9357. /*
  9358. * Only allow additional targets if
  9359. * the initiator role is disabled.
  9360. * The hardware cannot handle a re-select-in
  9361. * on the initiator id during a re-select-out
  9362. * on a different target id.
  9363. */
  9364. status = CAM_TID_INVALID;
  9365. } else if ((ahd->flags & AHD_INITIATORROLE) != 0
  9366. || ahd->enabled_luns > 0) {
  9367. /*
  9368. * Only allow our target id to change
  9369. * if the initiator role is not configured
  9370. * and there are no enabled luns which
  9371. * are attached to the currently registered
  9372. * scsi id.
  9373. */
  9374. status = CAM_TID_INVALID;
  9375. }
  9376. }
  9377. }
  9378. if (status != CAM_REQ_CMP) {
  9379. ccb->ccb_h.status = status;
  9380. return;
  9381. }
  9382. /*
  9383. * We now have an id that is valid.
  9384. * If we aren't in target mode, switch modes.
  9385. */
  9386. if ((ahd->flags & AHD_TARGETROLE) == 0
  9387. && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) {
  9388. u_long s;
  9389. printk("Configuring Target Mode\n");
  9390. ahd_lock(ahd, &s);
  9391. if (LIST_FIRST(&ahd->pending_scbs) != NULL) {
  9392. ccb->ccb_h.status = CAM_BUSY;
  9393. ahd_unlock(ahd, &s);
  9394. return;
  9395. }
  9396. ahd->flags |= AHD_TARGETROLE;
  9397. if ((ahd->features & AHD_MULTIROLE) == 0)
  9398. ahd->flags &= ~AHD_INITIATORROLE;
  9399. ahd_pause(ahd);
  9400. ahd_loadseq(ahd);
  9401. ahd_restart(ahd);
  9402. ahd_unlock(ahd, &s);
  9403. }
  9404. cel = &ccb->cel;
  9405. target = ccb->ccb_h.target_id;
  9406. lun = ccb->ccb_h.target_lun;
  9407. channel = SIM_CHANNEL(ahd, sim);
  9408. target_mask = 0x01 << target;
  9409. if (channel == 'B')
  9410. target_mask <<= 8;
  9411. if (cel->enable != 0) {
  9412. u_int scsiseq1;
  9413. /* Are we already enabled?? */
  9414. if (lstate != NULL) {
  9415. xpt_print_path(ccb->ccb_h.path);
  9416. printk("Lun already enabled\n");
  9417. ccb->ccb_h.status = CAM_LUN_ALRDY_ENA;
  9418. return;
  9419. }
  9420. if (cel->grp6_len != 0
  9421. || cel->grp7_len != 0) {
  9422. /*
  9423. * Don't (yet?) support vendor
  9424. * specific commands.
  9425. */
  9426. ccb->ccb_h.status = CAM_REQ_INVALID;
  9427. printk("Non-zero Group Codes\n");
  9428. return;
  9429. }
  9430. /*
  9431. * Seems to be okay.
  9432. * Setup our data structures.
  9433. */
  9434. if (target != CAM_TARGET_WILDCARD && tstate == NULL) {
  9435. tstate = ahd_alloc_tstate(ahd, target, channel);
  9436. if (tstate == NULL) {
  9437. xpt_print_path(ccb->ccb_h.path);
  9438. printk("Couldn't allocate tstate\n");
  9439. ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
  9440. return;
  9441. }
  9442. }
  9443. lstate = kzalloc(sizeof(*lstate), GFP_ATOMIC);
  9444. if (lstate == NULL) {
  9445. xpt_print_path(ccb->ccb_h.path);
  9446. printk("Couldn't allocate lstate\n");
  9447. ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
  9448. return;
  9449. }
  9450. status = xpt_create_path(&lstate->path, /*periph*/NULL,
  9451. xpt_path_path_id(ccb->ccb_h.path),
  9452. xpt_path_target_id(ccb->ccb_h.path),
  9453. xpt_path_lun_id(ccb->ccb_h.path));
  9454. if (status != CAM_REQ_CMP) {
  9455. kfree(lstate);
  9456. xpt_print_path(ccb->ccb_h.path);
  9457. printk("Couldn't allocate path\n");
  9458. ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
  9459. return;
  9460. }
  9461. SLIST_INIT(&lstate->accept_tios);
  9462. SLIST_INIT(&lstate->immed_notifies);
  9463. ahd_lock(ahd, &s);
  9464. ahd_pause(ahd);
  9465. if (target != CAM_TARGET_WILDCARD) {
  9466. tstate->enabled_luns[lun] = lstate;
  9467. ahd->enabled_luns++;
  9468. if ((ahd->features & AHD_MULTI_TID) != 0) {
  9469. u_int targid_mask;
  9470. targid_mask = ahd_inw(ahd, TARGID);
  9471. targid_mask |= target_mask;
  9472. ahd_outw(ahd, TARGID, targid_mask);
  9473. ahd_update_scsiid(ahd, targid_mask);
  9474. } else {
  9475. u_int our_id;
  9476. char channel;
  9477. channel = SIM_CHANNEL(ahd, sim);
  9478. our_id = SIM_SCSI_ID(ahd, sim);
  9479. /*
  9480. * This can only happen if selections
  9481. * are not enabled
  9482. */
  9483. if (target != our_id) {
  9484. u_int sblkctl;
  9485. char cur_channel;
  9486. int swap;
  9487. sblkctl = ahd_inb(ahd, SBLKCTL);
  9488. cur_channel = (sblkctl & SELBUSB)
  9489. ? 'B' : 'A';
  9490. if ((ahd->features & AHD_TWIN) == 0)
  9491. cur_channel = 'A';
  9492. swap = cur_channel != channel;
  9493. ahd->our_id = target;
  9494. if (swap)
  9495. ahd_outb(ahd, SBLKCTL,
  9496. sblkctl ^ SELBUSB);
  9497. ahd_outb(ahd, SCSIID, target);
  9498. if (swap)
  9499. ahd_outb(ahd, SBLKCTL, sblkctl);
  9500. }
  9501. }
  9502. } else
  9503. ahd->black_hole = lstate;
  9504. /* Allow select-in operations */
  9505. if (ahd->black_hole != NULL && ahd->enabled_luns > 0) {
  9506. scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE);
  9507. scsiseq1 |= ENSELI;
  9508. ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq1);
  9509. scsiseq1 = ahd_inb(ahd, SCSISEQ1);
  9510. scsiseq1 |= ENSELI;
  9511. ahd_outb(ahd, SCSISEQ1, scsiseq1);
  9512. }
  9513. ahd_unpause(ahd);
  9514. ahd_unlock(ahd, &s);
  9515. ccb->ccb_h.status = CAM_REQ_CMP;
  9516. xpt_print_path(ccb->ccb_h.path);
  9517. printk("Lun now enabled for target mode\n");
  9518. } else {
  9519. struct scb *scb;
  9520. int i, empty;
  9521. if (lstate == NULL) {
  9522. ccb->ccb_h.status = CAM_LUN_INVALID;
  9523. return;
  9524. }
  9525. ahd_lock(ahd, &s);
  9526. ccb->ccb_h.status = CAM_REQ_CMP;
  9527. LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) {
  9528. struct ccb_hdr *ccbh;
  9529. ccbh = &scb->io_ctx->ccb_h;
  9530. if (ccbh->func_code == XPT_CONT_TARGET_IO
  9531. && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){
  9532. printk("CTIO pending\n");
  9533. ccb->ccb_h.status = CAM_REQ_INVALID;
  9534. ahd_unlock(ahd, &s);
  9535. return;
  9536. }
  9537. }
  9538. if (SLIST_FIRST(&lstate->accept_tios) != NULL) {
  9539. printk("ATIOs pending\n");
  9540. ccb->ccb_h.status = CAM_REQ_INVALID;
  9541. }
  9542. if (SLIST_FIRST(&lstate->immed_notifies) != NULL) {
  9543. printk("INOTs pending\n");
  9544. ccb->ccb_h.status = CAM_REQ_INVALID;
  9545. }
  9546. if (ccb->ccb_h.status != CAM_REQ_CMP) {
  9547. ahd_unlock(ahd, &s);
  9548. return;
  9549. }
  9550. xpt_print_path(ccb->ccb_h.path);
  9551. printk("Target mode disabled\n");
  9552. xpt_free_path(lstate->path);
  9553. kfree(lstate);
  9554. ahd_pause(ahd);
  9555. /* Can we clean up the target too? */
  9556. if (target != CAM_TARGET_WILDCARD) {
  9557. tstate->enabled_luns[lun] = NULL;
  9558. ahd->enabled_luns--;
  9559. for (empty = 1, i = 0; i < 8; i++)
  9560. if (tstate->enabled_luns[i] != NULL) {
  9561. empty = 0;
  9562. break;
  9563. }
  9564. if (empty) {
  9565. ahd_free_tstate(ahd, target, channel,
  9566. /*force*/FALSE);
  9567. if (ahd->features & AHD_MULTI_TID) {
  9568. u_int targid_mask;
  9569. targid_mask = ahd_inw(ahd, TARGID);
  9570. targid_mask &= ~target_mask;
  9571. ahd_outw(ahd, TARGID, targid_mask);
  9572. ahd_update_scsiid(ahd, targid_mask);
  9573. }
  9574. }
  9575. } else {
  9576. ahd->black_hole = NULL;
  9577. /*
  9578. * We can't allow selections without
  9579. * our black hole device.
  9580. */
  9581. empty = TRUE;
  9582. }
  9583. if (ahd->enabled_luns == 0) {
  9584. /* Disallow select-in */
  9585. u_int scsiseq1;
  9586. scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE);
  9587. scsiseq1 &= ~ENSELI;
  9588. ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq1);
  9589. scsiseq1 = ahd_inb(ahd, SCSISEQ1);
  9590. scsiseq1 &= ~ENSELI;
  9591. ahd_outb(ahd, SCSISEQ1, scsiseq1);
  9592. if ((ahd->features & AHD_MULTIROLE) == 0) {
  9593. printk("Configuring Initiator Mode\n");
  9594. ahd->flags &= ~AHD_TARGETROLE;
  9595. ahd->flags |= AHD_INITIATORROLE;
  9596. ahd_pause(ahd);
  9597. ahd_loadseq(ahd);
  9598. ahd_restart(ahd);
  9599. /*
  9600. * Unpaused. The extra unpause
  9601. * that follows is harmless.
  9602. */
  9603. }
  9604. }
  9605. ahd_unpause(ahd);
  9606. ahd_unlock(ahd, &s);
  9607. }
  9608. #endif
  9609. }
  9610. static void
  9611. ahd_update_scsiid(struct ahd_softc *ahd, u_int targid_mask)
  9612. {
  9613. #if NOT_YET
  9614. u_int scsiid_mask;
  9615. u_int scsiid;
  9616. if ((ahd->features & AHD_MULTI_TID) == 0)
  9617. panic("ahd_update_scsiid called on non-multitid unit\n");
  9618. /*
  9619. * Since we will rely on the TARGID mask
  9620. * for selection enables, ensure that OID
  9621. * in SCSIID is not set to some other ID
  9622. * that we don't want to allow selections on.
  9623. */
  9624. if ((ahd->features & AHD_ULTRA2) != 0)
  9625. scsiid = ahd_inb(ahd, SCSIID_ULTRA2);
  9626. else
  9627. scsiid = ahd_inb(ahd, SCSIID);
  9628. scsiid_mask = 0x1 << (scsiid & OID);
  9629. if ((targid_mask & scsiid_mask) == 0) {
  9630. u_int our_id;
  9631. /* ffs counts from 1 */
  9632. our_id = ffs(targid_mask);
  9633. if (our_id == 0)
  9634. our_id = ahd->our_id;
  9635. else
  9636. our_id--;
  9637. scsiid &= TID;
  9638. scsiid |= our_id;
  9639. }
  9640. if ((ahd->features & AHD_ULTRA2) != 0)
  9641. ahd_outb(ahd, SCSIID_ULTRA2, scsiid);
  9642. else
  9643. ahd_outb(ahd, SCSIID, scsiid);
  9644. #endif
  9645. }
  9646. static void
  9647. ahd_run_tqinfifo(struct ahd_softc *ahd, int paused)
  9648. {
  9649. struct target_cmd *cmd;
  9650. ahd_sync_tqinfifo(ahd, BUS_DMASYNC_POSTREAD);
  9651. while ((cmd = &ahd->targetcmds[ahd->tqinfifonext])->cmd_valid != 0) {
  9652. /*
  9653. * Only advance through the queue if we
  9654. * have the resources to process the command.
  9655. */
  9656. if (ahd_handle_target_cmd(ahd, cmd) != 0)
  9657. break;
  9658. cmd->cmd_valid = 0;
  9659. ahd_dmamap_sync(ahd, ahd->shared_data_dmat,
  9660. ahd->shared_data_map.dmamap,
  9661. ahd_targetcmd_offset(ahd, ahd->tqinfifonext),
  9662. sizeof(struct target_cmd),
  9663. BUS_DMASYNC_PREREAD);
  9664. ahd->tqinfifonext++;
  9665. /*
  9666. * Lazily update our position in the target mode incoming
  9667. * command queue as seen by the sequencer.
  9668. */
  9669. if ((ahd->tqinfifonext & (HOST_TQINPOS - 1)) == 1) {
  9670. u_int hs_mailbox;
  9671. hs_mailbox = ahd_inb(ahd, HS_MAILBOX);
  9672. hs_mailbox &= ~HOST_TQINPOS;
  9673. hs_mailbox |= ahd->tqinfifonext & HOST_TQINPOS;
  9674. ahd_outb(ahd, HS_MAILBOX, hs_mailbox);
  9675. }
  9676. }
  9677. }
  9678. static int
  9679. ahd_handle_target_cmd(struct ahd_softc *ahd, struct target_cmd *cmd)
  9680. {
  9681. struct ahd_tmode_tstate *tstate;
  9682. struct ahd_tmode_lstate *lstate;
  9683. struct ccb_accept_tio *atio;
  9684. uint8_t *byte;
  9685. int initiator;
  9686. int target;
  9687. int lun;
  9688. initiator = SCSIID_TARGET(ahd, cmd->scsiid);
  9689. target = SCSIID_OUR_ID(cmd->scsiid);
  9690. lun = (cmd->identify & MSG_IDENTIFY_LUNMASK);
  9691. byte = cmd->bytes;
  9692. tstate = ahd->enabled_targets[target];
  9693. lstate = NULL;
  9694. if (tstate != NULL)
  9695. lstate = tstate->enabled_luns[lun];
  9696. /*
  9697. * Commands for disabled luns go to the black hole driver.
  9698. */
  9699. if (lstate == NULL)
  9700. lstate = ahd->black_hole;
  9701. atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios);
  9702. if (atio == NULL) {
  9703. ahd->flags |= AHD_TQINFIFO_BLOCKED;
  9704. /*
  9705. * Wait for more ATIOs from the peripheral driver for this lun.
  9706. */
  9707. return (1);
  9708. } else
  9709. ahd->flags &= ~AHD_TQINFIFO_BLOCKED;
  9710. #ifdef AHD_DEBUG
  9711. if ((ahd_debug & AHD_SHOW_TQIN) != 0)
  9712. printk("Incoming command from %d for %d:%d%s\n",
  9713. initiator, target, lun,
  9714. lstate == ahd->black_hole ? "(Black Holed)" : "");
  9715. #endif
  9716. SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle);
  9717. if (lstate == ahd->black_hole) {
  9718. /* Fill in the wildcards */
  9719. atio->ccb_h.target_id = target;
  9720. atio->ccb_h.target_lun = lun;
  9721. }
  9722. /*
  9723. * Package it up and send it off to
  9724. * whomever has this lun enabled.
  9725. */
  9726. atio->sense_len = 0;
  9727. atio->init_id = initiator;
  9728. if (byte[0] != 0xFF) {
  9729. /* Tag was included */
  9730. atio->tag_action = *byte++;
  9731. atio->tag_id = *byte++;
  9732. atio->ccb_h.flags = CAM_TAG_ACTION_VALID;
  9733. } else {
  9734. atio->ccb_h.flags = 0;
  9735. }
  9736. byte++;
  9737. /* Okay. Now determine the cdb size based on the command code */
  9738. switch (*byte >> CMD_GROUP_CODE_SHIFT) {
  9739. case 0:
  9740. atio->cdb_len = 6;
  9741. break;
  9742. case 1:
  9743. case 2:
  9744. atio->cdb_len = 10;
  9745. break;
  9746. case 4:
  9747. atio->cdb_len = 16;
  9748. break;
  9749. case 5:
  9750. atio->cdb_len = 12;
  9751. break;
  9752. case 3:
  9753. default:
  9754. /* Only copy the opcode. */
  9755. atio->cdb_len = 1;
  9756. printk("Reserved or VU command code type encountered\n");
  9757. break;
  9758. }
  9759. memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len);
  9760. atio->ccb_h.status |= CAM_CDB_RECVD;
  9761. if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) {
  9762. /*
  9763. * We weren't allowed to disconnect.
  9764. * We're hanging on the bus until a
  9765. * continue target I/O comes in response
  9766. * to this accept tio.
  9767. */
  9768. #ifdef AHD_DEBUG
  9769. if ((ahd_debug & AHD_SHOW_TQIN) != 0)
  9770. printk("Received Immediate Command %d:%d:%d - %p\n",
  9771. initiator, target, lun, ahd->pending_device);
  9772. #endif
  9773. ahd->pending_device = lstate;
  9774. ahd_freeze_ccb((union ccb *)atio);
  9775. atio->ccb_h.flags |= CAM_DIS_DISCONNECT;
  9776. }
  9777. xpt_done((union ccb*)atio);
  9778. return (0);
  9779. }
  9780. #endif