rtc-tps6586x.c 8.4 KB

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  1. /*
  2. * rtc-tps6586x.c: RTC driver for TI PMIC TPS6586X
  3. *
  4. * Copyright (c) 2012, NVIDIA Corporation.
  5. *
  6. * Author: Laxman Dewangan <ldewangan@nvidia.com>
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation version 2.
  11. *
  12. * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
  13. * whether express or implied; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  15. * General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
  20. * 02111-1307, USA
  21. */
  22. #include <linux/device.h>
  23. #include <linux/err.h>
  24. #include <linux/init.h>
  25. #include <linux/kernel.h>
  26. #include <linux/mfd/tps6586x.h>
  27. #include <linux/module.h>
  28. #include <linux/platform_device.h>
  29. #include <linux/pm_runtime.h>
  30. #include <linux/rtc.h>
  31. #include <linux/slab.h>
  32. #define RTC_CTRL 0xc0
  33. #define POR_RESET_N BIT(7)
  34. #define OSC_SRC_SEL BIT(6)
  35. #define RTC_ENABLE BIT(5) /* enables alarm */
  36. #define RTC_BUF_ENABLE BIT(4) /* 32 KHz buffer enable */
  37. #define PRE_BYPASS BIT(3) /* 0=1KHz or 1=32KHz updates */
  38. #define CL_SEL_MASK (BIT(2)|BIT(1))
  39. #define CL_SEL_POS 1
  40. #define RTC_ALARM1_HI 0xc1
  41. #define RTC_COUNT4 0xc6
  42. /* start a PMU RTC access by reading the register prior to the RTC_COUNT4 */
  43. #define RTC_COUNT4_DUMMYREAD 0xc5
  44. /*only 14-bits width in second*/
  45. #define ALM1_VALID_RANGE_IN_SEC 0x3FFF
  46. #define TPS6586X_RTC_CL_SEL_1_5PF 0x0
  47. #define TPS6586X_RTC_CL_SEL_6_5PF 0x1
  48. #define TPS6586X_RTC_CL_SEL_7_5PF 0x2
  49. #define TPS6586X_RTC_CL_SEL_12_5PF 0x3
  50. struct tps6586x_rtc {
  51. struct device *dev;
  52. struct rtc_device *rtc;
  53. int irq;
  54. bool irq_en;
  55. };
  56. static inline struct device *to_tps6586x_dev(struct device *dev)
  57. {
  58. return dev->parent;
  59. }
  60. static int tps6586x_rtc_read_time(struct device *dev, struct rtc_time *tm)
  61. {
  62. struct device *tps_dev = to_tps6586x_dev(dev);
  63. unsigned long long ticks = 0;
  64. time64_t seconds;
  65. u8 buff[6];
  66. int ret;
  67. int i;
  68. ret = tps6586x_reads(tps_dev, RTC_COUNT4_DUMMYREAD, sizeof(buff), buff);
  69. if (ret < 0) {
  70. dev_err(dev, "read counter failed with err %d\n", ret);
  71. return ret;
  72. }
  73. for (i = 1; i < sizeof(buff); i++) {
  74. ticks <<= 8;
  75. ticks |= buff[i];
  76. }
  77. seconds = ticks >> 10;
  78. rtc_time64_to_tm(seconds, tm);
  79. return 0;
  80. }
  81. static int tps6586x_rtc_set_time(struct device *dev, struct rtc_time *tm)
  82. {
  83. struct device *tps_dev = to_tps6586x_dev(dev);
  84. unsigned long long ticks;
  85. time64_t seconds;
  86. u8 buff[5];
  87. int ret;
  88. seconds = rtc_tm_to_time64(tm);
  89. ticks = (unsigned long long)seconds << 10;
  90. buff[0] = (ticks >> 32) & 0xff;
  91. buff[1] = (ticks >> 24) & 0xff;
  92. buff[2] = (ticks >> 16) & 0xff;
  93. buff[3] = (ticks >> 8) & 0xff;
  94. buff[4] = ticks & 0xff;
  95. /* Disable RTC before changing time */
  96. ret = tps6586x_clr_bits(tps_dev, RTC_CTRL, RTC_ENABLE);
  97. if (ret < 0) {
  98. dev_err(dev, "failed to clear RTC_ENABLE\n");
  99. return ret;
  100. }
  101. ret = tps6586x_writes(tps_dev, RTC_COUNT4, sizeof(buff), buff);
  102. if (ret < 0) {
  103. dev_err(dev, "failed to program new time\n");
  104. return ret;
  105. }
  106. /* Enable RTC */
  107. ret = tps6586x_set_bits(tps_dev, RTC_CTRL, RTC_ENABLE);
  108. if (ret < 0) {
  109. dev_err(dev, "failed to set RTC_ENABLE\n");
  110. return ret;
  111. }
  112. return 0;
  113. }
  114. static int tps6586x_rtc_alarm_irq_enable(struct device *dev,
  115. unsigned int enabled)
  116. {
  117. struct tps6586x_rtc *rtc = dev_get_drvdata(dev);
  118. if (enabled && !rtc->irq_en) {
  119. enable_irq(rtc->irq);
  120. rtc->irq_en = true;
  121. } else if (!enabled && rtc->irq_en) {
  122. disable_irq(rtc->irq);
  123. rtc->irq_en = false;
  124. }
  125. return 0;
  126. }
  127. static int tps6586x_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
  128. {
  129. struct device *tps_dev = to_tps6586x_dev(dev);
  130. time64_t seconds;
  131. unsigned long ticks;
  132. unsigned long rtc_current_time;
  133. unsigned long long rticks = 0;
  134. u8 buff[3];
  135. u8 rbuff[6];
  136. int ret;
  137. int i;
  138. seconds = rtc_tm_to_time64(&alrm->time);
  139. ret = tps6586x_rtc_alarm_irq_enable(dev, alrm->enabled);
  140. if (ret < 0) {
  141. dev_err(dev, "can't set alarm irq, err %d\n", ret);
  142. return ret;
  143. }
  144. ret = tps6586x_reads(tps_dev, RTC_COUNT4_DUMMYREAD,
  145. sizeof(rbuff), rbuff);
  146. if (ret < 0) {
  147. dev_err(dev, "read counter failed with err %d\n", ret);
  148. return ret;
  149. }
  150. for (i = 1; i < sizeof(rbuff); i++) {
  151. rticks <<= 8;
  152. rticks |= rbuff[i];
  153. }
  154. rtc_current_time = rticks >> 10;
  155. if ((seconds - rtc_current_time) > ALM1_VALID_RANGE_IN_SEC)
  156. seconds = rtc_current_time - 1;
  157. ticks = (unsigned long long)seconds << 10;
  158. buff[0] = (ticks >> 16) & 0xff;
  159. buff[1] = (ticks >> 8) & 0xff;
  160. buff[2] = ticks & 0xff;
  161. ret = tps6586x_writes(tps_dev, RTC_ALARM1_HI, sizeof(buff), buff);
  162. if (ret)
  163. dev_err(dev, "programming alarm failed with err %d\n", ret);
  164. return ret;
  165. }
  166. static int tps6586x_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
  167. {
  168. struct device *tps_dev = to_tps6586x_dev(dev);
  169. unsigned long ticks;
  170. time64_t seconds;
  171. u8 buff[3];
  172. int ret;
  173. ret = tps6586x_reads(tps_dev, RTC_ALARM1_HI, sizeof(buff), buff);
  174. if (ret) {
  175. dev_err(dev, "read RTC_ALARM1_HI failed with err %d\n", ret);
  176. return ret;
  177. }
  178. ticks = (buff[0] << 16) | (buff[1] << 8) | buff[2];
  179. seconds = ticks >> 10;
  180. rtc_time64_to_tm(seconds, &alrm->time);
  181. return 0;
  182. }
  183. static const struct rtc_class_ops tps6586x_rtc_ops = {
  184. .read_time = tps6586x_rtc_read_time,
  185. .set_time = tps6586x_rtc_set_time,
  186. .set_alarm = tps6586x_rtc_set_alarm,
  187. .read_alarm = tps6586x_rtc_read_alarm,
  188. .alarm_irq_enable = tps6586x_rtc_alarm_irq_enable,
  189. };
  190. static irqreturn_t tps6586x_rtc_irq(int irq, void *data)
  191. {
  192. struct tps6586x_rtc *rtc = data;
  193. rtc_update_irq(rtc->rtc, 1, RTC_IRQF | RTC_AF);
  194. return IRQ_HANDLED;
  195. }
  196. static int tps6586x_rtc_probe(struct platform_device *pdev)
  197. {
  198. struct device *tps_dev = to_tps6586x_dev(&pdev->dev);
  199. struct tps6586x_rtc *rtc;
  200. int ret;
  201. rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
  202. if (!rtc)
  203. return -ENOMEM;
  204. rtc->dev = &pdev->dev;
  205. rtc->irq = platform_get_irq(pdev, 0);
  206. /* 1 kHz tick mode, enable tick counting */
  207. ret = tps6586x_update(tps_dev, RTC_CTRL,
  208. RTC_ENABLE | OSC_SRC_SEL |
  209. ((TPS6586X_RTC_CL_SEL_1_5PF << CL_SEL_POS) & CL_SEL_MASK),
  210. RTC_ENABLE | OSC_SRC_SEL | PRE_BYPASS | CL_SEL_MASK);
  211. if (ret < 0) {
  212. dev_err(&pdev->dev, "unable to start counter\n");
  213. return ret;
  214. }
  215. device_init_wakeup(&pdev->dev, 1);
  216. platform_set_drvdata(pdev, rtc);
  217. rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
  218. if (IS_ERR(rtc->rtc)) {
  219. ret = PTR_ERR(rtc->rtc);
  220. dev_err(&pdev->dev, "RTC allocate device: ret %d\n", ret);
  221. goto fail_rtc_register;
  222. }
  223. rtc->rtc->ops = &tps6586x_rtc_ops;
  224. rtc->rtc->range_max = (1ULL << 30) - 1; /* 30-bit seconds */
  225. rtc->rtc->start_secs = mktime64(2009, 1, 1, 0, 0, 0);
  226. rtc->rtc->set_start_time = true;
  227. ret = devm_request_threaded_irq(&pdev->dev, rtc->irq, NULL,
  228. tps6586x_rtc_irq,
  229. IRQF_ONESHOT,
  230. dev_name(&pdev->dev), rtc);
  231. if (ret < 0) {
  232. dev_err(&pdev->dev, "request IRQ(%d) failed with ret %d\n",
  233. rtc->irq, ret);
  234. goto fail_rtc_register;
  235. }
  236. disable_irq(rtc->irq);
  237. ret = rtc_register_device(rtc->rtc);
  238. if (ret) {
  239. dev_err(&pdev->dev, "RTC device register: ret %d\n", ret);
  240. goto fail_rtc_register;
  241. }
  242. return 0;
  243. fail_rtc_register:
  244. tps6586x_update(tps_dev, RTC_CTRL, 0,
  245. RTC_ENABLE | OSC_SRC_SEL | PRE_BYPASS | CL_SEL_MASK);
  246. return ret;
  247. };
  248. static int tps6586x_rtc_remove(struct platform_device *pdev)
  249. {
  250. struct device *tps_dev = to_tps6586x_dev(&pdev->dev);
  251. tps6586x_update(tps_dev, RTC_CTRL, 0,
  252. RTC_ENABLE | OSC_SRC_SEL | PRE_BYPASS | CL_SEL_MASK);
  253. return 0;
  254. }
  255. #ifdef CONFIG_PM_SLEEP
  256. static int tps6586x_rtc_suspend(struct device *dev)
  257. {
  258. struct tps6586x_rtc *rtc = dev_get_drvdata(dev);
  259. if (device_may_wakeup(dev))
  260. enable_irq_wake(rtc->irq);
  261. return 0;
  262. }
  263. static int tps6586x_rtc_resume(struct device *dev)
  264. {
  265. struct tps6586x_rtc *rtc = dev_get_drvdata(dev);
  266. if (device_may_wakeup(dev))
  267. disable_irq_wake(rtc->irq);
  268. return 0;
  269. }
  270. #endif
  271. static SIMPLE_DEV_PM_OPS(tps6586x_pm_ops, tps6586x_rtc_suspend,
  272. tps6586x_rtc_resume);
  273. static struct platform_driver tps6586x_rtc_driver = {
  274. .driver = {
  275. .name = "tps6586x-rtc",
  276. .pm = &tps6586x_pm_ops,
  277. },
  278. .probe = tps6586x_rtc_probe,
  279. .remove = tps6586x_rtc_remove,
  280. };
  281. module_platform_driver(tps6586x_rtc_driver);
  282. MODULE_ALIAS("platform:tps6586x-rtc");
  283. MODULE_DESCRIPTION("TI TPS6586x RTC driver");
  284. MODULE_AUTHOR("Laxman dewangan <ldewangan@nvidia.com>");
  285. MODULE_LICENSE("GPL v2");