rtc-sunxi.c 13 KB

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  1. /*
  2. * An RTC driver for Allwinner A10/A20
  3. *
  4. * Copyright (c) 2013, Carlo Caione <carlo.caione@gmail.com>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along
  17. * with this program; if not, write to the Free Software Foundation, Inc.,
  18. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
  19. */
  20. #include <linux/delay.h>
  21. #include <linux/err.h>
  22. #include <linux/fs.h>
  23. #include <linux/init.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/io.h>
  26. #include <linux/kernel.h>
  27. #include <linux/module.h>
  28. #include <linux/of.h>
  29. #include <linux/of_address.h>
  30. #include <linux/of_device.h>
  31. #include <linux/platform_device.h>
  32. #include <linux/rtc.h>
  33. #include <linux/types.h>
  34. #define SUNXI_LOSC_CTRL 0x0000
  35. #define SUNXI_LOSC_CTRL_RTC_HMS_ACC BIT(8)
  36. #define SUNXI_LOSC_CTRL_RTC_YMD_ACC BIT(7)
  37. #define SUNXI_RTC_YMD 0x0004
  38. #define SUNXI_RTC_HMS 0x0008
  39. #define SUNXI_ALRM_DHMS 0x000c
  40. #define SUNXI_ALRM_EN 0x0014
  41. #define SUNXI_ALRM_EN_CNT_EN BIT(8)
  42. #define SUNXI_ALRM_IRQ_EN 0x0018
  43. #define SUNXI_ALRM_IRQ_EN_CNT_IRQ_EN BIT(0)
  44. #define SUNXI_ALRM_IRQ_STA 0x001c
  45. #define SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND BIT(0)
  46. #define SUNXI_MASK_DH 0x0000001f
  47. #define SUNXI_MASK_SM 0x0000003f
  48. #define SUNXI_MASK_M 0x0000000f
  49. #define SUNXI_MASK_LY 0x00000001
  50. #define SUNXI_MASK_D 0x00000ffe
  51. #define SUNXI_MASK_M 0x0000000f
  52. #define SUNXI_GET(x, mask, shift) (((x) & ((mask) << (shift))) \
  53. >> (shift))
  54. #define SUNXI_SET(x, mask, shift) (((x) & (mask)) << (shift))
  55. /*
  56. * Get date values
  57. */
  58. #define SUNXI_DATE_GET_DAY_VALUE(x) SUNXI_GET(x, SUNXI_MASK_DH, 0)
  59. #define SUNXI_DATE_GET_MON_VALUE(x) SUNXI_GET(x, SUNXI_MASK_M, 8)
  60. #define SUNXI_DATE_GET_YEAR_VALUE(x, mask) SUNXI_GET(x, mask, 16)
  61. /*
  62. * Get time values
  63. */
  64. #define SUNXI_TIME_GET_SEC_VALUE(x) SUNXI_GET(x, SUNXI_MASK_SM, 0)
  65. #define SUNXI_TIME_GET_MIN_VALUE(x) SUNXI_GET(x, SUNXI_MASK_SM, 8)
  66. #define SUNXI_TIME_GET_HOUR_VALUE(x) SUNXI_GET(x, SUNXI_MASK_DH, 16)
  67. /*
  68. * Get alarm values
  69. */
  70. #define SUNXI_ALRM_GET_SEC_VALUE(x) SUNXI_GET(x, SUNXI_MASK_SM, 0)
  71. #define SUNXI_ALRM_GET_MIN_VALUE(x) SUNXI_GET(x, SUNXI_MASK_SM, 8)
  72. #define SUNXI_ALRM_GET_HOUR_VALUE(x) SUNXI_GET(x, SUNXI_MASK_DH, 16)
  73. /*
  74. * Set date values
  75. */
  76. #define SUNXI_DATE_SET_DAY_VALUE(x) SUNXI_DATE_GET_DAY_VALUE(x)
  77. #define SUNXI_DATE_SET_MON_VALUE(x) SUNXI_SET(x, SUNXI_MASK_M, 8)
  78. #define SUNXI_DATE_SET_YEAR_VALUE(x, mask) SUNXI_SET(x, mask, 16)
  79. #define SUNXI_LEAP_SET_VALUE(x, shift) SUNXI_SET(x, SUNXI_MASK_LY, shift)
  80. /*
  81. * Set time values
  82. */
  83. #define SUNXI_TIME_SET_SEC_VALUE(x) SUNXI_TIME_GET_SEC_VALUE(x)
  84. #define SUNXI_TIME_SET_MIN_VALUE(x) SUNXI_SET(x, SUNXI_MASK_SM, 8)
  85. #define SUNXI_TIME_SET_HOUR_VALUE(x) SUNXI_SET(x, SUNXI_MASK_DH, 16)
  86. /*
  87. * Set alarm values
  88. */
  89. #define SUNXI_ALRM_SET_SEC_VALUE(x) SUNXI_ALRM_GET_SEC_VALUE(x)
  90. #define SUNXI_ALRM_SET_MIN_VALUE(x) SUNXI_SET(x, SUNXI_MASK_SM, 8)
  91. #define SUNXI_ALRM_SET_HOUR_VALUE(x) SUNXI_SET(x, SUNXI_MASK_DH, 16)
  92. #define SUNXI_ALRM_SET_DAY_VALUE(x) SUNXI_SET(x, SUNXI_MASK_D, 21)
  93. /*
  94. * Time unit conversions
  95. */
  96. #define SEC_IN_MIN 60
  97. #define SEC_IN_HOUR (60 * SEC_IN_MIN)
  98. #define SEC_IN_DAY (24 * SEC_IN_HOUR)
  99. /*
  100. * The year parameter passed to the driver is usually an offset relative to
  101. * the year 1900. This macro is used to convert this offset to another one
  102. * relative to the minimum year allowed by the hardware.
  103. */
  104. #define SUNXI_YEAR_OFF(x) ((x)->min - 1900)
  105. /*
  106. * min and max year are arbitrary set considering the limited range of the
  107. * hardware register field
  108. */
  109. struct sunxi_rtc_data_year {
  110. unsigned int min; /* min year allowed */
  111. unsigned int max; /* max year allowed */
  112. unsigned int mask; /* mask for the year field */
  113. unsigned char leap_shift; /* bit shift to get the leap year */
  114. };
  115. static const struct sunxi_rtc_data_year data_year_param[] = {
  116. [0] = {
  117. .min = 2010,
  118. .max = 2073,
  119. .mask = 0x3f,
  120. .leap_shift = 22,
  121. },
  122. [1] = {
  123. .min = 1970,
  124. .max = 2225,
  125. .mask = 0xff,
  126. .leap_shift = 24,
  127. },
  128. };
  129. struct sunxi_rtc_dev {
  130. struct rtc_device *rtc;
  131. struct device *dev;
  132. const struct sunxi_rtc_data_year *data_year;
  133. void __iomem *base;
  134. int irq;
  135. };
  136. static irqreturn_t sunxi_rtc_alarmirq(int irq, void *id)
  137. {
  138. struct sunxi_rtc_dev *chip = (struct sunxi_rtc_dev *) id;
  139. u32 val;
  140. val = readl(chip->base + SUNXI_ALRM_IRQ_STA);
  141. if (val & SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND) {
  142. val |= SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND;
  143. writel(val, chip->base + SUNXI_ALRM_IRQ_STA);
  144. rtc_update_irq(chip->rtc, 1, RTC_AF | RTC_IRQF);
  145. return IRQ_HANDLED;
  146. }
  147. return IRQ_NONE;
  148. }
  149. static void sunxi_rtc_setaie(unsigned int to, struct sunxi_rtc_dev *chip)
  150. {
  151. u32 alrm_val = 0;
  152. u32 alrm_irq_val = 0;
  153. if (to) {
  154. alrm_val = readl(chip->base + SUNXI_ALRM_EN);
  155. alrm_val |= SUNXI_ALRM_EN_CNT_EN;
  156. alrm_irq_val = readl(chip->base + SUNXI_ALRM_IRQ_EN);
  157. alrm_irq_val |= SUNXI_ALRM_IRQ_EN_CNT_IRQ_EN;
  158. } else {
  159. writel(SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND,
  160. chip->base + SUNXI_ALRM_IRQ_STA);
  161. }
  162. writel(alrm_val, chip->base + SUNXI_ALRM_EN);
  163. writel(alrm_irq_val, chip->base + SUNXI_ALRM_IRQ_EN);
  164. }
  165. static int sunxi_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
  166. {
  167. struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
  168. struct rtc_time *alrm_tm = &wkalrm->time;
  169. u32 alrm;
  170. u32 alrm_en;
  171. u32 date;
  172. alrm = readl(chip->base + SUNXI_ALRM_DHMS);
  173. date = readl(chip->base + SUNXI_RTC_YMD);
  174. alrm_tm->tm_sec = SUNXI_ALRM_GET_SEC_VALUE(alrm);
  175. alrm_tm->tm_min = SUNXI_ALRM_GET_MIN_VALUE(alrm);
  176. alrm_tm->tm_hour = SUNXI_ALRM_GET_HOUR_VALUE(alrm);
  177. alrm_tm->tm_mday = SUNXI_DATE_GET_DAY_VALUE(date);
  178. alrm_tm->tm_mon = SUNXI_DATE_GET_MON_VALUE(date);
  179. alrm_tm->tm_year = SUNXI_DATE_GET_YEAR_VALUE(date,
  180. chip->data_year->mask);
  181. alrm_tm->tm_mon -= 1;
  182. /*
  183. * switch from (data_year->min)-relative offset to
  184. * a (1900)-relative one
  185. */
  186. alrm_tm->tm_year += SUNXI_YEAR_OFF(chip->data_year);
  187. alrm_en = readl(chip->base + SUNXI_ALRM_IRQ_EN);
  188. if (alrm_en & SUNXI_ALRM_EN_CNT_EN)
  189. wkalrm->enabled = 1;
  190. return 0;
  191. }
  192. static int sunxi_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
  193. {
  194. struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
  195. u32 date, time;
  196. /*
  197. * read again in case it changes
  198. */
  199. do {
  200. date = readl(chip->base + SUNXI_RTC_YMD);
  201. time = readl(chip->base + SUNXI_RTC_HMS);
  202. } while ((date != readl(chip->base + SUNXI_RTC_YMD)) ||
  203. (time != readl(chip->base + SUNXI_RTC_HMS)));
  204. rtc_tm->tm_sec = SUNXI_TIME_GET_SEC_VALUE(time);
  205. rtc_tm->tm_min = SUNXI_TIME_GET_MIN_VALUE(time);
  206. rtc_tm->tm_hour = SUNXI_TIME_GET_HOUR_VALUE(time);
  207. rtc_tm->tm_mday = SUNXI_DATE_GET_DAY_VALUE(date);
  208. rtc_tm->tm_mon = SUNXI_DATE_GET_MON_VALUE(date);
  209. rtc_tm->tm_year = SUNXI_DATE_GET_YEAR_VALUE(date,
  210. chip->data_year->mask);
  211. rtc_tm->tm_mon -= 1;
  212. /*
  213. * switch from (data_year->min)-relative offset to
  214. * a (1900)-relative one
  215. */
  216. rtc_tm->tm_year += SUNXI_YEAR_OFF(chip->data_year);
  217. return 0;
  218. }
  219. static int sunxi_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
  220. {
  221. struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
  222. struct rtc_time *alrm_tm = &wkalrm->time;
  223. struct rtc_time tm_now;
  224. u32 alrm;
  225. time64_t diff;
  226. unsigned long time_gap;
  227. unsigned long time_gap_day;
  228. unsigned long time_gap_hour;
  229. unsigned long time_gap_min;
  230. int ret;
  231. ret = sunxi_rtc_gettime(dev, &tm_now);
  232. if (ret < 0) {
  233. dev_err(dev, "Error in getting time\n");
  234. return -EINVAL;
  235. }
  236. diff = rtc_tm_sub(alrm_tm, &tm_now);
  237. if (diff <= 0) {
  238. dev_err(dev, "Date to set in the past\n");
  239. return -EINVAL;
  240. }
  241. if (diff > 255 * SEC_IN_DAY) {
  242. dev_err(dev, "Day must be in the range 0 - 255\n");
  243. return -EINVAL;
  244. }
  245. time_gap = diff;
  246. time_gap_day = time_gap / SEC_IN_DAY;
  247. time_gap -= time_gap_day * SEC_IN_DAY;
  248. time_gap_hour = time_gap / SEC_IN_HOUR;
  249. time_gap -= time_gap_hour * SEC_IN_HOUR;
  250. time_gap_min = time_gap / SEC_IN_MIN;
  251. time_gap -= time_gap_min * SEC_IN_MIN;
  252. sunxi_rtc_setaie(0, chip);
  253. writel(0, chip->base + SUNXI_ALRM_DHMS);
  254. usleep_range(100, 300);
  255. alrm = SUNXI_ALRM_SET_SEC_VALUE(time_gap) |
  256. SUNXI_ALRM_SET_MIN_VALUE(time_gap_min) |
  257. SUNXI_ALRM_SET_HOUR_VALUE(time_gap_hour) |
  258. SUNXI_ALRM_SET_DAY_VALUE(time_gap_day);
  259. writel(alrm, chip->base + SUNXI_ALRM_DHMS);
  260. writel(0, chip->base + SUNXI_ALRM_IRQ_EN);
  261. writel(SUNXI_ALRM_IRQ_EN_CNT_IRQ_EN, chip->base + SUNXI_ALRM_IRQ_EN);
  262. sunxi_rtc_setaie(wkalrm->enabled, chip);
  263. return 0;
  264. }
  265. static int sunxi_rtc_wait(struct sunxi_rtc_dev *chip, int offset,
  266. unsigned int mask, unsigned int ms_timeout)
  267. {
  268. const unsigned long timeout = jiffies + msecs_to_jiffies(ms_timeout);
  269. u32 reg;
  270. do {
  271. reg = readl(chip->base + offset);
  272. reg &= mask;
  273. if (reg == mask)
  274. return 0;
  275. } while (time_before(jiffies, timeout));
  276. return -ETIMEDOUT;
  277. }
  278. static int sunxi_rtc_settime(struct device *dev, struct rtc_time *rtc_tm)
  279. {
  280. struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
  281. u32 date = 0;
  282. u32 time = 0;
  283. unsigned int year;
  284. /*
  285. * the input rtc_tm->tm_year is the offset relative to 1900. We use
  286. * the SUNXI_YEAR_OFF macro to rebase it with respect to the min year
  287. * allowed by the hardware
  288. */
  289. year = rtc_tm->tm_year + 1900;
  290. if (year < chip->data_year->min || year > chip->data_year->max) {
  291. dev_err(dev, "rtc only supports year in range %u - %u\n",
  292. chip->data_year->min, chip->data_year->max);
  293. return -EINVAL;
  294. }
  295. rtc_tm->tm_year -= SUNXI_YEAR_OFF(chip->data_year);
  296. rtc_tm->tm_mon += 1;
  297. date = SUNXI_DATE_SET_DAY_VALUE(rtc_tm->tm_mday) |
  298. SUNXI_DATE_SET_MON_VALUE(rtc_tm->tm_mon) |
  299. SUNXI_DATE_SET_YEAR_VALUE(rtc_tm->tm_year,
  300. chip->data_year->mask);
  301. if (is_leap_year(year))
  302. date |= SUNXI_LEAP_SET_VALUE(1, chip->data_year->leap_shift);
  303. time = SUNXI_TIME_SET_SEC_VALUE(rtc_tm->tm_sec) |
  304. SUNXI_TIME_SET_MIN_VALUE(rtc_tm->tm_min) |
  305. SUNXI_TIME_SET_HOUR_VALUE(rtc_tm->tm_hour);
  306. writel(0, chip->base + SUNXI_RTC_HMS);
  307. writel(0, chip->base + SUNXI_RTC_YMD);
  308. writel(time, chip->base + SUNXI_RTC_HMS);
  309. /*
  310. * After writing the RTC HH-MM-SS register, the
  311. * SUNXI_LOSC_CTRL_RTC_HMS_ACC bit is set and it will not
  312. * be cleared until the real writing operation is finished
  313. */
  314. if (sunxi_rtc_wait(chip, SUNXI_LOSC_CTRL,
  315. SUNXI_LOSC_CTRL_RTC_HMS_ACC, 50)) {
  316. dev_err(dev, "Failed to set rtc time.\n");
  317. return -1;
  318. }
  319. writel(date, chip->base + SUNXI_RTC_YMD);
  320. /*
  321. * After writing the RTC YY-MM-DD register, the
  322. * SUNXI_LOSC_CTRL_RTC_YMD_ACC bit is set and it will not
  323. * be cleared until the real writing operation is finished
  324. */
  325. if (sunxi_rtc_wait(chip, SUNXI_LOSC_CTRL,
  326. SUNXI_LOSC_CTRL_RTC_YMD_ACC, 50)) {
  327. dev_err(dev, "Failed to set rtc time.\n");
  328. return -1;
  329. }
  330. return 0;
  331. }
  332. static int sunxi_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
  333. {
  334. struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
  335. if (!enabled)
  336. sunxi_rtc_setaie(enabled, chip);
  337. return 0;
  338. }
  339. static const struct rtc_class_ops sunxi_rtc_ops = {
  340. .read_time = sunxi_rtc_gettime,
  341. .set_time = sunxi_rtc_settime,
  342. .read_alarm = sunxi_rtc_getalarm,
  343. .set_alarm = sunxi_rtc_setalarm,
  344. .alarm_irq_enable = sunxi_rtc_alarm_irq_enable
  345. };
  346. static const struct of_device_id sunxi_rtc_dt_ids[] = {
  347. { .compatible = "allwinner,sun4i-a10-rtc", .data = &data_year_param[0] },
  348. { .compatible = "allwinner,sun7i-a20-rtc", .data = &data_year_param[1] },
  349. { /* sentinel */ },
  350. };
  351. MODULE_DEVICE_TABLE(of, sunxi_rtc_dt_ids);
  352. static int sunxi_rtc_probe(struct platform_device *pdev)
  353. {
  354. struct sunxi_rtc_dev *chip;
  355. struct resource *res;
  356. int ret;
  357. chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
  358. if (!chip)
  359. return -ENOMEM;
  360. platform_set_drvdata(pdev, chip);
  361. chip->dev = &pdev->dev;
  362. chip->rtc = devm_rtc_allocate_device(&pdev->dev);
  363. if (IS_ERR(chip->rtc))
  364. return PTR_ERR(chip->rtc);
  365. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  366. chip->base = devm_ioremap_resource(&pdev->dev, res);
  367. if (IS_ERR(chip->base))
  368. return PTR_ERR(chip->base);
  369. chip->irq = platform_get_irq(pdev, 0);
  370. if (chip->irq < 0) {
  371. dev_err(&pdev->dev, "No IRQ resource\n");
  372. return chip->irq;
  373. }
  374. ret = devm_request_irq(&pdev->dev, chip->irq, sunxi_rtc_alarmirq,
  375. 0, dev_name(&pdev->dev), chip);
  376. if (ret) {
  377. dev_err(&pdev->dev, "Could not request IRQ\n");
  378. return ret;
  379. }
  380. chip->data_year = of_device_get_match_data(&pdev->dev);
  381. if (!chip->data_year) {
  382. dev_err(&pdev->dev, "Unable to setup RTC data\n");
  383. return -ENODEV;
  384. }
  385. /* clear the alarm count value */
  386. writel(0, chip->base + SUNXI_ALRM_DHMS);
  387. /* disable alarm, not generate irq pending */
  388. writel(0, chip->base + SUNXI_ALRM_EN);
  389. /* disable alarm week/cnt irq, unset to cpu */
  390. writel(0, chip->base + SUNXI_ALRM_IRQ_EN);
  391. /* clear alarm week/cnt irq pending */
  392. writel(SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND, chip->base +
  393. SUNXI_ALRM_IRQ_STA);
  394. chip->rtc->ops = &sunxi_rtc_ops;
  395. ret = rtc_register_device(chip->rtc);
  396. if (ret) {
  397. dev_err(&pdev->dev, "unable to register device\n");
  398. return ret;
  399. }
  400. dev_info(&pdev->dev, "RTC enabled\n");
  401. return 0;
  402. }
  403. static struct platform_driver sunxi_rtc_driver = {
  404. .probe = sunxi_rtc_probe,
  405. .driver = {
  406. .name = "sunxi-rtc",
  407. .of_match_table = sunxi_rtc_dt_ids,
  408. },
  409. };
  410. module_platform_driver(sunxi_rtc_driver);
  411. MODULE_DESCRIPTION("sunxi RTC driver");
  412. MODULE_AUTHOR("Carlo Caione <carlo.caione@gmail.com>");
  413. MODULE_LICENSE("GPL");