ptp_qoriq.c 15 KB

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  1. /*
  2. * PTP 1588 clock for Freescale QorIQ 1588 timer
  3. *
  4. * Copyright (C) 2010 OMICRON electronics GmbH
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19. */
  20. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  21. #include <linux/device.h>
  22. #include <linux/hrtimer.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/kernel.h>
  25. #include <linux/module.h>
  26. #include <linux/of.h>
  27. #include <linux/of_platform.h>
  28. #include <linux/timex.h>
  29. #include <linux/slab.h>
  30. #include <linux/clk.h>
  31. #include <linux/fsl/ptp_qoriq.h>
  32. /*
  33. * Register access functions
  34. */
  35. /* Caller must hold qoriq_ptp->lock. */
  36. static u64 tmr_cnt_read(struct qoriq_ptp *qoriq_ptp)
  37. {
  38. struct qoriq_ptp_registers *regs = &qoriq_ptp->regs;
  39. u64 ns;
  40. u32 lo, hi;
  41. lo = qoriq_read(&regs->ctrl_regs->tmr_cnt_l);
  42. hi = qoriq_read(&regs->ctrl_regs->tmr_cnt_h);
  43. ns = ((u64) hi) << 32;
  44. ns |= lo;
  45. return ns;
  46. }
  47. /* Caller must hold qoriq_ptp->lock. */
  48. static void tmr_cnt_write(struct qoriq_ptp *qoriq_ptp, u64 ns)
  49. {
  50. struct qoriq_ptp_registers *regs = &qoriq_ptp->regs;
  51. u32 hi = ns >> 32;
  52. u32 lo = ns & 0xffffffff;
  53. qoriq_write(&regs->ctrl_regs->tmr_cnt_l, lo);
  54. qoriq_write(&regs->ctrl_regs->tmr_cnt_h, hi);
  55. }
  56. /* Caller must hold qoriq_ptp->lock. */
  57. static void set_alarm(struct qoriq_ptp *qoriq_ptp)
  58. {
  59. struct qoriq_ptp_registers *regs = &qoriq_ptp->regs;
  60. u64 ns;
  61. u32 lo, hi;
  62. ns = tmr_cnt_read(qoriq_ptp) + 1500000000ULL;
  63. ns = div_u64(ns, 1000000000UL) * 1000000000ULL;
  64. ns -= qoriq_ptp->tclk_period;
  65. hi = ns >> 32;
  66. lo = ns & 0xffffffff;
  67. qoriq_write(&regs->alarm_regs->tmr_alarm1_l, lo);
  68. qoriq_write(&regs->alarm_regs->tmr_alarm1_h, hi);
  69. }
  70. /* Caller must hold qoriq_ptp->lock. */
  71. static void set_fipers(struct qoriq_ptp *qoriq_ptp)
  72. {
  73. struct qoriq_ptp_registers *regs = &qoriq_ptp->regs;
  74. set_alarm(qoriq_ptp);
  75. qoriq_write(&regs->fiper_regs->tmr_fiper1, qoriq_ptp->tmr_fiper1);
  76. qoriq_write(&regs->fiper_regs->tmr_fiper2, qoriq_ptp->tmr_fiper2);
  77. }
  78. /*
  79. * Interrupt service routine
  80. */
  81. static irqreturn_t isr(int irq, void *priv)
  82. {
  83. struct qoriq_ptp *qoriq_ptp = priv;
  84. struct qoriq_ptp_registers *regs = &qoriq_ptp->regs;
  85. struct ptp_clock_event event;
  86. u64 ns;
  87. u32 ack = 0, lo, hi, mask, val;
  88. val = qoriq_read(&regs->ctrl_regs->tmr_tevent);
  89. if (val & ETS1) {
  90. ack |= ETS1;
  91. hi = qoriq_read(&regs->etts_regs->tmr_etts1_h);
  92. lo = qoriq_read(&regs->etts_regs->tmr_etts1_l);
  93. event.type = PTP_CLOCK_EXTTS;
  94. event.index = 0;
  95. event.timestamp = ((u64) hi) << 32;
  96. event.timestamp |= lo;
  97. ptp_clock_event(qoriq_ptp->clock, &event);
  98. }
  99. if (val & ETS2) {
  100. ack |= ETS2;
  101. hi = qoriq_read(&regs->etts_regs->tmr_etts2_h);
  102. lo = qoriq_read(&regs->etts_regs->tmr_etts2_l);
  103. event.type = PTP_CLOCK_EXTTS;
  104. event.index = 1;
  105. event.timestamp = ((u64) hi) << 32;
  106. event.timestamp |= lo;
  107. ptp_clock_event(qoriq_ptp->clock, &event);
  108. }
  109. if (val & ALM2) {
  110. ack |= ALM2;
  111. if (qoriq_ptp->alarm_value) {
  112. event.type = PTP_CLOCK_ALARM;
  113. event.index = 0;
  114. event.timestamp = qoriq_ptp->alarm_value;
  115. ptp_clock_event(qoriq_ptp->clock, &event);
  116. }
  117. if (qoriq_ptp->alarm_interval) {
  118. ns = qoriq_ptp->alarm_value + qoriq_ptp->alarm_interval;
  119. hi = ns >> 32;
  120. lo = ns & 0xffffffff;
  121. spin_lock(&qoriq_ptp->lock);
  122. qoriq_write(&regs->alarm_regs->tmr_alarm2_l, lo);
  123. qoriq_write(&regs->alarm_regs->tmr_alarm2_h, hi);
  124. spin_unlock(&qoriq_ptp->lock);
  125. qoriq_ptp->alarm_value = ns;
  126. } else {
  127. qoriq_write(&regs->ctrl_regs->tmr_tevent, ALM2);
  128. spin_lock(&qoriq_ptp->lock);
  129. mask = qoriq_read(&regs->ctrl_regs->tmr_temask);
  130. mask &= ~ALM2EN;
  131. qoriq_write(&regs->ctrl_regs->tmr_temask, mask);
  132. spin_unlock(&qoriq_ptp->lock);
  133. qoriq_ptp->alarm_value = 0;
  134. qoriq_ptp->alarm_interval = 0;
  135. }
  136. }
  137. if (val & PP1) {
  138. ack |= PP1;
  139. event.type = PTP_CLOCK_PPS;
  140. ptp_clock_event(qoriq_ptp->clock, &event);
  141. }
  142. if (ack) {
  143. qoriq_write(&regs->ctrl_regs->tmr_tevent, ack);
  144. return IRQ_HANDLED;
  145. } else
  146. return IRQ_NONE;
  147. }
  148. /*
  149. * PTP clock operations
  150. */
  151. static int ptp_qoriq_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
  152. {
  153. u64 adj, diff;
  154. u32 tmr_add;
  155. int neg_adj = 0;
  156. struct qoriq_ptp *qoriq_ptp = container_of(ptp, struct qoriq_ptp, caps);
  157. struct qoriq_ptp_registers *regs = &qoriq_ptp->regs;
  158. if (scaled_ppm < 0) {
  159. neg_adj = 1;
  160. scaled_ppm = -scaled_ppm;
  161. }
  162. tmr_add = qoriq_ptp->tmr_add;
  163. adj = tmr_add;
  164. /* calculate diff as adj*(scaled_ppm/65536)/1000000
  165. * and round() to the nearest integer
  166. */
  167. adj *= scaled_ppm;
  168. diff = div_u64(adj, 8000000);
  169. diff = (diff >> 13) + ((diff >> 12) & 1);
  170. tmr_add = neg_adj ? tmr_add - diff : tmr_add + diff;
  171. qoriq_write(&regs->ctrl_regs->tmr_add, tmr_add);
  172. return 0;
  173. }
  174. static int ptp_qoriq_adjtime(struct ptp_clock_info *ptp, s64 delta)
  175. {
  176. s64 now;
  177. unsigned long flags;
  178. struct qoriq_ptp *qoriq_ptp = container_of(ptp, struct qoriq_ptp, caps);
  179. spin_lock_irqsave(&qoriq_ptp->lock, flags);
  180. now = tmr_cnt_read(qoriq_ptp);
  181. now += delta;
  182. tmr_cnt_write(qoriq_ptp, now);
  183. set_fipers(qoriq_ptp);
  184. spin_unlock_irqrestore(&qoriq_ptp->lock, flags);
  185. return 0;
  186. }
  187. static int ptp_qoriq_gettime(struct ptp_clock_info *ptp,
  188. struct timespec64 *ts)
  189. {
  190. u64 ns;
  191. unsigned long flags;
  192. struct qoriq_ptp *qoriq_ptp = container_of(ptp, struct qoriq_ptp, caps);
  193. spin_lock_irqsave(&qoriq_ptp->lock, flags);
  194. ns = tmr_cnt_read(qoriq_ptp);
  195. spin_unlock_irqrestore(&qoriq_ptp->lock, flags);
  196. *ts = ns_to_timespec64(ns);
  197. return 0;
  198. }
  199. static int ptp_qoriq_settime(struct ptp_clock_info *ptp,
  200. const struct timespec64 *ts)
  201. {
  202. u64 ns;
  203. unsigned long flags;
  204. struct qoriq_ptp *qoriq_ptp = container_of(ptp, struct qoriq_ptp, caps);
  205. ns = timespec64_to_ns(ts);
  206. spin_lock_irqsave(&qoriq_ptp->lock, flags);
  207. tmr_cnt_write(qoriq_ptp, ns);
  208. set_fipers(qoriq_ptp);
  209. spin_unlock_irqrestore(&qoriq_ptp->lock, flags);
  210. return 0;
  211. }
  212. static int ptp_qoriq_enable(struct ptp_clock_info *ptp,
  213. struct ptp_clock_request *rq, int on)
  214. {
  215. struct qoriq_ptp *qoriq_ptp = container_of(ptp, struct qoriq_ptp, caps);
  216. struct qoriq_ptp_registers *regs = &qoriq_ptp->regs;
  217. unsigned long flags;
  218. u32 bit, mask;
  219. switch (rq->type) {
  220. case PTP_CLK_REQ_EXTTS:
  221. switch (rq->extts.index) {
  222. case 0:
  223. bit = ETS1EN;
  224. break;
  225. case 1:
  226. bit = ETS2EN;
  227. break;
  228. default:
  229. return -EINVAL;
  230. }
  231. spin_lock_irqsave(&qoriq_ptp->lock, flags);
  232. mask = qoriq_read(&regs->ctrl_regs->tmr_temask);
  233. if (on)
  234. mask |= bit;
  235. else
  236. mask &= ~bit;
  237. qoriq_write(&regs->ctrl_regs->tmr_temask, mask);
  238. spin_unlock_irqrestore(&qoriq_ptp->lock, flags);
  239. return 0;
  240. case PTP_CLK_REQ_PPS:
  241. spin_lock_irqsave(&qoriq_ptp->lock, flags);
  242. mask = qoriq_read(&regs->ctrl_regs->tmr_temask);
  243. if (on)
  244. mask |= PP1EN;
  245. else
  246. mask &= ~PP1EN;
  247. qoriq_write(&regs->ctrl_regs->tmr_temask, mask);
  248. spin_unlock_irqrestore(&qoriq_ptp->lock, flags);
  249. return 0;
  250. default:
  251. break;
  252. }
  253. return -EOPNOTSUPP;
  254. }
  255. static const struct ptp_clock_info ptp_qoriq_caps = {
  256. .owner = THIS_MODULE,
  257. .name = "qoriq ptp clock",
  258. .max_adj = 512000,
  259. .n_alarm = 0,
  260. .n_ext_ts = N_EXT_TS,
  261. .n_per_out = 0,
  262. .n_pins = 0,
  263. .pps = 1,
  264. .adjfine = ptp_qoriq_adjfine,
  265. .adjtime = ptp_qoriq_adjtime,
  266. .gettime64 = ptp_qoriq_gettime,
  267. .settime64 = ptp_qoriq_settime,
  268. .enable = ptp_qoriq_enable,
  269. };
  270. /**
  271. * qoriq_ptp_nominal_freq - calculate nominal frequency according to
  272. * reference clock frequency
  273. *
  274. * @clk_src: reference clock frequency
  275. *
  276. * The nominal frequency is the desired clock frequency.
  277. * It should be less than the reference clock frequency.
  278. * It should be a factor of 1000MHz.
  279. *
  280. * Return the nominal frequency
  281. */
  282. static u32 qoriq_ptp_nominal_freq(u32 clk_src)
  283. {
  284. u32 remainder = 0;
  285. clk_src /= 1000000;
  286. remainder = clk_src % 100;
  287. if (remainder) {
  288. clk_src -= remainder;
  289. clk_src += 100;
  290. }
  291. do {
  292. clk_src -= 100;
  293. } while (1000 % clk_src);
  294. return clk_src * 1000000;
  295. }
  296. /**
  297. * qoriq_ptp_auto_config - calculate a set of default configurations
  298. *
  299. * @qoriq_ptp: pointer to qoriq_ptp
  300. * @node: pointer to device_node
  301. *
  302. * If below dts properties are not provided, this function will be
  303. * called to calculate a set of default configurations for them.
  304. * "fsl,tclk-period"
  305. * "fsl,tmr-prsc"
  306. * "fsl,tmr-add"
  307. * "fsl,tmr-fiper1"
  308. * "fsl,tmr-fiper2"
  309. * "fsl,max-adj"
  310. *
  311. * Return 0 if success
  312. */
  313. static int qoriq_ptp_auto_config(struct qoriq_ptp *qoriq_ptp,
  314. struct device_node *node)
  315. {
  316. struct clk *clk;
  317. u64 freq_comp;
  318. u64 max_adj;
  319. u32 nominal_freq;
  320. u32 remainder = 0;
  321. u32 clk_src = 0;
  322. qoriq_ptp->cksel = DEFAULT_CKSEL;
  323. clk = of_clk_get(node, 0);
  324. if (!IS_ERR(clk)) {
  325. clk_src = clk_get_rate(clk);
  326. clk_put(clk);
  327. }
  328. if (clk_src <= 100000000UL) {
  329. pr_err("error reference clock value, or lower than 100MHz\n");
  330. return -EINVAL;
  331. }
  332. nominal_freq = qoriq_ptp_nominal_freq(clk_src);
  333. if (!nominal_freq)
  334. return -EINVAL;
  335. qoriq_ptp->tclk_period = 1000000000UL / nominal_freq;
  336. qoriq_ptp->tmr_prsc = DEFAULT_TMR_PRSC;
  337. /* Calculate initial frequency compensation value for TMR_ADD register.
  338. * freq_comp = ceil(2^32 / freq_ratio)
  339. * freq_ratio = reference_clock_freq / nominal_freq
  340. */
  341. freq_comp = ((u64)1 << 32) * nominal_freq;
  342. freq_comp = div_u64_rem(freq_comp, clk_src, &remainder);
  343. if (remainder)
  344. freq_comp++;
  345. qoriq_ptp->tmr_add = freq_comp;
  346. qoriq_ptp->tmr_fiper1 = DEFAULT_FIPER1_PERIOD - qoriq_ptp->tclk_period;
  347. qoriq_ptp->tmr_fiper2 = DEFAULT_FIPER2_PERIOD - qoriq_ptp->tclk_period;
  348. /* max_adj = 1000000000 * (freq_ratio - 1.0) - 1
  349. * freq_ratio = reference_clock_freq / nominal_freq
  350. */
  351. max_adj = 1000000000ULL * (clk_src - nominal_freq);
  352. max_adj = div_u64(max_adj, nominal_freq) - 1;
  353. qoriq_ptp->caps.max_adj = max_adj;
  354. return 0;
  355. }
  356. static int qoriq_ptp_probe(struct platform_device *dev)
  357. {
  358. struct device_node *node = dev->dev.of_node;
  359. struct qoriq_ptp *qoriq_ptp;
  360. struct qoriq_ptp_registers *regs;
  361. struct timespec64 now;
  362. int err = -ENOMEM;
  363. u32 tmr_ctrl;
  364. unsigned long flags;
  365. void __iomem *base;
  366. qoriq_ptp = kzalloc(sizeof(*qoriq_ptp), GFP_KERNEL);
  367. if (!qoriq_ptp)
  368. goto no_memory;
  369. err = -EINVAL;
  370. qoriq_ptp->caps = ptp_qoriq_caps;
  371. if (of_property_read_u32(node, "fsl,cksel", &qoriq_ptp->cksel))
  372. qoriq_ptp->cksel = DEFAULT_CKSEL;
  373. if (of_property_read_u32(node,
  374. "fsl,tclk-period", &qoriq_ptp->tclk_period) ||
  375. of_property_read_u32(node,
  376. "fsl,tmr-prsc", &qoriq_ptp->tmr_prsc) ||
  377. of_property_read_u32(node,
  378. "fsl,tmr-add", &qoriq_ptp->tmr_add) ||
  379. of_property_read_u32(node,
  380. "fsl,tmr-fiper1", &qoriq_ptp->tmr_fiper1) ||
  381. of_property_read_u32(node,
  382. "fsl,tmr-fiper2", &qoriq_ptp->tmr_fiper2) ||
  383. of_property_read_u32(node,
  384. "fsl,max-adj", &qoriq_ptp->caps.max_adj)) {
  385. pr_warn("device tree node missing required elements, try automatic configuration\n");
  386. if (qoriq_ptp_auto_config(qoriq_ptp, node))
  387. goto no_config;
  388. }
  389. err = -ENODEV;
  390. qoriq_ptp->irq = platform_get_irq(dev, 0);
  391. if (qoriq_ptp->irq < 0) {
  392. pr_err("irq not in device tree\n");
  393. goto no_node;
  394. }
  395. if (request_irq(qoriq_ptp->irq, isr, IRQF_SHARED, DRIVER, qoriq_ptp)) {
  396. pr_err("request_irq failed\n");
  397. goto no_node;
  398. }
  399. qoriq_ptp->rsrc = platform_get_resource(dev, IORESOURCE_MEM, 0);
  400. if (!qoriq_ptp->rsrc) {
  401. pr_err("no resource\n");
  402. goto no_resource;
  403. }
  404. if (request_resource(&iomem_resource, qoriq_ptp->rsrc)) {
  405. pr_err("resource busy\n");
  406. goto no_resource;
  407. }
  408. spin_lock_init(&qoriq_ptp->lock);
  409. base = ioremap(qoriq_ptp->rsrc->start,
  410. resource_size(qoriq_ptp->rsrc));
  411. if (!base) {
  412. pr_err("ioremap ptp registers failed\n");
  413. goto no_ioremap;
  414. }
  415. qoriq_ptp->base = base;
  416. if (of_device_is_compatible(node, "fsl,fman-ptp-timer")) {
  417. qoriq_ptp->regs.ctrl_regs = base + FMAN_CTRL_REGS_OFFSET;
  418. qoriq_ptp->regs.alarm_regs = base + FMAN_ALARM_REGS_OFFSET;
  419. qoriq_ptp->regs.fiper_regs = base + FMAN_FIPER_REGS_OFFSET;
  420. qoriq_ptp->regs.etts_regs = base + FMAN_ETTS_REGS_OFFSET;
  421. } else {
  422. qoriq_ptp->regs.ctrl_regs = base + CTRL_REGS_OFFSET;
  423. qoriq_ptp->regs.alarm_regs = base + ALARM_REGS_OFFSET;
  424. qoriq_ptp->regs.fiper_regs = base + FIPER_REGS_OFFSET;
  425. qoriq_ptp->regs.etts_regs = base + ETTS_REGS_OFFSET;
  426. }
  427. ktime_get_real_ts64(&now);
  428. ptp_qoriq_settime(&qoriq_ptp->caps, &now);
  429. tmr_ctrl =
  430. (qoriq_ptp->tclk_period & TCLK_PERIOD_MASK) << TCLK_PERIOD_SHIFT |
  431. (qoriq_ptp->cksel & CKSEL_MASK) << CKSEL_SHIFT;
  432. spin_lock_irqsave(&qoriq_ptp->lock, flags);
  433. regs = &qoriq_ptp->regs;
  434. qoriq_write(&regs->ctrl_regs->tmr_ctrl, tmr_ctrl);
  435. qoriq_write(&regs->ctrl_regs->tmr_add, qoriq_ptp->tmr_add);
  436. qoriq_write(&regs->ctrl_regs->tmr_prsc, qoriq_ptp->tmr_prsc);
  437. qoriq_write(&regs->fiper_regs->tmr_fiper1, qoriq_ptp->tmr_fiper1);
  438. qoriq_write(&regs->fiper_regs->tmr_fiper2, qoriq_ptp->tmr_fiper2);
  439. set_alarm(qoriq_ptp);
  440. qoriq_write(&regs->ctrl_regs->tmr_ctrl, tmr_ctrl|FIPERST|RTPE|TE|FRD);
  441. spin_unlock_irqrestore(&qoriq_ptp->lock, flags);
  442. qoriq_ptp->clock = ptp_clock_register(&qoriq_ptp->caps, &dev->dev);
  443. if (IS_ERR(qoriq_ptp->clock)) {
  444. err = PTR_ERR(qoriq_ptp->clock);
  445. goto no_clock;
  446. }
  447. qoriq_ptp->phc_index = ptp_clock_index(qoriq_ptp->clock);
  448. platform_set_drvdata(dev, qoriq_ptp);
  449. return 0;
  450. no_clock:
  451. iounmap(qoriq_ptp->base);
  452. no_ioremap:
  453. release_resource(qoriq_ptp->rsrc);
  454. no_resource:
  455. free_irq(qoriq_ptp->irq, qoriq_ptp);
  456. no_config:
  457. no_node:
  458. kfree(qoriq_ptp);
  459. no_memory:
  460. return err;
  461. }
  462. static int qoriq_ptp_remove(struct platform_device *dev)
  463. {
  464. struct qoriq_ptp *qoriq_ptp = platform_get_drvdata(dev);
  465. struct qoriq_ptp_registers *regs = &qoriq_ptp->regs;
  466. qoriq_write(&regs->ctrl_regs->tmr_temask, 0);
  467. qoriq_write(&regs->ctrl_regs->tmr_ctrl, 0);
  468. ptp_clock_unregister(qoriq_ptp->clock);
  469. iounmap(qoriq_ptp->base);
  470. release_resource(qoriq_ptp->rsrc);
  471. free_irq(qoriq_ptp->irq, qoriq_ptp);
  472. kfree(qoriq_ptp);
  473. return 0;
  474. }
  475. static const struct of_device_id match_table[] = {
  476. { .compatible = "fsl,etsec-ptp" },
  477. { .compatible = "fsl,fman-ptp-timer" },
  478. {},
  479. };
  480. MODULE_DEVICE_TABLE(of, match_table);
  481. static struct platform_driver qoriq_ptp_driver = {
  482. .driver = {
  483. .name = "ptp_qoriq",
  484. .of_match_table = match_table,
  485. },
  486. .probe = qoriq_ptp_probe,
  487. .remove = qoriq_ptp_remove,
  488. };
  489. module_platform_driver(qoriq_ptp_driver);
  490. MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>");
  491. MODULE_DESCRIPTION("PTP clock for Freescale QorIQ 1588 timer");
  492. MODULE_LICENSE("GPL");