sa1111_neponset.c 3.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * linux/drivers/pcmcia/sa1100_neponset.c
  4. *
  5. * Neponset PCMCIA specific routines
  6. */
  7. #include <linux/module.h>
  8. #include <linux/kernel.h>
  9. #include <linux/device.h>
  10. #include <linux/errno.h>
  11. #include <linux/init.h>
  12. #include <mach/hardware.h>
  13. #include <asm/mach-types.h>
  14. #include <mach/neponset.h>
  15. #include <asm/hardware/sa1111.h>
  16. #include "sa1111_generic.h"
  17. /*
  18. * Neponset uses the Maxim MAX1600, with the following connections:
  19. *
  20. * MAX1600 Neponset
  21. *
  22. * A0VCC SA-1111 GPIO A<1>
  23. * A1VCC SA-1111 GPIO A<0>
  24. * A0VPP CPLD NCR A0VPP
  25. * A1VPP CPLD NCR A1VPP
  26. * B0VCC SA-1111 GPIO A<2>
  27. * B1VCC SA-1111 GPIO A<3>
  28. * B0VPP ground (slot B is CF)
  29. * B1VPP ground (slot B is CF)
  30. *
  31. * VX VCC (5V)
  32. * VY VCC3_3 (3.3V)
  33. * 12INA 12V
  34. * 12INB ground (slot B is CF)
  35. *
  36. * The MAX1600 CODE pin is tied to ground, placing the device in
  37. * "Standard Intel code" mode. Refer to the Maxim data sheet for
  38. * the corresponding truth table.
  39. */
  40. static int
  41. neponset_pcmcia_configure_socket(struct soc_pcmcia_socket *skt, const socket_state_t *state)
  42. {
  43. struct sa1111_pcmcia_socket *s = to_skt(skt);
  44. unsigned int ncr_mask, ncr_set, pa_dwr_mask, pa_dwr_set;
  45. int ret;
  46. switch (skt->nr) {
  47. case 0:
  48. pa_dwr_mask = GPIO_A0 | GPIO_A1;
  49. ncr_mask = NCR_A0VPP | NCR_A1VPP;
  50. if (state->Vpp == 0)
  51. ncr_set = 0;
  52. else if (state->Vpp == 120)
  53. ncr_set = NCR_A1VPP;
  54. else if (state->Vpp == state->Vcc)
  55. ncr_set = NCR_A0VPP;
  56. else {
  57. printk(KERN_ERR "%s(): unrecognized VPP %u\n",
  58. __func__, state->Vpp);
  59. return -1;
  60. }
  61. break;
  62. case 1:
  63. pa_dwr_mask = GPIO_A2 | GPIO_A3;
  64. ncr_mask = 0;
  65. ncr_set = 0;
  66. if (state->Vpp != state->Vcc && state->Vpp != 0) {
  67. printk(KERN_ERR "%s(): CF slot cannot support VPP %u\n",
  68. __func__, state->Vpp);
  69. return -1;
  70. }
  71. break;
  72. default:
  73. return -1;
  74. }
  75. /*
  76. * pa_dwr_set is the mask for selecting Vcc on both sockets.
  77. * pa_dwr_mask selects which bits (and therefore socket) we change.
  78. */
  79. switch (state->Vcc) {
  80. default:
  81. case 0: pa_dwr_set = 0; break;
  82. case 33: pa_dwr_set = GPIO_A1|GPIO_A2; break;
  83. case 50: pa_dwr_set = GPIO_A0|GPIO_A3; break;
  84. }
  85. ret = sa1111_pcmcia_configure_socket(skt, state);
  86. if (ret == 0) {
  87. neponset_ncr_frob(ncr_mask, ncr_set);
  88. sa1111_set_io(s->dev, pa_dwr_mask, pa_dwr_set);
  89. }
  90. return ret;
  91. }
  92. static struct pcmcia_low_level neponset_pcmcia_ops = {
  93. .owner = THIS_MODULE,
  94. .configure_socket = neponset_pcmcia_configure_socket,
  95. .first = 0,
  96. .nr = 2,
  97. };
  98. int pcmcia_neponset_init(struct sa1111_dev *sadev)
  99. {
  100. /*
  101. * Set GPIO_A<3:0> to be outputs for the MAX1600,
  102. * and switch to standby mode.
  103. */
  104. sa1111_set_io_dir(sadev, GPIO_A0|GPIO_A1|GPIO_A2|GPIO_A3, 0, 0);
  105. sa1111_set_io(sadev, GPIO_A0|GPIO_A1|GPIO_A2|GPIO_A3, 0);
  106. sa1111_set_sleep_io(sadev, GPIO_A0|GPIO_A1|GPIO_A2|GPIO_A3, 0);
  107. sa11xx_drv_pcmcia_ops(&neponset_pcmcia_ops);
  108. return sa1111_pcmcia_add(sadev, &neponset_pcmcia_ops,
  109. sa11xx_drv_pcmcia_add_one);
  110. }