fw.c 22 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2009-2014 Realtek Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * The full GNU General Public License is included in this distribution in the
  15. * file called LICENSE.
  16. *
  17. * Contact Information:
  18. * wlanfae <wlanfae@realtek.com>
  19. * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20. * Hsinchu 300, Taiwan.
  21. *
  22. * Larry Finger <Larry.Finger@lwfinger.net>
  23. *
  24. *****************************************************************************/
  25. #include "../wifi.h"
  26. #include "../pci.h"
  27. #include "../base.h"
  28. #include "../core.h"
  29. #include "reg.h"
  30. #include "def.h"
  31. #include "fw.h"
  32. #include "../rtl8723com/fw_common.h"
  33. static bool _rtl8723be_check_fw_read_last_h2c(struct ieee80211_hw *hw,
  34. u8 boxnum)
  35. {
  36. struct rtl_priv *rtlpriv = rtl_priv(hw);
  37. u8 val_hmetfr;
  38. bool result = false;
  39. val_hmetfr = rtl_read_byte(rtlpriv, REG_HMETFR);
  40. if (((val_hmetfr >> boxnum) & BIT(0)) == 0)
  41. result = true;
  42. return result;
  43. }
  44. static void _rtl8723be_fill_h2c_command(struct ieee80211_hw *hw, u8 element_id,
  45. u32 cmd_len, u8 *p_cmdbuffer)
  46. {
  47. struct rtl_priv *rtlpriv = rtl_priv(hw);
  48. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  49. u8 boxnum;
  50. u16 box_reg = 0, box_extreg = 0;
  51. u8 u1b_tmp;
  52. bool isfw_read = false;
  53. u8 buf_index = 0;
  54. bool bwrite_sucess = false;
  55. u8 wait_h2c_limmit = 100;
  56. u8 wait_writeh2c_limmit = 100;
  57. u8 boxcontent[4], boxextcontent[4];
  58. u32 h2c_waitcounter = 0;
  59. unsigned long flag;
  60. u8 idx;
  61. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "come in\n");
  62. while (true) {
  63. spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
  64. if (rtlhal->h2c_setinprogress) {
  65. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  66. "H2C set in progress! Wait to set..element_id(%d).\n",
  67. element_id);
  68. while (rtlhal->h2c_setinprogress) {
  69. spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock,
  70. flag);
  71. h2c_waitcounter++;
  72. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  73. "Wait 100 us (%d times)...\n",
  74. h2c_waitcounter);
  75. udelay(100);
  76. if (h2c_waitcounter > 1000)
  77. return;
  78. spin_lock_irqsave(&rtlpriv->locks.h2c_lock,
  79. flag);
  80. }
  81. spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
  82. } else {
  83. rtlhal->h2c_setinprogress = true;
  84. spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
  85. break;
  86. }
  87. }
  88. while (!bwrite_sucess) {
  89. wait_writeh2c_limmit--;
  90. if (wait_writeh2c_limmit == 0) {
  91. pr_err("Write H2C fail because no trigger for FW INT!\n");
  92. break;
  93. }
  94. boxnum = rtlhal->last_hmeboxnum;
  95. switch (boxnum) {
  96. case 0:
  97. box_reg = REG_HMEBOX_0;
  98. box_extreg = REG_HMEBOX_EXT_0;
  99. break;
  100. case 1:
  101. box_reg = REG_HMEBOX_1;
  102. box_extreg = REG_HMEBOX_EXT_1;
  103. break;
  104. case 2:
  105. box_reg = REG_HMEBOX_2;
  106. box_extreg = REG_HMEBOX_EXT_2;
  107. break;
  108. case 3:
  109. box_reg = REG_HMEBOX_3;
  110. box_extreg = REG_HMEBOX_EXT_3;
  111. break;
  112. default:
  113. pr_err("switch case %#x not processed\n",
  114. boxnum);
  115. break;
  116. }
  117. isfw_read = _rtl8723be_check_fw_read_last_h2c(hw, boxnum);
  118. while (!isfw_read) {
  119. wait_h2c_limmit--;
  120. if (wait_h2c_limmit == 0) {
  121. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  122. "Waiting too long for FW read clear HMEBox(%d)!\n",
  123. boxnum);
  124. break;
  125. }
  126. udelay(10);
  127. isfw_read = _rtl8723be_check_fw_read_last_h2c(hw,
  128. boxnum);
  129. u1b_tmp = rtl_read_byte(rtlpriv, 0x130);
  130. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  131. "Waiting for FW read clear HMEBox(%d)!!! 0x130 = %2x\n",
  132. boxnum, u1b_tmp);
  133. }
  134. if (!isfw_read) {
  135. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  136. "Write H2C register BOX[%d] fail!!!!! Fw do not read.\n",
  137. boxnum);
  138. break;
  139. }
  140. memset(boxcontent, 0, sizeof(boxcontent));
  141. memset(boxextcontent, 0, sizeof(boxextcontent));
  142. boxcontent[0] = element_id;
  143. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  144. "Write element_id box_reg(%4x) = %2x\n",
  145. box_reg, element_id);
  146. switch (cmd_len) {
  147. case 1:
  148. case 2:
  149. case 3:
  150. /*boxcontent[0] &= ~(BIT(7));*/
  151. memcpy((u8 *)(boxcontent) + 1,
  152. p_cmdbuffer + buf_index, cmd_len);
  153. for (idx = 0; idx < 4; idx++) {
  154. rtl_write_byte(rtlpriv, box_reg + idx,
  155. boxcontent[idx]);
  156. }
  157. break;
  158. case 4:
  159. case 5:
  160. case 6:
  161. case 7:
  162. /*boxcontent[0] |= (BIT(7));*/
  163. memcpy((u8 *)(boxextcontent),
  164. p_cmdbuffer + buf_index+3, cmd_len-3);
  165. memcpy((u8 *)(boxcontent) + 1,
  166. p_cmdbuffer + buf_index, 3);
  167. for (idx = 0; idx < 4; idx++) {
  168. rtl_write_byte(rtlpriv, box_extreg + idx,
  169. boxextcontent[idx]);
  170. }
  171. for (idx = 0; idx < 4; idx++) {
  172. rtl_write_byte(rtlpriv, box_reg + idx,
  173. boxcontent[idx]);
  174. }
  175. break;
  176. default:
  177. pr_err("switch case %#x not processed\n",
  178. cmd_len);
  179. break;
  180. }
  181. bwrite_sucess = true;
  182. rtlhal->last_hmeboxnum = boxnum + 1;
  183. if (rtlhal->last_hmeboxnum == 4)
  184. rtlhal->last_hmeboxnum = 0;
  185. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  186. "pHalData->last_hmeboxnum = %d\n",
  187. rtlhal->last_hmeboxnum);
  188. }
  189. spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
  190. rtlhal->h2c_setinprogress = false;
  191. spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
  192. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "go out\n");
  193. }
  194. void rtl8723be_fill_h2c_cmd(struct ieee80211_hw *hw, u8 element_id,
  195. u32 cmd_len, u8 *p_cmdbuffer)
  196. {
  197. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  198. u32 tmp_cmdbuf[2];
  199. if (!rtlhal->fw_ready) {
  200. WARN_ONCE(true,
  201. "rtl8723be: error H2C cmd because of Fw download fail!!!\n");
  202. return;
  203. }
  204. memset(tmp_cmdbuf, 0, 8);
  205. memcpy(tmp_cmdbuf, p_cmdbuffer, cmd_len);
  206. _rtl8723be_fill_h2c_command(hw, element_id, cmd_len,
  207. (u8 *)&tmp_cmdbuf);
  208. return;
  209. }
  210. void rtl8723be_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode)
  211. {
  212. struct rtl_priv *rtlpriv = rtl_priv(hw);
  213. u8 u1_h2c_set_pwrmode[H2C_PWEMODE_LENGTH] = { 0 };
  214. struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  215. u8 rlbm, power_state = 0, byte5 = 0;
  216. u8 awake_intvl; /* DTIM = (awake_intvl - 1) */
  217. struct rtl_btc_ops *btc_ops = rtlpriv->btcoexist.btc_ops;
  218. bool bt_ctrl_lps = (rtlpriv->cfg->ops->get_btc_status() ?
  219. btc_ops->btc_is_bt_ctrl_lps(rtlpriv) : false);
  220. bool bt_lps_on = (rtlpriv->cfg->ops->get_btc_status() ?
  221. btc_ops->btc_is_bt_lps_on(rtlpriv) : false);
  222. if (bt_ctrl_lps)
  223. mode = (bt_lps_on ? FW_PS_MIN_MODE : FW_PS_ACTIVE_MODE);
  224. RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, "FW LPS mode = %d (coex:%d)\n",
  225. mode, bt_ctrl_lps);
  226. switch (mode) {
  227. case FW_PS_MIN_MODE:
  228. rlbm = 0;
  229. awake_intvl = 2;
  230. break;
  231. case FW_PS_MAX_MODE:
  232. rlbm = 1;
  233. awake_intvl = 2;
  234. break;
  235. case FW_PS_DTIM_MODE:
  236. rlbm = 2;
  237. awake_intvl = ppsc->reg_max_lps_awakeintvl;
  238. /* hw->conf.ps_dtim_period or mac->vif->bss_conf.dtim_period
  239. * is only used in swlps.
  240. */
  241. break;
  242. default:
  243. rlbm = 2;
  244. awake_intvl = 4;
  245. break;
  246. }
  247. if (rtlpriv->mac80211.p2p) {
  248. awake_intvl = 2;
  249. rlbm = 1;
  250. }
  251. if (mode == FW_PS_ACTIVE_MODE) {
  252. byte5 = 0x40;
  253. power_state = FW_PWR_STATE_ACTIVE;
  254. } else {
  255. if (bt_ctrl_lps) {
  256. byte5 = btc_ops->btc_get_lps_val(rtlpriv);
  257. power_state = btc_ops->btc_get_rpwm_val(rtlpriv);
  258. if ((rlbm == 2) && (byte5 & BIT(4))) {
  259. /* Keep awake interval to 1 to prevent from
  260. * decreasing coex performance
  261. */
  262. awake_intvl = 2;
  263. rlbm = 2;
  264. }
  265. } else {
  266. byte5 = 0x40;
  267. power_state = FW_PWR_STATE_RF_OFF;
  268. }
  269. }
  270. SET_H2CCMD_PWRMODE_PARM_MODE(u1_h2c_set_pwrmode, ((mode) ? 1 : 0));
  271. SET_H2CCMD_PWRMODE_PARM_RLBM(u1_h2c_set_pwrmode, rlbm);
  272. SET_H2CCMD_PWRMODE_PARM_SMART_PS(u1_h2c_set_pwrmode,
  273. bt_ctrl_lps ? 0 : ppsc->smart_ps);
  274. SET_H2CCMD_PWRMODE_PARM_AWAKE_INTERVAL(u1_h2c_set_pwrmode,
  275. awake_intvl);
  276. SET_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(u1_h2c_set_pwrmode, 0);
  277. SET_H2CCMD_PWRMODE_PARM_PWR_STATE(u1_h2c_set_pwrmode, power_state);
  278. SET_H2CCMD_PWRMODE_PARM_BYTE5(u1_h2c_set_pwrmode, byte5);
  279. RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
  280. "rtl92c_set_fw_pwrmode(): u1_h2c_set_pwrmode\n",
  281. u1_h2c_set_pwrmode, H2C_PWEMODE_LENGTH);
  282. if (rtlpriv->cfg->ops->get_btc_status())
  283. btc_ops->btc_record_pwr_mode(rtlpriv, u1_h2c_set_pwrmode,
  284. H2C_PWEMODE_LENGTH);
  285. rtl8723be_fill_h2c_cmd(hw, H2C_8723B_SETPWRMODE, H2C_PWEMODE_LENGTH,
  286. u1_h2c_set_pwrmode);
  287. }
  288. void rtl8723be_set_fw_media_status_rpt_cmd(struct ieee80211_hw *hw, u8 mstatus)
  289. {
  290. u8 parm[3] = { 0, 0, 0 };
  291. /* parm[0]: bit0=0-->Disconnect, bit0=1-->Connect
  292. * bit1=0-->update Media Status to MACID
  293. * bit1=1-->update Media Status from MACID to MACID_End
  294. * parm[1]: MACID, if this is INFRA_STA, MacID = 0
  295. * parm[2]: MACID_End
  296. */
  297. SET_H2CCMD_MSRRPT_PARM_OPMODE(parm, mstatus);
  298. SET_H2CCMD_MSRRPT_PARM_MACID_IND(parm, 0);
  299. rtl8723be_fill_h2c_cmd(hw, H2C_8723B_MSRRPT, 3, parm);
  300. }
  301. #define BEACON_PG 0 /* ->1 */
  302. #define PSPOLL_PG 2
  303. #define NULL_PG 3
  304. #define PROBERSP_PG 4 /* ->5 */
  305. #define QOS_NULL_PG 6
  306. #define BT_QOS_NULL_PG 7
  307. #define TOTAL_RESERVED_PKT_LEN 1024 /* can be up to 1280 (tx_bndy=245) */
  308. static u8 reserved_page_packet[TOTAL_RESERVED_PKT_LEN] = {
  309. /* page 0 beacon */
  310. 0x80, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF,
  311. 0xFF, 0xFF, 0x00, 0xE0, 0x4C, 0x02, 0xB1, 0x78,
  312. 0xEC, 0x1A, 0x59, 0x0B, 0xAD, 0xD4, 0x20, 0x00,
  313. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  314. 0x64, 0x00, 0x10, 0x04, 0x00, 0x05, 0x54, 0x65,
  315. 0x73, 0x74, 0x32, 0x01, 0x08, 0x82, 0x84, 0x0B,
  316. 0x16, 0x24, 0x30, 0x48, 0x6C, 0x03, 0x01, 0x06,
  317. 0x06, 0x02, 0x00, 0x00, 0x2A, 0x01, 0x02, 0x32,
  318. 0x04, 0x0C, 0x12, 0x18, 0x60, 0x2D, 0x1A, 0x6C,
  319. 0x09, 0x03, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00,
  320. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  321. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  322. 0x00, 0x3D, 0x00, 0xDD, 0x07, 0x00, 0xE0, 0x4C,
  323. 0x02, 0x02, 0x00, 0x00, 0xDD, 0x18, 0x00, 0x50,
  324. 0xF2, 0x01, 0x01, 0x00, 0x00, 0x50, 0xF2, 0x04,
  325. 0x01, 0x00, 0x00, 0x50, 0xF2, 0x04, 0x01, 0x00,
  326. /* page 1 beacon */
  327. 0x00, 0x50, 0xF2, 0x02, 0x00, 0x00, 0x00, 0x00,
  328. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  329. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  330. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  331. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  332. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  333. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  334. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  335. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  336. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  337. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  338. 0x10, 0x00, 0x28, 0x8C, 0x00, 0x12, 0x00, 0x00,
  339. 0x00, 0x00, 0x00, 0x00, 0x00, 0x81, 0x00, 0x00,
  340. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  341. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  342. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  343. /* page 2 ps-poll */
  344. 0xA4, 0x10, 0x01, 0xC0, 0xEC, 0x1A, 0x59, 0x0B,
  345. 0xAD, 0xD4, 0x00, 0xE0, 0x4C, 0x02, 0xB1, 0x78,
  346. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  347. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  348. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  349. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  350. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  351. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  352. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  353. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  354. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  355. 0x18, 0x00, 0x28, 0x8C, 0x00, 0x12, 0x00, 0x00,
  356. 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
  357. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  358. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  359. 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  360. /* page 3 null */
  361. 0x48, 0x01, 0x00, 0x00, 0xEC, 0x1A, 0x59, 0x0B,
  362. 0xAD, 0xD4, 0x00, 0xE0, 0x4C, 0x02, 0xB1, 0x78,
  363. 0xEC, 0x1A, 0x59, 0x0B, 0xAD, 0xD4, 0x00, 0x00,
  364. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  365. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  366. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  367. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  368. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  369. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  370. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  371. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  372. 0x72, 0x00, 0x28, 0x8C, 0x00, 0x12, 0x00, 0x00,
  373. 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
  374. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  375. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  376. 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  377. /* page 4 probe_resp */
  378. 0x50, 0x00, 0x00, 0x00, 0x00, 0x40, 0x10, 0x10,
  379. 0x00, 0x03, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
  380. 0x00, 0x40, 0x10, 0x10, 0x00, 0x03, 0x00, 0x00,
  381. 0x9E, 0x46, 0x15, 0x32, 0x27, 0xF2, 0x2D, 0x00,
  382. 0x64, 0x00, 0x00, 0x04, 0x00, 0x0C, 0x6C, 0x69,
  383. 0x6E, 0x6B, 0x73, 0x79, 0x73, 0x5F, 0x77, 0x6C,
  384. 0x61, 0x6E, 0x01, 0x04, 0x82, 0x84, 0x8B, 0x96,
  385. 0x03, 0x01, 0x01, 0x06, 0x02, 0x00, 0x00, 0x2A,
  386. 0x01, 0x00, 0x32, 0x08, 0x24, 0x30, 0x48, 0x6C,
  387. 0x0C, 0x12, 0x18, 0x60, 0x2D, 0x1A, 0x6C, 0x18,
  388. 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  389. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  390. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  391. 0x3D, 0x00, 0xDD, 0x06, 0x00, 0xE0, 0x4C, 0x02,
  392. 0x01, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  393. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  394. /* page 5 probe_resp */
  395. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  396. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  397. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  398. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  399. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  400. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  401. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  402. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  403. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  404. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  405. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  406. 0x1A, 0x00, 0x28, 0x8C, 0x00, 0x12, 0x00, 0x00,
  407. 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
  408. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  409. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  410. 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  411. /* page 6 qos null data */
  412. 0xC8, 0x01, 0x00, 0x00, 0x84, 0xC9, 0xB2, 0xA7,
  413. 0xB3, 0x6E, 0x00, 0xE0, 0x4C, 0x02, 0x51, 0x02,
  414. 0x84, 0xC9, 0xB2, 0xA7, 0xB3, 0x6E, 0x00, 0x00,
  415. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  416. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  417. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  418. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  419. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  420. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  421. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  422. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  423. 0x1A, 0x00, 0x28, 0x8C, 0x00, 0x12, 0x00, 0x00,
  424. 0x00, 0x00, 0x80, 0x00, 0x00, 0x01, 0x00, 0x00,
  425. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  426. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  427. 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  428. /* page 7 BT-qos null data */
  429. 0xC8, 0x01, 0x00, 0x00, 0x84, 0xC9, 0xB2, 0xA7,
  430. 0xB3, 0x6E, 0x00, 0xE0, 0x4C, 0x02, 0x51, 0x02,
  431. 0x84, 0xC9, 0xB2, 0xA7, 0xB3, 0x6E, 0x00, 0x00,
  432. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  433. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  434. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  435. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  436. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  437. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  438. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  439. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  440. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  441. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  442. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  443. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  444. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  445. };
  446. void rtl8723be_set_fw_rsvdpagepkt(struct ieee80211_hw *hw,
  447. bool b_dl_finished)
  448. {
  449. struct rtl_priv *rtlpriv = rtl_priv(hw);
  450. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  451. struct sk_buff *skb = NULL;
  452. u32 totalpacketlen;
  453. bool rtstatus;
  454. u8 u1rsvdpageloc[5] = { 0 };
  455. bool b_dlok = false;
  456. u8 *beacon;
  457. u8 *p_pspoll;
  458. u8 *nullfunc;
  459. u8 *p_probersp;
  460. u8 *qosnull;
  461. u8 *btqosnull;
  462. /*---------------------------------------------------------
  463. * (1) beacon
  464. *---------------------------------------------------------
  465. */
  466. beacon = &reserved_page_packet[BEACON_PG * 128];
  467. SET_80211_HDR_ADDRESS2(beacon, mac->mac_addr);
  468. SET_80211_HDR_ADDRESS3(beacon, mac->bssid);
  469. /*-------------------------------------------------------
  470. * (2) ps-poll
  471. *-------------------------------------------------------
  472. */
  473. p_pspoll = &reserved_page_packet[PSPOLL_PG * 128];
  474. SET_80211_PS_POLL_AID(p_pspoll, (mac->assoc_id | 0xc000));
  475. SET_80211_PS_POLL_BSSID(p_pspoll, mac->bssid);
  476. SET_80211_PS_POLL_TA(p_pspoll, mac->mac_addr);
  477. SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(u1rsvdpageloc, PSPOLL_PG);
  478. /*--------------------------------------------------------
  479. * (3) null data
  480. *--------------------------------------------------------
  481. */
  482. nullfunc = &reserved_page_packet[NULL_PG * 128];
  483. SET_80211_HDR_ADDRESS1(nullfunc, mac->bssid);
  484. SET_80211_HDR_ADDRESS2(nullfunc, mac->mac_addr);
  485. SET_80211_HDR_ADDRESS3(nullfunc, mac->bssid);
  486. SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(u1rsvdpageloc, NULL_PG);
  487. /*---------------------------------------------------------
  488. * (4) probe response
  489. *---------------------------------------------------------
  490. */
  491. p_probersp = &reserved_page_packet[PROBERSP_PG * 128];
  492. SET_80211_HDR_ADDRESS1(p_probersp, mac->bssid);
  493. SET_80211_HDR_ADDRESS2(p_probersp, mac->mac_addr);
  494. SET_80211_HDR_ADDRESS3(p_probersp, mac->bssid);
  495. SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(u1rsvdpageloc, PROBERSP_PG);
  496. /*---------------------------------------------------------
  497. * (5) QoS Null
  498. *---------------------------------------------------------
  499. */
  500. qosnull = &reserved_page_packet[QOS_NULL_PG * 128];
  501. SET_80211_HDR_ADDRESS1(qosnull, mac->bssid);
  502. SET_80211_HDR_ADDRESS2(qosnull, mac->mac_addr);
  503. SET_80211_HDR_ADDRESS3(qosnull, mac->bssid);
  504. SET_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(u1rsvdpageloc, QOS_NULL_PG);
  505. /*---------------------------------------------------------
  506. * (5) QoS Null
  507. *---------------------------------------------------------
  508. */
  509. btqosnull = &reserved_page_packet[BT_QOS_NULL_PG * 128];
  510. SET_80211_HDR_ADDRESS1(btqosnull, mac->bssid);
  511. SET_80211_HDR_ADDRESS2(btqosnull, mac->mac_addr);
  512. SET_80211_HDR_ADDRESS3(btqosnull, mac->bssid);
  513. SET_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(u1rsvdpageloc, BT_QOS_NULL_PG);
  514. totalpacketlen = TOTAL_RESERVED_PKT_LEN;
  515. RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD,
  516. "rtl8723be_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL\n",
  517. &reserved_page_packet[0], totalpacketlen);
  518. RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
  519. "rtl8723be_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL\n",
  520. u1rsvdpageloc, sizeof(u1rsvdpageloc));
  521. skb = dev_alloc_skb(totalpacketlen);
  522. if (!skb)
  523. return;
  524. skb_put_data(skb, &reserved_page_packet, totalpacketlen);
  525. rtstatus = rtl_cmd_send_packet(hw, skb);
  526. if (rtstatus)
  527. b_dlok = true;
  528. if (b_dlok) {
  529. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  530. "Set RSVD page location to Fw.\n");
  531. RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG, "H2C_RSVDPAGE:\n",
  532. u1rsvdpageloc, sizeof(u1rsvdpageloc));
  533. rtl8723be_fill_h2c_cmd(hw, H2C_8723B_RSVDPAGE,
  534. sizeof(u1rsvdpageloc), u1rsvdpageloc);
  535. } else
  536. RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
  537. "Set RSVD page location to Fw FAIL!!!!!!.\n");
  538. }
  539. /*Should check FW support p2p or not.*/
  540. static void rtl8723be_set_p2p_ctw_period_cmd(struct ieee80211_hw *hw,
  541. u8 ctwindow)
  542. {
  543. u8 u1_ctwindow_period[1] = { ctwindow};
  544. rtl8723be_fill_h2c_cmd(hw, H2C_8723B_P2P_PS_CTW_CMD, 1,
  545. u1_ctwindow_period);
  546. }
  547. void rtl8723be_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw,
  548. u8 p2p_ps_state)
  549. {
  550. struct rtl_priv *rtlpriv = rtl_priv(hw);
  551. struct rtl_ps_ctl *rtlps = rtl_psc(rtl_priv(hw));
  552. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  553. struct rtl_p2p_ps_info *p2pinfo = &(rtlps->p2p_ps_info);
  554. struct p2p_ps_offload_t *p2p_ps_offload = &rtlhal->p2p_ps_offload;
  555. u8 i;
  556. u16 ctwindow;
  557. u32 start_time, tsf_low;
  558. switch (p2p_ps_state) {
  559. case P2P_PS_DISABLE:
  560. RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_DISABLE\n");
  561. memset(p2p_ps_offload, 0, sizeof(*p2p_ps_offload));
  562. break;
  563. case P2P_PS_ENABLE:
  564. RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_ENABLE\n");
  565. /* update CTWindow value. */
  566. if (p2pinfo->ctwindow > 0) {
  567. p2p_ps_offload->ctwindow_en = 1;
  568. ctwindow = p2pinfo->ctwindow;
  569. rtl8723be_set_p2p_ctw_period_cmd(hw, ctwindow);
  570. }
  571. /* hw only support 2 set of NoA */
  572. for (i = 0 ; i < p2pinfo->noa_num ; i++) {
  573. /* To control the register setting
  574. * for which NOA
  575. */
  576. rtl_write_byte(rtlpriv, 0x5cf, (i << 4));
  577. if (i == 0)
  578. p2p_ps_offload->noa0_en = 1;
  579. else
  580. p2p_ps_offload->noa1_en = 1;
  581. /* config P2P NoA Descriptor Register */
  582. rtl_write_dword(rtlpriv, 0x5E0,
  583. p2pinfo->noa_duration[i]);
  584. rtl_write_dword(rtlpriv, 0x5E4,
  585. p2pinfo->noa_interval[i]);
  586. /*Get Current TSF value */
  587. tsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
  588. start_time = p2pinfo->noa_start_time[i];
  589. if (p2pinfo->noa_count_type[i] != 1) {
  590. while (start_time <= (tsf_low + (50 * 1024))) {
  591. start_time += p2pinfo->noa_interval[i];
  592. if (p2pinfo->noa_count_type[i] != 255)
  593. p2pinfo->noa_count_type[i]--;
  594. }
  595. }
  596. rtl_write_dword(rtlpriv, 0x5E8, start_time);
  597. rtl_write_dword(rtlpriv, 0x5EC,
  598. p2pinfo->noa_count_type[i]);
  599. }
  600. if ((p2pinfo->opp_ps == 1) ||
  601. (p2pinfo->noa_num > 0)) {
  602. /* rst p2p circuit */
  603. rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, BIT(4));
  604. p2p_ps_offload->offload_en = 1;
  605. if (P2P_ROLE_GO == rtlpriv->mac80211.p2p) {
  606. p2p_ps_offload->role = 1;
  607. p2p_ps_offload->allstasleep = 0;
  608. } else {
  609. p2p_ps_offload->role = 0;
  610. }
  611. p2p_ps_offload->discovery = 0;
  612. }
  613. break;
  614. case P2P_PS_SCAN:
  615. RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_SCAN\n");
  616. p2p_ps_offload->discovery = 1;
  617. break;
  618. case P2P_PS_SCAN_DONE:
  619. RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_SCAN_DONE\n");
  620. p2p_ps_offload->discovery = 0;
  621. p2pinfo->p2p_ps_state = P2P_PS_ENABLE;
  622. break;
  623. default:
  624. break;
  625. }
  626. rtl8723be_fill_h2c_cmd(hw, H2C_8723B_P2P_PS_OFFLOAD, 1,
  627. (u8 *)p2p_ps_offload);
  628. }