dm.c 45 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313
  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2009-2012 Realtek Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * The full GNU General Public License is included in this distribution in the
  15. * file called LICENSE.
  16. *
  17. * Contact Information:
  18. * wlanfae <wlanfae@realtek.com>
  19. * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20. * Hsinchu 300, Taiwan.
  21. *
  22. * Larry Finger <Larry.Finger@lwfinger.net>
  23. *
  24. *****************************************************************************/
  25. #include "../wifi.h"
  26. #include "../base.h"
  27. #include "../core.h"
  28. #include "reg.h"
  29. #include "def.h"
  30. #include "phy.h"
  31. #include "dm.h"
  32. #include "fw.h"
  33. #define UNDEC_SM_PWDB entry_min_undec_sm_pwdb
  34. static const u32 ofdmswing_table[OFDM_TABLE_SIZE_92D] = {
  35. 0x7f8001fe, /* 0, +6.0dB */
  36. 0x788001e2, /* 1, +5.5dB */
  37. 0x71c001c7, /* 2, +5.0dB */
  38. 0x6b8001ae, /* 3, +4.5dB */
  39. 0x65400195, /* 4, +4.0dB */
  40. 0x5fc0017f, /* 5, +3.5dB */
  41. 0x5a400169, /* 6, +3.0dB */
  42. 0x55400155, /* 7, +2.5dB */
  43. 0x50800142, /* 8, +2.0dB */
  44. 0x4c000130, /* 9, +1.5dB */
  45. 0x47c0011f, /* 10, +1.0dB */
  46. 0x43c0010f, /* 11, +0.5dB */
  47. 0x40000100, /* 12, +0dB */
  48. 0x3c8000f2, /* 13, -0.5dB */
  49. 0x390000e4, /* 14, -1.0dB */
  50. 0x35c000d7, /* 15, -1.5dB */
  51. 0x32c000cb, /* 16, -2.0dB */
  52. 0x300000c0, /* 17, -2.5dB */
  53. 0x2d4000b5, /* 18, -3.0dB */
  54. 0x2ac000ab, /* 19, -3.5dB */
  55. 0x288000a2, /* 20, -4.0dB */
  56. 0x26000098, /* 21, -4.5dB */
  57. 0x24000090, /* 22, -5.0dB */
  58. 0x22000088, /* 23, -5.5dB */
  59. 0x20000080, /* 24, -6.0dB */
  60. 0x1e400079, /* 25, -6.5dB */
  61. 0x1c800072, /* 26, -7.0dB */
  62. 0x1b00006c, /* 27. -7.5dB */
  63. 0x19800066, /* 28, -8.0dB */
  64. 0x18000060, /* 29, -8.5dB */
  65. 0x16c0005b, /* 30, -9.0dB */
  66. 0x15800056, /* 31, -9.5dB */
  67. 0x14400051, /* 32, -10.0dB */
  68. 0x1300004c, /* 33, -10.5dB */
  69. 0x12000048, /* 34, -11.0dB */
  70. 0x11000044, /* 35, -11.5dB */
  71. 0x10000040, /* 36, -12.0dB */
  72. 0x0f00003c, /* 37, -12.5dB */
  73. 0x0e400039, /* 38, -13.0dB */
  74. 0x0d800036, /* 39, -13.5dB */
  75. 0x0cc00033, /* 40, -14.0dB */
  76. 0x0c000030, /* 41, -14.5dB */
  77. 0x0b40002d, /* 42, -15.0dB */
  78. };
  79. static const u8 cckswing_table_ch1ch13[CCK_TABLE_SIZE][8] = {
  80. {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */
  81. {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */
  82. {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB */
  83. {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB */
  84. {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */
  85. {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB */
  86. {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB */
  87. {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB */
  88. {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */
  89. {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB */
  90. {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */
  91. {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB */
  92. {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0dB */
  93. {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB */
  94. {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */
  95. {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB */
  96. {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */
  97. {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB */
  98. {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */
  99. {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB */
  100. {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB */
  101. {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB */
  102. {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB */
  103. {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB */
  104. {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB */
  105. {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB */
  106. {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB */
  107. {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB */
  108. {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB */
  109. {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB */
  110. {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB */
  111. {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB */
  112. {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB */
  113. };
  114. static const u8 cckswing_table_ch14[CCK_TABLE_SIZE][8] = {
  115. {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */
  116. {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */
  117. {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */
  118. {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB */
  119. {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */
  120. {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB */
  121. {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */
  122. {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */
  123. {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */
  124. {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB */
  125. {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */
  126. {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB */
  127. {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0dB */
  128. {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */
  129. {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */
  130. {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB */
  131. {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */
  132. {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB */
  133. {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */
  134. {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB */
  135. {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB */
  136. {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB */
  137. {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB */
  138. {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB */
  139. {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB */
  140. {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB */
  141. {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB */
  142. {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB */
  143. {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB */
  144. {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB */
  145. {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB */
  146. {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB */
  147. {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB */
  148. };
  149. static void rtl92d_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
  150. {
  151. u32 ret_value;
  152. struct rtl_priv *rtlpriv = rtl_priv(hw);
  153. struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
  154. unsigned long flag = 0;
  155. /* hold ofdm counter */
  156. rtl_set_bbreg(hw, ROFDM0_LSTF, BIT(31), 1); /* hold page C counter */
  157. rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(31), 1); /*hold page D counter */
  158. ret_value = rtl_get_bbreg(hw, ROFDM0_FRAMESYNC, MASKDWORD);
  159. falsealm_cnt->cnt_fast_fsync_fail = (ret_value & 0xffff);
  160. falsealm_cnt->cnt_sb_search_fail = ((ret_value & 0xffff0000) >> 16);
  161. ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD);
  162. falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16);
  163. ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD);
  164. falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff);
  165. falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);
  166. ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD);
  167. falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff);
  168. falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail +
  169. falsealm_cnt->cnt_rate_illegal +
  170. falsealm_cnt->cnt_crc8_fail +
  171. falsealm_cnt->cnt_mcs_fail +
  172. falsealm_cnt->cnt_fast_fsync_fail +
  173. falsealm_cnt->cnt_sb_search_fail;
  174. if (rtlpriv->rtlhal.current_bandtype != BAND_ON_5G) {
  175. /* hold cck counter */
  176. rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
  177. ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, MASKBYTE0);
  178. falsealm_cnt->cnt_cck_fail = ret_value;
  179. ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERUPPER, MASKBYTE3);
  180. falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8;
  181. rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
  182. } else {
  183. falsealm_cnt->cnt_cck_fail = 0;
  184. }
  185. /* reset false alarm counter registers */
  186. falsealm_cnt->cnt_all = falsealm_cnt->cnt_fast_fsync_fail +
  187. falsealm_cnt->cnt_sb_search_fail +
  188. falsealm_cnt->cnt_parity_fail +
  189. falsealm_cnt->cnt_rate_illegal +
  190. falsealm_cnt->cnt_crc8_fail +
  191. falsealm_cnt->cnt_mcs_fail +
  192. falsealm_cnt->cnt_cck_fail;
  193. rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 1);
  194. /* update ofdm counter */
  195. rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 0);
  196. /* update page C counter */
  197. rtl_set_bbreg(hw, ROFDM0_LSTF, BIT(31), 0);
  198. /* update page D counter */
  199. rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(31), 0);
  200. if (rtlpriv->rtlhal.current_bandtype != BAND_ON_5G) {
  201. /* reset cck counter */
  202. rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
  203. rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 0);
  204. /* enable cck counter */
  205. rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 2);
  206. rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
  207. }
  208. RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
  209. "Cnt_Fast_Fsync_fail = %x, Cnt_SB_Search_fail = %x\n",
  210. falsealm_cnt->cnt_fast_fsync_fail,
  211. falsealm_cnt->cnt_sb_search_fail);
  212. RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
  213. "Cnt_Parity_Fail = %x, Cnt_Rate_Illegal = %x, Cnt_Crc8_fail = %x, Cnt_Mcs_fail = %x\n",
  214. falsealm_cnt->cnt_parity_fail,
  215. falsealm_cnt->cnt_rate_illegal,
  216. falsealm_cnt->cnt_crc8_fail,
  217. falsealm_cnt->cnt_mcs_fail);
  218. RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
  219. "Cnt_Ofdm_fail = %x, Cnt_Cck_fail = %x, Cnt_all = %x\n",
  220. falsealm_cnt->cnt_ofdm_fail,
  221. falsealm_cnt->cnt_cck_fail,
  222. falsealm_cnt->cnt_all);
  223. }
  224. static void rtl92d_dm_find_minimum_rssi(struct ieee80211_hw *hw)
  225. {
  226. struct rtl_priv *rtlpriv = rtl_priv(hw);
  227. struct dig_t *de_digtable = &rtlpriv->dm_digtable;
  228. struct rtl_mac *mac = rtl_mac(rtlpriv);
  229. /* Determine the minimum RSSI */
  230. if ((mac->link_state < MAC80211_LINKED) &&
  231. (rtlpriv->dm.UNDEC_SM_PWDB == 0)) {
  232. de_digtable->min_undec_pwdb_for_dm = 0;
  233. RT_TRACE(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD,
  234. "Not connected to any\n");
  235. }
  236. if (mac->link_state >= MAC80211_LINKED) {
  237. if (mac->opmode == NL80211_IFTYPE_AP ||
  238. mac->opmode == NL80211_IFTYPE_ADHOC) {
  239. de_digtable->min_undec_pwdb_for_dm =
  240. rtlpriv->dm.UNDEC_SM_PWDB;
  241. RT_TRACE(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD,
  242. "AP Client PWDB = 0x%lx\n",
  243. rtlpriv->dm.UNDEC_SM_PWDB);
  244. } else {
  245. de_digtable->min_undec_pwdb_for_dm =
  246. rtlpriv->dm.undec_sm_pwdb;
  247. RT_TRACE(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD,
  248. "STA Default Port PWDB = 0x%x\n",
  249. de_digtable->min_undec_pwdb_for_dm);
  250. }
  251. } else {
  252. de_digtable->min_undec_pwdb_for_dm = rtlpriv->dm.UNDEC_SM_PWDB;
  253. RT_TRACE(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD,
  254. "AP Ext Port or disconnect PWDB = 0x%x\n",
  255. de_digtable->min_undec_pwdb_for_dm);
  256. }
  257. RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, "MinUndecoratedPWDBForDM =%d\n",
  258. de_digtable->min_undec_pwdb_for_dm);
  259. }
  260. static void rtl92d_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
  261. {
  262. struct rtl_priv *rtlpriv = rtl_priv(hw);
  263. struct dig_t *de_digtable = &rtlpriv->dm_digtable;
  264. unsigned long flag = 0;
  265. if (de_digtable->cursta_cstate == DIG_STA_CONNECT) {
  266. if (de_digtable->pre_cck_pd_state == CCK_PD_STAGE_LOWRSSI) {
  267. if (de_digtable->min_undec_pwdb_for_dm <= 25)
  268. de_digtable->cur_cck_pd_state =
  269. CCK_PD_STAGE_LOWRSSI;
  270. else
  271. de_digtable->cur_cck_pd_state =
  272. CCK_PD_STAGE_HIGHRSSI;
  273. } else {
  274. if (de_digtable->min_undec_pwdb_for_dm <= 20)
  275. de_digtable->cur_cck_pd_state =
  276. CCK_PD_STAGE_LOWRSSI;
  277. else
  278. de_digtable->cur_cck_pd_state =
  279. CCK_PD_STAGE_HIGHRSSI;
  280. }
  281. } else {
  282. de_digtable->cur_cck_pd_state = CCK_PD_STAGE_LOWRSSI;
  283. }
  284. if (de_digtable->pre_cck_pd_state != de_digtable->cur_cck_pd_state) {
  285. if (de_digtable->cur_cck_pd_state == CCK_PD_STAGE_LOWRSSI) {
  286. rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
  287. rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x83);
  288. rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
  289. } else {
  290. rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
  291. rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
  292. rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
  293. }
  294. de_digtable->pre_cck_pd_state = de_digtable->cur_cck_pd_state;
  295. }
  296. RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, "CurSTAConnectState=%s\n",
  297. de_digtable->cursta_cstate == DIG_STA_CONNECT ?
  298. "DIG_STA_CONNECT " : "DIG_STA_DISCONNECT");
  299. RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, "CCKPDStage=%s\n",
  300. de_digtable->cur_cck_pd_state == CCK_PD_STAGE_LOWRSSI ?
  301. "Low RSSI " : "High RSSI ");
  302. RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, "is92d single phy =%x\n",
  303. IS_92D_SINGLEPHY(rtlpriv->rtlhal.version));
  304. }
  305. void rtl92d_dm_write_dig(struct ieee80211_hw *hw)
  306. {
  307. struct rtl_priv *rtlpriv = rtl_priv(hw);
  308. struct dig_t *de_digtable = &rtlpriv->dm_digtable;
  309. RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
  310. "cur_igvalue = 0x%x, pre_igvalue = 0x%x, back_val = %d\n",
  311. de_digtable->cur_igvalue, de_digtable->pre_igvalue,
  312. de_digtable->back_val);
  313. if (de_digtable->dig_enable_flag == false) {
  314. RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, "DIG is disabled\n");
  315. de_digtable->pre_igvalue = 0x17;
  316. return;
  317. }
  318. if (de_digtable->pre_igvalue != de_digtable->cur_igvalue) {
  319. rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f,
  320. de_digtable->cur_igvalue);
  321. rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, 0x7f,
  322. de_digtable->cur_igvalue);
  323. de_digtable->pre_igvalue = de_digtable->cur_igvalue;
  324. }
  325. }
  326. static void rtl92d_early_mode_enabled(struct rtl_priv *rtlpriv)
  327. {
  328. struct dig_t *de_digtable = &rtlpriv->dm_digtable;
  329. if ((rtlpriv->mac80211.link_state >= MAC80211_LINKED) &&
  330. (rtlpriv->mac80211.vendor == PEER_CISCO)) {
  331. RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, "IOT_PEER = CISCO\n");
  332. if (de_digtable->last_min_undec_pwdb_for_dm >= 50
  333. && de_digtable->min_undec_pwdb_for_dm < 50) {
  334. rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL, 0x00);
  335. RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
  336. "Early Mode Off\n");
  337. } else if (de_digtable->last_min_undec_pwdb_for_dm <= 55 &&
  338. de_digtable->min_undec_pwdb_for_dm > 55) {
  339. rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL, 0x0f);
  340. RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
  341. "Early Mode On\n");
  342. }
  343. } else if (!(rtl_read_byte(rtlpriv, REG_EARLY_MODE_CONTROL) & 0xf)) {
  344. rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL, 0x0f);
  345. RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, "Early Mode On\n");
  346. }
  347. }
  348. static void rtl92d_dm_dig(struct ieee80211_hw *hw)
  349. {
  350. struct rtl_priv *rtlpriv = rtl_priv(hw);
  351. struct dig_t *de_digtable = &rtlpriv->dm_digtable;
  352. u8 value_igi = de_digtable->cur_igvalue;
  353. struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
  354. RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, "==>\n");
  355. if (rtlpriv->rtlhal.earlymode_enable) {
  356. rtl92d_early_mode_enabled(rtlpriv);
  357. de_digtable->last_min_undec_pwdb_for_dm =
  358. de_digtable->min_undec_pwdb_for_dm;
  359. }
  360. if (!rtlpriv->dm.dm_initialgain_enable)
  361. return;
  362. /* because we will send data pkt when scanning
  363. * this will cause some ap like gear-3700 wep TP
  364. * lower if we return here, this is the diff of
  365. * mac80211 driver vs ieee80211 driver */
  366. /* if (rtlpriv->mac80211.act_scanning)
  367. * return; */
  368. /* Not STA mode return tmp */
  369. if (rtlpriv->mac80211.opmode != NL80211_IFTYPE_STATION)
  370. return;
  371. RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, "progress\n");
  372. /* Decide the current status and if modify initial gain or not */
  373. if (rtlpriv->mac80211.link_state >= MAC80211_LINKED)
  374. de_digtable->cursta_cstate = DIG_STA_CONNECT;
  375. else
  376. de_digtable->cursta_cstate = DIG_STA_DISCONNECT;
  377. /* adjust initial gain according to false alarm counter */
  378. if (falsealm_cnt->cnt_all < DM_DIG_FA_TH0)
  379. value_igi--;
  380. else if (falsealm_cnt->cnt_all < DM_DIG_FA_TH1)
  381. value_igi += 0;
  382. else if (falsealm_cnt->cnt_all < DM_DIG_FA_TH2)
  383. value_igi++;
  384. else if (falsealm_cnt->cnt_all >= DM_DIG_FA_TH2)
  385. value_igi += 2;
  386. RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
  387. "dm_DIG() Before: large_fa_hit=%d, forbidden_igi=%x\n",
  388. de_digtable->large_fa_hit, de_digtable->forbidden_igi);
  389. RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
  390. "dm_DIG() Before: Recover_cnt=%d, rx_gain_min=%x\n",
  391. de_digtable->recover_cnt, de_digtable->rx_gain_min);
  392. /* deal with abnormally large false alarm */
  393. if (falsealm_cnt->cnt_all > 10000) {
  394. RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
  395. "dm_DIG(): Abnormally false alarm case\n");
  396. de_digtable->large_fa_hit++;
  397. if (de_digtable->forbidden_igi < de_digtable->cur_igvalue) {
  398. de_digtable->forbidden_igi = de_digtable->cur_igvalue;
  399. de_digtable->large_fa_hit = 1;
  400. }
  401. if (de_digtable->large_fa_hit >= 3) {
  402. if ((de_digtable->forbidden_igi + 1) > DM_DIG_MAX)
  403. de_digtable->rx_gain_min = DM_DIG_MAX;
  404. else
  405. de_digtable->rx_gain_min =
  406. (de_digtable->forbidden_igi + 1);
  407. de_digtable->recover_cnt = 3600; /* 3600=2hr */
  408. }
  409. } else {
  410. /* Recovery mechanism for IGI lower bound */
  411. if (de_digtable->recover_cnt != 0) {
  412. de_digtable->recover_cnt--;
  413. } else {
  414. if (de_digtable->large_fa_hit == 0) {
  415. if ((de_digtable->forbidden_igi - 1) <
  416. DM_DIG_FA_LOWER) {
  417. de_digtable->forbidden_igi =
  418. DM_DIG_FA_LOWER;
  419. de_digtable->rx_gain_min =
  420. DM_DIG_FA_LOWER;
  421. } else {
  422. de_digtable->forbidden_igi--;
  423. de_digtable->rx_gain_min =
  424. (de_digtable->forbidden_igi + 1);
  425. }
  426. } else if (de_digtable->large_fa_hit == 3) {
  427. de_digtable->large_fa_hit = 0;
  428. }
  429. }
  430. }
  431. RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
  432. "dm_DIG() After: large_fa_hit=%d, forbidden_igi=%x\n",
  433. de_digtable->large_fa_hit, de_digtable->forbidden_igi);
  434. RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
  435. "dm_DIG() After: recover_cnt=%d, rx_gain_min=%x\n",
  436. de_digtable->recover_cnt, de_digtable->rx_gain_min);
  437. if (value_igi > DM_DIG_MAX)
  438. value_igi = DM_DIG_MAX;
  439. else if (value_igi < de_digtable->rx_gain_min)
  440. value_igi = de_digtable->rx_gain_min;
  441. de_digtable->cur_igvalue = value_igi;
  442. rtl92d_dm_write_dig(hw);
  443. if (rtlpriv->rtlhal.current_bandtype != BAND_ON_5G)
  444. rtl92d_dm_cck_packet_detection_thresh(hw);
  445. RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, "<<==\n");
  446. }
  447. static void rtl92d_dm_init_dynamic_txpower(struct ieee80211_hw *hw)
  448. {
  449. struct rtl_priv *rtlpriv = rtl_priv(hw);
  450. rtlpriv->dm.dynamic_txpower_enable = true;
  451. rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
  452. rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
  453. }
  454. static void rtl92d_dm_dynamic_txpower(struct ieee80211_hw *hw)
  455. {
  456. struct rtl_priv *rtlpriv = rtl_priv(hw);
  457. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  458. struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
  459. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  460. long undec_sm_pwdb;
  461. if ((!rtlpriv->dm.dynamic_txpower_enable)
  462. || rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) {
  463. rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
  464. return;
  465. }
  466. if ((mac->link_state < MAC80211_LINKED) &&
  467. (rtlpriv->dm.UNDEC_SM_PWDB == 0)) {
  468. RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
  469. "Not connected to any\n");
  470. rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
  471. rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
  472. return;
  473. }
  474. if (mac->link_state >= MAC80211_LINKED) {
  475. if (mac->opmode == NL80211_IFTYPE_ADHOC) {
  476. undec_sm_pwdb =
  477. rtlpriv->dm.UNDEC_SM_PWDB;
  478. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  479. "IBSS Client PWDB = 0x%lx\n",
  480. undec_sm_pwdb);
  481. } else {
  482. undec_sm_pwdb =
  483. rtlpriv->dm.undec_sm_pwdb;
  484. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  485. "STA Default Port PWDB = 0x%lx\n",
  486. undec_sm_pwdb);
  487. }
  488. } else {
  489. undec_sm_pwdb =
  490. rtlpriv->dm.UNDEC_SM_PWDB;
  491. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  492. "AP Ext Port PWDB = 0x%lx\n",
  493. undec_sm_pwdb);
  494. }
  495. if (rtlhal->current_bandtype == BAND_ON_5G) {
  496. if (undec_sm_pwdb >= 0x33) {
  497. rtlpriv->dm.dynamic_txhighpower_lvl =
  498. TXHIGHPWRLEVEL_LEVEL2;
  499. RT_TRACE(rtlpriv, COMP_HIPWR, DBG_LOUD,
  500. "5G:TxHighPwrLevel_Level2 (TxPwr=0x0)\n");
  501. } else if ((undec_sm_pwdb < 0x33)
  502. && (undec_sm_pwdb >= 0x2b)) {
  503. rtlpriv->dm.dynamic_txhighpower_lvl =
  504. TXHIGHPWRLEVEL_LEVEL1;
  505. RT_TRACE(rtlpriv, COMP_HIPWR, DBG_LOUD,
  506. "5G:TxHighPwrLevel_Level1 (TxPwr=0x10)\n");
  507. } else if (undec_sm_pwdb < 0x2b) {
  508. rtlpriv->dm.dynamic_txhighpower_lvl =
  509. TXHIGHPWRLEVEL_NORMAL;
  510. RT_TRACE(rtlpriv, COMP_HIPWR, DBG_LOUD,
  511. "5G:TxHighPwrLevel_Normal\n");
  512. }
  513. } else {
  514. if (undec_sm_pwdb >=
  515. TX_POWER_NEAR_FIELD_THRESH_LVL2) {
  516. rtlpriv->dm.dynamic_txhighpower_lvl =
  517. TXHIGHPWRLEVEL_LEVEL2;
  518. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  519. "TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x0)\n");
  520. } else
  521. if ((undec_sm_pwdb <
  522. (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3))
  523. && (undec_sm_pwdb >=
  524. TX_POWER_NEAR_FIELD_THRESH_LVL1)) {
  525. rtlpriv->dm.dynamic_txhighpower_lvl =
  526. TXHIGHPWRLEVEL_LEVEL1;
  527. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  528. "TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x10)\n");
  529. } else if (undec_sm_pwdb <
  530. (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) {
  531. rtlpriv->dm.dynamic_txhighpower_lvl =
  532. TXHIGHPWRLEVEL_NORMAL;
  533. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  534. "TXHIGHPWRLEVEL_NORMAL\n");
  535. }
  536. }
  537. if ((rtlpriv->dm.dynamic_txhighpower_lvl != rtlpriv->dm.last_dtp_lvl)) {
  538. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  539. "PHY_SetTxPowerLevel8192S() Channel = %d\n",
  540. rtlphy->current_channel);
  541. rtl92d_phy_set_txpower_level(hw, rtlphy->current_channel);
  542. }
  543. rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl;
  544. }
  545. static void rtl92d_dm_pwdb_monitor(struct ieee80211_hw *hw)
  546. {
  547. struct rtl_priv *rtlpriv = rtl_priv(hw);
  548. /* AP & ADHOC & MESH will return tmp */
  549. if (rtlpriv->mac80211.opmode != NL80211_IFTYPE_STATION)
  550. return;
  551. /* Indicate Rx signal strength to FW. */
  552. if (rtlpriv->dm.useramask) {
  553. u32 temp = rtlpriv->dm.undec_sm_pwdb;
  554. temp <<= 16;
  555. temp |= 0x100;
  556. /* fw v12 cmdid 5:use max macid ,for nic ,
  557. * default macid is 0 ,max macid is 1 */
  558. rtl92d_fill_h2c_cmd(hw, H2C_RSSI_REPORT, 3, (u8 *) (&temp));
  559. } else {
  560. rtl_write_byte(rtlpriv, 0x4fe,
  561. (u8) rtlpriv->dm.undec_sm_pwdb);
  562. }
  563. }
  564. void rtl92d_dm_init_edca_turbo(struct ieee80211_hw *hw)
  565. {
  566. struct rtl_priv *rtlpriv = rtl_priv(hw);
  567. rtlpriv->dm.current_turbo_edca = false;
  568. rtlpriv->dm.is_any_nonbepkts = false;
  569. rtlpriv->dm.is_cur_rdlstate = false;
  570. }
  571. static void rtl92d_dm_check_edca_turbo(struct ieee80211_hw *hw)
  572. {
  573. struct rtl_priv *rtlpriv = rtl_priv(hw);
  574. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  575. static u64 last_txok_cnt;
  576. static u64 last_rxok_cnt;
  577. u64 cur_txok_cnt;
  578. u64 cur_rxok_cnt;
  579. u32 edca_be_ul = 0x5ea42b;
  580. u32 edca_be_dl = 0x5ea42b;
  581. if (mac->link_state != MAC80211_LINKED) {
  582. rtlpriv->dm.current_turbo_edca = false;
  583. goto exit;
  584. }
  585. /* Enable BEQ TxOP limit configuration in wireless G-mode. */
  586. /* To check whether we shall force turn on TXOP configuration. */
  587. if ((!rtlpriv->dm.disable_framebursting) &&
  588. (rtlpriv->sec.pairwise_enc_algorithm == WEP40_ENCRYPTION ||
  589. rtlpriv->sec.pairwise_enc_algorithm == WEP104_ENCRYPTION ||
  590. rtlpriv->sec.pairwise_enc_algorithm == TKIP_ENCRYPTION)) {
  591. /* Force TxOP limit to 0x005e for UL. */
  592. if (!(edca_be_ul & 0xffff0000))
  593. edca_be_ul |= 0x005e0000;
  594. /* Force TxOP limit to 0x005e for DL. */
  595. if (!(edca_be_dl & 0xffff0000))
  596. edca_be_dl |= 0x005e0000;
  597. }
  598. if ((!rtlpriv->dm.is_any_nonbepkts) &&
  599. (!rtlpriv->dm.disable_framebursting)) {
  600. cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt;
  601. cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt;
  602. if (cur_rxok_cnt > 4 * cur_txok_cnt) {
  603. if (!rtlpriv->dm.is_cur_rdlstate ||
  604. !rtlpriv->dm.current_turbo_edca) {
  605. rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM,
  606. edca_be_dl);
  607. rtlpriv->dm.is_cur_rdlstate = true;
  608. }
  609. } else {
  610. if (rtlpriv->dm.is_cur_rdlstate ||
  611. !rtlpriv->dm.current_turbo_edca) {
  612. rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM,
  613. edca_be_ul);
  614. rtlpriv->dm.is_cur_rdlstate = false;
  615. }
  616. }
  617. rtlpriv->dm.current_turbo_edca = true;
  618. } else {
  619. if (rtlpriv->dm.current_turbo_edca) {
  620. u8 tmp = AC0_BE;
  621. rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
  622. &tmp);
  623. rtlpriv->dm.current_turbo_edca = false;
  624. }
  625. }
  626. exit:
  627. rtlpriv->dm.is_any_nonbepkts = false;
  628. last_txok_cnt = rtlpriv->stats.txbytesunicast;
  629. last_rxok_cnt = rtlpriv->stats.rxbytesunicast;
  630. }
  631. static void rtl92d_dm_rxgain_tracking_thermalmeter(struct ieee80211_hw *hw)
  632. {
  633. struct rtl_priv *rtlpriv = rtl_priv(hw);
  634. u8 index_mapping[RX_INDEX_MAPPING_NUM] = {
  635. 0x0f, 0x0f, 0x0d, 0x0c, 0x0b,
  636. 0x0a, 0x09, 0x08, 0x07, 0x06,
  637. 0x05, 0x04, 0x04, 0x03, 0x02
  638. };
  639. int i;
  640. u32 u4tmp;
  641. u4tmp = (index_mapping[(rtlpriv->efuse.eeprom_thermalmeter -
  642. rtlpriv->dm.thermalvalue_rxgain)]) << 12;
  643. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  644. "===> Rx Gain %x\n", u4tmp);
  645. for (i = RF90_PATH_A; i < rtlpriv->phy.num_total_rfpath; i++)
  646. rtl_set_rfreg(hw, i, 0x3C, RFREG_OFFSET_MASK,
  647. (rtlpriv->phy.reg_rf3c[i] & (~(0xF000))) | u4tmp);
  648. }
  649. static void rtl92d_bandtype_2_4G(struct ieee80211_hw *hw, long *temp_cckg,
  650. u8 *cck_index_old)
  651. {
  652. struct rtl_priv *rtlpriv = rtl_priv(hw);
  653. int i;
  654. unsigned long flag = 0;
  655. long temp_cck;
  656. /* Query CCK default setting From 0xa24 */
  657. rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
  658. temp_cck = rtl_get_bbreg(hw, RCCK0_TXFILTER2,
  659. MASKDWORD) & MASKCCK;
  660. rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
  661. for (i = 0; i < CCK_TABLE_LENGTH; i++) {
  662. if (rtlpriv->dm.cck_inch14) {
  663. if (!memcmp((void *)&temp_cck,
  664. (void *)&cckswing_table_ch14[i][2], 4)) {
  665. *cck_index_old = (u8) i;
  666. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  667. "Initial reg0x%x = 0x%lx, cck_index=0x%x, ch 14 %d\n",
  668. RCCK0_TXFILTER2, temp_cck,
  669. *cck_index_old,
  670. rtlpriv->dm.cck_inch14);
  671. break;
  672. }
  673. } else {
  674. if (!memcmp((void *) &temp_cck,
  675. &cckswing_table_ch1ch13[i][2], 4)) {
  676. *cck_index_old = (u8) i;
  677. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  678. "Initial reg0x%x = 0x%lx, cck_index = 0x%x, ch14 %d\n",
  679. RCCK0_TXFILTER2, temp_cck,
  680. *cck_index_old,
  681. rtlpriv->dm.cck_inch14);
  682. break;
  683. }
  684. }
  685. }
  686. *temp_cckg = temp_cck;
  687. }
  688. static void rtl92d_bandtype_5G(struct rtl_hal *rtlhal, u8 *ofdm_index,
  689. bool *internal_pa, u8 thermalvalue, u8 delta,
  690. u8 rf, struct rtl_efuse *rtlefuse,
  691. struct rtl_priv *rtlpriv, struct rtl_phy *rtlphy,
  692. u8 index_mapping[5][INDEX_MAPPING_NUM],
  693. u8 index_mapping_pa[8][INDEX_MAPPING_NUM])
  694. {
  695. int i;
  696. u8 index;
  697. u8 offset = 0;
  698. for (i = 0; i < rf; i++) {
  699. if (rtlhal->macphymode == DUALMAC_DUALPHY &&
  700. rtlhal->interfaceindex == 1) /* MAC 1 5G */
  701. *internal_pa = rtlefuse->internal_pa_5g[1];
  702. else
  703. *internal_pa = rtlefuse->internal_pa_5g[i];
  704. if (*internal_pa) {
  705. if (rtlhal->interfaceindex == 1 || i == rf)
  706. offset = 4;
  707. else
  708. offset = 0;
  709. if (rtlphy->current_channel >= 100 &&
  710. rtlphy->current_channel <= 165)
  711. offset += 2;
  712. } else {
  713. if (rtlhal->interfaceindex == 1 || i == rf)
  714. offset = 2;
  715. else
  716. offset = 0;
  717. }
  718. if (thermalvalue > rtlefuse->eeprom_thermalmeter)
  719. offset++;
  720. if (*internal_pa) {
  721. if (delta > INDEX_MAPPING_NUM - 1)
  722. index = index_mapping_pa[offset]
  723. [INDEX_MAPPING_NUM - 1];
  724. else
  725. index =
  726. index_mapping_pa[offset][delta];
  727. } else {
  728. if (delta > INDEX_MAPPING_NUM - 1)
  729. index =
  730. index_mapping[offset][INDEX_MAPPING_NUM - 1];
  731. else
  732. index = index_mapping[offset][delta];
  733. }
  734. if (thermalvalue > rtlefuse->eeprom_thermalmeter) {
  735. if (*internal_pa && thermalvalue > 0x12) {
  736. ofdm_index[i] = rtlpriv->dm.ofdm_index[i] -
  737. ((delta / 2) * 3 + (delta % 2));
  738. } else {
  739. ofdm_index[i] -= index;
  740. }
  741. } else {
  742. ofdm_index[i] += index;
  743. }
  744. }
  745. }
  746. static void rtl92d_dm_txpower_tracking_callback_thermalmeter(
  747. struct ieee80211_hw *hw)
  748. {
  749. struct rtl_priv *rtlpriv = rtl_priv(hw);
  750. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  751. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  752. struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
  753. u8 thermalvalue, delta, delta_lck, delta_iqk, delta_rxgain;
  754. u8 offset, thermalvalue_avg_count = 0;
  755. u32 thermalvalue_avg = 0;
  756. bool internal_pa = false;
  757. long ele_a = 0, ele_d, temp_cck, val_x, value32;
  758. long val_y, ele_c = 0;
  759. u8 ofdm_index[3];
  760. s8 cck_index = 0;
  761. u8 ofdm_index_old[3] = {0, 0, 0};
  762. s8 cck_index_old = 0;
  763. u8 index;
  764. int i;
  765. bool is2t = IS_92D_SINGLEPHY(rtlhal->version);
  766. u8 ofdm_min_index = 6, ofdm_min_index_internal_pa = 3, rf;
  767. u8 indexforchannel =
  768. rtl92d_get_rightchnlplace_for_iqk(rtlphy->current_channel);
  769. u8 index_mapping[5][INDEX_MAPPING_NUM] = {
  770. /* 5G, path A/MAC 0, decrease power */
  771. {0, 1, 3, 6, 8, 9, 11, 13, 14, 16, 17, 18, 18},
  772. /* 5G, path A/MAC 0, increase power */
  773. {0, 2, 4, 5, 7, 10, 12, 14, 16, 18, 18, 18, 18},
  774. /* 5G, path B/MAC 1, decrease power */
  775. {0, 2, 3, 6, 8, 9, 11, 13, 14, 16, 17, 18, 18},
  776. /* 5G, path B/MAC 1, increase power */
  777. {0, 2, 4, 5, 7, 10, 13, 16, 16, 18, 18, 18, 18},
  778. /* 2.4G, for decreas power */
  779. {0, 1, 2, 3, 4, 5, 6, 7, 7, 8, 9, 10, 10},
  780. };
  781. u8 index_mapping_internal_pa[8][INDEX_MAPPING_NUM] = {
  782. /* 5G, path A/MAC 0, ch36-64, decrease power */
  783. {0, 1, 2, 4, 6, 7, 9, 11, 12, 14, 15, 16, 16},
  784. /* 5G, path A/MAC 0, ch36-64, increase power */
  785. {0, 2, 4, 5, 7, 10, 12, 14, 16, 18, 18, 18, 18},
  786. /* 5G, path A/MAC 0, ch100-165, decrease power */
  787. {0, 1, 2, 3, 5, 6, 8, 10, 11, 13, 14, 15, 15},
  788. /* 5G, path A/MAC 0, ch100-165, increase power */
  789. {0, 2, 4, 5, 7, 10, 12, 14, 16, 18, 18, 18, 18},
  790. /* 5G, path B/MAC 1, ch36-64, decrease power */
  791. {0, 1, 2, 4, 6, 7, 9, 11, 12, 14, 15, 16, 16},
  792. /* 5G, path B/MAC 1, ch36-64, increase power */
  793. {0, 2, 4, 5, 7, 10, 13, 16, 16, 18, 18, 18, 18},
  794. /* 5G, path B/MAC 1, ch100-165, decrease power */
  795. {0, 1, 2, 3, 5, 6, 8, 9, 10, 12, 13, 14, 14},
  796. /* 5G, path B/MAC 1, ch100-165, increase power */
  797. {0, 2, 4, 5, 7, 10, 13, 16, 16, 18, 18, 18, 18},
  798. };
  799. rtlpriv->dm.txpower_trackinginit = true;
  800. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, "\n");
  801. thermalvalue = (u8) rtl_get_rfreg(hw, RF90_PATH_A, RF_T_METER, 0xf800);
  802. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  803. "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x\n",
  804. thermalvalue,
  805. rtlpriv->dm.thermalvalue, rtlefuse->eeprom_thermalmeter);
  806. rtl92d_phy_ap_calibrate(hw, (thermalvalue -
  807. rtlefuse->eeprom_thermalmeter));
  808. if (is2t)
  809. rf = 2;
  810. else
  811. rf = 1;
  812. if (thermalvalue) {
  813. ele_d = rtl_get_bbreg(hw, ROFDM0_XATxIQIMBALANCE,
  814. MASKDWORD) & MASKOFDM_D;
  815. for (i = 0; i < OFDM_TABLE_SIZE_92D; i++) {
  816. if (ele_d == (ofdmswing_table[i] & MASKOFDM_D)) {
  817. ofdm_index_old[0] = (u8) i;
  818. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  819. "Initial pathA ele_d reg0x%x = 0x%lx, ofdm_index=0x%x\n",
  820. ROFDM0_XATxIQIMBALANCE,
  821. ele_d, ofdm_index_old[0]);
  822. break;
  823. }
  824. }
  825. if (is2t) {
  826. ele_d = rtl_get_bbreg(hw, ROFDM0_XBTxIQIMBALANCE,
  827. MASKDWORD) & MASKOFDM_D;
  828. for (i = 0; i < OFDM_TABLE_SIZE_92D; i++) {
  829. if (ele_d ==
  830. (ofdmswing_table[i] & MASKOFDM_D)) {
  831. ofdm_index_old[1] = (u8) i;
  832. RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
  833. DBG_LOUD,
  834. "Initial pathB ele_d reg 0x%x = 0x%lx, ofdm_index = 0x%x\n",
  835. ROFDM0_XBTxIQIMBALANCE, ele_d,
  836. ofdm_index_old[1]);
  837. break;
  838. }
  839. }
  840. }
  841. if (rtlhal->current_bandtype == BAND_ON_2_4G) {
  842. rtl92d_bandtype_2_4G(hw, &temp_cck, &cck_index_old);
  843. } else {
  844. temp_cck = 0x090e1317;
  845. cck_index_old = 12;
  846. }
  847. if (!rtlpriv->dm.thermalvalue) {
  848. rtlpriv->dm.thermalvalue =
  849. rtlefuse->eeprom_thermalmeter;
  850. rtlpriv->dm.thermalvalue_lck = thermalvalue;
  851. rtlpriv->dm.thermalvalue_iqk = thermalvalue;
  852. rtlpriv->dm.thermalvalue_rxgain =
  853. rtlefuse->eeprom_thermalmeter;
  854. for (i = 0; i < rf; i++)
  855. rtlpriv->dm.ofdm_index[i] = ofdm_index_old[i];
  856. rtlpriv->dm.cck_index = cck_index_old;
  857. }
  858. if (rtlhal->reloadtxpowerindex) {
  859. for (i = 0; i < rf; i++)
  860. rtlpriv->dm.ofdm_index[i] = ofdm_index_old[i];
  861. rtlpriv->dm.cck_index = cck_index_old;
  862. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  863. "reload ofdm index for band switch\n");
  864. }
  865. rtlpriv->dm.thermalvalue_avg
  866. [rtlpriv->dm.thermalvalue_avg_index] = thermalvalue;
  867. rtlpriv->dm.thermalvalue_avg_index++;
  868. if (rtlpriv->dm.thermalvalue_avg_index == AVG_THERMAL_NUM)
  869. rtlpriv->dm.thermalvalue_avg_index = 0;
  870. for (i = 0; i < AVG_THERMAL_NUM; i++) {
  871. if (rtlpriv->dm.thermalvalue_avg[i]) {
  872. thermalvalue_avg +=
  873. rtlpriv->dm.thermalvalue_avg[i];
  874. thermalvalue_avg_count++;
  875. }
  876. }
  877. if (thermalvalue_avg_count)
  878. thermalvalue = (u8) (thermalvalue_avg /
  879. thermalvalue_avg_count);
  880. if (rtlhal->reloadtxpowerindex) {
  881. delta = (thermalvalue > rtlefuse->eeprom_thermalmeter) ?
  882. (thermalvalue - rtlefuse->eeprom_thermalmeter) :
  883. (rtlefuse->eeprom_thermalmeter - thermalvalue);
  884. rtlhal->reloadtxpowerindex = false;
  885. rtlpriv->dm.done_txpower = false;
  886. } else if (rtlpriv->dm.done_txpower) {
  887. delta = (thermalvalue > rtlpriv->dm.thermalvalue) ?
  888. (thermalvalue - rtlpriv->dm.thermalvalue) :
  889. (rtlpriv->dm.thermalvalue - thermalvalue);
  890. } else {
  891. delta = (thermalvalue > rtlefuse->eeprom_thermalmeter) ?
  892. (thermalvalue - rtlefuse->eeprom_thermalmeter) :
  893. (rtlefuse->eeprom_thermalmeter - thermalvalue);
  894. }
  895. delta_lck = (thermalvalue > rtlpriv->dm.thermalvalue_lck) ?
  896. (thermalvalue - rtlpriv->dm.thermalvalue_lck) :
  897. (rtlpriv->dm.thermalvalue_lck - thermalvalue);
  898. delta_iqk = (thermalvalue > rtlpriv->dm.thermalvalue_iqk) ?
  899. (thermalvalue - rtlpriv->dm.thermalvalue_iqk) :
  900. (rtlpriv->dm.thermalvalue_iqk - thermalvalue);
  901. delta_rxgain =
  902. (thermalvalue > rtlpriv->dm.thermalvalue_rxgain) ?
  903. (thermalvalue - rtlpriv->dm.thermalvalue_rxgain) :
  904. (rtlpriv->dm.thermalvalue_rxgain - thermalvalue);
  905. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  906. "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x delta 0x%x delta_lck 0x%x delta_iqk 0x%x\n",
  907. thermalvalue, rtlpriv->dm.thermalvalue,
  908. rtlefuse->eeprom_thermalmeter, delta, delta_lck,
  909. delta_iqk);
  910. if ((delta_lck > rtlefuse->delta_lck) &&
  911. (rtlefuse->delta_lck != 0)) {
  912. rtlpriv->dm.thermalvalue_lck = thermalvalue;
  913. rtl92d_phy_lc_calibrate(hw);
  914. }
  915. if (delta > 0 && rtlpriv->dm.txpower_track_control) {
  916. rtlpriv->dm.done_txpower = true;
  917. delta = (thermalvalue > rtlefuse->eeprom_thermalmeter) ?
  918. (thermalvalue - rtlefuse->eeprom_thermalmeter) :
  919. (rtlefuse->eeprom_thermalmeter - thermalvalue);
  920. if (rtlhal->current_bandtype == BAND_ON_2_4G) {
  921. offset = 4;
  922. if (delta > INDEX_MAPPING_NUM - 1)
  923. index = index_mapping[offset]
  924. [INDEX_MAPPING_NUM - 1];
  925. else
  926. index = index_mapping[offset][delta];
  927. if (thermalvalue > rtlpriv->dm.thermalvalue) {
  928. for (i = 0; i < rf; i++)
  929. ofdm_index[i] -= delta;
  930. cck_index -= delta;
  931. } else {
  932. for (i = 0; i < rf; i++)
  933. ofdm_index[i] += index;
  934. cck_index += index;
  935. }
  936. } else if (rtlhal->current_bandtype == BAND_ON_5G) {
  937. rtl92d_bandtype_5G(rtlhal, ofdm_index,
  938. &internal_pa, thermalvalue,
  939. delta, rf, rtlefuse, rtlpriv,
  940. rtlphy, index_mapping,
  941. index_mapping_internal_pa);
  942. }
  943. if (is2t) {
  944. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  945. "temp OFDM_A_index=0x%x, OFDM_B_index = 0x%x,cck_index=0x%x\n",
  946. rtlpriv->dm.ofdm_index[0],
  947. rtlpriv->dm.ofdm_index[1],
  948. rtlpriv->dm.cck_index);
  949. } else {
  950. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  951. "temp OFDM_A_index=0x%x,cck_index = 0x%x\n",
  952. rtlpriv->dm.ofdm_index[0],
  953. rtlpriv->dm.cck_index);
  954. }
  955. for (i = 0; i < rf; i++) {
  956. if (ofdm_index[i] > OFDM_TABLE_SIZE_92D - 1)
  957. ofdm_index[i] = OFDM_TABLE_SIZE_92D - 1;
  958. else if (ofdm_index[i] < ofdm_min_index)
  959. ofdm_index[i] = ofdm_min_index;
  960. }
  961. if (rtlhal->current_bandtype == BAND_ON_2_4G) {
  962. if (cck_index > CCK_TABLE_SIZE - 1) {
  963. cck_index = CCK_TABLE_SIZE - 1;
  964. } else if (internal_pa ||
  965. rtlhal->current_bandtype ==
  966. BAND_ON_2_4G) {
  967. if (ofdm_index[i] <
  968. ofdm_min_index_internal_pa)
  969. ofdm_index[i] =
  970. ofdm_min_index_internal_pa;
  971. } else if (cck_index < 0) {
  972. cck_index = 0;
  973. }
  974. }
  975. if (is2t) {
  976. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  977. "new OFDM_A_index=0x%x, OFDM_B_index = 0x%x, cck_index=0x%x\n",
  978. ofdm_index[0], ofdm_index[1],
  979. cck_index);
  980. } else {
  981. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  982. "new OFDM_A_index=0x%x,cck_index = 0x%x\n",
  983. ofdm_index[0], cck_index);
  984. }
  985. ele_d = (ofdmswing_table[(u8) ofdm_index[0]] &
  986. 0xFFC00000) >> 22;
  987. val_x = rtlphy->iqk_matrix
  988. [indexforchannel].value[0][0];
  989. val_y = rtlphy->iqk_matrix
  990. [indexforchannel].value[0][1];
  991. if (val_x != 0) {
  992. if ((val_x & 0x00000200) != 0)
  993. val_x = val_x | 0xFFFFFC00;
  994. ele_a =
  995. ((val_x * ele_d) >> 8) & 0x000003FF;
  996. /* new element C = element D x Y */
  997. if ((val_y & 0x00000200) != 0)
  998. val_y = val_y | 0xFFFFFC00;
  999. ele_c = ((val_y * ele_d) >> 8) & 0x000003FF;
  1000. /* wirte new elements A, C, D to regC80 and
  1001. * regC94, element B is always 0 */
  1002. value32 = (ele_d << 22) | ((ele_c & 0x3F) <<
  1003. 16) | ele_a;
  1004. rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE,
  1005. MASKDWORD, value32);
  1006. value32 = (ele_c & 0x000003C0) >> 6;
  1007. rtl_set_bbreg(hw, ROFDM0_XCTxAFE, MASKH4BITS,
  1008. value32);
  1009. value32 = ((val_x * ele_d) >> 7) & 0x01;
  1010. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24),
  1011. value32);
  1012. } else {
  1013. rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE,
  1014. MASKDWORD,
  1015. ofdmswing_table
  1016. [(u8)ofdm_index[0]]);
  1017. rtl_set_bbreg(hw, ROFDM0_XCTxAFE, MASKH4BITS,
  1018. 0x00);
  1019. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  1020. BIT(24), 0x00);
  1021. }
  1022. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  1023. "TxPwrTracking for interface %d path A: X = 0x%lx, Y = 0x%lx ele_A = 0x%lx ele_C = 0x%lx ele_D = 0x%lx 0xe94 = 0x%lx 0xe9c = 0x%lx\n",
  1024. rtlhal->interfaceindex,
  1025. val_x, val_y, ele_a, ele_c, ele_d,
  1026. val_x, val_y);
  1027. if (cck_index >= CCK_TABLE_SIZE)
  1028. cck_index = CCK_TABLE_SIZE - 1;
  1029. if (cck_index < 0)
  1030. cck_index = 0;
  1031. if (rtlhal->current_bandtype == BAND_ON_2_4G) {
  1032. /* Adjust CCK according to IQK result */
  1033. if (!rtlpriv->dm.cck_inch14) {
  1034. rtl_write_byte(rtlpriv, 0xa22,
  1035. cckswing_table_ch1ch13
  1036. [(u8)cck_index][0]);
  1037. rtl_write_byte(rtlpriv, 0xa23,
  1038. cckswing_table_ch1ch13
  1039. [(u8)cck_index][1]);
  1040. rtl_write_byte(rtlpriv, 0xa24,
  1041. cckswing_table_ch1ch13
  1042. [(u8)cck_index][2]);
  1043. rtl_write_byte(rtlpriv, 0xa25,
  1044. cckswing_table_ch1ch13
  1045. [(u8)cck_index][3]);
  1046. rtl_write_byte(rtlpriv, 0xa26,
  1047. cckswing_table_ch1ch13
  1048. [(u8)cck_index][4]);
  1049. rtl_write_byte(rtlpriv, 0xa27,
  1050. cckswing_table_ch1ch13
  1051. [(u8)cck_index][5]);
  1052. rtl_write_byte(rtlpriv, 0xa28,
  1053. cckswing_table_ch1ch13
  1054. [(u8)cck_index][6]);
  1055. rtl_write_byte(rtlpriv, 0xa29,
  1056. cckswing_table_ch1ch13
  1057. [(u8)cck_index][7]);
  1058. } else {
  1059. rtl_write_byte(rtlpriv, 0xa22,
  1060. cckswing_table_ch14
  1061. [(u8)cck_index][0]);
  1062. rtl_write_byte(rtlpriv, 0xa23,
  1063. cckswing_table_ch14
  1064. [(u8)cck_index][1]);
  1065. rtl_write_byte(rtlpriv, 0xa24,
  1066. cckswing_table_ch14
  1067. [(u8)cck_index][2]);
  1068. rtl_write_byte(rtlpriv, 0xa25,
  1069. cckswing_table_ch14
  1070. [(u8)cck_index][3]);
  1071. rtl_write_byte(rtlpriv, 0xa26,
  1072. cckswing_table_ch14
  1073. [(u8)cck_index][4]);
  1074. rtl_write_byte(rtlpriv, 0xa27,
  1075. cckswing_table_ch14
  1076. [(u8)cck_index][5]);
  1077. rtl_write_byte(rtlpriv, 0xa28,
  1078. cckswing_table_ch14
  1079. [(u8)cck_index][6]);
  1080. rtl_write_byte(rtlpriv, 0xa29,
  1081. cckswing_table_ch14
  1082. [(u8)cck_index][7]);
  1083. }
  1084. }
  1085. if (is2t) {
  1086. ele_d = (ofdmswing_table[(u8) ofdm_index[1]] &
  1087. 0xFFC00000) >> 22;
  1088. val_x = rtlphy->iqk_matrix
  1089. [indexforchannel].value[0][4];
  1090. val_y = rtlphy->iqk_matrix
  1091. [indexforchannel].value[0][5];
  1092. if (val_x != 0) {
  1093. if ((val_x & 0x00000200) != 0)
  1094. /* consider minus */
  1095. val_x = val_x | 0xFFFFFC00;
  1096. ele_a = ((val_x * ele_d) >> 8) &
  1097. 0x000003FF;
  1098. /* new element C = element D x Y */
  1099. if ((val_y & 0x00000200) != 0)
  1100. val_y =
  1101. val_y | 0xFFFFFC00;
  1102. ele_c =
  1103. ((val_y *
  1104. ele_d) >> 8) & 0x00003FF;
  1105. /* write new elements A, C, D to regC88
  1106. * and regC9C, element B is always 0
  1107. */
  1108. value32 = (ele_d << 22) |
  1109. ((ele_c & 0x3F) << 16) |
  1110. ele_a;
  1111. rtl_set_bbreg(hw,
  1112. ROFDM0_XBTxIQIMBALANCE,
  1113. MASKDWORD, value32);
  1114. value32 = (ele_c & 0x000003C0) >> 6;
  1115. rtl_set_bbreg(hw, ROFDM0_XDTxAFE,
  1116. MASKH4BITS, value32);
  1117. value32 = ((val_x * ele_d) >> 7) & 0x01;
  1118. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  1119. BIT(28), value32);
  1120. } else {
  1121. rtl_set_bbreg(hw,
  1122. ROFDM0_XBTxIQIMBALANCE,
  1123. MASKDWORD,
  1124. ofdmswing_table
  1125. [(u8) ofdm_index[1]]);
  1126. rtl_set_bbreg(hw, ROFDM0_XDTxAFE,
  1127. MASKH4BITS, 0x00);
  1128. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  1129. BIT(28), 0x00);
  1130. }
  1131. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  1132. "TxPwrTracking path B: X = 0x%lx, Y = 0x%lx ele_A = 0x%lx ele_C = 0x%lx ele_D = 0x%lx 0xeb4 = 0x%lx 0xebc = 0x%lx\n",
  1133. val_x, val_y, ele_a, ele_c,
  1134. ele_d, val_x, val_y);
  1135. }
  1136. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  1137. "TxPwrTracking 0xc80 = 0x%x, 0xc94 = 0x%x RF 0x24 = 0x%x\n",
  1138. rtl_get_bbreg(hw, 0xc80, MASKDWORD),
  1139. rtl_get_bbreg(hw, 0xc94, MASKDWORD),
  1140. rtl_get_rfreg(hw, RF90_PATH_A, 0x24,
  1141. RFREG_OFFSET_MASK));
  1142. }
  1143. if ((delta_iqk > rtlefuse->delta_iqk) &&
  1144. (rtlefuse->delta_iqk != 0)) {
  1145. rtl92d_phy_reset_iqk_result(hw);
  1146. rtlpriv->dm.thermalvalue_iqk = thermalvalue;
  1147. rtl92d_phy_iq_calibrate(hw);
  1148. }
  1149. if (delta_rxgain > 0 && rtlhal->current_bandtype == BAND_ON_5G
  1150. && thermalvalue <= rtlefuse->eeprom_thermalmeter) {
  1151. rtlpriv->dm.thermalvalue_rxgain = thermalvalue;
  1152. rtl92d_dm_rxgain_tracking_thermalmeter(hw);
  1153. }
  1154. if (rtlpriv->dm.txpower_track_control)
  1155. rtlpriv->dm.thermalvalue = thermalvalue;
  1156. }
  1157. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, "<===\n");
  1158. }
  1159. static void rtl92d_dm_initialize_txpower_tracking(struct ieee80211_hw *hw)
  1160. {
  1161. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1162. rtlpriv->dm.txpower_tracking = true;
  1163. rtlpriv->dm.txpower_trackinginit = false;
  1164. rtlpriv->dm.txpower_track_control = true;
  1165. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  1166. "pMgntInfo->txpower_tracking = %d\n",
  1167. rtlpriv->dm.txpower_tracking);
  1168. }
  1169. void rtl92d_dm_check_txpower_tracking_thermal_meter(struct ieee80211_hw *hw)
  1170. {
  1171. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1172. if (!rtlpriv->dm.txpower_tracking)
  1173. return;
  1174. if (!rtlpriv->dm.tm_trigger) {
  1175. rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER, BIT(17) |
  1176. BIT(16), 0x03);
  1177. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  1178. "Trigger 92S Thermal Meter!!\n");
  1179. rtlpriv->dm.tm_trigger = 1;
  1180. return;
  1181. } else {
  1182. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  1183. "Schedule TxPowerTracking direct call!!\n");
  1184. rtl92d_dm_txpower_tracking_callback_thermalmeter(hw);
  1185. rtlpriv->dm.tm_trigger = 0;
  1186. }
  1187. }
  1188. void rtl92d_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw)
  1189. {
  1190. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1191. struct rate_adaptive *ra = &(rtlpriv->ra);
  1192. ra->ratr_state = DM_RATR_STA_INIT;
  1193. ra->pre_ratr_state = DM_RATR_STA_INIT;
  1194. if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER)
  1195. rtlpriv->dm.useramask = true;
  1196. else
  1197. rtlpriv->dm.useramask = false;
  1198. }
  1199. void rtl92d_dm_init(struct ieee80211_hw *hw)
  1200. {
  1201. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1202. rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER;
  1203. rtl_dm_diginit(hw, 0x20);
  1204. rtlpriv->dm_digtable.rx_gain_max = DM_DIG_FA_UPPER;
  1205. rtlpriv->dm_digtable.rx_gain_min = DM_DIG_FA_LOWER;
  1206. rtl92d_dm_init_dynamic_txpower(hw);
  1207. rtl92d_dm_init_edca_turbo(hw);
  1208. rtl92d_dm_init_rate_adaptive_mask(hw);
  1209. rtl92d_dm_initialize_txpower_tracking(hw);
  1210. }
  1211. void rtl92d_dm_watchdog(struct ieee80211_hw *hw)
  1212. {
  1213. struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  1214. bool fw_current_inpsmode = false;
  1215. bool fwps_awake = true;
  1216. /* 1. RF is OFF. (No need to do DM.)
  1217. * 2. Fw is under power saving mode for FwLPS.
  1218. * (Prevent from SW/FW I/O racing.)
  1219. * 3. IPS workitem is scheduled. (Prevent from IPS sequence
  1220. * to be swapped with DM.
  1221. * 4. RFChangeInProgress is TRUE.
  1222. * (Prevent from broken by IPS/HW/SW Rf off.) */
  1223. if ((ppsc->rfpwr_state == ERFON) && ((!fw_current_inpsmode) &&
  1224. fwps_awake) && (!ppsc->rfchange_inprogress)) {
  1225. rtl92d_dm_pwdb_monitor(hw);
  1226. rtl92d_dm_false_alarm_counter_statistics(hw);
  1227. rtl92d_dm_find_minimum_rssi(hw);
  1228. rtl92d_dm_dig(hw);
  1229. /* rtl92d_dm_dynamic_bb_powersaving(hw); */
  1230. rtl92d_dm_dynamic_txpower(hw);
  1231. /* rtl92d_dm_check_txpower_tracking_thermal_meter(hw); */
  1232. /* rtl92d_dm_refresh_rate_adaptive_mask(hw); */
  1233. /* rtl92d_dm_interrupt_migration(hw); */
  1234. rtl92d_dm_check_edca_turbo(hw);
  1235. }
  1236. }