ampdu.c 33 KB

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  1. /*
  2. * Copyright (c) 2010 Broadcom Corporation
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11. * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13. * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14. * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <net/mac80211.h>
  17. #include "rate.h"
  18. #include "scb.h"
  19. #include "phy/phy_hal.h"
  20. #include "antsel.h"
  21. #include "main.h"
  22. #include "ampdu.h"
  23. #include "debug.h"
  24. #include "brcms_trace_events.h"
  25. /* max number of mpdus in an ampdu */
  26. #define AMPDU_MAX_MPDU 32
  27. /* max number of mpdus in an ampdu to a legacy */
  28. #define AMPDU_NUM_MPDU_LEGACY 16
  29. /* max Tx ba window size (in pdu) */
  30. #define AMPDU_TX_BA_MAX_WSIZE 64
  31. /* default Tx ba window size (in pdu) */
  32. #define AMPDU_TX_BA_DEF_WSIZE 64
  33. /* default Rx ba window size (in pdu) */
  34. #define AMPDU_RX_BA_DEF_WSIZE 64
  35. /* max Rx ba window size (in pdu) */
  36. #define AMPDU_RX_BA_MAX_WSIZE 64
  37. /* max dur of tx ampdu (in msec) */
  38. #define AMPDU_MAX_DUR 5
  39. /* default tx retry limit */
  40. #define AMPDU_DEF_RETRY_LIMIT 5
  41. /* default tx retry limit at reg rate */
  42. #define AMPDU_DEF_RR_RETRY_LIMIT 2
  43. /* default ffpld reserved bytes */
  44. #define AMPDU_DEF_FFPLD_RSVD 2048
  45. /* # of inis to be freed on detach */
  46. #define AMPDU_INI_FREE 10
  47. /* max # of mpdus released at a time */
  48. #define AMPDU_SCB_MAX_RELEASE 20
  49. #define NUM_FFPLD_FIFO 4 /* number of fifo concerned by pre-loading */
  50. #define FFPLD_TX_MAX_UNFL 200 /* default value of the average number of ampdu
  51. * without underflows
  52. */
  53. #define FFPLD_MPDU_SIZE 1800 /* estimate of maximum mpdu size */
  54. #define FFPLD_MAX_MCS 23 /* we don't deal with mcs 32 */
  55. #define FFPLD_PLD_INCR 1000 /* increments in bytes */
  56. #define FFPLD_MAX_AMPDU_CNT 5000 /* maximum number of ampdu we
  57. * accumulate between resets.
  58. */
  59. #define AMPDU_DELIMITER_LEN 4
  60. /* max allowed number of mpdus in an ampdu (2 streams) */
  61. #define AMPDU_NUM_MPDU 16
  62. #define TX_SEQ_TO_INDEX(seq) ((seq) % AMPDU_TX_BA_MAX_WSIZE)
  63. /* max possible overhead per mpdu in the ampdu; 3 is for roundup if needed */
  64. #define AMPDU_MAX_MPDU_OVERHEAD (FCS_LEN + DOT11_ICV_AES_LEN +\
  65. AMPDU_DELIMITER_LEN + 3\
  66. + DOT11_A4_HDR_LEN + DOT11_QOS_LEN + DOT11_IV_MAX_LEN)
  67. /* modulo add/sub, bound = 2^k */
  68. #define MODADD_POW2(x, y, bound) (((x) + (y)) & ((bound) - 1))
  69. #define MODSUB_POW2(x, y, bound) (((x) - (y)) & ((bound) - 1))
  70. /* structure to hold tx fifo information and pre-loading state
  71. * counters specific to tx underflows of ampdus
  72. * some counters might be redundant with the ones in wlc or ampdu structures.
  73. * This allows to maintain a specific state independently of
  74. * how often and/or when the wlc counters are updated.
  75. *
  76. * ampdu_pld_size: number of bytes to be pre-loaded
  77. * mcs2ampdu_table: per-mcs max # of mpdus in an ampdu
  78. * prev_txfunfl: num of underflows last read from the HW macstats counter
  79. * accum_txfunfl: num of underflows since we modified pld params
  80. * accum_txampdu: num of tx ampdu since we modified pld params
  81. * prev_txampdu: previous reading of tx ampdu
  82. * dmaxferrate: estimated dma avg xfer rate in kbits/sec
  83. */
  84. struct brcms_fifo_info {
  85. u16 ampdu_pld_size;
  86. u8 mcs2ampdu_table[FFPLD_MAX_MCS + 1];
  87. u16 prev_txfunfl;
  88. u32 accum_txfunfl;
  89. u32 accum_txampdu;
  90. u32 prev_txampdu;
  91. u32 dmaxferrate;
  92. };
  93. /* AMPDU module specific state
  94. *
  95. * wlc: pointer to main wlc structure
  96. * scb_handle: scb cubby handle to retrieve data from scb
  97. * ini_enable: per-tid initiator enable/disable of ampdu
  98. * ba_tx_wsize: Tx ba window size (in pdu)
  99. * ba_rx_wsize: Rx ba window size (in pdu)
  100. * retry_limit: mpdu transmit retry limit
  101. * rr_retry_limit: mpdu transmit retry limit at regular rate
  102. * retry_limit_tid: per-tid mpdu transmit retry limit
  103. * rr_retry_limit_tid: per-tid mpdu transmit retry limit at regular rate
  104. * mpdu_density: min mpdu spacing (0-7) ==> 2^(x-1)/8 usec
  105. * max_pdu: max pdus allowed in ampdu
  106. * dur: max duration of an ampdu (in msec)
  107. * rx_factor: maximum rx ampdu factor (0-3) ==> 2^(13+x) bytes
  108. * ffpld_rsvd: number of bytes to reserve for preload
  109. * max_txlen: max size of ampdu per mcs, bw and sgi
  110. * mfbr: enable multiple fallback rate
  111. * tx_max_funl: underflows should be kept such that
  112. * (tx_max_funfl*underflows) < tx frames
  113. * fifo_tb: table of fifo infos
  114. */
  115. struct ampdu_info {
  116. struct brcms_c_info *wlc;
  117. int scb_handle;
  118. u8 ini_enable[AMPDU_MAX_SCB_TID];
  119. u8 ba_tx_wsize;
  120. u8 ba_rx_wsize;
  121. u8 retry_limit;
  122. u8 rr_retry_limit;
  123. u8 retry_limit_tid[AMPDU_MAX_SCB_TID];
  124. u8 rr_retry_limit_tid[AMPDU_MAX_SCB_TID];
  125. u8 mpdu_density;
  126. s8 max_pdu;
  127. u8 dur;
  128. u8 rx_factor;
  129. u32 ffpld_rsvd;
  130. u32 max_txlen[MCS_TABLE_SIZE][2][2];
  131. bool mfbr;
  132. u32 tx_max_funl;
  133. struct brcms_fifo_info fifo_tb[NUM_FFPLD_FIFO];
  134. };
  135. /* used for flushing ampdu packets */
  136. struct cb_del_ampdu_pars {
  137. struct ieee80211_sta *sta;
  138. u16 tid;
  139. };
  140. static void brcms_c_scb_ampdu_update_max_txlen(struct ampdu_info *ampdu, u8 dur)
  141. {
  142. u32 rate, mcs;
  143. for (mcs = 0; mcs < MCS_TABLE_SIZE; mcs++) {
  144. /* rate is in Kbps; dur is in msec ==> len = (rate * dur) / 8 */
  145. /* 20MHz, No SGI */
  146. rate = mcs_2_rate(mcs, false, false);
  147. ampdu->max_txlen[mcs][0][0] = (rate * dur) >> 3;
  148. /* 40 MHz, No SGI */
  149. rate = mcs_2_rate(mcs, true, false);
  150. ampdu->max_txlen[mcs][1][0] = (rate * dur) >> 3;
  151. /* 20MHz, SGI */
  152. rate = mcs_2_rate(mcs, false, true);
  153. ampdu->max_txlen[mcs][0][1] = (rate * dur) >> 3;
  154. /* 40 MHz, SGI */
  155. rate = mcs_2_rate(mcs, true, true);
  156. ampdu->max_txlen[mcs][1][1] = (rate * dur) >> 3;
  157. }
  158. }
  159. static bool brcms_c_ampdu_cap(struct ampdu_info *ampdu)
  160. {
  161. if (BRCMS_PHY_11N_CAP(ampdu->wlc->band))
  162. return true;
  163. else
  164. return false;
  165. }
  166. static int brcms_c_ampdu_set(struct ampdu_info *ampdu, bool on)
  167. {
  168. struct brcms_c_info *wlc = ampdu->wlc;
  169. struct bcma_device *core = wlc->hw->d11core;
  170. wlc->pub->_ampdu = false;
  171. if (on) {
  172. if (!(wlc->pub->_n_enab & SUPPORT_11N)) {
  173. brcms_err(core, "wl%d: driver not nmode enabled\n",
  174. wlc->pub->unit);
  175. return -ENOTSUPP;
  176. }
  177. if (!brcms_c_ampdu_cap(ampdu)) {
  178. brcms_err(core, "wl%d: device not ampdu capable\n",
  179. wlc->pub->unit);
  180. return -ENOTSUPP;
  181. }
  182. wlc->pub->_ampdu = on;
  183. }
  184. return 0;
  185. }
  186. static void brcms_c_ffpld_init(struct ampdu_info *ampdu)
  187. {
  188. int i, j;
  189. struct brcms_fifo_info *fifo;
  190. for (j = 0; j < NUM_FFPLD_FIFO; j++) {
  191. fifo = (ampdu->fifo_tb + j);
  192. fifo->ampdu_pld_size = 0;
  193. for (i = 0; i <= FFPLD_MAX_MCS; i++)
  194. fifo->mcs2ampdu_table[i] = 255;
  195. fifo->dmaxferrate = 0;
  196. fifo->accum_txampdu = 0;
  197. fifo->prev_txfunfl = 0;
  198. fifo->accum_txfunfl = 0;
  199. }
  200. }
  201. struct ampdu_info *brcms_c_ampdu_attach(struct brcms_c_info *wlc)
  202. {
  203. struct ampdu_info *ampdu;
  204. int i;
  205. ampdu = kzalloc(sizeof(struct ampdu_info), GFP_ATOMIC);
  206. if (!ampdu)
  207. return NULL;
  208. ampdu->wlc = wlc;
  209. for (i = 0; i < AMPDU_MAX_SCB_TID; i++)
  210. ampdu->ini_enable[i] = true;
  211. /* Disable ampdu for VO by default */
  212. ampdu->ini_enable[PRIO_8021D_VO] = false;
  213. ampdu->ini_enable[PRIO_8021D_NC] = false;
  214. /* Disable ampdu for BK by default since not enough fifo space */
  215. ampdu->ini_enable[PRIO_8021D_NONE] = false;
  216. ampdu->ini_enable[PRIO_8021D_BK] = false;
  217. ampdu->ba_tx_wsize = AMPDU_TX_BA_DEF_WSIZE;
  218. ampdu->ba_rx_wsize = AMPDU_RX_BA_DEF_WSIZE;
  219. ampdu->mpdu_density = AMPDU_DEF_MPDU_DENSITY;
  220. ampdu->max_pdu = AUTO;
  221. ampdu->dur = AMPDU_MAX_DUR;
  222. ampdu->ffpld_rsvd = AMPDU_DEF_FFPLD_RSVD;
  223. /*
  224. * bump max ampdu rcv size to 64k for all 11n
  225. * devices except 4321A0 and 4321A1
  226. */
  227. if (BRCMS_ISNPHY(wlc->band) && NREV_LT(wlc->band->phyrev, 2))
  228. ampdu->rx_factor = IEEE80211_HT_MAX_AMPDU_32K;
  229. else
  230. ampdu->rx_factor = IEEE80211_HT_MAX_AMPDU_64K;
  231. ampdu->retry_limit = AMPDU_DEF_RETRY_LIMIT;
  232. ampdu->rr_retry_limit = AMPDU_DEF_RR_RETRY_LIMIT;
  233. for (i = 0; i < AMPDU_MAX_SCB_TID; i++) {
  234. ampdu->retry_limit_tid[i] = ampdu->retry_limit;
  235. ampdu->rr_retry_limit_tid[i] = ampdu->rr_retry_limit;
  236. }
  237. brcms_c_scb_ampdu_update_max_txlen(ampdu, ampdu->dur);
  238. ampdu->mfbr = false;
  239. /* try to set ampdu to the default value */
  240. brcms_c_ampdu_set(ampdu, wlc->pub->_ampdu);
  241. ampdu->tx_max_funl = FFPLD_TX_MAX_UNFL;
  242. brcms_c_ffpld_init(ampdu);
  243. return ampdu;
  244. }
  245. void brcms_c_ampdu_detach(struct ampdu_info *ampdu)
  246. {
  247. kfree(ampdu);
  248. }
  249. static void brcms_c_scb_ampdu_update_config(struct ampdu_info *ampdu,
  250. struct scb *scb)
  251. {
  252. struct scb_ampdu *scb_ampdu = &scb->scb_ampdu;
  253. int i;
  254. scb_ampdu->max_pdu = AMPDU_NUM_MPDU;
  255. /* go back to legacy size if some preloading is occurring */
  256. for (i = 0; i < NUM_FFPLD_FIFO; i++) {
  257. if (ampdu->fifo_tb[i].ampdu_pld_size > FFPLD_PLD_INCR)
  258. scb_ampdu->max_pdu = AMPDU_NUM_MPDU_LEGACY;
  259. }
  260. /* apply user override */
  261. if (ampdu->max_pdu != AUTO)
  262. scb_ampdu->max_pdu = (u8) ampdu->max_pdu;
  263. scb_ampdu->release = min_t(u8, scb_ampdu->max_pdu,
  264. AMPDU_SCB_MAX_RELEASE);
  265. if (scb_ampdu->max_rx_ampdu_bytes)
  266. scb_ampdu->release = min_t(u8, scb_ampdu->release,
  267. scb_ampdu->max_rx_ampdu_bytes / 1600);
  268. scb_ampdu->release = min(scb_ampdu->release,
  269. ampdu->fifo_tb[TX_AC_BE_FIFO].
  270. mcs2ampdu_table[FFPLD_MAX_MCS]);
  271. }
  272. static void brcms_c_scb_ampdu_update_config_all(struct ampdu_info *ampdu)
  273. {
  274. brcms_c_scb_ampdu_update_config(ampdu, &ampdu->wlc->pri_scb);
  275. }
  276. static void brcms_c_ffpld_calc_mcs2ampdu_table(struct ampdu_info *ampdu, int f)
  277. {
  278. int i;
  279. u32 phy_rate, dma_rate, tmp;
  280. u8 max_mpdu;
  281. struct brcms_fifo_info *fifo = (ampdu->fifo_tb + f);
  282. /* recompute the dma rate */
  283. /* note : we divide/multiply by 100 to avoid integer overflows */
  284. max_mpdu = min_t(u8, fifo->mcs2ampdu_table[FFPLD_MAX_MCS],
  285. AMPDU_NUM_MPDU_LEGACY);
  286. phy_rate = mcs_2_rate(FFPLD_MAX_MCS, true, false);
  287. dma_rate =
  288. (((phy_rate / 100) *
  289. (max_mpdu * FFPLD_MPDU_SIZE - fifo->ampdu_pld_size))
  290. / (max_mpdu * FFPLD_MPDU_SIZE)) * 100;
  291. fifo->dmaxferrate = dma_rate;
  292. /* fill up the mcs2ampdu table; do not recalc the last mcs */
  293. dma_rate = dma_rate >> 7;
  294. for (i = 0; i < FFPLD_MAX_MCS; i++) {
  295. /* shifting to keep it within integer range */
  296. phy_rate = mcs_2_rate(i, true, false) >> 7;
  297. if (phy_rate > dma_rate) {
  298. tmp = ((fifo->ampdu_pld_size * phy_rate) /
  299. ((phy_rate - dma_rate) * FFPLD_MPDU_SIZE)) + 1;
  300. tmp = min_t(u32, tmp, 255);
  301. fifo->mcs2ampdu_table[i] = (u8) tmp;
  302. }
  303. }
  304. }
  305. /* evaluate the dma transfer rate using the tx underflows as feedback.
  306. * If necessary, increase tx fifo preloading. If not enough,
  307. * decrease maximum ampdu size for each mcs till underflows stop
  308. * Return 1 if pre-loading not active, -1 if not an underflow event,
  309. * 0 if pre-loading module took care of the event.
  310. */
  311. static int brcms_c_ffpld_check_txfunfl(struct brcms_c_info *wlc, int fid)
  312. {
  313. struct ampdu_info *ampdu = wlc->ampdu;
  314. u32 phy_rate = mcs_2_rate(FFPLD_MAX_MCS, true, false);
  315. u32 txunfl_ratio;
  316. u8 max_mpdu;
  317. u32 current_ampdu_cnt = 0;
  318. u16 max_pld_size;
  319. u32 new_txunfl;
  320. struct brcms_fifo_info *fifo = (ampdu->fifo_tb + fid);
  321. uint xmtfifo_sz;
  322. u16 cur_txunfl;
  323. /* return if we got here for a different reason than underflows */
  324. cur_txunfl = brcms_b_read_shm(wlc->hw,
  325. M_UCODE_MACSTAT +
  326. offsetof(struct macstat, txfunfl[fid]));
  327. new_txunfl = (u16) (cur_txunfl - fifo->prev_txfunfl);
  328. if (new_txunfl == 0) {
  329. brcms_dbg_ht(wlc->hw->d11core,
  330. "TX status FRAG set but no tx underflows\n");
  331. return -1;
  332. }
  333. fifo->prev_txfunfl = cur_txunfl;
  334. if (!ampdu->tx_max_funl)
  335. return 1;
  336. /* check if fifo is big enough */
  337. if (brcms_b_xmtfifo_sz_get(wlc->hw, fid, &xmtfifo_sz))
  338. return -1;
  339. if ((TXFIFO_SIZE_UNIT * (u32) xmtfifo_sz) <= ampdu->ffpld_rsvd)
  340. return 1;
  341. max_pld_size = TXFIFO_SIZE_UNIT * xmtfifo_sz - ampdu->ffpld_rsvd;
  342. fifo->accum_txfunfl += new_txunfl;
  343. /* we need to wait for at least 10 underflows */
  344. if (fifo->accum_txfunfl < 10)
  345. return 0;
  346. brcms_dbg_ht(wlc->hw->d11core, "ampdu_count %d tx_underflows %d\n",
  347. current_ampdu_cnt, fifo->accum_txfunfl);
  348. /*
  349. compute the current ratio of tx unfl per ampdu.
  350. When the current ampdu count becomes too
  351. big while the ratio remains small, we reset
  352. the current count in order to not
  353. introduce too big of a latency in detecting a
  354. large amount of tx underflows later.
  355. */
  356. txunfl_ratio = current_ampdu_cnt / fifo->accum_txfunfl;
  357. if (txunfl_ratio > ampdu->tx_max_funl) {
  358. if (current_ampdu_cnt >= FFPLD_MAX_AMPDU_CNT)
  359. fifo->accum_txfunfl = 0;
  360. return 0;
  361. }
  362. max_mpdu = min_t(u8, fifo->mcs2ampdu_table[FFPLD_MAX_MCS],
  363. AMPDU_NUM_MPDU_LEGACY);
  364. /* In case max value max_pdu is already lower than
  365. the fifo depth, there is nothing more we can do.
  366. */
  367. if (fifo->ampdu_pld_size >= max_mpdu * FFPLD_MPDU_SIZE) {
  368. fifo->accum_txfunfl = 0;
  369. return 0;
  370. }
  371. if (fifo->ampdu_pld_size < max_pld_size) {
  372. /* increment by TX_FIFO_PLD_INC bytes */
  373. fifo->ampdu_pld_size += FFPLD_PLD_INCR;
  374. if (fifo->ampdu_pld_size > max_pld_size)
  375. fifo->ampdu_pld_size = max_pld_size;
  376. /* update scb release size */
  377. brcms_c_scb_ampdu_update_config_all(ampdu);
  378. /*
  379. * compute a new dma xfer rate for max_mpdu @ max mcs.
  380. * This is the minimum dma rate that can achieve no
  381. * underflow condition for the current mpdu size.
  382. *
  383. * note : we divide/multiply by 100 to avoid integer overflows
  384. */
  385. fifo->dmaxferrate =
  386. (((phy_rate / 100) *
  387. (max_mpdu * FFPLD_MPDU_SIZE - fifo->ampdu_pld_size))
  388. / (max_mpdu * FFPLD_MPDU_SIZE)) * 100;
  389. brcms_dbg_ht(wlc->hw->d11core,
  390. "DMA estimated transfer rate %d; "
  391. "pre-load size %d\n",
  392. fifo->dmaxferrate, fifo->ampdu_pld_size);
  393. } else {
  394. /* decrease ampdu size */
  395. if (fifo->mcs2ampdu_table[FFPLD_MAX_MCS] > 1) {
  396. if (fifo->mcs2ampdu_table[FFPLD_MAX_MCS] == 255)
  397. fifo->mcs2ampdu_table[FFPLD_MAX_MCS] =
  398. AMPDU_NUM_MPDU_LEGACY - 1;
  399. else
  400. fifo->mcs2ampdu_table[FFPLD_MAX_MCS] -= 1;
  401. /* recompute the table */
  402. brcms_c_ffpld_calc_mcs2ampdu_table(ampdu, fid);
  403. /* update scb release size */
  404. brcms_c_scb_ampdu_update_config_all(ampdu);
  405. }
  406. }
  407. fifo->accum_txfunfl = 0;
  408. return 0;
  409. }
  410. void
  411. brcms_c_ampdu_tx_operational(struct brcms_c_info *wlc, u8 tid,
  412. u8 ba_wsize, /* negotiated ba window size (in pdu) */
  413. uint max_rx_ampdu_bytes) /* from ht_cap in beacon */
  414. {
  415. struct scb_ampdu *scb_ampdu;
  416. struct scb_ampdu_tid_ini *ini;
  417. struct ampdu_info *ampdu = wlc->ampdu;
  418. struct scb *scb = &wlc->pri_scb;
  419. scb_ampdu = &scb->scb_ampdu;
  420. if (!ampdu->ini_enable[tid]) {
  421. brcms_err(wlc->hw->d11core, "%s: Rejecting tid %d\n",
  422. __func__, tid);
  423. return;
  424. }
  425. ini = &scb_ampdu->ini[tid];
  426. ini->tid = tid;
  427. ini->scb = scb_ampdu->scb;
  428. ini->ba_wsize = ba_wsize;
  429. scb_ampdu->max_rx_ampdu_bytes = max_rx_ampdu_bytes;
  430. }
  431. void brcms_c_ampdu_reset_session(struct brcms_ampdu_session *session,
  432. struct brcms_c_info *wlc)
  433. {
  434. session->wlc = wlc;
  435. skb_queue_head_init(&session->skb_list);
  436. session->max_ampdu_len = 0; /* determined from first MPDU */
  437. session->max_ampdu_frames = 0; /* determined from first MPDU */
  438. session->ampdu_len = 0;
  439. session->dma_len = 0;
  440. }
  441. /*
  442. * Preps the given packet for AMPDU based on the session data. If the
  443. * frame cannot be accomodated in the current session, -ENOSPC is
  444. * returned.
  445. */
  446. int brcms_c_ampdu_add_frame(struct brcms_ampdu_session *session,
  447. struct sk_buff *p)
  448. {
  449. struct brcms_c_info *wlc = session->wlc;
  450. struct ampdu_info *ampdu = wlc->ampdu;
  451. struct scb *scb = &wlc->pri_scb;
  452. struct scb_ampdu *scb_ampdu = &scb->scb_ampdu;
  453. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(p);
  454. struct ieee80211_tx_rate *txrate = tx_info->status.rates;
  455. struct d11txh *txh = (struct d11txh *)p->data;
  456. unsigned ampdu_frames;
  457. u8 ndelim, tid;
  458. u8 *plcp;
  459. uint len;
  460. u16 mcl;
  461. bool fbr_iscck;
  462. bool rr;
  463. ndelim = txh->RTSPLCPFallback[AMPDU_FBR_NULL_DELIM];
  464. plcp = (u8 *)(txh + 1);
  465. fbr_iscck = !(le16_to_cpu(txh->XtraFrameTypes) & 0x03);
  466. len = fbr_iscck ? BRCMS_GET_CCK_PLCP_LEN(txh->FragPLCPFallback) :
  467. BRCMS_GET_MIMO_PLCP_LEN(txh->FragPLCPFallback);
  468. len = roundup(len, 4) + (ndelim + 1) * AMPDU_DELIMITER_LEN;
  469. ampdu_frames = skb_queue_len(&session->skb_list);
  470. if (ampdu_frames != 0) {
  471. struct sk_buff *first;
  472. if (ampdu_frames + 1 > session->max_ampdu_frames ||
  473. session->ampdu_len + len > session->max_ampdu_len)
  474. return -ENOSPC;
  475. /*
  476. * We aren't really out of space if the new frame is of
  477. * a different priority, but we want the same behaviour
  478. * so return -ENOSPC anyway.
  479. *
  480. * XXX: The old AMPDU code did this, but is it really
  481. * necessary?
  482. */
  483. first = skb_peek(&session->skb_list);
  484. if (p->priority != first->priority)
  485. return -ENOSPC;
  486. }
  487. /*
  488. * Now that we're sure this frame can be accomodated, update the
  489. * session information.
  490. */
  491. session->ampdu_len += len;
  492. session->dma_len += p->len;
  493. tid = (u8)p->priority;
  494. /* Handle retry limits */
  495. if (txrate[0].count <= ampdu->rr_retry_limit_tid[tid]) {
  496. txrate[0].count++;
  497. rr = true;
  498. } else {
  499. txrate[1].count++;
  500. rr = false;
  501. }
  502. if (ampdu_frames == 0) {
  503. u8 plcp0, plcp3, is40, sgi, mcs;
  504. uint fifo = le16_to_cpu(txh->TxFrameID) & TXFID_QUEUE_MASK;
  505. struct brcms_fifo_info *f = &ampdu->fifo_tb[fifo];
  506. if (rr) {
  507. plcp0 = plcp[0];
  508. plcp3 = plcp[3];
  509. } else {
  510. plcp0 = txh->FragPLCPFallback[0];
  511. plcp3 = txh->FragPLCPFallback[3];
  512. }
  513. /* Limit AMPDU size based on MCS */
  514. is40 = (plcp0 & MIMO_PLCP_40MHZ) ? 1 : 0;
  515. sgi = plcp3_issgi(plcp3) ? 1 : 0;
  516. mcs = plcp0 & ~MIMO_PLCP_40MHZ;
  517. session->max_ampdu_len = min(scb_ampdu->max_rx_ampdu_bytes,
  518. ampdu->max_txlen[mcs][is40][sgi]);
  519. session->max_ampdu_frames = scb_ampdu->max_pdu;
  520. if (mcs_2_rate(mcs, true, false) >= f->dmaxferrate) {
  521. session->max_ampdu_frames =
  522. min_t(u16, f->mcs2ampdu_table[mcs],
  523. session->max_ampdu_frames);
  524. }
  525. }
  526. /*
  527. * Treat all frames as "middle" frames of AMPDU here. First and
  528. * last frames must be fixed up after all MPDUs have been prepped.
  529. */
  530. mcl = le16_to_cpu(txh->MacTxControlLow);
  531. mcl &= ~TXC_AMPDU_MASK;
  532. mcl |= (TXC_AMPDU_MIDDLE << TXC_AMPDU_SHIFT);
  533. mcl &= ~(TXC_STARTMSDU | TXC_SENDRTS | TXC_SENDCTS);
  534. txh->MacTxControlLow = cpu_to_le16(mcl);
  535. txh->PreloadSize = 0; /* always default to 0 */
  536. skb_queue_tail(&session->skb_list, p);
  537. return 0;
  538. }
  539. void brcms_c_ampdu_finalize(struct brcms_ampdu_session *session)
  540. {
  541. struct brcms_c_info *wlc = session->wlc;
  542. struct ampdu_info *ampdu = wlc->ampdu;
  543. struct sk_buff *first, *last;
  544. struct d11txh *txh;
  545. struct ieee80211_tx_info *tx_info;
  546. struct ieee80211_tx_rate *txrate;
  547. u8 ndelim;
  548. u8 *plcp;
  549. uint len;
  550. uint fifo;
  551. struct brcms_fifo_info *f;
  552. u16 mcl;
  553. bool fbr;
  554. bool fbr_iscck;
  555. struct ieee80211_rts *rts;
  556. bool use_rts = false, use_cts = false;
  557. u16 dma_len = session->dma_len;
  558. u16 mimo_ctlchbw = PHY_TXC1_BW_20MHZ;
  559. u32 rspec = 0, rspec_fallback = 0;
  560. u32 rts_rspec = 0, rts_rspec_fallback = 0;
  561. u8 plcp0, plcp3, is40, sgi, mcs;
  562. u16 mch;
  563. u8 preamble_type = BRCMS_GF_PREAMBLE;
  564. u8 fbr_preamble_type = BRCMS_GF_PREAMBLE;
  565. u8 rts_preamble_type = BRCMS_LONG_PREAMBLE;
  566. u8 rts_fbr_preamble_type = BRCMS_LONG_PREAMBLE;
  567. if (skb_queue_empty(&session->skb_list))
  568. return;
  569. first = skb_peek(&session->skb_list);
  570. last = skb_peek_tail(&session->skb_list);
  571. /* Need to fix up last MPDU first to adjust AMPDU length */
  572. txh = (struct d11txh *)last->data;
  573. fifo = le16_to_cpu(txh->TxFrameID) & TXFID_QUEUE_MASK;
  574. f = &ampdu->fifo_tb[fifo];
  575. mcl = le16_to_cpu(txh->MacTxControlLow);
  576. mcl &= ~TXC_AMPDU_MASK;
  577. mcl |= (TXC_AMPDU_LAST << TXC_AMPDU_SHIFT);
  578. txh->MacTxControlLow = cpu_to_le16(mcl);
  579. /* remove the null delimiter after last mpdu */
  580. ndelim = txh->RTSPLCPFallback[AMPDU_FBR_NULL_DELIM];
  581. txh->RTSPLCPFallback[AMPDU_FBR_NULL_DELIM] = 0;
  582. session->ampdu_len -= ndelim * AMPDU_DELIMITER_LEN;
  583. /* remove the pad len from last mpdu */
  584. fbr_iscck = ((le16_to_cpu(txh->XtraFrameTypes) & 0x3) == 0);
  585. len = fbr_iscck ? BRCMS_GET_CCK_PLCP_LEN(txh->FragPLCPFallback) :
  586. BRCMS_GET_MIMO_PLCP_LEN(txh->FragPLCPFallback);
  587. session->ampdu_len -= roundup(len, 4) - len;
  588. /* Now fix up the first MPDU */
  589. tx_info = IEEE80211_SKB_CB(first);
  590. txrate = tx_info->status.rates;
  591. txh = (struct d11txh *)first->data;
  592. plcp = (u8 *)(txh + 1);
  593. rts = (struct ieee80211_rts *)&txh->rts_frame;
  594. mcl = le16_to_cpu(txh->MacTxControlLow);
  595. /* If only one MPDU leave it marked as last */
  596. if (first != last) {
  597. mcl &= ~TXC_AMPDU_MASK;
  598. mcl |= (TXC_AMPDU_FIRST << TXC_AMPDU_SHIFT);
  599. }
  600. mcl |= TXC_STARTMSDU;
  601. if (ieee80211_is_rts(rts->frame_control)) {
  602. mcl |= TXC_SENDRTS;
  603. use_rts = true;
  604. }
  605. if (ieee80211_is_cts(rts->frame_control)) {
  606. mcl |= TXC_SENDCTS;
  607. use_cts = true;
  608. }
  609. txh->MacTxControlLow = cpu_to_le16(mcl);
  610. fbr = txrate[1].count > 0;
  611. if (!fbr) {
  612. plcp0 = plcp[0];
  613. plcp3 = plcp[3];
  614. } else {
  615. plcp0 = txh->FragPLCPFallback[0];
  616. plcp3 = txh->FragPLCPFallback[3];
  617. }
  618. is40 = (plcp0 & MIMO_PLCP_40MHZ) ? 1 : 0;
  619. sgi = plcp3_issgi(plcp3) ? 1 : 0;
  620. mcs = plcp0 & ~MIMO_PLCP_40MHZ;
  621. if (is40) {
  622. if (CHSPEC_SB_UPPER(wlc_phy_chanspec_get(wlc->band->pi)))
  623. mimo_ctlchbw = PHY_TXC1_BW_20MHZ_UP;
  624. else
  625. mimo_ctlchbw = PHY_TXC1_BW_20MHZ;
  626. }
  627. /* rebuild the rspec and rspec_fallback */
  628. rspec = RSPEC_MIMORATE;
  629. rspec |= plcp[0] & ~MIMO_PLCP_40MHZ;
  630. if (plcp[0] & MIMO_PLCP_40MHZ)
  631. rspec |= (PHY_TXC1_BW_40MHZ << RSPEC_BW_SHIFT);
  632. fbr_iscck = !(le16_to_cpu(txh->XtraFrameTypes) & 0x03);
  633. if (fbr_iscck) {
  634. rspec_fallback =
  635. cck_rspec(cck_phy2mac_rate(txh->FragPLCPFallback[0]));
  636. } else {
  637. rspec_fallback = RSPEC_MIMORATE;
  638. rspec_fallback |= txh->FragPLCPFallback[0] & ~MIMO_PLCP_40MHZ;
  639. if (txh->FragPLCPFallback[0] & MIMO_PLCP_40MHZ)
  640. rspec_fallback |= PHY_TXC1_BW_40MHZ << RSPEC_BW_SHIFT;
  641. }
  642. if (use_rts || use_cts) {
  643. rts_rspec =
  644. brcms_c_rspec_to_rts_rspec(wlc, rspec,
  645. false, mimo_ctlchbw);
  646. rts_rspec_fallback =
  647. brcms_c_rspec_to_rts_rspec(wlc, rspec_fallback,
  648. false, mimo_ctlchbw);
  649. }
  650. BRCMS_SET_MIMO_PLCP_LEN(plcp, session->ampdu_len);
  651. /* mark plcp to indicate ampdu */
  652. BRCMS_SET_MIMO_PLCP_AMPDU(plcp);
  653. /* reset the mixed mode header durations */
  654. if (txh->MModeLen) {
  655. u16 mmodelen = brcms_c_calc_lsig_len(wlc, rspec,
  656. session->ampdu_len);
  657. txh->MModeLen = cpu_to_le16(mmodelen);
  658. preamble_type = BRCMS_MM_PREAMBLE;
  659. }
  660. if (txh->MModeFbrLen) {
  661. u16 mmfbrlen = brcms_c_calc_lsig_len(wlc, rspec_fallback,
  662. session->ampdu_len);
  663. txh->MModeFbrLen = cpu_to_le16(mmfbrlen);
  664. fbr_preamble_type = BRCMS_MM_PREAMBLE;
  665. }
  666. /* set the preload length */
  667. if (mcs_2_rate(mcs, true, false) >= f->dmaxferrate) {
  668. dma_len = min(dma_len, f->ampdu_pld_size);
  669. txh->PreloadSize = cpu_to_le16(dma_len);
  670. } else {
  671. txh->PreloadSize = 0;
  672. }
  673. mch = le16_to_cpu(txh->MacTxControlHigh);
  674. /* update RTS dur fields */
  675. if (use_rts || use_cts) {
  676. u16 durid;
  677. if ((mch & TXC_PREAMBLE_RTS_MAIN_SHORT) ==
  678. TXC_PREAMBLE_RTS_MAIN_SHORT)
  679. rts_preamble_type = BRCMS_SHORT_PREAMBLE;
  680. if ((mch & TXC_PREAMBLE_RTS_FB_SHORT) ==
  681. TXC_PREAMBLE_RTS_FB_SHORT)
  682. rts_fbr_preamble_type = BRCMS_SHORT_PREAMBLE;
  683. durid = brcms_c_compute_rtscts_dur(wlc, use_cts, rts_rspec,
  684. rspec, rts_preamble_type,
  685. preamble_type,
  686. session->ampdu_len, true);
  687. rts->duration = cpu_to_le16(durid);
  688. durid = brcms_c_compute_rtscts_dur(wlc, use_cts,
  689. rts_rspec_fallback,
  690. rspec_fallback,
  691. rts_fbr_preamble_type,
  692. fbr_preamble_type,
  693. session->ampdu_len, true);
  694. txh->RTSDurFallback = cpu_to_le16(durid);
  695. /* set TxFesTimeNormal */
  696. txh->TxFesTimeNormal = rts->duration;
  697. /* set fallback rate version of TxFesTimeNormal */
  698. txh->TxFesTimeFallback = txh->RTSDurFallback;
  699. }
  700. /* set flag and plcp for fallback rate */
  701. if (fbr) {
  702. mch |= TXC_AMPDU_FBR;
  703. txh->MacTxControlHigh = cpu_to_le16(mch);
  704. BRCMS_SET_MIMO_PLCP_AMPDU(plcp);
  705. BRCMS_SET_MIMO_PLCP_AMPDU(txh->FragPLCPFallback);
  706. }
  707. brcms_dbg_ht(wlc->hw->d11core, "wl%d: count %d ampdu_len %d\n",
  708. wlc->pub->unit, skb_queue_len(&session->skb_list),
  709. session->ampdu_len);
  710. }
  711. static void
  712. brcms_c_ampdu_rate_status(struct brcms_c_info *wlc,
  713. struct ieee80211_tx_info *tx_info,
  714. struct tx_status *txs, u8 mcs)
  715. {
  716. struct ieee80211_tx_rate *txrate = tx_info->status.rates;
  717. int i;
  718. /* clear the rest of the rates */
  719. for (i = 2; i < IEEE80211_TX_MAX_RATES; i++) {
  720. txrate[i].idx = -1;
  721. txrate[i].count = 0;
  722. }
  723. }
  724. static void
  725. brcms_c_ampdu_dotxstatus_complete(struct ampdu_info *ampdu, struct scb *scb,
  726. struct sk_buff *p, struct tx_status *txs,
  727. u32 s1, u32 s2)
  728. {
  729. struct scb_ampdu *scb_ampdu;
  730. struct brcms_c_info *wlc = ampdu->wlc;
  731. struct scb_ampdu_tid_ini *ini;
  732. u8 bitmap[8], queue, tid;
  733. struct d11txh *txh;
  734. u8 *plcp;
  735. struct ieee80211_hdr *h;
  736. u16 seq, start_seq = 0, bindex, index, mcl;
  737. u8 mcs = 0;
  738. bool ba_recd = false, ack_recd = false;
  739. u8 suc_mpdu = 0, tot_mpdu = 0;
  740. uint supr_status;
  741. bool update_rate = true, retry = true, tx_error = false;
  742. u16 mimoantsel = 0;
  743. u8 antselid = 0;
  744. u8 retry_limit, rr_retry_limit;
  745. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(p);
  746. #ifdef DEBUG
  747. u8 hole[AMPDU_MAX_MPDU];
  748. memset(hole, 0, sizeof(hole));
  749. #endif
  750. scb_ampdu = &scb->scb_ampdu;
  751. tid = (u8) (p->priority);
  752. ini = &scb_ampdu->ini[tid];
  753. retry_limit = ampdu->retry_limit_tid[tid];
  754. rr_retry_limit = ampdu->rr_retry_limit_tid[tid];
  755. memset(bitmap, 0, sizeof(bitmap));
  756. queue = txs->frameid & TXFID_QUEUE_MASK;
  757. supr_status = txs->status & TX_STATUS_SUPR_MASK;
  758. if (txs->status & TX_STATUS_ACK_RCV) {
  759. if (TX_STATUS_SUPR_UF == supr_status)
  760. update_rate = false;
  761. WARN_ON(!(txs->status & TX_STATUS_INTERMEDIATE));
  762. start_seq = txs->sequence >> SEQNUM_SHIFT;
  763. bitmap[0] = (txs->status & TX_STATUS_BA_BMAP03_MASK) >>
  764. TX_STATUS_BA_BMAP03_SHIFT;
  765. WARN_ON(s1 & TX_STATUS_INTERMEDIATE);
  766. WARN_ON(!(s1 & TX_STATUS_AMPDU));
  767. bitmap[0] |=
  768. (s1 & TX_STATUS_BA_BMAP47_MASK) <<
  769. TX_STATUS_BA_BMAP47_SHIFT;
  770. bitmap[1] = (s1 >> 8) & 0xff;
  771. bitmap[2] = (s1 >> 16) & 0xff;
  772. bitmap[3] = (s1 >> 24) & 0xff;
  773. bitmap[4] = s2 & 0xff;
  774. bitmap[5] = (s2 >> 8) & 0xff;
  775. bitmap[6] = (s2 >> 16) & 0xff;
  776. bitmap[7] = (s2 >> 24) & 0xff;
  777. ba_recd = true;
  778. } else {
  779. if (supr_status) {
  780. update_rate = false;
  781. if (supr_status == TX_STATUS_SUPR_BADCH) {
  782. brcms_dbg_ht(wlc->hw->d11core,
  783. "%s: Pkt tx suppressed, illegal channel possibly %d\n",
  784. __func__, CHSPEC_CHANNEL(
  785. wlc->default_bss->chanspec));
  786. } else {
  787. if (supr_status != TX_STATUS_SUPR_FRAG)
  788. brcms_err(wlc->hw->d11core,
  789. "%s: supr_status 0x%x\n",
  790. __func__, supr_status);
  791. }
  792. /* no need to retry for badch; will fail again */
  793. if (supr_status == TX_STATUS_SUPR_BADCH ||
  794. supr_status == TX_STATUS_SUPR_EXPTIME) {
  795. retry = false;
  796. } else if (supr_status == TX_STATUS_SUPR_EXPTIME) {
  797. /* TX underflow:
  798. * try tuning pre-loading or ampdu size
  799. */
  800. } else if (supr_status == TX_STATUS_SUPR_FRAG) {
  801. /*
  802. * if there were underflows, but pre-loading
  803. * is not active, notify rate adaptation.
  804. */
  805. if (brcms_c_ffpld_check_txfunfl(wlc, queue) > 0)
  806. tx_error = true;
  807. }
  808. } else if (txs->phyerr) {
  809. update_rate = false;
  810. brcms_dbg_ht(wlc->hw->d11core,
  811. "%s: ampdu tx phy error (0x%x)\n",
  812. __func__, txs->phyerr);
  813. }
  814. }
  815. /* loop through all pkts and retry if not acked */
  816. while (p) {
  817. tx_info = IEEE80211_SKB_CB(p);
  818. txh = (struct d11txh *) p->data;
  819. mcl = le16_to_cpu(txh->MacTxControlLow);
  820. plcp = (u8 *) (txh + 1);
  821. h = (struct ieee80211_hdr *)(plcp + D11_PHY_HDR_LEN);
  822. seq = le16_to_cpu(h->seq_ctrl) >> SEQNUM_SHIFT;
  823. trace_brcms_txdesc(&wlc->hw->d11core->dev, txh, sizeof(*txh));
  824. if (tot_mpdu == 0) {
  825. mcs = plcp[0] & MIMO_PLCP_MCS_MASK;
  826. mimoantsel = le16_to_cpu(txh->ABI_MimoAntSel);
  827. }
  828. index = TX_SEQ_TO_INDEX(seq);
  829. ack_recd = false;
  830. if (ba_recd) {
  831. bindex = MODSUB_POW2(seq, start_seq, SEQNUM_MAX);
  832. brcms_dbg_ht(wlc->hw->d11core,
  833. "tid %d seq %d, start_seq %d, bindex %d set %d, index %d\n",
  834. tid, seq, start_seq, bindex,
  835. isset(bitmap, bindex), index);
  836. /* if acked then clear bit and free packet */
  837. if ((bindex < AMPDU_TX_BA_MAX_WSIZE)
  838. && isset(bitmap, bindex)) {
  839. ini->txretry[index] = 0;
  840. /*
  841. * ampdu_ack_len:
  842. * number of acked aggregated frames
  843. */
  844. /* ampdu_len: number of aggregated frames */
  845. brcms_c_ampdu_rate_status(wlc, tx_info, txs,
  846. mcs);
  847. tx_info->flags |= IEEE80211_TX_STAT_ACK;
  848. tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
  849. tx_info->status.ampdu_ack_len =
  850. tx_info->status.ampdu_len = 1;
  851. skb_pull(p, D11_PHY_HDR_LEN);
  852. skb_pull(p, D11_TXH_LEN);
  853. ieee80211_tx_status_irqsafe(wlc->pub->ieee_hw,
  854. p);
  855. ack_recd = true;
  856. suc_mpdu++;
  857. }
  858. }
  859. /* either retransmit or send bar if ack not recd */
  860. if (!ack_recd) {
  861. if (retry && (ini->txretry[index] < (int)retry_limit)) {
  862. int ret;
  863. ini->txretry[index]++;
  864. ret = brcms_c_txfifo(wlc, queue, p);
  865. /*
  866. * We shouldn't be out of space in the DMA
  867. * ring here since we're reinserting a frame
  868. * that was just pulled out.
  869. */
  870. WARN_ONCE(ret, "queue %d out of txds\n", queue);
  871. } else {
  872. /* Retry timeout */
  873. ieee80211_tx_info_clear_status(tx_info);
  874. tx_info->status.ampdu_ack_len = 0;
  875. tx_info->status.ampdu_len = 1;
  876. tx_info->flags |=
  877. IEEE80211_TX_STAT_AMPDU_NO_BACK;
  878. skb_pull(p, D11_PHY_HDR_LEN);
  879. skb_pull(p, D11_TXH_LEN);
  880. brcms_dbg_ht(wlc->hw->d11core,
  881. "BA Timeout, seq %d\n",
  882. seq);
  883. ieee80211_tx_status_irqsafe(wlc->pub->ieee_hw,
  884. p);
  885. }
  886. }
  887. tot_mpdu++;
  888. /* break out if last packet of ampdu */
  889. if (((mcl & TXC_AMPDU_MASK) >> TXC_AMPDU_SHIFT) ==
  890. TXC_AMPDU_LAST)
  891. break;
  892. p = dma_getnexttxp(wlc->hw->di[queue], DMA_RANGE_TRANSMITTED);
  893. }
  894. /* update rate state */
  895. antselid = brcms_c_antsel_antsel2id(wlc->asi, mimoantsel);
  896. }
  897. void
  898. brcms_c_ampdu_dotxstatus(struct ampdu_info *ampdu, struct scb *scb,
  899. struct sk_buff *p, struct tx_status *txs)
  900. {
  901. struct scb_ampdu *scb_ampdu;
  902. struct brcms_c_info *wlc = ampdu->wlc;
  903. struct scb_ampdu_tid_ini *ini;
  904. u32 s1 = 0, s2 = 0;
  905. struct ieee80211_tx_info *tx_info;
  906. tx_info = IEEE80211_SKB_CB(p);
  907. /* BMAC_NOTE: For the split driver, second level txstatus comes later
  908. * So if the ACK was received then wait for the second level else just
  909. * call the first one
  910. */
  911. if (txs->status & TX_STATUS_ACK_RCV) {
  912. u8 status_delay = 0;
  913. /* wait till the next 8 bytes of txstatus is available */
  914. s1 = bcma_read32(wlc->hw->d11core, D11REGOFFS(frmtxstatus));
  915. while ((s1 & TXS_V) == 0) {
  916. udelay(1);
  917. status_delay++;
  918. if (status_delay > 10)
  919. return; /* error condition */
  920. s1 = bcma_read32(wlc->hw->d11core,
  921. D11REGOFFS(frmtxstatus));
  922. }
  923. s2 = bcma_read32(wlc->hw->d11core, D11REGOFFS(frmtxstatus2));
  924. }
  925. if (scb) {
  926. scb_ampdu = &scb->scb_ampdu;
  927. ini = &scb_ampdu->ini[p->priority];
  928. brcms_c_ampdu_dotxstatus_complete(ampdu, scb, p, txs, s1, s2);
  929. } else {
  930. /* loop through all pkts and free */
  931. u8 queue = txs->frameid & TXFID_QUEUE_MASK;
  932. struct d11txh *txh;
  933. u16 mcl;
  934. while (p) {
  935. tx_info = IEEE80211_SKB_CB(p);
  936. txh = (struct d11txh *) p->data;
  937. trace_brcms_txdesc(&wlc->hw->d11core->dev, txh,
  938. sizeof(*txh));
  939. mcl = le16_to_cpu(txh->MacTxControlLow);
  940. brcmu_pkt_buf_free_skb(p);
  941. /* break out if last packet of ampdu */
  942. if (((mcl & TXC_AMPDU_MASK) >> TXC_AMPDU_SHIFT) ==
  943. TXC_AMPDU_LAST)
  944. break;
  945. p = dma_getnexttxp(wlc->hw->di[queue],
  946. DMA_RANGE_TRANSMITTED);
  947. }
  948. }
  949. }
  950. void brcms_c_ampdu_macaddr_upd(struct brcms_c_info *wlc)
  951. {
  952. char template[T_RAM_ACCESS_SZ * 2];
  953. /* driver needs to write the ta in the template; ta is at offset 16 */
  954. memset(template, 0, sizeof(template));
  955. memcpy(template, wlc->pub->cur_etheraddr, ETH_ALEN);
  956. brcms_b_write_template_ram(wlc->hw, (T_BA_TPL_BASE + 16),
  957. (T_RAM_ACCESS_SZ * 2),
  958. template);
  959. }
  960. bool brcms_c_aggregatable(struct brcms_c_info *wlc, u8 tid)
  961. {
  962. return wlc->ampdu->ini_enable[tid];
  963. }
  964. void brcms_c_ampdu_shm_upd(struct ampdu_info *ampdu)
  965. {
  966. struct brcms_c_info *wlc = ampdu->wlc;
  967. /*
  968. * Extend ucode internal watchdog timer to
  969. * match larger received frames
  970. */
  971. if ((ampdu->rx_factor & IEEE80211_HT_AMPDU_PARM_FACTOR) ==
  972. IEEE80211_HT_MAX_AMPDU_64K) {
  973. brcms_b_write_shm(wlc->hw, M_MIMO_MAXSYM, MIMO_MAXSYM_MAX);
  974. brcms_b_write_shm(wlc->hw, M_WATCHDOG_8TU, WATCHDOG_8TU_MAX);
  975. } else {
  976. brcms_b_write_shm(wlc->hw, M_MIMO_MAXSYM, MIMO_MAXSYM_DEF);
  977. brcms_b_write_shm(wlc->hw, M_WATCHDOG_8TU, WATCHDOG_8TU_DEF);
  978. }
  979. }
  980. /*
  981. * callback function that helps invalidating ampdu packets in a DMA queue
  982. */
  983. static void dma_cb_fn_ampdu(void *txi, void *arg_a)
  984. {
  985. struct ieee80211_sta *sta = arg_a;
  986. struct ieee80211_tx_info *tx_info = (struct ieee80211_tx_info *)txi;
  987. if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) &&
  988. (tx_info->rate_driver_data[0] == sta || sta == NULL))
  989. tx_info->rate_driver_data[0] = NULL;
  990. }
  991. /*
  992. * When a remote party is no longer available for ampdu communication, any
  993. * pending tx ampdu packets in the driver have to be flushed.
  994. */
  995. void brcms_c_ampdu_flush(struct brcms_c_info *wlc,
  996. struct ieee80211_sta *sta, u16 tid)
  997. {
  998. brcms_c_inval_dma_pkts(wlc->hw, sta, dma_cb_fn_ampdu);
  999. }