hw.c 6.4 KB

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  1. /*
  2. * Copyright (c) 2009 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/export.h>
  17. #include <asm/unaligned.h>
  18. #include "ath.h"
  19. #include "reg.h"
  20. #define REG_READ (common->ops->read)
  21. #define REG_WRITE(_ah, _reg, _val) (common->ops->write)(_ah, _val, _reg)
  22. /**
  23. * ath_hw_set_bssid_mask - filter out bssids we listen
  24. *
  25. * @common: the ath_common struct for the device.
  26. *
  27. * BSSID masking is a method used by AR5212 and newer hardware to inform PCU
  28. * which bits of the interface's MAC address should be looked at when trying
  29. * to decide which packets to ACK. In station mode and AP mode with a single
  30. * BSS every bit matters since we lock to only one BSS. In AP mode with
  31. * multiple BSSes (virtual interfaces) not every bit matters because hw must
  32. * accept frames for all BSSes and so we tweak some bits of our mac address
  33. * in order to have multiple BSSes.
  34. *
  35. * NOTE: This is a simple filter and does *not* filter out all
  36. * relevant frames. Some frames that are not for us might get ACKed from us
  37. * by PCU because they just match the mask.
  38. *
  39. * When handling multiple BSSes you can get the BSSID mask by computing the
  40. * set of ~ ( MAC XOR BSSID ) for all bssids we handle.
  41. *
  42. * When you do this you are essentially computing the common bits of all your
  43. * BSSes. Later it is assumed the hardware will "and" (&) the BSSID mask with
  44. * the MAC address to obtain the relevant bits and compare the result with
  45. * (frame's BSSID & mask) to see if they match.
  46. *
  47. * Simple example: on your card you have have two BSSes you have created with
  48. * BSSID-01 and BSSID-02. Lets assume BSSID-01 will not use the MAC address.
  49. * There is another BSSID-03 but you are not part of it. For simplicity's sake,
  50. * assuming only 4 bits for a mac address and for BSSIDs you can then have:
  51. *
  52. * \
  53. * MAC: 0001 |
  54. * BSSID-01: 0100 | --> Belongs to us
  55. * BSSID-02: 1001 |
  56. * /
  57. * -------------------
  58. * BSSID-03: 0110 | --> External
  59. * -------------------
  60. *
  61. * Our bssid_mask would then be:
  62. *
  63. * On loop iteration for BSSID-01:
  64. * ~(0001 ^ 0100) -> ~(0101)
  65. * -> 1010
  66. * bssid_mask = 1010
  67. *
  68. * On loop iteration for BSSID-02:
  69. * bssid_mask &= ~(0001 ^ 1001)
  70. * bssid_mask = (1010) & ~(0001 ^ 1001)
  71. * bssid_mask = (1010) & ~(1000)
  72. * bssid_mask = (1010) & (0111)
  73. * bssid_mask = 0010
  74. *
  75. * A bssid_mask of 0010 means "only pay attention to the second least
  76. * significant bit". This is because its the only bit common
  77. * amongst the MAC and all BSSIDs we support. To findout what the real
  78. * common bit is we can simply "&" the bssid_mask now with any BSSID we have
  79. * or our MAC address (we assume the hardware uses the MAC address).
  80. *
  81. * Now, suppose there's an incoming frame for BSSID-03:
  82. *
  83. * IFRAME-01: 0110
  84. *
  85. * An easy eye-inspeciton of this already should tell you that this frame
  86. * will not pass our check. This is because the bssid_mask tells the
  87. * hardware to only look at the second least significant bit and the
  88. * common bit amongst the MAC and BSSIDs is 0, this frame has the 2nd LSB
  89. * as 1, which does not match 0.
  90. *
  91. * So with IFRAME-01 we *assume* the hardware will do:
  92. *
  93. * allow = (IFRAME-01 & bssid_mask) == (bssid_mask & MAC) ? 1 : 0;
  94. * --> allow = (0110 & 0010) == (0010 & 0001) ? 1 : 0;
  95. * --> allow = (0010) == 0000 ? 1 : 0;
  96. * --> allow = 0
  97. *
  98. * Lets now test a frame that should work:
  99. *
  100. * IFRAME-02: 0001 (we should allow)
  101. *
  102. * allow = (IFRAME-02 & bssid_mask) == (bssid_mask & MAC) ? 1 : 0;
  103. * --> allow = (0001 & 0010) == (0010 & 0001) ? 1 :0;
  104. * --> allow = (0000) == (0000)
  105. * --> allow = 1
  106. *
  107. * Other examples:
  108. *
  109. * IFRAME-03: 0100 --> allowed
  110. * IFRAME-04: 1001 --> allowed
  111. * IFRAME-05: 1101 --> allowed but its not for us!!!
  112. *
  113. */
  114. void ath_hw_setbssidmask(struct ath_common *common)
  115. {
  116. void *ah = common->ah;
  117. u32 id1;
  118. REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
  119. id1 = REG_READ(ah, AR_STA_ID1) & ~AR_STA_ID1_SADH_MASK;
  120. id1 |= get_unaligned_le16(common->macaddr + 4);
  121. REG_WRITE(ah, AR_STA_ID1, id1);
  122. REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(common->bssidmask));
  123. REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(common->bssidmask + 4));
  124. }
  125. EXPORT_SYMBOL(ath_hw_setbssidmask);
  126. /**
  127. * ath_hw_cycle_counters_update - common function to update cycle counters
  128. *
  129. * @common: the ath_common struct for the device.
  130. *
  131. * This function is used to update all cycle counters in one place.
  132. * It has to be called while holding common->cc_lock!
  133. */
  134. void ath_hw_cycle_counters_update(struct ath_common *common)
  135. {
  136. u32 cycles, busy, rx, tx;
  137. void *ah = common->ah;
  138. /* freeze */
  139. REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC);
  140. /* read */
  141. cycles = REG_READ(ah, AR_CCCNT);
  142. busy = REG_READ(ah, AR_RCCNT);
  143. rx = REG_READ(ah, AR_RFCNT);
  144. tx = REG_READ(ah, AR_TFCNT);
  145. /* clear */
  146. REG_WRITE(ah, AR_CCCNT, 0);
  147. REG_WRITE(ah, AR_RFCNT, 0);
  148. REG_WRITE(ah, AR_RCCNT, 0);
  149. REG_WRITE(ah, AR_TFCNT, 0);
  150. /* unfreeze */
  151. REG_WRITE(ah, AR_MIBC, 0);
  152. /* update all cycle counters here */
  153. common->cc_ani.cycles += cycles;
  154. common->cc_ani.rx_busy += busy;
  155. common->cc_ani.rx_frame += rx;
  156. common->cc_ani.tx_frame += tx;
  157. common->cc_survey.cycles += cycles;
  158. common->cc_survey.rx_busy += busy;
  159. common->cc_survey.rx_frame += rx;
  160. common->cc_survey.tx_frame += tx;
  161. }
  162. EXPORT_SYMBOL(ath_hw_cycle_counters_update);
  163. int32_t ath_hw_get_listen_time(struct ath_common *common)
  164. {
  165. struct ath_cycle_counters *cc = &common->cc_ani;
  166. int32_t listen_time;
  167. listen_time = (cc->cycles - cc->rx_frame - cc->tx_frame) /
  168. (common->clockrate * 1000);
  169. memset(cc, 0, sizeof(*cc));
  170. return listen_time;
  171. }
  172. EXPORT_SYMBOL(ath_hw_get_listen_time);