spectrum.c 144 KB

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  1. // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
  2. /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
  3. #include <linux/kernel.h>
  4. #include <linux/module.h>
  5. #include <linux/types.h>
  6. #include <linux/pci.h>
  7. #include <linux/netdevice.h>
  8. #include <linux/etherdevice.h>
  9. #include <linux/ethtool.h>
  10. #include <linux/slab.h>
  11. #include <linux/device.h>
  12. #include <linux/skbuff.h>
  13. #include <linux/if_vlan.h>
  14. #include <linux/if_bridge.h>
  15. #include <linux/workqueue.h>
  16. #include <linux/jiffies.h>
  17. #include <linux/bitops.h>
  18. #include <linux/list.h>
  19. #include <linux/notifier.h>
  20. #include <linux/dcbnl.h>
  21. #include <linux/inetdevice.h>
  22. #include <linux/netlink.h>
  23. #include <net/switchdev.h>
  24. #include <net/pkt_cls.h>
  25. #include <net/tc_act/tc_mirred.h>
  26. #include <net/netevent.h>
  27. #include <net/tc_act/tc_sample.h>
  28. #include <net/addrconf.h>
  29. #include "spectrum.h"
  30. #include "pci.h"
  31. #include "core.h"
  32. #include "reg.h"
  33. #include "port.h"
  34. #include "trap.h"
  35. #include "txheader.h"
  36. #include "spectrum_cnt.h"
  37. #include "spectrum_dpipe.h"
  38. #include "spectrum_acl_flex_actions.h"
  39. #include "spectrum_span.h"
  40. #include "../mlxfw/mlxfw.h"
  41. #define MLXSW_SP_FWREV_MINOR_TO_BRANCH(minor) ((minor) / 100)
  42. #define MLXSW_SP1_FWREV_MAJOR 13
  43. #define MLXSW_SP1_FWREV_MINOR 1703
  44. #define MLXSW_SP1_FWREV_SUBMINOR 4
  45. #define MLXSW_SP1_FWREV_CAN_RESET_MINOR 1702
  46. static const struct mlxsw_fw_rev mlxsw_sp1_fw_rev = {
  47. .major = MLXSW_SP1_FWREV_MAJOR,
  48. .minor = MLXSW_SP1_FWREV_MINOR,
  49. .subminor = MLXSW_SP1_FWREV_SUBMINOR,
  50. .can_reset_minor = MLXSW_SP1_FWREV_CAN_RESET_MINOR,
  51. };
  52. #define MLXSW_SP1_FW_FILENAME \
  53. "mellanox/mlxsw_spectrum-" __stringify(MLXSW_SP1_FWREV_MAJOR) \
  54. "." __stringify(MLXSW_SP1_FWREV_MINOR) \
  55. "." __stringify(MLXSW_SP1_FWREV_SUBMINOR) ".mfa2"
  56. static const char mlxsw_sp1_driver_name[] = "mlxsw_spectrum";
  57. static const char mlxsw_sp2_driver_name[] = "mlxsw_spectrum2";
  58. static const char mlxsw_sp_driver_version[] = "1.0";
  59. /* tx_hdr_version
  60. * Tx header version.
  61. * Must be set to 1.
  62. */
  63. MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
  64. /* tx_hdr_ctl
  65. * Packet control type.
  66. * 0 - Ethernet control (e.g. EMADs, LACP)
  67. * 1 - Ethernet data
  68. */
  69. MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
  70. /* tx_hdr_proto
  71. * Packet protocol type. Must be set to 1 (Ethernet).
  72. */
  73. MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
  74. /* tx_hdr_rx_is_router
  75. * Packet is sent from the router. Valid for data packets only.
  76. */
  77. MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
  78. /* tx_hdr_fid_valid
  79. * Indicates if the 'fid' field is valid and should be used for
  80. * forwarding lookup. Valid for data packets only.
  81. */
  82. MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
  83. /* tx_hdr_swid
  84. * Switch partition ID. Must be set to 0.
  85. */
  86. MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
  87. /* tx_hdr_control_tclass
  88. * Indicates if the packet should use the control TClass and not one
  89. * of the data TClasses.
  90. */
  91. MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
  92. /* tx_hdr_etclass
  93. * Egress TClass to be used on the egress device on the egress port.
  94. */
  95. MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
  96. /* tx_hdr_port_mid
  97. * Destination local port for unicast packets.
  98. * Destination multicast ID for multicast packets.
  99. *
  100. * Control packets are directed to a specific egress port, while data
  101. * packets are transmitted through the CPU port (0) into the switch partition,
  102. * where forwarding rules are applied.
  103. */
  104. MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
  105. /* tx_hdr_fid
  106. * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
  107. * set, otherwise calculated based on the packet's VID using VID to FID mapping.
  108. * Valid for data packets only.
  109. */
  110. MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
  111. /* tx_hdr_type
  112. * 0 - Data packets
  113. * 6 - Control packets
  114. */
  115. MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
  116. struct mlxsw_sp_mlxfw_dev {
  117. struct mlxfw_dev mlxfw_dev;
  118. struct mlxsw_sp *mlxsw_sp;
  119. };
  120. static int mlxsw_sp_component_query(struct mlxfw_dev *mlxfw_dev,
  121. u16 component_index, u32 *p_max_size,
  122. u8 *p_align_bits, u16 *p_max_write_size)
  123. {
  124. struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
  125. container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
  126. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
  127. char mcqi_pl[MLXSW_REG_MCQI_LEN];
  128. int err;
  129. mlxsw_reg_mcqi_pack(mcqi_pl, component_index);
  130. err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcqi), mcqi_pl);
  131. if (err)
  132. return err;
  133. mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits,
  134. p_max_write_size);
  135. *p_align_bits = max_t(u8, *p_align_bits, 2);
  136. *p_max_write_size = min_t(u16, *p_max_write_size,
  137. MLXSW_REG_MCDA_MAX_DATA_LEN);
  138. return 0;
  139. }
  140. static int mlxsw_sp_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
  141. {
  142. struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
  143. container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
  144. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
  145. char mcc_pl[MLXSW_REG_MCC_LEN];
  146. u8 control_state;
  147. int err;
  148. mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0);
  149. err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
  150. if (err)
  151. return err;
  152. mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state);
  153. if (control_state != MLXFW_FSM_STATE_IDLE)
  154. return -EBUSY;
  155. mlxsw_reg_mcc_pack(mcc_pl,
  156. MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
  157. 0, *fwhandle, 0);
  158. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
  159. }
  160. static int mlxsw_sp_fsm_component_update(struct mlxfw_dev *mlxfw_dev,
  161. u32 fwhandle, u16 component_index,
  162. u32 component_size)
  163. {
  164. struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
  165. container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
  166. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
  167. char mcc_pl[MLXSW_REG_MCC_LEN];
  168. mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
  169. component_index, fwhandle, component_size);
  170. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
  171. }
  172. static int mlxsw_sp_fsm_block_download(struct mlxfw_dev *mlxfw_dev,
  173. u32 fwhandle, u8 *data, u16 size,
  174. u32 offset)
  175. {
  176. struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
  177. container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
  178. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
  179. char mcda_pl[MLXSW_REG_MCDA_LEN];
  180. mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data);
  181. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcda), mcda_pl);
  182. }
  183. static int mlxsw_sp_fsm_component_verify(struct mlxfw_dev *mlxfw_dev,
  184. u32 fwhandle, u16 component_index)
  185. {
  186. struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
  187. container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
  188. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
  189. char mcc_pl[MLXSW_REG_MCC_LEN];
  190. mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
  191. component_index, fwhandle, 0);
  192. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
  193. }
  194. static int mlxsw_sp_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
  195. {
  196. struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
  197. container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
  198. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
  199. char mcc_pl[MLXSW_REG_MCC_LEN];
  200. mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0,
  201. fwhandle, 0);
  202. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
  203. }
  204. static int mlxsw_sp_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
  205. enum mlxfw_fsm_state *fsm_state,
  206. enum mlxfw_fsm_state_err *fsm_state_err)
  207. {
  208. struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
  209. container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
  210. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
  211. char mcc_pl[MLXSW_REG_MCC_LEN];
  212. u8 control_state;
  213. u8 error_code;
  214. int err;
  215. mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0);
  216. err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
  217. if (err)
  218. return err;
  219. mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state);
  220. *fsm_state = control_state;
  221. *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
  222. MLXFW_FSM_STATE_ERR_MAX);
  223. return 0;
  224. }
  225. static void mlxsw_sp_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
  226. {
  227. struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
  228. container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
  229. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
  230. char mcc_pl[MLXSW_REG_MCC_LEN];
  231. mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0,
  232. fwhandle, 0);
  233. mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
  234. }
  235. static void mlxsw_sp_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
  236. {
  237. struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
  238. container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
  239. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
  240. char mcc_pl[MLXSW_REG_MCC_LEN];
  241. mlxsw_reg_mcc_pack(mcc_pl,
  242. MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
  243. fwhandle, 0);
  244. mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
  245. }
  246. static const struct mlxfw_dev_ops mlxsw_sp_mlxfw_dev_ops = {
  247. .component_query = mlxsw_sp_component_query,
  248. .fsm_lock = mlxsw_sp_fsm_lock,
  249. .fsm_component_update = mlxsw_sp_fsm_component_update,
  250. .fsm_block_download = mlxsw_sp_fsm_block_download,
  251. .fsm_component_verify = mlxsw_sp_fsm_component_verify,
  252. .fsm_activate = mlxsw_sp_fsm_activate,
  253. .fsm_query_state = mlxsw_sp_fsm_query_state,
  254. .fsm_cancel = mlxsw_sp_fsm_cancel,
  255. .fsm_release = mlxsw_sp_fsm_release
  256. };
  257. static int mlxsw_sp_firmware_flash(struct mlxsw_sp *mlxsw_sp,
  258. const struct firmware *firmware)
  259. {
  260. struct mlxsw_sp_mlxfw_dev mlxsw_sp_mlxfw_dev = {
  261. .mlxfw_dev = {
  262. .ops = &mlxsw_sp_mlxfw_dev_ops,
  263. .psid = mlxsw_sp->bus_info->psid,
  264. .psid_size = strlen(mlxsw_sp->bus_info->psid),
  265. },
  266. .mlxsw_sp = mlxsw_sp
  267. };
  268. int err;
  269. mlxsw_core_fw_flash_start(mlxsw_sp->core);
  270. err = mlxfw_firmware_flash(&mlxsw_sp_mlxfw_dev.mlxfw_dev, firmware);
  271. mlxsw_core_fw_flash_end(mlxsw_sp->core);
  272. return err;
  273. }
  274. static int mlxsw_sp_fw_rev_validate(struct mlxsw_sp *mlxsw_sp)
  275. {
  276. const struct mlxsw_fw_rev *rev = &mlxsw_sp->bus_info->fw_rev;
  277. const struct mlxsw_fw_rev *req_rev = mlxsw_sp->req_rev;
  278. const char *fw_filename = mlxsw_sp->fw_filename;
  279. const struct firmware *firmware;
  280. int err;
  281. /* Don't check if driver does not require it */
  282. if (!req_rev || !fw_filename)
  283. return 0;
  284. /* Validate driver & FW are compatible */
  285. if (rev->major != req_rev->major) {
  286. WARN(1, "Mismatch in major FW version [%d:%d] is never expected; Please contact support\n",
  287. rev->major, req_rev->major);
  288. return -EINVAL;
  289. }
  290. if (MLXSW_SP_FWREV_MINOR_TO_BRANCH(rev->minor) ==
  291. MLXSW_SP_FWREV_MINOR_TO_BRANCH(req_rev->minor) &&
  292. (rev->minor > req_rev->minor ||
  293. (rev->minor == req_rev->minor &&
  294. rev->subminor >= req_rev->subminor)))
  295. return 0;
  296. dev_info(mlxsw_sp->bus_info->dev, "The firmware version %d.%d.%d is incompatible with the driver\n",
  297. rev->major, rev->minor, rev->subminor);
  298. dev_info(mlxsw_sp->bus_info->dev, "Flashing firmware using file %s\n",
  299. fw_filename);
  300. err = request_firmware_direct(&firmware, fw_filename,
  301. mlxsw_sp->bus_info->dev);
  302. if (err) {
  303. dev_err(mlxsw_sp->bus_info->dev, "Could not request firmware file %s\n",
  304. fw_filename);
  305. return err;
  306. }
  307. err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
  308. release_firmware(firmware);
  309. if (err)
  310. dev_err(mlxsw_sp->bus_info->dev, "Could not upgrade firmware\n");
  311. /* On FW flash success, tell the caller FW reset is needed
  312. * if current FW supports it.
  313. */
  314. if (rev->minor >= req_rev->can_reset_minor)
  315. return err ? err : -EAGAIN;
  316. else
  317. return 0;
  318. }
  319. int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp,
  320. unsigned int counter_index, u64 *packets,
  321. u64 *bytes)
  322. {
  323. char mgpc_pl[MLXSW_REG_MGPC_LEN];
  324. int err;
  325. mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP,
  326. MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
  327. err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
  328. if (err)
  329. return err;
  330. if (packets)
  331. *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl);
  332. if (bytes)
  333. *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl);
  334. return 0;
  335. }
  336. static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp,
  337. unsigned int counter_index)
  338. {
  339. char mgpc_pl[MLXSW_REG_MGPC_LEN];
  340. mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR,
  341. MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
  342. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
  343. }
  344. int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp,
  345. unsigned int *p_counter_index)
  346. {
  347. int err;
  348. err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
  349. p_counter_index);
  350. if (err)
  351. return err;
  352. err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index);
  353. if (err)
  354. goto err_counter_clear;
  355. return 0;
  356. err_counter_clear:
  357. mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
  358. *p_counter_index);
  359. return err;
  360. }
  361. void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp,
  362. unsigned int counter_index)
  363. {
  364. mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
  365. counter_index);
  366. }
  367. static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
  368. const struct mlxsw_tx_info *tx_info)
  369. {
  370. char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
  371. memset(txhdr, 0, MLXSW_TXHDR_LEN);
  372. mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
  373. mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
  374. mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
  375. mlxsw_tx_hdr_swid_set(txhdr, 0);
  376. mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
  377. mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
  378. mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
  379. }
  380. enum mlxsw_reg_spms_state mlxsw_sp_stp_spms_state(u8 state)
  381. {
  382. switch (state) {
  383. case BR_STATE_FORWARDING:
  384. return MLXSW_REG_SPMS_STATE_FORWARDING;
  385. case BR_STATE_LEARNING:
  386. return MLXSW_REG_SPMS_STATE_LEARNING;
  387. case BR_STATE_LISTENING: /* fall-through */
  388. case BR_STATE_DISABLED: /* fall-through */
  389. case BR_STATE_BLOCKING:
  390. return MLXSW_REG_SPMS_STATE_DISCARDING;
  391. default:
  392. BUG();
  393. }
  394. }
  395. int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
  396. u8 state)
  397. {
  398. enum mlxsw_reg_spms_state spms_state = mlxsw_sp_stp_spms_state(state);
  399. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  400. char *spms_pl;
  401. int err;
  402. spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
  403. if (!spms_pl)
  404. return -ENOMEM;
  405. mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
  406. mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
  407. err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
  408. kfree(spms_pl);
  409. return err;
  410. }
  411. static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
  412. {
  413. char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
  414. int err;
  415. err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
  416. if (err)
  417. return err;
  418. mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
  419. return 0;
  420. }
  421. static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port,
  422. bool enable, u32 rate)
  423. {
  424. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  425. char mpsc_pl[MLXSW_REG_MPSC_LEN];
  426. mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate);
  427. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl);
  428. }
  429. static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
  430. bool is_up)
  431. {
  432. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  433. char paos_pl[MLXSW_REG_PAOS_LEN];
  434. mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
  435. is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
  436. MLXSW_PORT_ADMIN_STATUS_DOWN);
  437. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
  438. }
  439. static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
  440. unsigned char *addr)
  441. {
  442. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  443. char ppad_pl[MLXSW_REG_PPAD_LEN];
  444. mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
  445. mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
  446. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
  447. }
  448. static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
  449. {
  450. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  451. unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
  452. ether_addr_copy(addr, mlxsw_sp->base_mac);
  453. addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
  454. return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
  455. }
  456. static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
  457. {
  458. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  459. char pmtu_pl[MLXSW_REG_PMTU_LEN];
  460. int max_mtu;
  461. int err;
  462. mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
  463. mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
  464. err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
  465. if (err)
  466. return err;
  467. max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
  468. if (mtu > max_mtu)
  469. return -EINVAL;
  470. mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
  471. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
  472. }
  473. static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
  474. {
  475. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  476. char pspa_pl[MLXSW_REG_PSPA_LEN];
  477. mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sp_port->local_port);
  478. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
  479. }
  480. int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable)
  481. {
  482. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  483. char svpe_pl[MLXSW_REG_SVPE_LEN];
  484. mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
  485. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
  486. }
  487. int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
  488. bool learn_enable)
  489. {
  490. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  491. char *spvmlr_pl;
  492. int err;
  493. spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
  494. if (!spvmlr_pl)
  495. return -ENOMEM;
  496. mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
  497. learn_enable);
  498. err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
  499. kfree(spvmlr_pl);
  500. return err;
  501. }
  502. static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port,
  503. u16 vid)
  504. {
  505. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  506. char spvid_pl[MLXSW_REG_SPVID_LEN];
  507. mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid);
  508. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl);
  509. }
  510. static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port,
  511. bool allow)
  512. {
  513. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  514. char spaft_pl[MLXSW_REG_SPAFT_LEN];
  515. mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow);
  516. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl);
  517. }
  518. int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
  519. {
  520. int err;
  521. if (!vid) {
  522. err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false);
  523. if (err)
  524. return err;
  525. } else {
  526. err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid);
  527. if (err)
  528. return err;
  529. err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true);
  530. if (err)
  531. goto err_port_allow_untagged_set;
  532. }
  533. mlxsw_sp_port->pvid = vid;
  534. return 0;
  535. err_port_allow_untagged_set:
  536. __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid);
  537. return err;
  538. }
  539. static int
  540. mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
  541. {
  542. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  543. char sspr_pl[MLXSW_REG_SSPR_LEN];
  544. mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
  545. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
  546. }
  547. static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
  548. u8 local_port, u8 *p_module,
  549. u8 *p_width, u8 *p_lane)
  550. {
  551. char pmlp_pl[MLXSW_REG_PMLP_LEN];
  552. int err;
  553. mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
  554. err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
  555. if (err)
  556. return err;
  557. *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
  558. *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
  559. *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
  560. return 0;
  561. }
  562. static int mlxsw_sp_port_module_map(struct mlxsw_sp_port *mlxsw_sp_port,
  563. u8 module, u8 width, u8 lane)
  564. {
  565. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  566. char pmlp_pl[MLXSW_REG_PMLP_LEN];
  567. int i;
  568. mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
  569. mlxsw_reg_pmlp_width_set(pmlp_pl, width);
  570. for (i = 0; i < width; i++) {
  571. mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
  572. mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
  573. }
  574. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
  575. }
  576. static int mlxsw_sp_port_module_unmap(struct mlxsw_sp_port *mlxsw_sp_port)
  577. {
  578. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  579. char pmlp_pl[MLXSW_REG_PMLP_LEN];
  580. mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
  581. mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
  582. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
  583. }
  584. static int mlxsw_sp_port_open(struct net_device *dev)
  585. {
  586. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  587. int err;
  588. err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
  589. if (err)
  590. return err;
  591. netif_start_queue(dev);
  592. return 0;
  593. }
  594. static int mlxsw_sp_port_stop(struct net_device *dev)
  595. {
  596. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  597. netif_stop_queue(dev);
  598. return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
  599. }
  600. static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
  601. struct net_device *dev)
  602. {
  603. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  604. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  605. struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
  606. const struct mlxsw_tx_info tx_info = {
  607. .local_port = mlxsw_sp_port->local_port,
  608. .is_emad = false,
  609. };
  610. u64 len;
  611. int err;
  612. if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
  613. return NETDEV_TX_BUSY;
  614. if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
  615. struct sk_buff *skb_orig = skb;
  616. skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
  617. if (!skb) {
  618. this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
  619. dev_kfree_skb_any(skb_orig);
  620. return NETDEV_TX_OK;
  621. }
  622. dev_consume_skb_any(skb_orig);
  623. }
  624. if (eth_skb_pad(skb)) {
  625. this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
  626. return NETDEV_TX_OK;
  627. }
  628. mlxsw_sp_txhdr_construct(skb, &tx_info);
  629. /* TX header is consumed by HW on the way so we shouldn't count its
  630. * bytes as being sent.
  631. */
  632. len = skb->len - MLXSW_TXHDR_LEN;
  633. /* Due to a race we might fail here because of a full queue. In that
  634. * unlikely case we simply drop the packet.
  635. */
  636. err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
  637. if (!err) {
  638. pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
  639. u64_stats_update_begin(&pcpu_stats->syncp);
  640. pcpu_stats->tx_packets++;
  641. pcpu_stats->tx_bytes += len;
  642. u64_stats_update_end(&pcpu_stats->syncp);
  643. } else {
  644. this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
  645. dev_kfree_skb_any(skb);
  646. }
  647. return NETDEV_TX_OK;
  648. }
  649. static void mlxsw_sp_set_rx_mode(struct net_device *dev)
  650. {
  651. }
  652. static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
  653. {
  654. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  655. struct sockaddr *addr = p;
  656. int err;
  657. if (!is_valid_ether_addr(addr->sa_data))
  658. return -EADDRNOTAVAIL;
  659. err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
  660. if (err)
  661. return err;
  662. memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
  663. return 0;
  664. }
  665. static u16 mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp *mlxsw_sp,
  666. int mtu)
  667. {
  668. return 2 * mlxsw_sp_bytes_cells(mlxsw_sp, mtu);
  669. }
  670. #define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */
  671. static u16 mlxsw_sp_pfc_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
  672. u16 delay)
  673. {
  674. delay = mlxsw_sp_bytes_cells(mlxsw_sp, DIV_ROUND_UP(delay,
  675. BITS_PER_BYTE));
  676. return MLXSW_SP_CELL_FACTOR * delay + mlxsw_sp_bytes_cells(mlxsw_sp,
  677. mtu);
  678. }
  679. /* Maximum delay buffer needed in case of PAUSE frames, in bytes.
  680. * Assumes 100m cable and maximum MTU.
  681. */
  682. #define MLXSW_SP_PAUSE_DELAY 58752
  683. static u16 mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
  684. u16 delay, bool pfc, bool pause)
  685. {
  686. if (pfc)
  687. return mlxsw_sp_pfc_delay_get(mlxsw_sp, mtu, delay);
  688. else if (pause)
  689. return mlxsw_sp_bytes_cells(mlxsw_sp, MLXSW_SP_PAUSE_DELAY);
  690. else
  691. return 0;
  692. }
  693. static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int index, u16 size, u16 thres,
  694. bool lossy)
  695. {
  696. if (lossy)
  697. mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, index, size);
  698. else
  699. mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, index, size,
  700. thres);
  701. }
  702. int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
  703. u8 *prio_tc, bool pause_en,
  704. struct ieee_pfc *my_pfc)
  705. {
  706. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  707. u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
  708. u16 delay = !!my_pfc ? my_pfc->delay : 0;
  709. char pbmc_pl[MLXSW_REG_PBMC_LEN];
  710. int i, j, err;
  711. mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
  712. err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
  713. if (err)
  714. return err;
  715. for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
  716. bool configure = false;
  717. bool pfc = false;
  718. u16 thres_cells;
  719. u16 delay_cells;
  720. bool lossy;
  721. for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
  722. if (prio_tc[j] == i) {
  723. pfc = pfc_en & BIT(j);
  724. configure = true;
  725. break;
  726. }
  727. }
  728. if (!configure)
  729. continue;
  730. lossy = !(pfc || pause_en);
  731. thres_cells = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu);
  732. delay_cells = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay,
  733. pfc, pause_en);
  734. mlxsw_sp_pg_buf_pack(pbmc_pl, i, thres_cells + delay_cells,
  735. thres_cells, lossy);
  736. }
  737. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
  738. }
  739. static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
  740. int mtu, bool pause_en)
  741. {
  742. u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
  743. bool dcb_en = !!mlxsw_sp_port->dcb.ets;
  744. struct ieee_pfc *my_pfc;
  745. u8 *prio_tc;
  746. prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
  747. my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
  748. return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
  749. pause_en, my_pfc);
  750. }
  751. static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
  752. {
  753. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  754. bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
  755. int err;
  756. err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
  757. if (err)
  758. return err;
  759. err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu);
  760. if (err)
  761. goto err_span_port_mtu_update;
  762. err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
  763. if (err)
  764. goto err_port_mtu_set;
  765. dev->mtu = mtu;
  766. return 0;
  767. err_port_mtu_set:
  768. mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu);
  769. err_span_port_mtu_update:
  770. mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
  771. return err;
  772. }
  773. static int
  774. mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
  775. struct rtnl_link_stats64 *stats)
  776. {
  777. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  778. struct mlxsw_sp_port_pcpu_stats *p;
  779. u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
  780. u32 tx_dropped = 0;
  781. unsigned int start;
  782. int i;
  783. for_each_possible_cpu(i) {
  784. p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
  785. do {
  786. start = u64_stats_fetch_begin_irq(&p->syncp);
  787. rx_packets = p->rx_packets;
  788. rx_bytes = p->rx_bytes;
  789. tx_packets = p->tx_packets;
  790. tx_bytes = p->tx_bytes;
  791. } while (u64_stats_fetch_retry_irq(&p->syncp, start));
  792. stats->rx_packets += rx_packets;
  793. stats->rx_bytes += rx_bytes;
  794. stats->tx_packets += tx_packets;
  795. stats->tx_bytes += tx_bytes;
  796. /* tx_dropped is u32, updated without syncp protection. */
  797. tx_dropped += p->tx_dropped;
  798. }
  799. stats->tx_dropped = tx_dropped;
  800. return 0;
  801. }
  802. static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
  803. {
  804. switch (attr_id) {
  805. case IFLA_OFFLOAD_XSTATS_CPU_HIT:
  806. return true;
  807. }
  808. return false;
  809. }
  810. static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
  811. void *sp)
  812. {
  813. switch (attr_id) {
  814. case IFLA_OFFLOAD_XSTATS_CPU_HIT:
  815. return mlxsw_sp_port_get_sw_stats64(dev, sp);
  816. }
  817. return -EINVAL;
  818. }
  819. static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
  820. int prio, char *ppcnt_pl)
  821. {
  822. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  823. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  824. mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
  825. return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
  826. }
  827. static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
  828. struct rtnl_link_stats64 *stats)
  829. {
  830. char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
  831. int err;
  832. err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
  833. 0, ppcnt_pl);
  834. if (err)
  835. goto out;
  836. stats->tx_packets =
  837. mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
  838. stats->rx_packets =
  839. mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
  840. stats->tx_bytes =
  841. mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
  842. stats->rx_bytes =
  843. mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
  844. stats->multicast =
  845. mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
  846. stats->rx_crc_errors =
  847. mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
  848. stats->rx_frame_errors =
  849. mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
  850. stats->rx_length_errors = (
  851. mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
  852. mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
  853. mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
  854. stats->rx_errors = (stats->rx_crc_errors +
  855. stats->rx_frame_errors + stats->rx_length_errors);
  856. out:
  857. return err;
  858. }
  859. static void
  860. mlxsw_sp_port_get_hw_xstats(struct net_device *dev,
  861. struct mlxsw_sp_port_xstats *xstats)
  862. {
  863. char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
  864. int err, i;
  865. err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_EXT_CNT, 0,
  866. ppcnt_pl);
  867. if (!err)
  868. xstats->ecn = mlxsw_reg_ppcnt_ecn_marked_get(ppcnt_pl);
  869. for (i = 0; i < TC_MAX_QUEUE; i++) {
  870. err = mlxsw_sp_port_get_stats_raw(dev,
  871. MLXSW_REG_PPCNT_TC_CONG_TC,
  872. i, ppcnt_pl);
  873. if (!err)
  874. xstats->wred_drop[i] =
  875. mlxsw_reg_ppcnt_wred_discard_get(ppcnt_pl);
  876. err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_TC_CNT,
  877. i, ppcnt_pl);
  878. if (err)
  879. continue;
  880. xstats->backlog[i] =
  881. mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl);
  882. xstats->tail_drop[i] =
  883. mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get(ppcnt_pl);
  884. }
  885. for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
  886. err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_PRIO_CNT,
  887. i, ppcnt_pl);
  888. if (err)
  889. continue;
  890. xstats->tx_packets[i] = mlxsw_reg_ppcnt_tx_frames_get(ppcnt_pl);
  891. xstats->tx_bytes[i] = mlxsw_reg_ppcnt_tx_octets_get(ppcnt_pl);
  892. }
  893. }
  894. static void update_stats_cache(struct work_struct *work)
  895. {
  896. struct mlxsw_sp_port *mlxsw_sp_port =
  897. container_of(work, struct mlxsw_sp_port,
  898. periodic_hw_stats.update_dw.work);
  899. if (!netif_carrier_ok(mlxsw_sp_port->dev))
  900. /* Note: mlxsw_sp_port_down_wipe_counters() clears the cache as
  901. * necessary when port goes down.
  902. */
  903. goto out;
  904. mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
  905. &mlxsw_sp_port->periodic_hw_stats.stats);
  906. mlxsw_sp_port_get_hw_xstats(mlxsw_sp_port->dev,
  907. &mlxsw_sp_port->periodic_hw_stats.xstats);
  908. out:
  909. mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw,
  910. MLXSW_HW_STATS_UPDATE_TIME);
  911. }
  912. /* Return the stats from a cache that is updated periodically,
  913. * as this function might get called in an atomic context.
  914. */
  915. static void
  916. mlxsw_sp_port_get_stats64(struct net_device *dev,
  917. struct rtnl_link_stats64 *stats)
  918. {
  919. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  920. memcpy(stats, &mlxsw_sp_port->periodic_hw_stats.stats, sizeof(*stats));
  921. }
  922. static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port,
  923. u16 vid_begin, u16 vid_end,
  924. bool is_member, bool untagged)
  925. {
  926. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  927. char *spvm_pl;
  928. int err;
  929. spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
  930. if (!spvm_pl)
  931. return -ENOMEM;
  932. mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
  933. vid_end, is_member, untagged);
  934. err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
  935. kfree(spvm_pl);
  936. return err;
  937. }
  938. int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
  939. u16 vid_end, bool is_member, bool untagged)
  940. {
  941. u16 vid, vid_e;
  942. int err;
  943. for (vid = vid_begin; vid <= vid_end;
  944. vid += MLXSW_REG_SPVM_REC_MAX_COUNT) {
  945. vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1),
  946. vid_end);
  947. err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e,
  948. is_member, untagged);
  949. if (err)
  950. return err;
  951. }
  952. return 0;
  953. }
  954. static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port)
  955. {
  956. struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp;
  957. list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp,
  958. &mlxsw_sp_port->vlans_list, list)
  959. mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
  960. }
  961. static struct mlxsw_sp_port_vlan *
  962. mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
  963. {
  964. struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
  965. bool untagged = vid == 1;
  966. int err;
  967. err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged);
  968. if (err)
  969. return ERR_PTR(err);
  970. mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL);
  971. if (!mlxsw_sp_port_vlan) {
  972. err = -ENOMEM;
  973. goto err_port_vlan_alloc;
  974. }
  975. mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port;
  976. mlxsw_sp_port_vlan->ref_count = 1;
  977. mlxsw_sp_port_vlan->vid = vid;
  978. list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list);
  979. return mlxsw_sp_port_vlan;
  980. err_port_vlan_alloc:
  981. mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
  982. return ERR_PTR(err);
  983. }
  984. static void
  985. mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
  986. {
  987. struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port;
  988. u16 vid = mlxsw_sp_port_vlan->vid;
  989. list_del(&mlxsw_sp_port_vlan->list);
  990. kfree(mlxsw_sp_port_vlan);
  991. mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
  992. }
  993. struct mlxsw_sp_port_vlan *
  994. mlxsw_sp_port_vlan_get(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
  995. {
  996. struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
  997. mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
  998. if (mlxsw_sp_port_vlan) {
  999. mlxsw_sp_port_vlan->ref_count++;
  1000. return mlxsw_sp_port_vlan;
  1001. }
  1002. return mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid);
  1003. }
  1004. void mlxsw_sp_port_vlan_put(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
  1005. {
  1006. struct mlxsw_sp_fid *fid = mlxsw_sp_port_vlan->fid;
  1007. if (--mlxsw_sp_port_vlan->ref_count != 0)
  1008. return;
  1009. if (mlxsw_sp_port_vlan->bridge_port)
  1010. mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan);
  1011. else if (fid)
  1012. mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
  1013. mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
  1014. }
  1015. static int mlxsw_sp_port_add_vid(struct net_device *dev,
  1016. __be16 __always_unused proto, u16 vid)
  1017. {
  1018. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  1019. /* VLAN 0 is added to HW filter when device goes up, but it is
  1020. * reserved in our case, so simply return.
  1021. */
  1022. if (!vid)
  1023. return 0;
  1024. return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_get(mlxsw_sp_port, vid));
  1025. }
  1026. static int mlxsw_sp_port_kill_vid(struct net_device *dev,
  1027. __be16 __always_unused proto, u16 vid)
  1028. {
  1029. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  1030. struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
  1031. /* VLAN 0 is removed from HW filter when device goes down, but
  1032. * it is reserved in our case, so simply return.
  1033. */
  1034. if (!vid)
  1035. return 0;
  1036. mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
  1037. if (!mlxsw_sp_port_vlan)
  1038. return 0;
  1039. mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
  1040. return 0;
  1041. }
  1042. static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
  1043. size_t len)
  1044. {
  1045. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  1046. return mlxsw_core_port_get_phys_port_name(mlxsw_sp_port->mlxsw_sp->core,
  1047. mlxsw_sp_port->local_port,
  1048. name, len);
  1049. }
  1050. static struct mlxsw_sp_port_mall_tc_entry *
  1051. mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port,
  1052. unsigned long cookie) {
  1053. struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
  1054. list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list)
  1055. if (mall_tc_entry->cookie == cookie)
  1056. return mall_tc_entry;
  1057. return NULL;
  1058. }
  1059. static int
  1060. mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
  1061. struct mlxsw_sp_port_mall_mirror_tc_entry *mirror,
  1062. const struct tc_action *a,
  1063. bool ingress)
  1064. {
  1065. enum mlxsw_sp_span_type span_type;
  1066. struct net_device *to_dev;
  1067. to_dev = tcf_mirred_dev(a);
  1068. if (!to_dev) {
  1069. netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n");
  1070. return -EINVAL;
  1071. }
  1072. mirror->ingress = ingress;
  1073. span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
  1074. return mlxsw_sp_span_mirror_add(mlxsw_sp_port, to_dev, span_type,
  1075. true, &mirror->span_id);
  1076. }
  1077. static void
  1078. mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
  1079. struct mlxsw_sp_port_mall_mirror_tc_entry *mirror)
  1080. {
  1081. enum mlxsw_sp_span_type span_type;
  1082. span_type = mirror->ingress ?
  1083. MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
  1084. mlxsw_sp_span_mirror_del(mlxsw_sp_port, mirror->span_id,
  1085. span_type, true);
  1086. }
  1087. static int
  1088. mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port,
  1089. struct tc_cls_matchall_offload *cls,
  1090. const struct tc_action *a,
  1091. bool ingress)
  1092. {
  1093. int err;
  1094. if (!mlxsw_sp_port->sample)
  1095. return -EOPNOTSUPP;
  1096. if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) {
  1097. netdev_err(mlxsw_sp_port->dev, "sample already active\n");
  1098. return -EEXIST;
  1099. }
  1100. if (tcf_sample_rate(a) > MLXSW_REG_MPSC_RATE_MAX) {
  1101. netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n");
  1102. return -EOPNOTSUPP;
  1103. }
  1104. rcu_assign_pointer(mlxsw_sp_port->sample->psample_group,
  1105. tcf_sample_psample_group(a));
  1106. mlxsw_sp_port->sample->truncate = tcf_sample_truncate(a);
  1107. mlxsw_sp_port->sample->trunc_size = tcf_sample_trunc_size(a);
  1108. mlxsw_sp_port->sample->rate = tcf_sample_rate(a);
  1109. err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, tcf_sample_rate(a));
  1110. if (err)
  1111. goto err_port_sample_set;
  1112. return 0;
  1113. err_port_sample_set:
  1114. RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
  1115. return err;
  1116. }
  1117. static void
  1118. mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port)
  1119. {
  1120. if (!mlxsw_sp_port->sample)
  1121. return;
  1122. mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1);
  1123. RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
  1124. }
  1125. static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
  1126. struct tc_cls_matchall_offload *f,
  1127. bool ingress)
  1128. {
  1129. struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
  1130. __be16 protocol = f->common.protocol;
  1131. const struct tc_action *a;
  1132. LIST_HEAD(actions);
  1133. int err;
  1134. if (!tcf_exts_has_one_action(f->exts)) {
  1135. netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n");
  1136. return -EOPNOTSUPP;
  1137. }
  1138. mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
  1139. if (!mall_tc_entry)
  1140. return -ENOMEM;
  1141. mall_tc_entry->cookie = f->cookie;
  1142. a = tcf_exts_first_action(f->exts);
  1143. if (is_tcf_mirred_egress_mirror(a) && protocol == htons(ETH_P_ALL)) {
  1144. struct mlxsw_sp_port_mall_mirror_tc_entry *mirror;
  1145. mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR;
  1146. mirror = &mall_tc_entry->mirror;
  1147. err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port,
  1148. mirror, a, ingress);
  1149. } else if (is_tcf_sample(a) && protocol == htons(ETH_P_ALL)) {
  1150. mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE;
  1151. err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, f,
  1152. a, ingress);
  1153. } else {
  1154. err = -EOPNOTSUPP;
  1155. }
  1156. if (err)
  1157. goto err_add_action;
  1158. list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list);
  1159. return 0;
  1160. err_add_action:
  1161. kfree(mall_tc_entry);
  1162. return err;
  1163. }
  1164. static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
  1165. struct tc_cls_matchall_offload *f)
  1166. {
  1167. struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
  1168. mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port,
  1169. f->cookie);
  1170. if (!mall_tc_entry) {
  1171. netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n");
  1172. return;
  1173. }
  1174. list_del(&mall_tc_entry->list);
  1175. switch (mall_tc_entry->type) {
  1176. case MLXSW_SP_PORT_MALL_MIRROR:
  1177. mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port,
  1178. &mall_tc_entry->mirror);
  1179. break;
  1180. case MLXSW_SP_PORT_MALL_SAMPLE:
  1181. mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port);
  1182. break;
  1183. default:
  1184. WARN_ON(1);
  1185. }
  1186. kfree(mall_tc_entry);
  1187. }
  1188. static int mlxsw_sp_setup_tc_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
  1189. struct tc_cls_matchall_offload *f,
  1190. bool ingress)
  1191. {
  1192. switch (f->command) {
  1193. case TC_CLSMATCHALL_REPLACE:
  1194. return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port, f,
  1195. ingress);
  1196. case TC_CLSMATCHALL_DESTROY:
  1197. mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port, f);
  1198. return 0;
  1199. default:
  1200. return -EOPNOTSUPP;
  1201. }
  1202. }
  1203. static int
  1204. mlxsw_sp_setup_tc_cls_flower(struct mlxsw_sp_acl_block *acl_block,
  1205. struct tc_cls_flower_offload *f)
  1206. {
  1207. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_acl_block_mlxsw_sp(acl_block);
  1208. switch (f->command) {
  1209. case TC_CLSFLOWER_REPLACE:
  1210. return mlxsw_sp_flower_replace(mlxsw_sp, acl_block, f);
  1211. case TC_CLSFLOWER_DESTROY:
  1212. mlxsw_sp_flower_destroy(mlxsw_sp, acl_block, f);
  1213. return 0;
  1214. case TC_CLSFLOWER_STATS:
  1215. return mlxsw_sp_flower_stats(mlxsw_sp, acl_block, f);
  1216. case TC_CLSFLOWER_TMPLT_CREATE:
  1217. return mlxsw_sp_flower_tmplt_create(mlxsw_sp, acl_block, f);
  1218. case TC_CLSFLOWER_TMPLT_DESTROY:
  1219. mlxsw_sp_flower_tmplt_destroy(mlxsw_sp, acl_block, f);
  1220. return 0;
  1221. default:
  1222. return -EOPNOTSUPP;
  1223. }
  1224. }
  1225. static int mlxsw_sp_setup_tc_block_cb_matchall(enum tc_setup_type type,
  1226. void *type_data,
  1227. void *cb_priv, bool ingress)
  1228. {
  1229. struct mlxsw_sp_port *mlxsw_sp_port = cb_priv;
  1230. switch (type) {
  1231. case TC_SETUP_CLSMATCHALL:
  1232. if (!tc_cls_can_offload_and_chain0(mlxsw_sp_port->dev,
  1233. type_data))
  1234. return -EOPNOTSUPP;
  1235. return mlxsw_sp_setup_tc_cls_matchall(mlxsw_sp_port, type_data,
  1236. ingress);
  1237. case TC_SETUP_CLSFLOWER:
  1238. return 0;
  1239. default:
  1240. return -EOPNOTSUPP;
  1241. }
  1242. }
  1243. static int mlxsw_sp_setup_tc_block_cb_matchall_ig(enum tc_setup_type type,
  1244. void *type_data,
  1245. void *cb_priv)
  1246. {
  1247. return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
  1248. cb_priv, true);
  1249. }
  1250. static int mlxsw_sp_setup_tc_block_cb_matchall_eg(enum tc_setup_type type,
  1251. void *type_data,
  1252. void *cb_priv)
  1253. {
  1254. return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
  1255. cb_priv, false);
  1256. }
  1257. static int mlxsw_sp_setup_tc_block_cb_flower(enum tc_setup_type type,
  1258. void *type_data, void *cb_priv)
  1259. {
  1260. struct mlxsw_sp_acl_block *acl_block = cb_priv;
  1261. switch (type) {
  1262. case TC_SETUP_CLSMATCHALL:
  1263. return 0;
  1264. case TC_SETUP_CLSFLOWER:
  1265. if (mlxsw_sp_acl_block_disabled(acl_block))
  1266. return -EOPNOTSUPP;
  1267. return mlxsw_sp_setup_tc_cls_flower(acl_block, type_data);
  1268. default:
  1269. return -EOPNOTSUPP;
  1270. }
  1271. }
  1272. static int
  1273. mlxsw_sp_setup_tc_block_flower_bind(struct mlxsw_sp_port *mlxsw_sp_port,
  1274. struct tcf_block *block, bool ingress,
  1275. struct netlink_ext_ack *extack)
  1276. {
  1277. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  1278. struct mlxsw_sp_acl_block *acl_block;
  1279. struct tcf_block_cb *block_cb;
  1280. int err;
  1281. block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower,
  1282. mlxsw_sp);
  1283. if (!block_cb) {
  1284. acl_block = mlxsw_sp_acl_block_create(mlxsw_sp, block->net);
  1285. if (!acl_block)
  1286. return -ENOMEM;
  1287. block_cb = __tcf_block_cb_register(block,
  1288. mlxsw_sp_setup_tc_block_cb_flower,
  1289. mlxsw_sp, acl_block, extack);
  1290. if (IS_ERR(block_cb)) {
  1291. err = PTR_ERR(block_cb);
  1292. goto err_cb_register;
  1293. }
  1294. } else {
  1295. acl_block = tcf_block_cb_priv(block_cb);
  1296. }
  1297. tcf_block_cb_incref(block_cb);
  1298. err = mlxsw_sp_acl_block_bind(mlxsw_sp, acl_block,
  1299. mlxsw_sp_port, ingress);
  1300. if (err)
  1301. goto err_block_bind;
  1302. if (ingress)
  1303. mlxsw_sp_port->ing_acl_block = acl_block;
  1304. else
  1305. mlxsw_sp_port->eg_acl_block = acl_block;
  1306. return 0;
  1307. err_block_bind:
  1308. if (!tcf_block_cb_decref(block_cb)) {
  1309. __tcf_block_cb_unregister(block, block_cb);
  1310. err_cb_register:
  1311. mlxsw_sp_acl_block_destroy(acl_block);
  1312. }
  1313. return err;
  1314. }
  1315. static void
  1316. mlxsw_sp_setup_tc_block_flower_unbind(struct mlxsw_sp_port *mlxsw_sp_port,
  1317. struct tcf_block *block, bool ingress)
  1318. {
  1319. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  1320. struct mlxsw_sp_acl_block *acl_block;
  1321. struct tcf_block_cb *block_cb;
  1322. int err;
  1323. block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower,
  1324. mlxsw_sp);
  1325. if (!block_cb)
  1326. return;
  1327. if (ingress)
  1328. mlxsw_sp_port->ing_acl_block = NULL;
  1329. else
  1330. mlxsw_sp_port->eg_acl_block = NULL;
  1331. acl_block = tcf_block_cb_priv(block_cb);
  1332. err = mlxsw_sp_acl_block_unbind(mlxsw_sp, acl_block,
  1333. mlxsw_sp_port, ingress);
  1334. if (!err && !tcf_block_cb_decref(block_cb)) {
  1335. __tcf_block_cb_unregister(block, block_cb);
  1336. mlxsw_sp_acl_block_destroy(acl_block);
  1337. }
  1338. }
  1339. static int mlxsw_sp_setup_tc_block(struct mlxsw_sp_port *mlxsw_sp_port,
  1340. struct tc_block_offload *f)
  1341. {
  1342. tc_setup_cb_t *cb;
  1343. bool ingress;
  1344. int err;
  1345. if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) {
  1346. cb = mlxsw_sp_setup_tc_block_cb_matchall_ig;
  1347. ingress = true;
  1348. } else if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_EGRESS) {
  1349. cb = mlxsw_sp_setup_tc_block_cb_matchall_eg;
  1350. ingress = false;
  1351. } else {
  1352. return -EOPNOTSUPP;
  1353. }
  1354. switch (f->command) {
  1355. case TC_BLOCK_BIND:
  1356. err = tcf_block_cb_register(f->block, cb, mlxsw_sp_port,
  1357. mlxsw_sp_port, f->extack);
  1358. if (err)
  1359. return err;
  1360. err = mlxsw_sp_setup_tc_block_flower_bind(mlxsw_sp_port,
  1361. f->block, ingress,
  1362. f->extack);
  1363. if (err) {
  1364. tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port);
  1365. return err;
  1366. }
  1367. return 0;
  1368. case TC_BLOCK_UNBIND:
  1369. mlxsw_sp_setup_tc_block_flower_unbind(mlxsw_sp_port,
  1370. f->block, ingress);
  1371. tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port);
  1372. return 0;
  1373. default:
  1374. return -EOPNOTSUPP;
  1375. }
  1376. }
  1377. static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type,
  1378. void *type_data)
  1379. {
  1380. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  1381. switch (type) {
  1382. case TC_SETUP_BLOCK:
  1383. return mlxsw_sp_setup_tc_block(mlxsw_sp_port, type_data);
  1384. case TC_SETUP_QDISC_RED:
  1385. return mlxsw_sp_setup_tc_red(mlxsw_sp_port, type_data);
  1386. case TC_SETUP_QDISC_PRIO:
  1387. return mlxsw_sp_setup_tc_prio(mlxsw_sp_port, type_data);
  1388. default:
  1389. return -EOPNOTSUPP;
  1390. }
  1391. }
  1392. static int mlxsw_sp_feature_hw_tc(struct net_device *dev, bool enable)
  1393. {
  1394. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  1395. if (!enable) {
  1396. if (mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->ing_acl_block) ||
  1397. mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->eg_acl_block) ||
  1398. !list_empty(&mlxsw_sp_port->mall_tc_list)) {
  1399. netdev_err(dev, "Active offloaded tc filters, can't turn hw_tc_offload off\n");
  1400. return -EINVAL;
  1401. }
  1402. mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->ing_acl_block);
  1403. mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->eg_acl_block);
  1404. } else {
  1405. mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->ing_acl_block);
  1406. mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->eg_acl_block);
  1407. }
  1408. return 0;
  1409. }
  1410. typedef int (*mlxsw_sp_feature_handler)(struct net_device *dev, bool enable);
  1411. static int mlxsw_sp_handle_feature(struct net_device *dev,
  1412. netdev_features_t wanted_features,
  1413. netdev_features_t feature,
  1414. mlxsw_sp_feature_handler feature_handler)
  1415. {
  1416. netdev_features_t changes = wanted_features ^ dev->features;
  1417. bool enable = !!(wanted_features & feature);
  1418. int err;
  1419. if (!(changes & feature))
  1420. return 0;
  1421. err = feature_handler(dev, enable);
  1422. if (err) {
  1423. netdev_err(dev, "%s feature %pNF failed, err %d\n",
  1424. enable ? "Enable" : "Disable", &feature, err);
  1425. return err;
  1426. }
  1427. if (enable)
  1428. dev->features |= feature;
  1429. else
  1430. dev->features &= ~feature;
  1431. return 0;
  1432. }
  1433. static int mlxsw_sp_set_features(struct net_device *dev,
  1434. netdev_features_t features)
  1435. {
  1436. return mlxsw_sp_handle_feature(dev, features, NETIF_F_HW_TC,
  1437. mlxsw_sp_feature_hw_tc);
  1438. }
  1439. static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
  1440. .ndo_open = mlxsw_sp_port_open,
  1441. .ndo_stop = mlxsw_sp_port_stop,
  1442. .ndo_start_xmit = mlxsw_sp_port_xmit,
  1443. .ndo_setup_tc = mlxsw_sp_setup_tc,
  1444. .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
  1445. .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
  1446. .ndo_change_mtu = mlxsw_sp_port_change_mtu,
  1447. .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
  1448. .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats,
  1449. .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats,
  1450. .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
  1451. .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
  1452. .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
  1453. .ndo_set_features = mlxsw_sp_set_features,
  1454. };
  1455. static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
  1456. struct ethtool_drvinfo *drvinfo)
  1457. {
  1458. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  1459. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  1460. strlcpy(drvinfo->driver, mlxsw_sp->bus_info->device_kind,
  1461. sizeof(drvinfo->driver));
  1462. strlcpy(drvinfo->version, mlxsw_sp_driver_version,
  1463. sizeof(drvinfo->version));
  1464. snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
  1465. "%d.%d.%d",
  1466. mlxsw_sp->bus_info->fw_rev.major,
  1467. mlxsw_sp->bus_info->fw_rev.minor,
  1468. mlxsw_sp->bus_info->fw_rev.subminor);
  1469. strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
  1470. sizeof(drvinfo->bus_info));
  1471. }
  1472. static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
  1473. struct ethtool_pauseparam *pause)
  1474. {
  1475. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  1476. pause->rx_pause = mlxsw_sp_port->link.rx_pause;
  1477. pause->tx_pause = mlxsw_sp_port->link.tx_pause;
  1478. }
  1479. static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
  1480. struct ethtool_pauseparam *pause)
  1481. {
  1482. char pfcc_pl[MLXSW_REG_PFCC_LEN];
  1483. mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
  1484. mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
  1485. mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
  1486. return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
  1487. pfcc_pl);
  1488. }
  1489. static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
  1490. struct ethtool_pauseparam *pause)
  1491. {
  1492. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  1493. bool pause_en = pause->tx_pause || pause->rx_pause;
  1494. int err;
  1495. if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
  1496. netdev_err(dev, "PFC already enabled on port\n");
  1497. return -EINVAL;
  1498. }
  1499. if (pause->autoneg) {
  1500. netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
  1501. return -EINVAL;
  1502. }
  1503. err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
  1504. if (err) {
  1505. netdev_err(dev, "Failed to configure port's headroom\n");
  1506. return err;
  1507. }
  1508. err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
  1509. if (err) {
  1510. netdev_err(dev, "Failed to set PAUSE parameters\n");
  1511. goto err_port_pause_configure;
  1512. }
  1513. mlxsw_sp_port->link.rx_pause = pause->rx_pause;
  1514. mlxsw_sp_port->link.tx_pause = pause->tx_pause;
  1515. return 0;
  1516. err_port_pause_configure:
  1517. pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
  1518. mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
  1519. return err;
  1520. }
  1521. struct mlxsw_sp_port_hw_stats {
  1522. char str[ETH_GSTRING_LEN];
  1523. u64 (*getter)(const char *payload);
  1524. bool cells_bytes;
  1525. };
  1526. static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
  1527. {
  1528. .str = "a_frames_transmitted_ok",
  1529. .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
  1530. },
  1531. {
  1532. .str = "a_frames_received_ok",
  1533. .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
  1534. },
  1535. {
  1536. .str = "a_frame_check_sequence_errors",
  1537. .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
  1538. },
  1539. {
  1540. .str = "a_alignment_errors",
  1541. .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
  1542. },
  1543. {
  1544. .str = "a_octets_transmitted_ok",
  1545. .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
  1546. },
  1547. {
  1548. .str = "a_octets_received_ok",
  1549. .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
  1550. },
  1551. {
  1552. .str = "a_multicast_frames_xmitted_ok",
  1553. .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
  1554. },
  1555. {
  1556. .str = "a_broadcast_frames_xmitted_ok",
  1557. .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
  1558. },
  1559. {
  1560. .str = "a_multicast_frames_received_ok",
  1561. .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
  1562. },
  1563. {
  1564. .str = "a_broadcast_frames_received_ok",
  1565. .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
  1566. },
  1567. {
  1568. .str = "a_in_range_length_errors",
  1569. .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
  1570. },
  1571. {
  1572. .str = "a_out_of_range_length_field",
  1573. .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
  1574. },
  1575. {
  1576. .str = "a_frame_too_long_errors",
  1577. .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
  1578. },
  1579. {
  1580. .str = "a_symbol_error_during_carrier",
  1581. .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
  1582. },
  1583. {
  1584. .str = "a_mac_control_frames_transmitted",
  1585. .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
  1586. },
  1587. {
  1588. .str = "a_mac_control_frames_received",
  1589. .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
  1590. },
  1591. {
  1592. .str = "a_unsupported_opcodes_received",
  1593. .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
  1594. },
  1595. {
  1596. .str = "a_pause_mac_ctrl_frames_received",
  1597. .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
  1598. },
  1599. {
  1600. .str = "a_pause_mac_ctrl_frames_xmitted",
  1601. .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
  1602. },
  1603. };
  1604. #define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
  1605. static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_rfc_2819_stats[] = {
  1606. {
  1607. .str = "ether_pkts64octets",
  1608. .getter = mlxsw_reg_ppcnt_ether_stats_pkts64octets_get,
  1609. },
  1610. {
  1611. .str = "ether_pkts65to127octets",
  1612. .getter = mlxsw_reg_ppcnt_ether_stats_pkts65to127octets_get,
  1613. },
  1614. {
  1615. .str = "ether_pkts128to255octets",
  1616. .getter = mlxsw_reg_ppcnt_ether_stats_pkts128to255octets_get,
  1617. },
  1618. {
  1619. .str = "ether_pkts256to511octets",
  1620. .getter = mlxsw_reg_ppcnt_ether_stats_pkts256to511octets_get,
  1621. },
  1622. {
  1623. .str = "ether_pkts512to1023octets",
  1624. .getter = mlxsw_reg_ppcnt_ether_stats_pkts512to1023octets_get,
  1625. },
  1626. {
  1627. .str = "ether_pkts1024to1518octets",
  1628. .getter = mlxsw_reg_ppcnt_ether_stats_pkts1024to1518octets_get,
  1629. },
  1630. {
  1631. .str = "ether_pkts1519to2047octets",
  1632. .getter = mlxsw_reg_ppcnt_ether_stats_pkts1519to2047octets_get,
  1633. },
  1634. {
  1635. .str = "ether_pkts2048to4095octets",
  1636. .getter = mlxsw_reg_ppcnt_ether_stats_pkts2048to4095octets_get,
  1637. },
  1638. {
  1639. .str = "ether_pkts4096to8191octets",
  1640. .getter = mlxsw_reg_ppcnt_ether_stats_pkts4096to8191octets_get,
  1641. },
  1642. {
  1643. .str = "ether_pkts8192to10239octets",
  1644. .getter = mlxsw_reg_ppcnt_ether_stats_pkts8192to10239octets_get,
  1645. },
  1646. };
  1647. #define MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN \
  1648. ARRAY_SIZE(mlxsw_sp_port_hw_rfc_2819_stats)
  1649. static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
  1650. {
  1651. .str = "rx_octets_prio",
  1652. .getter = mlxsw_reg_ppcnt_rx_octets_get,
  1653. },
  1654. {
  1655. .str = "rx_frames_prio",
  1656. .getter = mlxsw_reg_ppcnt_rx_frames_get,
  1657. },
  1658. {
  1659. .str = "tx_octets_prio",
  1660. .getter = mlxsw_reg_ppcnt_tx_octets_get,
  1661. },
  1662. {
  1663. .str = "tx_frames_prio",
  1664. .getter = mlxsw_reg_ppcnt_tx_frames_get,
  1665. },
  1666. {
  1667. .str = "rx_pause_prio",
  1668. .getter = mlxsw_reg_ppcnt_rx_pause_get,
  1669. },
  1670. {
  1671. .str = "rx_pause_duration_prio",
  1672. .getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
  1673. },
  1674. {
  1675. .str = "tx_pause_prio",
  1676. .getter = mlxsw_reg_ppcnt_tx_pause_get,
  1677. },
  1678. {
  1679. .str = "tx_pause_duration_prio",
  1680. .getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
  1681. },
  1682. };
  1683. #define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
  1684. static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
  1685. {
  1686. .str = "tc_transmit_queue_tc",
  1687. .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get,
  1688. .cells_bytes = true,
  1689. },
  1690. {
  1691. .str = "tc_no_buffer_discard_uc_tc",
  1692. .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
  1693. },
  1694. };
  1695. #define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
  1696. #define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
  1697. MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN + \
  1698. (MLXSW_SP_PORT_HW_PRIO_STATS_LEN * \
  1699. IEEE_8021QAZ_MAX_TCS) + \
  1700. (MLXSW_SP_PORT_HW_TC_STATS_LEN * \
  1701. TC_MAX_QUEUE))
  1702. static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
  1703. {
  1704. int i;
  1705. for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
  1706. snprintf(*p, ETH_GSTRING_LEN, "%.29s_%.1d",
  1707. mlxsw_sp_port_hw_prio_stats[i].str, prio);
  1708. *p += ETH_GSTRING_LEN;
  1709. }
  1710. }
  1711. static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
  1712. {
  1713. int i;
  1714. for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
  1715. snprintf(*p, ETH_GSTRING_LEN, "%.29s_%.1d",
  1716. mlxsw_sp_port_hw_tc_stats[i].str, tc);
  1717. *p += ETH_GSTRING_LEN;
  1718. }
  1719. }
  1720. static void mlxsw_sp_port_get_strings(struct net_device *dev,
  1721. u32 stringset, u8 *data)
  1722. {
  1723. u8 *p = data;
  1724. int i;
  1725. switch (stringset) {
  1726. case ETH_SS_STATS:
  1727. for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
  1728. memcpy(p, mlxsw_sp_port_hw_stats[i].str,
  1729. ETH_GSTRING_LEN);
  1730. p += ETH_GSTRING_LEN;
  1731. }
  1732. for (i = 0; i < MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN; i++) {
  1733. memcpy(p, mlxsw_sp_port_hw_rfc_2819_stats[i].str,
  1734. ETH_GSTRING_LEN);
  1735. p += ETH_GSTRING_LEN;
  1736. }
  1737. for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
  1738. mlxsw_sp_port_get_prio_strings(&p, i);
  1739. for (i = 0; i < TC_MAX_QUEUE; i++)
  1740. mlxsw_sp_port_get_tc_strings(&p, i);
  1741. break;
  1742. }
  1743. }
  1744. static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
  1745. enum ethtool_phys_id_state state)
  1746. {
  1747. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  1748. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  1749. char mlcr_pl[MLXSW_REG_MLCR_LEN];
  1750. bool active;
  1751. switch (state) {
  1752. case ETHTOOL_ID_ACTIVE:
  1753. active = true;
  1754. break;
  1755. case ETHTOOL_ID_INACTIVE:
  1756. active = false;
  1757. break;
  1758. default:
  1759. return -EOPNOTSUPP;
  1760. }
  1761. mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
  1762. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
  1763. }
  1764. static int
  1765. mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
  1766. int *p_len, enum mlxsw_reg_ppcnt_grp grp)
  1767. {
  1768. switch (grp) {
  1769. case MLXSW_REG_PPCNT_IEEE_8023_CNT:
  1770. *p_hw_stats = mlxsw_sp_port_hw_stats;
  1771. *p_len = MLXSW_SP_PORT_HW_STATS_LEN;
  1772. break;
  1773. case MLXSW_REG_PPCNT_RFC_2819_CNT:
  1774. *p_hw_stats = mlxsw_sp_port_hw_rfc_2819_stats;
  1775. *p_len = MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN;
  1776. break;
  1777. case MLXSW_REG_PPCNT_PRIO_CNT:
  1778. *p_hw_stats = mlxsw_sp_port_hw_prio_stats;
  1779. *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
  1780. break;
  1781. case MLXSW_REG_PPCNT_TC_CNT:
  1782. *p_hw_stats = mlxsw_sp_port_hw_tc_stats;
  1783. *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
  1784. break;
  1785. default:
  1786. WARN_ON(1);
  1787. return -EOPNOTSUPP;
  1788. }
  1789. return 0;
  1790. }
  1791. static void __mlxsw_sp_port_get_stats(struct net_device *dev,
  1792. enum mlxsw_reg_ppcnt_grp grp, int prio,
  1793. u64 *data, int data_index)
  1794. {
  1795. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  1796. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  1797. struct mlxsw_sp_port_hw_stats *hw_stats;
  1798. char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
  1799. int i, len;
  1800. int err;
  1801. err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
  1802. if (err)
  1803. return;
  1804. mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl);
  1805. for (i = 0; i < len; i++) {
  1806. data[data_index + i] = hw_stats[i].getter(ppcnt_pl);
  1807. if (!hw_stats[i].cells_bytes)
  1808. continue;
  1809. data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp,
  1810. data[data_index + i]);
  1811. }
  1812. }
  1813. static void mlxsw_sp_port_get_stats(struct net_device *dev,
  1814. struct ethtool_stats *stats, u64 *data)
  1815. {
  1816. int i, data_index = 0;
  1817. /* IEEE 802.3 Counters */
  1818. __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
  1819. data, data_index);
  1820. data_index = MLXSW_SP_PORT_HW_STATS_LEN;
  1821. /* RFC 2819 Counters */
  1822. __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_RFC_2819_CNT, 0,
  1823. data, data_index);
  1824. data_index += MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN;
  1825. /* Per-Priority Counters */
  1826. for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
  1827. __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
  1828. data, data_index);
  1829. data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
  1830. }
  1831. /* Per-TC Counters */
  1832. for (i = 0; i < TC_MAX_QUEUE; i++) {
  1833. __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
  1834. data, data_index);
  1835. data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
  1836. }
  1837. }
  1838. static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
  1839. {
  1840. switch (sset) {
  1841. case ETH_SS_STATS:
  1842. return MLXSW_SP_PORT_ETHTOOL_STATS_LEN;
  1843. default:
  1844. return -EOPNOTSUPP;
  1845. }
  1846. }
  1847. struct mlxsw_sp_port_link_mode {
  1848. enum ethtool_link_mode_bit_indices mask_ethtool;
  1849. u32 mask;
  1850. u32 speed;
  1851. };
  1852. static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
  1853. {
  1854. .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
  1855. .mask_ethtool = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
  1856. .speed = SPEED_100,
  1857. },
  1858. {
  1859. .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
  1860. MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
  1861. .mask_ethtool = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
  1862. .speed = SPEED_1000,
  1863. },
  1864. {
  1865. .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
  1866. .mask_ethtool = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
  1867. .speed = SPEED_10000,
  1868. },
  1869. {
  1870. .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
  1871. MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
  1872. .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
  1873. .speed = SPEED_10000,
  1874. },
  1875. {
  1876. .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
  1877. MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
  1878. MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
  1879. MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
  1880. .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
  1881. .speed = SPEED_10000,
  1882. },
  1883. {
  1884. .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
  1885. .mask_ethtool = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
  1886. .speed = SPEED_20000,
  1887. },
  1888. {
  1889. .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
  1890. .mask_ethtool = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
  1891. .speed = SPEED_40000,
  1892. },
  1893. {
  1894. .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
  1895. .mask_ethtool = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
  1896. .speed = SPEED_40000,
  1897. },
  1898. {
  1899. .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
  1900. .mask_ethtool = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
  1901. .speed = SPEED_40000,
  1902. },
  1903. {
  1904. .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
  1905. .mask_ethtool = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
  1906. .speed = SPEED_40000,
  1907. },
  1908. {
  1909. .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR,
  1910. .mask_ethtool = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
  1911. .speed = SPEED_25000,
  1912. },
  1913. {
  1914. .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR,
  1915. .mask_ethtool = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
  1916. .speed = SPEED_25000,
  1917. },
  1918. {
  1919. .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
  1920. .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
  1921. .speed = SPEED_25000,
  1922. },
  1923. {
  1924. .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
  1925. .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
  1926. .speed = SPEED_25000,
  1927. },
  1928. {
  1929. .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2,
  1930. .mask_ethtool = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
  1931. .speed = SPEED_50000,
  1932. },
  1933. {
  1934. .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
  1935. .mask_ethtool = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
  1936. .speed = SPEED_50000,
  1937. },
  1938. {
  1939. .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2,
  1940. .mask_ethtool = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
  1941. .speed = SPEED_50000,
  1942. },
  1943. {
  1944. .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
  1945. .mask_ethtool = ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT,
  1946. .speed = SPEED_56000,
  1947. },
  1948. {
  1949. .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
  1950. .mask_ethtool = ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT,
  1951. .speed = SPEED_56000,
  1952. },
  1953. {
  1954. .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
  1955. .mask_ethtool = ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT,
  1956. .speed = SPEED_56000,
  1957. },
  1958. {
  1959. .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
  1960. .mask_ethtool = ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT,
  1961. .speed = SPEED_56000,
  1962. },
  1963. {
  1964. .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,
  1965. .mask_ethtool = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
  1966. .speed = SPEED_100000,
  1967. },
  1968. {
  1969. .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,
  1970. .mask_ethtool = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
  1971. .speed = SPEED_100000,
  1972. },
  1973. {
  1974. .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
  1975. .mask_ethtool = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
  1976. .speed = SPEED_100000,
  1977. },
  1978. {
  1979. .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
  1980. .mask_ethtool = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
  1981. .speed = SPEED_100000,
  1982. },
  1983. };
  1984. #define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
  1985. static void
  1986. mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto,
  1987. struct ethtool_link_ksettings *cmd)
  1988. {
  1989. if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
  1990. MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
  1991. MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
  1992. MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
  1993. MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
  1994. MLXSW_REG_PTYS_ETH_SPEED_SGMII))
  1995. ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
  1996. if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
  1997. MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
  1998. MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
  1999. MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
  2000. MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
  2001. ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
  2002. }
  2003. static void mlxsw_sp_from_ptys_link(u32 ptys_eth_proto, unsigned long *mode)
  2004. {
  2005. int i;
  2006. for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
  2007. if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
  2008. __set_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
  2009. mode);
  2010. }
  2011. }
  2012. static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
  2013. struct ethtool_link_ksettings *cmd)
  2014. {
  2015. u32 speed = SPEED_UNKNOWN;
  2016. u8 duplex = DUPLEX_UNKNOWN;
  2017. int i;
  2018. if (!carrier_ok)
  2019. goto out;
  2020. for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
  2021. if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
  2022. speed = mlxsw_sp_port_link_mode[i].speed;
  2023. duplex = DUPLEX_FULL;
  2024. break;
  2025. }
  2026. }
  2027. out:
  2028. cmd->base.speed = speed;
  2029. cmd->base.duplex = duplex;
  2030. }
  2031. static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
  2032. {
  2033. if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
  2034. MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
  2035. MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
  2036. MLXSW_REG_PTYS_ETH_SPEED_SGMII))
  2037. return PORT_FIBRE;
  2038. if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
  2039. MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
  2040. MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
  2041. return PORT_DA;
  2042. if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
  2043. MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
  2044. MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
  2045. MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
  2046. return PORT_NONE;
  2047. return PORT_OTHER;
  2048. }
  2049. static u32
  2050. mlxsw_sp_to_ptys_advert_link(const struct ethtool_link_ksettings *cmd)
  2051. {
  2052. u32 ptys_proto = 0;
  2053. int i;
  2054. for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
  2055. if (test_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
  2056. cmd->link_modes.advertising))
  2057. ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
  2058. }
  2059. return ptys_proto;
  2060. }
  2061. static u32 mlxsw_sp_to_ptys_speed(u32 speed)
  2062. {
  2063. u32 ptys_proto = 0;
  2064. int i;
  2065. for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
  2066. if (speed == mlxsw_sp_port_link_mode[i].speed)
  2067. ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
  2068. }
  2069. return ptys_proto;
  2070. }
  2071. static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
  2072. {
  2073. u32 ptys_proto = 0;
  2074. int i;
  2075. for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
  2076. if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
  2077. ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
  2078. }
  2079. return ptys_proto;
  2080. }
  2081. static void mlxsw_sp_port_get_link_supported(u32 eth_proto_cap,
  2082. struct ethtool_link_ksettings *cmd)
  2083. {
  2084. ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause);
  2085. ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
  2086. ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
  2087. mlxsw_sp_from_ptys_supported_port(eth_proto_cap, cmd);
  2088. mlxsw_sp_from_ptys_link(eth_proto_cap, cmd->link_modes.supported);
  2089. }
  2090. static void mlxsw_sp_port_get_link_advertise(u32 eth_proto_admin, bool autoneg,
  2091. struct ethtool_link_ksettings *cmd)
  2092. {
  2093. if (!autoneg)
  2094. return;
  2095. ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
  2096. mlxsw_sp_from_ptys_link(eth_proto_admin, cmd->link_modes.advertising);
  2097. }
  2098. static void
  2099. mlxsw_sp_port_get_link_lp_advertise(u32 eth_proto_lp, u8 autoneg_status,
  2100. struct ethtool_link_ksettings *cmd)
  2101. {
  2102. if (autoneg_status != MLXSW_REG_PTYS_AN_STATUS_OK || !eth_proto_lp)
  2103. return;
  2104. ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
  2105. mlxsw_sp_from_ptys_link(eth_proto_lp, cmd->link_modes.lp_advertising);
  2106. }
  2107. static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev,
  2108. struct ethtool_link_ksettings *cmd)
  2109. {
  2110. u32 eth_proto_cap, eth_proto_admin, eth_proto_oper, eth_proto_lp;
  2111. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  2112. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  2113. char ptys_pl[MLXSW_REG_PTYS_LEN];
  2114. u8 autoneg_status;
  2115. bool autoneg;
  2116. int err;
  2117. autoneg = mlxsw_sp_port->link.autoneg;
  2118. mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0, false);
  2119. err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
  2120. if (err)
  2121. return err;
  2122. mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin,
  2123. &eth_proto_oper);
  2124. mlxsw_sp_port_get_link_supported(eth_proto_cap, cmd);
  2125. mlxsw_sp_port_get_link_advertise(eth_proto_admin, autoneg, cmd);
  2126. eth_proto_lp = mlxsw_reg_ptys_eth_proto_lp_advertise_get(ptys_pl);
  2127. autoneg_status = mlxsw_reg_ptys_an_status_get(ptys_pl);
  2128. mlxsw_sp_port_get_link_lp_advertise(eth_proto_lp, autoneg_status, cmd);
  2129. cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
  2130. cmd->base.port = mlxsw_sp_port_connector_port(eth_proto_oper);
  2131. mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev), eth_proto_oper,
  2132. cmd);
  2133. return 0;
  2134. }
  2135. static int
  2136. mlxsw_sp_port_set_link_ksettings(struct net_device *dev,
  2137. const struct ethtool_link_ksettings *cmd)
  2138. {
  2139. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  2140. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  2141. char ptys_pl[MLXSW_REG_PTYS_LEN];
  2142. u32 eth_proto_cap, eth_proto_new;
  2143. bool autoneg;
  2144. int err;
  2145. mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0, false);
  2146. err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
  2147. if (err)
  2148. return err;
  2149. mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, NULL, NULL);
  2150. autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
  2151. if (!autoneg && cmd->base.speed == SPEED_56000) {
  2152. netdev_err(dev, "56G not supported with autoneg off\n");
  2153. return -EINVAL;
  2154. }
  2155. eth_proto_new = autoneg ?
  2156. mlxsw_sp_to_ptys_advert_link(cmd) :
  2157. mlxsw_sp_to_ptys_speed(cmd->base.speed);
  2158. eth_proto_new = eth_proto_new & eth_proto_cap;
  2159. if (!eth_proto_new) {
  2160. netdev_err(dev, "No supported speed requested\n");
  2161. return -EINVAL;
  2162. }
  2163. mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
  2164. eth_proto_new, autoneg);
  2165. err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
  2166. if (err)
  2167. return err;
  2168. mlxsw_sp_port->link.autoneg = autoneg;
  2169. if (!netif_running(dev))
  2170. return 0;
  2171. mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
  2172. mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
  2173. return 0;
  2174. }
  2175. static int mlxsw_sp_flash_device(struct net_device *dev,
  2176. struct ethtool_flash *flash)
  2177. {
  2178. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  2179. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  2180. const struct firmware *firmware;
  2181. int err;
  2182. if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
  2183. return -EOPNOTSUPP;
  2184. dev_hold(dev);
  2185. rtnl_unlock();
  2186. err = request_firmware_direct(&firmware, flash->data, &dev->dev);
  2187. if (err)
  2188. goto out;
  2189. err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
  2190. release_firmware(firmware);
  2191. out:
  2192. rtnl_lock();
  2193. dev_put(dev);
  2194. return err;
  2195. }
  2196. #define MLXSW_SP_I2C_ADDR_LOW 0x50
  2197. #define MLXSW_SP_I2C_ADDR_HIGH 0x51
  2198. #define MLXSW_SP_EEPROM_PAGE_LENGTH 256
  2199. static int mlxsw_sp_query_module_eeprom(struct mlxsw_sp_port *mlxsw_sp_port,
  2200. u16 offset, u16 size, void *data,
  2201. unsigned int *p_read_size)
  2202. {
  2203. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  2204. char eeprom_tmp[MLXSW_SP_REG_MCIA_EEPROM_SIZE];
  2205. char mcia_pl[MLXSW_REG_MCIA_LEN];
  2206. u16 i2c_addr;
  2207. int status;
  2208. int err;
  2209. size = min_t(u16, size, MLXSW_SP_REG_MCIA_EEPROM_SIZE);
  2210. if (offset < MLXSW_SP_EEPROM_PAGE_LENGTH &&
  2211. offset + size > MLXSW_SP_EEPROM_PAGE_LENGTH)
  2212. /* Cross pages read, read until offset 256 in low page */
  2213. size = MLXSW_SP_EEPROM_PAGE_LENGTH - offset;
  2214. i2c_addr = MLXSW_SP_I2C_ADDR_LOW;
  2215. if (offset >= MLXSW_SP_EEPROM_PAGE_LENGTH) {
  2216. i2c_addr = MLXSW_SP_I2C_ADDR_HIGH;
  2217. offset -= MLXSW_SP_EEPROM_PAGE_LENGTH;
  2218. }
  2219. mlxsw_reg_mcia_pack(mcia_pl, mlxsw_sp_port->mapping.module,
  2220. 0, 0, offset, size, i2c_addr);
  2221. err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcia), mcia_pl);
  2222. if (err)
  2223. return err;
  2224. status = mlxsw_reg_mcia_status_get(mcia_pl);
  2225. if (status)
  2226. return -EIO;
  2227. mlxsw_reg_mcia_eeprom_memcpy_from(mcia_pl, eeprom_tmp);
  2228. memcpy(data, eeprom_tmp, size);
  2229. *p_read_size = size;
  2230. return 0;
  2231. }
  2232. enum mlxsw_sp_eeprom_module_info_rev_id {
  2233. MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00,
  2234. MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01,
  2235. MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03,
  2236. };
  2237. enum mlxsw_sp_eeprom_module_info_id {
  2238. MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP = 0x03,
  2239. MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP = 0x0C,
  2240. MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D,
  2241. MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11,
  2242. };
  2243. enum mlxsw_sp_eeprom_module_info {
  2244. MLXSW_SP_EEPROM_MODULE_INFO_ID,
  2245. MLXSW_SP_EEPROM_MODULE_INFO_REV_ID,
  2246. MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
  2247. };
  2248. static int mlxsw_sp_get_module_info(struct net_device *netdev,
  2249. struct ethtool_modinfo *modinfo)
  2250. {
  2251. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
  2252. u8 module_info[MLXSW_SP_EEPROM_MODULE_INFO_SIZE];
  2253. u8 module_rev_id, module_id;
  2254. unsigned int read_size;
  2255. int err;
  2256. err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, 0,
  2257. MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
  2258. module_info, &read_size);
  2259. if (err)
  2260. return err;
  2261. if (read_size < MLXSW_SP_EEPROM_MODULE_INFO_SIZE)
  2262. return -EIO;
  2263. module_rev_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_REV_ID];
  2264. module_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_ID];
  2265. switch (module_id) {
  2266. case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP:
  2267. modinfo->type = ETH_MODULE_SFF_8436;
  2268. modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
  2269. break;
  2270. case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS:
  2271. case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28:
  2272. if (module_id == MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 ||
  2273. module_rev_id >= MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636) {
  2274. modinfo->type = ETH_MODULE_SFF_8636;
  2275. modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
  2276. } else {
  2277. modinfo->type = ETH_MODULE_SFF_8436;
  2278. modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
  2279. }
  2280. break;
  2281. case MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP:
  2282. modinfo->type = ETH_MODULE_SFF_8472;
  2283. modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
  2284. break;
  2285. default:
  2286. return -EINVAL;
  2287. }
  2288. return 0;
  2289. }
  2290. static int mlxsw_sp_get_module_eeprom(struct net_device *netdev,
  2291. struct ethtool_eeprom *ee,
  2292. u8 *data)
  2293. {
  2294. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
  2295. int offset = ee->offset;
  2296. unsigned int read_size;
  2297. int i = 0;
  2298. int err;
  2299. if (!ee->len)
  2300. return -EINVAL;
  2301. memset(data, 0, ee->len);
  2302. while (i < ee->len) {
  2303. err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, offset,
  2304. ee->len - i, data + i,
  2305. &read_size);
  2306. if (err) {
  2307. netdev_err(mlxsw_sp_port->dev, "Eeprom query failed\n");
  2308. return err;
  2309. }
  2310. i += read_size;
  2311. offset += read_size;
  2312. }
  2313. return 0;
  2314. }
  2315. static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
  2316. .get_drvinfo = mlxsw_sp_port_get_drvinfo,
  2317. .get_link = ethtool_op_get_link,
  2318. .get_pauseparam = mlxsw_sp_port_get_pauseparam,
  2319. .set_pauseparam = mlxsw_sp_port_set_pauseparam,
  2320. .get_strings = mlxsw_sp_port_get_strings,
  2321. .set_phys_id = mlxsw_sp_port_set_phys_id,
  2322. .get_ethtool_stats = mlxsw_sp_port_get_stats,
  2323. .get_sset_count = mlxsw_sp_port_get_sset_count,
  2324. .get_link_ksettings = mlxsw_sp_port_get_link_ksettings,
  2325. .set_link_ksettings = mlxsw_sp_port_set_link_ksettings,
  2326. .flash_device = mlxsw_sp_flash_device,
  2327. .get_module_info = mlxsw_sp_get_module_info,
  2328. .get_module_eeprom = mlxsw_sp_get_module_eeprom,
  2329. };
  2330. static int
  2331. mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
  2332. {
  2333. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  2334. u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
  2335. char ptys_pl[MLXSW_REG_PTYS_LEN];
  2336. u32 eth_proto_admin;
  2337. eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
  2338. mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
  2339. eth_proto_admin, mlxsw_sp_port->link.autoneg);
  2340. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
  2341. }
  2342. int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
  2343. enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
  2344. bool dwrr, u8 dwrr_weight)
  2345. {
  2346. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  2347. char qeec_pl[MLXSW_REG_QEEC_LEN];
  2348. mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
  2349. next_index);
  2350. mlxsw_reg_qeec_de_set(qeec_pl, true);
  2351. mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
  2352. mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
  2353. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
  2354. }
  2355. int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
  2356. enum mlxsw_reg_qeec_hr hr, u8 index,
  2357. u8 next_index, u32 maxrate)
  2358. {
  2359. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  2360. char qeec_pl[MLXSW_REG_QEEC_LEN];
  2361. mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
  2362. next_index);
  2363. mlxsw_reg_qeec_mase_set(qeec_pl, true);
  2364. mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
  2365. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
  2366. }
  2367. static int mlxsw_sp_port_min_bw_set(struct mlxsw_sp_port *mlxsw_sp_port,
  2368. enum mlxsw_reg_qeec_hr hr, u8 index,
  2369. u8 next_index, u32 minrate)
  2370. {
  2371. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  2372. char qeec_pl[MLXSW_REG_QEEC_LEN];
  2373. mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
  2374. next_index);
  2375. mlxsw_reg_qeec_mise_set(qeec_pl, true);
  2376. mlxsw_reg_qeec_min_shaper_rate_set(qeec_pl, minrate);
  2377. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
  2378. }
  2379. int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
  2380. u8 switch_prio, u8 tclass)
  2381. {
  2382. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  2383. char qtct_pl[MLXSW_REG_QTCT_LEN];
  2384. mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
  2385. tclass);
  2386. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
  2387. }
  2388. static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
  2389. {
  2390. int err, i;
  2391. /* Setup the elements hierarcy, so that each TC is linked to
  2392. * one subgroup, which are all member in the same group.
  2393. */
  2394. err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
  2395. MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
  2396. 0);
  2397. if (err)
  2398. return err;
  2399. for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
  2400. err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
  2401. MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
  2402. 0, false, 0);
  2403. if (err)
  2404. return err;
  2405. }
  2406. for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
  2407. err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
  2408. MLXSW_REG_QEEC_HIERARCY_TC, i, i,
  2409. false, 0);
  2410. if (err)
  2411. return err;
  2412. err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
  2413. MLXSW_REG_QEEC_HIERARCY_TC,
  2414. i + 8, i,
  2415. true, 100);
  2416. if (err)
  2417. return err;
  2418. }
  2419. /* Make sure the max shaper is disabled in all hierarchies that
  2420. * support it.
  2421. */
  2422. err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
  2423. MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
  2424. MLXSW_REG_QEEC_MAS_DIS);
  2425. if (err)
  2426. return err;
  2427. for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
  2428. err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
  2429. MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
  2430. i, 0,
  2431. MLXSW_REG_QEEC_MAS_DIS);
  2432. if (err)
  2433. return err;
  2434. }
  2435. for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
  2436. err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
  2437. MLXSW_REG_QEEC_HIERARCY_TC,
  2438. i, i,
  2439. MLXSW_REG_QEEC_MAS_DIS);
  2440. if (err)
  2441. return err;
  2442. err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
  2443. MLXSW_REG_QEEC_HIERARCY_TC,
  2444. i + 8, i,
  2445. MLXSW_REG_QEEC_MAS_DIS);
  2446. if (err)
  2447. return err;
  2448. }
  2449. /* Configure the min shaper for multicast TCs. */
  2450. for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
  2451. err = mlxsw_sp_port_min_bw_set(mlxsw_sp_port,
  2452. MLXSW_REG_QEEC_HIERARCY_TC,
  2453. i + 8, i,
  2454. MLXSW_REG_QEEC_MIS_MIN);
  2455. if (err)
  2456. return err;
  2457. }
  2458. /* Map all priorities to traffic class 0. */
  2459. for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
  2460. err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
  2461. if (err)
  2462. return err;
  2463. }
  2464. return 0;
  2465. }
  2466. static int mlxsw_sp_port_tc_mc_mode_set(struct mlxsw_sp_port *mlxsw_sp_port,
  2467. bool enable)
  2468. {
  2469. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  2470. char qtctm_pl[MLXSW_REG_QTCTM_LEN];
  2471. mlxsw_reg_qtctm_pack(qtctm_pl, mlxsw_sp_port->local_port, enable);
  2472. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtctm), qtctm_pl);
  2473. }
  2474. static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
  2475. bool split, u8 module, u8 width, u8 lane)
  2476. {
  2477. struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
  2478. struct mlxsw_sp_port *mlxsw_sp_port;
  2479. struct net_device *dev;
  2480. int err;
  2481. err = mlxsw_core_port_init(mlxsw_sp->core, local_port);
  2482. if (err) {
  2483. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
  2484. local_port);
  2485. return err;
  2486. }
  2487. dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
  2488. if (!dev) {
  2489. err = -ENOMEM;
  2490. goto err_alloc_etherdev;
  2491. }
  2492. SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
  2493. mlxsw_sp_port = netdev_priv(dev);
  2494. mlxsw_sp_port->dev = dev;
  2495. mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
  2496. mlxsw_sp_port->local_port = local_port;
  2497. mlxsw_sp_port->pvid = 1;
  2498. mlxsw_sp_port->split = split;
  2499. mlxsw_sp_port->mapping.module = module;
  2500. mlxsw_sp_port->mapping.width = width;
  2501. mlxsw_sp_port->mapping.lane = lane;
  2502. mlxsw_sp_port->link.autoneg = 1;
  2503. INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list);
  2504. INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list);
  2505. mlxsw_sp_port->pcpu_stats =
  2506. netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
  2507. if (!mlxsw_sp_port->pcpu_stats) {
  2508. err = -ENOMEM;
  2509. goto err_alloc_stats;
  2510. }
  2511. mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample),
  2512. GFP_KERNEL);
  2513. if (!mlxsw_sp_port->sample) {
  2514. err = -ENOMEM;
  2515. goto err_alloc_sample;
  2516. }
  2517. INIT_DELAYED_WORK(&mlxsw_sp_port->periodic_hw_stats.update_dw,
  2518. &update_stats_cache);
  2519. dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
  2520. dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
  2521. err = mlxsw_sp_port_module_map(mlxsw_sp_port, module, width, lane);
  2522. if (err) {
  2523. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n",
  2524. mlxsw_sp_port->local_port);
  2525. goto err_port_module_map;
  2526. }
  2527. err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
  2528. if (err) {
  2529. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
  2530. mlxsw_sp_port->local_port);
  2531. goto err_port_swid_set;
  2532. }
  2533. err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
  2534. if (err) {
  2535. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
  2536. mlxsw_sp_port->local_port);
  2537. goto err_dev_addr_init;
  2538. }
  2539. netif_carrier_off(dev);
  2540. dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
  2541. NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
  2542. dev->hw_features |= NETIF_F_HW_TC;
  2543. dev->min_mtu = 0;
  2544. dev->max_mtu = ETH_MAX_MTU;
  2545. /* Each packet needs to have a Tx header (metadata) on top all other
  2546. * headers.
  2547. */
  2548. dev->needed_headroom = MLXSW_TXHDR_LEN;
  2549. err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
  2550. if (err) {
  2551. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
  2552. mlxsw_sp_port->local_port);
  2553. goto err_port_system_port_mapping_set;
  2554. }
  2555. err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
  2556. if (err) {
  2557. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
  2558. mlxsw_sp_port->local_port);
  2559. goto err_port_speed_by_width_set;
  2560. }
  2561. err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
  2562. if (err) {
  2563. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
  2564. mlxsw_sp_port->local_port);
  2565. goto err_port_mtu_set;
  2566. }
  2567. err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
  2568. if (err)
  2569. goto err_port_admin_status_set;
  2570. err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
  2571. if (err) {
  2572. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
  2573. mlxsw_sp_port->local_port);
  2574. goto err_port_buffers_init;
  2575. }
  2576. err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
  2577. if (err) {
  2578. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
  2579. mlxsw_sp_port->local_port);
  2580. goto err_port_ets_init;
  2581. }
  2582. err = mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, true);
  2583. if (err) {
  2584. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC MC mode\n",
  2585. mlxsw_sp_port->local_port);
  2586. goto err_port_tc_mc_mode;
  2587. }
  2588. /* ETS and buffers must be initialized before DCB. */
  2589. err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
  2590. if (err) {
  2591. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
  2592. mlxsw_sp_port->local_port);
  2593. goto err_port_dcb_init;
  2594. }
  2595. err = mlxsw_sp_port_fids_init(mlxsw_sp_port);
  2596. if (err) {
  2597. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n",
  2598. mlxsw_sp_port->local_port);
  2599. goto err_port_fids_init;
  2600. }
  2601. err = mlxsw_sp_tc_qdisc_init(mlxsw_sp_port);
  2602. if (err) {
  2603. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC qdiscs\n",
  2604. mlxsw_sp_port->local_port);
  2605. goto err_port_qdiscs_init;
  2606. }
  2607. mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
  2608. if (IS_ERR(mlxsw_sp_port_vlan)) {
  2609. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n",
  2610. mlxsw_sp_port->local_port);
  2611. err = PTR_ERR(mlxsw_sp_port_vlan);
  2612. goto err_port_vlan_get;
  2613. }
  2614. mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
  2615. mlxsw_sp->ports[local_port] = mlxsw_sp_port;
  2616. err = register_netdev(dev);
  2617. if (err) {
  2618. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
  2619. mlxsw_sp_port->local_port);
  2620. goto err_register_netdev;
  2621. }
  2622. mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
  2623. mlxsw_sp_port, dev, module + 1,
  2624. mlxsw_sp_port->split, lane / width);
  2625. mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 0);
  2626. return 0;
  2627. err_register_netdev:
  2628. mlxsw_sp->ports[local_port] = NULL;
  2629. mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
  2630. mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
  2631. err_port_vlan_get:
  2632. mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
  2633. err_port_qdiscs_init:
  2634. mlxsw_sp_port_fids_fini(mlxsw_sp_port);
  2635. err_port_fids_init:
  2636. mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
  2637. err_port_dcb_init:
  2638. mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false);
  2639. err_port_tc_mc_mode:
  2640. err_port_ets_init:
  2641. err_port_buffers_init:
  2642. err_port_admin_status_set:
  2643. err_port_mtu_set:
  2644. err_port_speed_by_width_set:
  2645. err_port_system_port_mapping_set:
  2646. err_dev_addr_init:
  2647. mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
  2648. err_port_swid_set:
  2649. mlxsw_sp_port_module_unmap(mlxsw_sp_port);
  2650. err_port_module_map:
  2651. kfree(mlxsw_sp_port->sample);
  2652. err_alloc_sample:
  2653. free_percpu(mlxsw_sp_port->pcpu_stats);
  2654. err_alloc_stats:
  2655. free_netdev(dev);
  2656. err_alloc_etherdev:
  2657. mlxsw_core_port_fini(mlxsw_sp->core, local_port);
  2658. return err;
  2659. }
  2660. static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
  2661. {
  2662. struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
  2663. cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw);
  2664. mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
  2665. unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
  2666. mlxsw_sp->ports[local_port] = NULL;
  2667. mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
  2668. mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
  2669. mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
  2670. mlxsw_sp_port_fids_fini(mlxsw_sp_port);
  2671. mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
  2672. mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false);
  2673. mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
  2674. mlxsw_sp_port_module_unmap(mlxsw_sp_port);
  2675. kfree(mlxsw_sp_port->sample);
  2676. free_percpu(mlxsw_sp_port->pcpu_stats);
  2677. WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list));
  2678. free_netdev(mlxsw_sp_port->dev);
  2679. mlxsw_core_port_fini(mlxsw_sp->core, local_port);
  2680. }
  2681. static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port)
  2682. {
  2683. return mlxsw_sp->ports[local_port] != NULL;
  2684. }
  2685. static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
  2686. {
  2687. int i;
  2688. for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++)
  2689. if (mlxsw_sp_port_created(mlxsw_sp, i))
  2690. mlxsw_sp_port_remove(mlxsw_sp, i);
  2691. kfree(mlxsw_sp->port_to_module);
  2692. kfree(mlxsw_sp->ports);
  2693. }
  2694. static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
  2695. {
  2696. unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
  2697. u8 module, width, lane;
  2698. size_t alloc_size;
  2699. int i;
  2700. int err;
  2701. alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports;
  2702. mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
  2703. if (!mlxsw_sp->ports)
  2704. return -ENOMEM;
  2705. mlxsw_sp->port_to_module = kmalloc_array(max_ports, sizeof(int),
  2706. GFP_KERNEL);
  2707. if (!mlxsw_sp->port_to_module) {
  2708. err = -ENOMEM;
  2709. goto err_port_to_module_alloc;
  2710. }
  2711. for (i = 1; i < max_ports; i++) {
  2712. /* Mark as invalid */
  2713. mlxsw_sp->port_to_module[i] = -1;
  2714. err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
  2715. &width, &lane);
  2716. if (err)
  2717. goto err_port_module_info_get;
  2718. if (!width)
  2719. continue;
  2720. mlxsw_sp->port_to_module[i] = module;
  2721. err = mlxsw_sp_port_create(mlxsw_sp, i, false,
  2722. module, width, lane);
  2723. if (err)
  2724. goto err_port_create;
  2725. }
  2726. return 0;
  2727. err_port_create:
  2728. err_port_module_info_get:
  2729. for (i--; i >= 1; i--)
  2730. if (mlxsw_sp_port_created(mlxsw_sp, i))
  2731. mlxsw_sp_port_remove(mlxsw_sp, i);
  2732. kfree(mlxsw_sp->port_to_module);
  2733. err_port_to_module_alloc:
  2734. kfree(mlxsw_sp->ports);
  2735. return err;
  2736. }
  2737. static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
  2738. {
  2739. u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
  2740. return local_port - offset;
  2741. }
  2742. static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
  2743. u8 module, unsigned int count)
  2744. {
  2745. u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
  2746. int err, i;
  2747. for (i = 0; i < count; i++) {
  2748. err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
  2749. module, width, i * width);
  2750. if (err)
  2751. goto err_port_create;
  2752. }
  2753. return 0;
  2754. err_port_create:
  2755. for (i--; i >= 0; i--)
  2756. if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
  2757. mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
  2758. return err;
  2759. }
  2760. static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
  2761. u8 base_port, unsigned int count)
  2762. {
  2763. u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
  2764. int i;
  2765. /* Split by four means we need to re-create two ports, otherwise
  2766. * only one.
  2767. */
  2768. count = count / 2;
  2769. for (i = 0; i < count; i++) {
  2770. local_port = base_port + i * 2;
  2771. if (mlxsw_sp->port_to_module[local_port] < 0)
  2772. continue;
  2773. module = mlxsw_sp->port_to_module[local_port];
  2774. mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
  2775. width, 0);
  2776. }
  2777. }
  2778. static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
  2779. unsigned int count,
  2780. struct netlink_ext_ack *extack)
  2781. {
  2782. struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
  2783. struct mlxsw_sp_port *mlxsw_sp_port;
  2784. u8 module, cur_width, base_port;
  2785. int i;
  2786. int err;
  2787. mlxsw_sp_port = mlxsw_sp->ports[local_port];
  2788. if (!mlxsw_sp_port) {
  2789. dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
  2790. local_port);
  2791. NL_SET_ERR_MSG_MOD(extack, "Port number does not exist");
  2792. return -EINVAL;
  2793. }
  2794. module = mlxsw_sp_port->mapping.module;
  2795. cur_width = mlxsw_sp_port->mapping.width;
  2796. if (count != 2 && count != 4) {
  2797. netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
  2798. NL_SET_ERR_MSG_MOD(extack, "Port can only be split into 2 or 4 ports");
  2799. return -EINVAL;
  2800. }
  2801. if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
  2802. netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
  2803. NL_SET_ERR_MSG_MOD(extack, "Port cannot be split further");
  2804. return -EINVAL;
  2805. }
  2806. /* Make sure we have enough slave (even) ports for the split. */
  2807. if (count == 2) {
  2808. base_port = local_port;
  2809. if (mlxsw_sp->ports[base_port + 1]) {
  2810. netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
  2811. NL_SET_ERR_MSG_MOD(extack, "Invalid split configuration");
  2812. return -EINVAL;
  2813. }
  2814. } else {
  2815. base_port = mlxsw_sp_cluster_base_port_get(local_port);
  2816. if (mlxsw_sp->ports[base_port + 1] ||
  2817. mlxsw_sp->ports[base_port + 3]) {
  2818. netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
  2819. NL_SET_ERR_MSG_MOD(extack, "Invalid split configuration");
  2820. return -EINVAL;
  2821. }
  2822. }
  2823. for (i = 0; i < count; i++)
  2824. if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
  2825. mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
  2826. err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
  2827. if (err) {
  2828. dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
  2829. goto err_port_split_create;
  2830. }
  2831. return 0;
  2832. err_port_split_create:
  2833. mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
  2834. return err;
  2835. }
  2836. static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port,
  2837. struct netlink_ext_ack *extack)
  2838. {
  2839. struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
  2840. struct mlxsw_sp_port *mlxsw_sp_port;
  2841. u8 cur_width, base_port;
  2842. unsigned int count;
  2843. int i;
  2844. mlxsw_sp_port = mlxsw_sp->ports[local_port];
  2845. if (!mlxsw_sp_port) {
  2846. dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
  2847. local_port);
  2848. NL_SET_ERR_MSG_MOD(extack, "Port number does not exist");
  2849. return -EINVAL;
  2850. }
  2851. if (!mlxsw_sp_port->split) {
  2852. netdev_err(mlxsw_sp_port->dev, "Port was not split\n");
  2853. NL_SET_ERR_MSG_MOD(extack, "Port was not split");
  2854. return -EINVAL;
  2855. }
  2856. cur_width = mlxsw_sp_port->mapping.width;
  2857. count = cur_width == 1 ? 4 : 2;
  2858. base_port = mlxsw_sp_cluster_base_port_get(local_port);
  2859. /* Determine which ports to remove. */
  2860. if (count == 2 && local_port >= base_port + 2)
  2861. base_port = base_port + 2;
  2862. for (i = 0; i < count; i++)
  2863. if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
  2864. mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
  2865. mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
  2866. return 0;
  2867. }
  2868. static void
  2869. mlxsw_sp_port_down_wipe_counters(struct mlxsw_sp_port *mlxsw_sp_port)
  2870. {
  2871. int i;
  2872. for (i = 0; i < TC_MAX_QUEUE; i++)
  2873. mlxsw_sp_port->periodic_hw_stats.xstats.backlog[i] = 0;
  2874. }
  2875. static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
  2876. char *pude_pl, void *priv)
  2877. {
  2878. struct mlxsw_sp *mlxsw_sp = priv;
  2879. struct mlxsw_sp_port *mlxsw_sp_port;
  2880. enum mlxsw_reg_pude_oper_status status;
  2881. u8 local_port;
  2882. local_port = mlxsw_reg_pude_local_port_get(pude_pl);
  2883. mlxsw_sp_port = mlxsw_sp->ports[local_port];
  2884. if (!mlxsw_sp_port)
  2885. return;
  2886. status = mlxsw_reg_pude_oper_status_get(pude_pl);
  2887. if (status == MLXSW_PORT_OPER_STATUS_UP) {
  2888. netdev_info(mlxsw_sp_port->dev, "link up\n");
  2889. netif_carrier_on(mlxsw_sp_port->dev);
  2890. } else {
  2891. netdev_info(mlxsw_sp_port->dev, "link down\n");
  2892. netif_carrier_off(mlxsw_sp_port->dev);
  2893. mlxsw_sp_port_down_wipe_counters(mlxsw_sp_port);
  2894. }
  2895. }
  2896. static void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
  2897. u8 local_port, void *priv)
  2898. {
  2899. struct mlxsw_sp *mlxsw_sp = priv;
  2900. struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
  2901. struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
  2902. if (unlikely(!mlxsw_sp_port)) {
  2903. dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
  2904. local_port);
  2905. return;
  2906. }
  2907. skb->dev = mlxsw_sp_port->dev;
  2908. pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
  2909. u64_stats_update_begin(&pcpu_stats->syncp);
  2910. pcpu_stats->rx_packets++;
  2911. pcpu_stats->rx_bytes += skb->len;
  2912. u64_stats_update_end(&pcpu_stats->syncp);
  2913. skb->protocol = eth_type_trans(skb, skb->dev);
  2914. netif_receive_skb(skb);
  2915. }
  2916. static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
  2917. void *priv)
  2918. {
  2919. skb->offload_fwd_mark = 1;
  2920. return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
  2921. }
  2922. static void mlxsw_sp_rx_listener_mr_mark_func(struct sk_buff *skb,
  2923. u8 local_port, void *priv)
  2924. {
  2925. skb->offload_mr_fwd_mark = 1;
  2926. skb->offload_fwd_mark = 1;
  2927. return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
  2928. }
  2929. static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port,
  2930. void *priv)
  2931. {
  2932. struct mlxsw_sp *mlxsw_sp = priv;
  2933. struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
  2934. struct psample_group *psample_group;
  2935. u32 size;
  2936. if (unlikely(!mlxsw_sp_port)) {
  2937. dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n",
  2938. local_port);
  2939. goto out;
  2940. }
  2941. if (unlikely(!mlxsw_sp_port->sample)) {
  2942. dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n",
  2943. local_port);
  2944. goto out;
  2945. }
  2946. size = mlxsw_sp_port->sample->truncate ?
  2947. mlxsw_sp_port->sample->trunc_size : skb->len;
  2948. rcu_read_lock();
  2949. psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group);
  2950. if (!psample_group)
  2951. goto out_unlock;
  2952. psample_sample_packet(psample_group, skb, size,
  2953. mlxsw_sp_port->dev->ifindex, 0,
  2954. mlxsw_sp_port->sample->rate);
  2955. out_unlock:
  2956. rcu_read_unlock();
  2957. out:
  2958. consume_skb(skb);
  2959. }
  2960. #define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
  2961. MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
  2962. _is_ctrl, SP_##_trap_group, DISCARD)
  2963. #define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
  2964. MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \
  2965. _is_ctrl, SP_##_trap_group, DISCARD)
  2966. #define MLXSW_SP_RXL_MR_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
  2967. MLXSW_RXL(mlxsw_sp_rx_listener_mr_mark_func, _trap_id, _action, \
  2968. _is_ctrl, SP_##_trap_group, DISCARD)
  2969. #define MLXSW_SP_EVENTL(_func, _trap_id) \
  2970. MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
  2971. static const struct mlxsw_listener mlxsw_sp_listener[] = {
  2972. /* Events */
  2973. MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
  2974. /* L2 traps */
  2975. MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true),
  2976. MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true),
  2977. MLXSW_SP_RXL_NO_MARK(LLDP, TRAP_TO_CPU, LLDP, true),
  2978. MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false),
  2979. MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false),
  2980. MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false),
  2981. MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false),
  2982. MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false),
  2983. MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false),
  2984. MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false),
  2985. MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false),
  2986. MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, IP2ME, false),
  2987. MLXSW_SP_RXL_MARK(IPV6_MLDV12_LISTENER_QUERY, MIRROR_TO_CPU, IPV6_MLD,
  2988. false),
  2989. MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
  2990. false),
  2991. MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_DONE, TRAP_TO_CPU, IPV6_MLD,
  2992. false),
  2993. MLXSW_SP_RXL_NO_MARK(IPV6_MLDV2_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
  2994. false),
  2995. /* L3 traps */
  2996. MLXSW_SP_RXL_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false),
  2997. MLXSW_SP_RXL_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false),
  2998. MLXSW_SP_RXL_MARK(LBERROR, TRAP_TO_CPU, ROUTER_EXP, false),
  2999. MLXSW_SP_RXL_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false),
  3000. MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP,
  3001. false),
  3002. MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, false),
  3003. MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false),
  3004. MLXSW_SP_RXL_MARK(IPV6_ALL_NODES_LINK, TRAP_TO_CPU, ROUTER_EXP, false),
  3005. MLXSW_SP_RXL_MARK(IPV6_ALL_ROUTERS_LINK, TRAP_TO_CPU, ROUTER_EXP,
  3006. false),
  3007. MLXSW_SP_RXL_MARK(IPV4_OSPF, TRAP_TO_CPU, OSPF, false),
  3008. MLXSW_SP_RXL_MARK(IPV6_OSPF, TRAP_TO_CPU, OSPF, false),
  3009. MLXSW_SP_RXL_MARK(IPV6_DHCP, TRAP_TO_CPU, DHCP, false),
  3010. MLXSW_SP_RXL_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false),
  3011. MLXSW_SP_RXL_MARK(IPV4_BGP, TRAP_TO_CPU, BGP, false),
  3012. MLXSW_SP_RXL_MARK(IPV6_BGP, TRAP_TO_CPU, BGP, false),
  3013. MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
  3014. false),
  3015. MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
  3016. false),
  3017. MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
  3018. false),
  3019. MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
  3020. false),
  3021. MLXSW_SP_RXL_MARK(L3_IPV6_REDIRECTION, TRAP_TO_CPU, IPV6_ND, false),
  3022. MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP,
  3023. false),
  3024. MLXSW_SP_RXL_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, HOST_MISS, false),
  3025. MLXSW_SP_RXL_MARK(HOST_MISS_IPV6, TRAP_TO_CPU, HOST_MISS, false),
  3026. MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV4, TRAP_TO_CPU, ROUTER_EXP, false),
  3027. MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV6, TRAP_TO_CPU, ROUTER_EXP, false),
  3028. MLXSW_SP_RXL_MARK(IPIP_DECAP_ERROR, TRAP_TO_CPU, ROUTER_EXP, false),
  3029. MLXSW_SP_RXL_MARK(IPV4_VRRP, TRAP_TO_CPU, ROUTER_EXP, false),
  3030. MLXSW_SP_RXL_MARK(IPV6_VRRP, TRAP_TO_CPU, ROUTER_EXP, false),
  3031. /* PKT Sample trap */
  3032. MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU,
  3033. false, SP_IP2ME, DISCARD),
  3034. /* ACL trap */
  3035. MLXSW_SP_RXL_NO_MARK(ACL0, TRAP_TO_CPU, IP2ME, false),
  3036. /* Multicast Router Traps */
  3037. MLXSW_SP_RXL_MARK(IPV4_PIM, TRAP_TO_CPU, PIM, false),
  3038. MLXSW_SP_RXL_MARK(IPV6_PIM, TRAP_TO_CPU, PIM, false),
  3039. MLXSW_SP_RXL_MARK(RPF, TRAP_TO_CPU, RPF, false),
  3040. MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false),
  3041. MLXSW_SP_RXL_MR_MARK(ACL2, TRAP_TO_CPU, MULTICAST, false),
  3042. };
  3043. static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
  3044. {
  3045. char qpcr_pl[MLXSW_REG_QPCR_LEN];
  3046. enum mlxsw_reg_qpcr_ir_units ir_units;
  3047. int max_cpu_policers;
  3048. bool is_bytes;
  3049. u8 burst_size;
  3050. u32 rate;
  3051. int i, err;
  3052. if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
  3053. return -EIO;
  3054. max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
  3055. ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
  3056. for (i = 0; i < max_cpu_policers; i++) {
  3057. is_bytes = false;
  3058. switch (i) {
  3059. case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
  3060. case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
  3061. case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
  3062. case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
  3063. case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
  3064. case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
  3065. rate = 128;
  3066. burst_size = 7;
  3067. break;
  3068. case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
  3069. case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
  3070. rate = 16 * 1024;
  3071. burst_size = 10;
  3072. break;
  3073. case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
  3074. case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
  3075. case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
  3076. case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
  3077. case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
  3078. case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
  3079. case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
  3080. case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
  3081. rate = 1024;
  3082. burst_size = 7;
  3083. break;
  3084. case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
  3085. rate = 4 * 1024;
  3086. burst_size = 4;
  3087. break;
  3088. default:
  3089. continue;
  3090. }
  3091. mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
  3092. burst_size);
  3093. err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
  3094. if (err)
  3095. return err;
  3096. }
  3097. return 0;
  3098. }
  3099. static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
  3100. {
  3101. char htgt_pl[MLXSW_REG_HTGT_LEN];
  3102. enum mlxsw_reg_htgt_trap_group i;
  3103. int max_cpu_policers;
  3104. int max_trap_groups;
  3105. u8 priority, tc;
  3106. u16 policer_id;
  3107. int err;
  3108. if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
  3109. return -EIO;
  3110. max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
  3111. max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
  3112. for (i = 0; i < max_trap_groups; i++) {
  3113. policer_id = i;
  3114. switch (i) {
  3115. case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
  3116. case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
  3117. case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
  3118. case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
  3119. case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
  3120. priority = 5;
  3121. tc = 5;
  3122. break;
  3123. case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
  3124. case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
  3125. priority = 4;
  3126. tc = 4;
  3127. break;
  3128. case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
  3129. case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
  3130. case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
  3131. priority = 3;
  3132. tc = 3;
  3133. break;
  3134. case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
  3135. case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
  3136. case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
  3137. priority = 2;
  3138. tc = 2;
  3139. break;
  3140. case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
  3141. case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
  3142. case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
  3143. case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
  3144. priority = 1;
  3145. tc = 1;
  3146. break;
  3147. case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
  3148. priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
  3149. tc = MLXSW_REG_HTGT_DEFAULT_TC;
  3150. policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
  3151. break;
  3152. default:
  3153. continue;
  3154. }
  3155. if (max_cpu_policers <= policer_id &&
  3156. policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
  3157. return -EIO;
  3158. mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
  3159. err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
  3160. if (err)
  3161. return err;
  3162. }
  3163. return 0;
  3164. }
  3165. static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
  3166. {
  3167. int i;
  3168. int err;
  3169. err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
  3170. if (err)
  3171. return err;
  3172. err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
  3173. if (err)
  3174. return err;
  3175. for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
  3176. err = mlxsw_core_trap_register(mlxsw_sp->core,
  3177. &mlxsw_sp_listener[i],
  3178. mlxsw_sp);
  3179. if (err)
  3180. goto err_listener_register;
  3181. }
  3182. return 0;
  3183. err_listener_register:
  3184. for (i--; i >= 0; i--) {
  3185. mlxsw_core_trap_unregister(mlxsw_sp->core,
  3186. &mlxsw_sp_listener[i],
  3187. mlxsw_sp);
  3188. }
  3189. return err;
  3190. }
  3191. static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
  3192. {
  3193. int i;
  3194. for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
  3195. mlxsw_core_trap_unregister(mlxsw_sp->core,
  3196. &mlxsw_sp_listener[i],
  3197. mlxsw_sp);
  3198. }
  3199. }
  3200. static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
  3201. {
  3202. char slcr_pl[MLXSW_REG_SLCR_LEN];
  3203. int err;
  3204. mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
  3205. MLXSW_REG_SLCR_LAG_HASH_DMAC |
  3206. MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
  3207. MLXSW_REG_SLCR_LAG_HASH_VLANID |
  3208. MLXSW_REG_SLCR_LAG_HASH_SIP |
  3209. MLXSW_REG_SLCR_LAG_HASH_DIP |
  3210. MLXSW_REG_SLCR_LAG_HASH_SPORT |
  3211. MLXSW_REG_SLCR_LAG_HASH_DPORT |
  3212. MLXSW_REG_SLCR_LAG_HASH_IPPROTO);
  3213. err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
  3214. if (err)
  3215. return err;
  3216. if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) ||
  3217. !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
  3218. return -EIO;
  3219. mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG),
  3220. sizeof(struct mlxsw_sp_upper),
  3221. GFP_KERNEL);
  3222. if (!mlxsw_sp->lags)
  3223. return -ENOMEM;
  3224. return 0;
  3225. }
  3226. static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
  3227. {
  3228. kfree(mlxsw_sp->lags);
  3229. }
  3230. static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
  3231. {
  3232. char htgt_pl[MLXSW_REG_HTGT_LEN];
  3233. mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
  3234. MLXSW_REG_HTGT_INVALID_POLICER,
  3235. MLXSW_REG_HTGT_DEFAULT_PRIORITY,
  3236. MLXSW_REG_HTGT_DEFAULT_TC);
  3237. return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
  3238. }
  3239. static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
  3240. unsigned long event, void *ptr);
  3241. static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
  3242. const struct mlxsw_bus_info *mlxsw_bus_info)
  3243. {
  3244. struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
  3245. int err;
  3246. mlxsw_sp->core = mlxsw_core;
  3247. mlxsw_sp->bus_info = mlxsw_bus_info;
  3248. err = mlxsw_sp_fw_rev_validate(mlxsw_sp);
  3249. if (err)
  3250. return err;
  3251. err = mlxsw_sp_base_mac_get(mlxsw_sp);
  3252. if (err) {
  3253. dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
  3254. return err;
  3255. }
  3256. err = mlxsw_sp_kvdl_init(mlxsw_sp);
  3257. if (err) {
  3258. dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize KVDL\n");
  3259. return err;
  3260. }
  3261. err = mlxsw_sp_fids_init(mlxsw_sp);
  3262. if (err) {
  3263. dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n");
  3264. goto err_fids_init;
  3265. }
  3266. err = mlxsw_sp_traps_init(mlxsw_sp);
  3267. if (err) {
  3268. dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
  3269. goto err_traps_init;
  3270. }
  3271. err = mlxsw_sp_buffers_init(mlxsw_sp);
  3272. if (err) {
  3273. dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
  3274. goto err_buffers_init;
  3275. }
  3276. err = mlxsw_sp_lag_init(mlxsw_sp);
  3277. if (err) {
  3278. dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
  3279. goto err_lag_init;
  3280. }
  3281. /* Initialize SPAN before router and switchdev, so that those components
  3282. * can call mlxsw_sp_span_respin().
  3283. */
  3284. err = mlxsw_sp_span_init(mlxsw_sp);
  3285. if (err) {
  3286. dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
  3287. goto err_span_init;
  3288. }
  3289. err = mlxsw_sp_switchdev_init(mlxsw_sp);
  3290. if (err) {
  3291. dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
  3292. goto err_switchdev_init;
  3293. }
  3294. err = mlxsw_sp_counter_pool_init(mlxsw_sp);
  3295. if (err) {
  3296. dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n");
  3297. goto err_counter_pool_init;
  3298. }
  3299. err = mlxsw_sp_afa_init(mlxsw_sp);
  3300. if (err) {
  3301. dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n");
  3302. goto err_afa_init;
  3303. }
  3304. err = mlxsw_sp_router_init(mlxsw_sp);
  3305. if (err) {
  3306. dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
  3307. goto err_router_init;
  3308. }
  3309. /* Initialize netdevice notifier after router and SPAN is initialized,
  3310. * so that the event handler can use router structures and call SPAN
  3311. * respin.
  3312. */
  3313. mlxsw_sp->netdevice_nb.notifier_call = mlxsw_sp_netdevice_event;
  3314. err = register_netdevice_notifier(&mlxsw_sp->netdevice_nb);
  3315. if (err) {
  3316. dev_err(mlxsw_sp->bus_info->dev, "Failed to register netdev notifier\n");
  3317. goto err_netdev_notifier;
  3318. }
  3319. err = mlxsw_sp_acl_init(mlxsw_sp);
  3320. if (err) {
  3321. dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n");
  3322. goto err_acl_init;
  3323. }
  3324. err = mlxsw_sp_dpipe_init(mlxsw_sp);
  3325. if (err) {
  3326. dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n");
  3327. goto err_dpipe_init;
  3328. }
  3329. err = mlxsw_sp_ports_create(mlxsw_sp);
  3330. if (err) {
  3331. dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
  3332. goto err_ports_create;
  3333. }
  3334. return 0;
  3335. err_ports_create:
  3336. mlxsw_sp_dpipe_fini(mlxsw_sp);
  3337. err_dpipe_init:
  3338. mlxsw_sp_acl_fini(mlxsw_sp);
  3339. err_acl_init:
  3340. unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
  3341. err_netdev_notifier:
  3342. mlxsw_sp_router_fini(mlxsw_sp);
  3343. err_router_init:
  3344. mlxsw_sp_afa_fini(mlxsw_sp);
  3345. err_afa_init:
  3346. mlxsw_sp_counter_pool_fini(mlxsw_sp);
  3347. err_counter_pool_init:
  3348. mlxsw_sp_switchdev_fini(mlxsw_sp);
  3349. err_switchdev_init:
  3350. mlxsw_sp_span_fini(mlxsw_sp);
  3351. err_span_init:
  3352. mlxsw_sp_lag_fini(mlxsw_sp);
  3353. err_lag_init:
  3354. mlxsw_sp_buffers_fini(mlxsw_sp);
  3355. err_buffers_init:
  3356. mlxsw_sp_traps_fini(mlxsw_sp);
  3357. err_traps_init:
  3358. mlxsw_sp_fids_fini(mlxsw_sp);
  3359. err_fids_init:
  3360. mlxsw_sp_kvdl_fini(mlxsw_sp);
  3361. return err;
  3362. }
  3363. static int mlxsw_sp1_init(struct mlxsw_core *mlxsw_core,
  3364. const struct mlxsw_bus_info *mlxsw_bus_info)
  3365. {
  3366. struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
  3367. mlxsw_sp->req_rev = &mlxsw_sp1_fw_rev;
  3368. mlxsw_sp->fw_filename = MLXSW_SP1_FW_FILENAME;
  3369. mlxsw_sp->kvdl_ops = &mlxsw_sp1_kvdl_ops;
  3370. mlxsw_sp->afa_ops = &mlxsw_sp1_act_afa_ops;
  3371. mlxsw_sp->afk_ops = &mlxsw_sp1_afk_ops;
  3372. mlxsw_sp->mr_tcam_ops = &mlxsw_sp1_mr_tcam_ops;
  3373. mlxsw_sp->acl_tcam_ops = &mlxsw_sp1_acl_tcam_ops;
  3374. return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info);
  3375. }
  3376. static int mlxsw_sp2_init(struct mlxsw_core *mlxsw_core,
  3377. const struct mlxsw_bus_info *mlxsw_bus_info)
  3378. {
  3379. struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
  3380. mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops;
  3381. mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops;
  3382. mlxsw_sp->afk_ops = &mlxsw_sp2_afk_ops;
  3383. mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops;
  3384. mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops;
  3385. return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info);
  3386. }
  3387. static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
  3388. {
  3389. struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
  3390. mlxsw_sp_ports_remove(mlxsw_sp);
  3391. mlxsw_sp_dpipe_fini(mlxsw_sp);
  3392. mlxsw_sp_acl_fini(mlxsw_sp);
  3393. unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
  3394. mlxsw_sp_router_fini(mlxsw_sp);
  3395. mlxsw_sp_afa_fini(mlxsw_sp);
  3396. mlxsw_sp_counter_pool_fini(mlxsw_sp);
  3397. mlxsw_sp_switchdev_fini(mlxsw_sp);
  3398. mlxsw_sp_span_fini(mlxsw_sp);
  3399. mlxsw_sp_lag_fini(mlxsw_sp);
  3400. mlxsw_sp_buffers_fini(mlxsw_sp);
  3401. mlxsw_sp_traps_fini(mlxsw_sp);
  3402. mlxsw_sp_fids_fini(mlxsw_sp);
  3403. mlxsw_sp_kvdl_fini(mlxsw_sp);
  3404. }
  3405. static const struct mlxsw_config_profile mlxsw_sp1_config_profile = {
  3406. .used_max_mid = 1,
  3407. .max_mid = MLXSW_SP_MID_MAX,
  3408. .used_flood_tables = 1,
  3409. .used_flood_mode = 1,
  3410. .flood_mode = 3,
  3411. .max_fid_offset_flood_tables = 3,
  3412. .fid_offset_flood_table_size = VLAN_N_VID - 1,
  3413. .max_fid_flood_tables = 3,
  3414. .fid_flood_table_size = MLXSW_SP_FID_8021D_MAX,
  3415. .used_max_ib_mc = 1,
  3416. .max_ib_mc = 0,
  3417. .used_max_pkey = 1,
  3418. .max_pkey = 0,
  3419. .used_kvd_sizes = 1,
  3420. .kvd_hash_single_parts = 59,
  3421. .kvd_hash_double_parts = 41,
  3422. .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE,
  3423. .swid_config = {
  3424. {
  3425. .used_type = 1,
  3426. .type = MLXSW_PORT_SWID_TYPE_ETH,
  3427. }
  3428. },
  3429. };
  3430. static const struct mlxsw_config_profile mlxsw_sp2_config_profile = {
  3431. .used_max_mid = 1,
  3432. .max_mid = MLXSW_SP_MID_MAX,
  3433. .used_flood_tables = 1,
  3434. .used_flood_mode = 1,
  3435. .flood_mode = 3,
  3436. .max_fid_offset_flood_tables = 3,
  3437. .fid_offset_flood_table_size = VLAN_N_VID - 1,
  3438. .max_fid_flood_tables = 3,
  3439. .fid_flood_table_size = MLXSW_SP_FID_8021D_MAX,
  3440. .used_max_ib_mc = 1,
  3441. .max_ib_mc = 0,
  3442. .used_max_pkey = 1,
  3443. .max_pkey = 0,
  3444. .swid_config = {
  3445. {
  3446. .used_type = 1,
  3447. .type = MLXSW_PORT_SWID_TYPE_ETH,
  3448. }
  3449. },
  3450. };
  3451. static void
  3452. mlxsw_sp_resource_size_params_prepare(struct mlxsw_core *mlxsw_core,
  3453. struct devlink_resource_size_params *kvd_size_params,
  3454. struct devlink_resource_size_params *linear_size_params,
  3455. struct devlink_resource_size_params *hash_double_size_params,
  3456. struct devlink_resource_size_params *hash_single_size_params)
  3457. {
  3458. u32 single_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
  3459. KVD_SINGLE_MIN_SIZE);
  3460. u32 double_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
  3461. KVD_DOUBLE_MIN_SIZE);
  3462. u32 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
  3463. u32 linear_size_min = 0;
  3464. devlink_resource_size_params_init(kvd_size_params, kvd_size, kvd_size,
  3465. MLXSW_SP_KVD_GRANULARITY,
  3466. DEVLINK_RESOURCE_UNIT_ENTRY);
  3467. devlink_resource_size_params_init(linear_size_params, linear_size_min,
  3468. kvd_size - single_size_min -
  3469. double_size_min,
  3470. MLXSW_SP_KVD_GRANULARITY,
  3471. DEVLINK_RESOURCE_UNIT_ENTRY);
  3472. devlink_resource_size_params_init(hash_double_size_params,
  3473. double_size_min,
  3474. kvd_size - single_size_min -
  3475. linear_size_min,
  3476. MLXSW_SP_KVD_GRANULARITY,
  3477. DEVLINK_RESOURCE_UNIT_ENTRY);
  3478. devlink_resource_size_params_init(hash_single_size_params,
  3479. single_size_min,
  3480. kvd_size - double_size_min -
  3481. linear_size_min,
  3482. MLXSW_SP_KVD_GRANULARITY,
  3483. DEVLINK_RESOURCE_UNIT_ENTRY);
  3484. }
  3485. static int mlxsw_sp1_resources_kvd_register(struct mlxsw_core *mlxsw_core)
  3486. {
  3487. struct devlink *devlink = priv_to_devlink(mlxsw_core);
  3488. struct devlink_resource_size_params hash_single_size_params;
  3489. struct devlink_resource_size_params hash_double_size_params;
  3490. struct devlink_resource_size_params linear_size_params;
  3491. struct devlink_resource_size_params kvd_size_params;
  3492. u32 kvd_size, single_size, double_size, linear_size;
  3493. const struct mlxsw_config_profile *profile;
  3494. int err;
  3495. profile = &mlxsw_sp1_config_profile;
  3496. if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE))
  3497. return -EIO;
  3498. mlxsw_sp_resource_size_params_prepare(mlxsw_core, &kvd_size_params,
  3499. &linear_size_params,
  3500. &hash_double_size_params,
  3501. &hash_single_size_params);
  3502. kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
  3503. err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD,
  3504. kvd_size, MLXSW_SP_RESOURCE_KVD,
  3505. DEVLINK_RESOURCE_ID_PARENT_TOP,
  3506. &kvd_size_params);
  3507. if (err)
  3508. return err;
  3509. linear_size = profile->kvd_linear_size;
  3510. err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_LINEAR,
  3511. linear_size,
  3512. MLXSW_SP_RESOURCE_KVD_LINEAR,
  3513. MLXSW_SP_RESOURCE_KVD,
  3514. &linear_size_params);
  3515. if (err)
  3516. return err;
  3517. err = mlxsw_sp1_kvdl_resources_register(mlxsw_core);
  3518. if (err)
  3519. return err;
  3520. double_size = kvd_size - linear_size;
  3521. double_size *= profile->kvd_hash_double_parts;
  3522. double_size /= profile->kvd_hash_double_parts +
  3523. profile->kvd_hash_single_parts;
  3524. double_size = rounddown(double_size, MLXSW_SP_KVD_GRANULARITY);
  3525. err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_DOUBLE,
  3526. double_size,
  3527. MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
  3528. MLXSW_SP_RESOURCE_KVD,
  3529. &hash_double_size_params);
  3530. if (err)
  3531. return err;
  3532. single_size = kvd_size - double_size - linear_size;
  3533. err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_SINGLE,
  3534. single_size,
  3535. MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
  3536. MLXSW_SP_RESOURCE_KVD,
  3537. &hash_single_size_params);
  3538. if (err)
  3539. return err;
  3540. return 0;
  3541. }
  3542. static int mlxsw_sp1_resources_register(struct mlxsw_core *mlxsw_core)
  3543. {
  3544. return mlxsw_sp1_resources_kvd_register(mlxsw_core);
  3545. }
  3546. static int mlxsw_sp2_resources_register(struct mlxsw_core *mlxsw_core)
  3547. {
  3548. return 0;
  3549. }
  3550. static int mlxsw_sp_kvd_sizes_get(struct mlxsw_core *mlxsw_core,
  3551. const struct mlxsw_config_profile *profile,
  3552. u64 *p_single_size, u64 *p_double_size,
  3553. u64 *p_linear_size)
  3554. {
  3555. struct devlink *devlink = priv_to_devlink(mlxsw_core);
  3556. u32 double_size;
  3557. int err;
  3558. if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
  3559. !MLXSW_CORE_RES_VALID(mlxsw_core, KVD_DOUBLE_MIN_SIZE))
  3560. return -EIO;
  3561. /* The hash part is what left of the kvd without the
  3562. * linear part. It is split to the single size and
  3563. * double size by the parts ratio from the profile.
  3564. * Both sizes must be a multiplications of the
  3565. * granularity from the profile. In case the user
  3566. * provided the sizes they are obtained via devlink.
  3567. */
  3568. err = devlink_resource_size_get(devlink,
  3569. MLXSW_SP_RESOURCE_KVD_LINEAR,
  3570. p_linear_size);
  3571. if (err)
  3572. *p_linear_size = profile->kvd_linear_size;
  3573. err = devlink_resource_size_get(devlink,
  3574. MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
  3575. p_double_size);
  3576. if (err) {
  3577. double_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
  3578. *p_linear_size;
  3579. double_size *= profile->kvd_hash_double_parts;
  3580. double_size /= profile->kvd_hash_double_parts +
  3581. profile->kvd_hash_single_parts;
  3582. *p_double_size = rounddown(double_size,
  3583. MLXSW_SP_KVD_GRANULARITY);
  3584. }
  3585. err = devlink_resource_size_get(devlink,
  3586. MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
  3587. p_single_size);
  3588. if (err)
  3589. *p_single_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
  3590. *p_double_size - *p_linear_size;
  3591. /* Check results are legal. */
  3592. if (*p_single_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
  3593. *p_double_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE) ||
  3594. MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) < *p_linear_size)
  3595. return -EIO;
  3596. return 0;
  3597. }
  3598. static struct mlxsw_driver mlxsw_sp1_driver = {
  3599. .kind = mlxsw_sp1_driver_name,
  3600. .priv_size = sizeof(struct mlxsw_sp),
  3601. .init = mlxsw_sp1_init,
  3602. .fini = mlxsw_sp_fini,
  3603. .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
  3604. .port_split = mlxsw_sp_port_split,
  3605. .port_unsplit = mlxsw_sp_port_unsplit,
  3606. .sb_pool_get = mlxsw_sp_sb_pool_get,
  3607. .sb_pool_set = mlxsw_sp_sb_pool_set,
  3608. .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
  3609. .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
  3610. .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
  3611. .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
  3612. .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
  3613. .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
  3614. .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
  3615. .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
  3616. .txhdr_construct = mlxsw_sp_txhdr_construct,
  3617. .resources_register = mlxsw_sp1_resources_register,
  3618. .kvd_sizes_get = mlxsw_sp_kvd_sizes_get,
  3619. .txhdr_len = MLXSW_TXHDR_LEN,
  3620. .profile = &mlxsw_sp1_config_profile,
  3621. .res_query_enabled = true,
  3622. };
  3623. static struct mlxsw_driver mlxsw_sp2_driver = {
  3624. .kind = mlxsw_sp2_driver_name,
  3625. .priv_size = sizeof(struct mlxsw_sp),
  3626. .init = mlxsw_sp2_init,
  3627. .fini = mlxsw_sp_fini,
  3628. .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
  3629. .port_split = mlxsw_sp_port_split,
  3630. .port_unsplit = mlxsw_sp_port_unsplit,
  3631. .sb_pool_get = mlxsw_sp_sb_pool_get,
  3632. .sb_pool_set = mlxsw_sp_sb_pool_set,
  3633. .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
  3634. .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
  3635. .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
  3636. .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
  3637. .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
  3638. .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
  3639. .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
  3640. .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
  3641. .txhdr_construct = mlxsw_sp_txhdr_construct,
  3642. .resources_register = mlxsw_sp2_resources_register,
  3643. .txhdr_len = MLXSW_TXHDR_LEN,
  3644. .profile = &mlxsw_sp2_config_profile,
  3645. .res_query_enabled = true,
  3646. };
  3647. bool mlxsw_sp_port_dev_check(const struct net_device *dev)
  3648. {
  3649. return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
  3650. }
  3651. static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data)
  3652. {
  3653. struct mlxsw_sp_port **p_mlxsw_sp_port = data;
  3654. int ret = 0;
  3655. if (mlxsw_sp_port_dev_check(lower_dev)) {
  3656. *p_mlxsw_sp_port = netdev_priv(lower_dev);
  3657. ret = 1;
  3658. }
  3659. return ret;
  3660. }
  3661. struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
  3662. {
  3663. struct mlxsw_sp_port *mlxsw_sp_port;
  3664. if (mlxsw_sp_port_dev_check(dev))
  3665. return netdev_priv(dev);
  3666. mlxsw_sp_port = NULL;
  3667. netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &mlxsw_sp_port);
  3668. return mlxsw_sp_port;
  3669. }
  3670. struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
  3671. {
  3672. struct mlxsw_sp_port *mlxsw_sp_port;
  3673. mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
  3674. return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
  3675. }
  3676. struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
  3677. {
  3678. struct mlxsw_sp_port *mlxsw_sp_port;
  3679. if (mlxsw_sp_port_dev_check(dev))
  3680. return netdev_priv(dev);
  3681. mlxsw_sp_port = NULL;
  3682. netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk,
  3683. &mlxsw_sp_port);
  3684. return mlxsw_sp_port;
  3685. }
  3686. struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
  3687. {
  3688. struct mlxsw_sp_port *mlxsw_sp_port;
  3689. rcu_read_lock();
  3690. mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
  3691. if (mlxsw_sp_port)
  3692. dev_hold(mlxsw_sp_port->dev);
  3693. rcu_read_unlock();
  3694. return mlxsw_sp_port;
  3695. }
  3696. void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
  3697. {
  3698. dev_put(mlxsw_sp_port->dev);
  3699. }
  3700. static void
  3701. mlxsw_sp_port_lag_uppers_cleanup(struct mlxsw_sp_port *mlxsw_sp_port,
  3702. struct net_device *lag_dev)
  3703. {
  3704. struct net_device *br_dev = netdev_master_upper_dev_get(lag_dev);
  3705. struct net_device *upper_dev;
  3706. struct list_head *iter;
  3707. if (netif_is_bridge_port(lag_dev))
  3708. mlxsw_sp_port_bridge_leave(mlxsw_sp_port, lag_dev, br_dev);
  3709. netdev_for_each_upper_dev_rcu(lag_dev, upper_dev, iter) {
  3710. if (!netif_is_bridge_port(upper_dev))
  3711. continue;
  3712. br_dev = netdev_master_upper_dev_get(upper_dev);
  3713. mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev, br_dev);
  3714. }
  3715. }
  3716. static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
  3717. {
  3718. char sldr_pl[MLXSW_REG_SLDR_LEN];
  3719. mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
  3720. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
  3721. }
  3722. static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
  3723. {
  3724. char sldr_pl[MLXSW_REG_SLDR_LEN];
  3725. mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
  3726. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
  3727. }
  3728. static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
  3729. u16 lag_id, u8 port_index)
  3730. {
  3731. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  3732. char slcor_pl[MLXSW_REG_SLCOR_LEN];
  3733. mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
  3734. lag_id, port_index);
  3735. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
  3736. }
  3737. static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
  3738. u16 lag_id)
  3739. {
  3740. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  3741. char slcor_pl[MLXSW_REG_SLCOR_LEN];
  3742. mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
  3743. lag_id);
  3744. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
  3745. }
  3746. static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
  3747. u16 lag_id)
  3748. {
  3749. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  3750. char slcor_pl[MLXSW_REG_SLCOR_LEN];
  3751. mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
  3752. lag_id);
  3753. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
  3754. }
  3755. static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
  3756. u16 lag_id)
  3757. {
  3758. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  3759. char slcor_pl[MLXSW_REG_SLCOR_LEN];
  3760. mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
  3761. lag_id);
  3762. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
  3763. }
  3764. static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
  3765. struct net_device *lag_dev,
  3766. u16 *p_lag_id)
  3767. {
  3768. struct mlxsw_sp_upper *lag;
  3769. int free_lag_id = -1;
  3770. u64 max_lag;
  3771. int i;
  3772. max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG);
  3773. for (i = 0; i < max_lag; i++) {
  3774. lag = mlxsw_sp_lag_get(mlxsw_sp, i);
  3775. if (lag->ref_count) {
  3776. if (lag->dev == lag_dev) {
  3777. *p_lag_id = i;
  3778. return 0;
  3779. }
  3780. } else if (free_lag_id < 0) {
  3781. free_lag_id = i;
  3782. }
  3783. }
  3784. if (free_lag_id < 0)
  3785. return -EBUSY;
  3786. *p_lag_id = free_lag_id;
  3787. return 0;
  3788. }
  3789. static bool
  3790. mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
  3791. struct net_device *lag_dev,
  3792. struct netdev_lag_upper_info *lag_upper_info,
  3793. struct netlink_ext_ack *extack)
  3794. {
  3795. u16 lag_id;
  3796. if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0) {
  3797. NL_SET_ERR_MSG_MOD(extack, "Exceeded number of supported LAG devices");
  3798. return false;
  3799. }
  3800. if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
  3801. NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type");
  3802. return false;
  3803. }
  3804. return true;
  3805. }
  3806. static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
  3807. u16 lag_id, u8 *p_port_index)
  3808. {
  3809. u64 max_lag_members;
  3810. int i;
  3811. max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
  3812. MAX_LAG_MEMBERS);
  3813. for (i = 0; i < max_lag_members; i++) {
  3814. if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
  3815. *p_port_index = i;
  3816. return 0;
  3817. }
  3818. }
  3819. return -EBUSY;
  3820. }
  3821. static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
  3822. struct net_device *lag_dev)
  3823. {
  3824. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  3825. struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
  3826. struct mlxsw_sp_upper *lag;
  3827. u16 lag_id;
  3828. u8 port_index;
  3829. int err;
  3830. err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
  3831. if (err)
  3832. return err;
  3833. lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
  3834. if (!lag->ref_count) {
  3835. err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
  3836. if (err)
  3837. return err;
  3838. lag->dev = lag_dev;
  3839. }
  3840. err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
  3841. if (err)
  3842. return err;
  3843. err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
  3844. if (err)
  3845. goto err_col_port_add;
  3846. mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
  3847. mlxsw_sp_port->local_port);
  3848. mlxsw_sp_port->lag_id = lag_id;
  3849. mlxsw_sp_port->lagged = 1;
  3850. lag->ref_count++;
  3851. /* Port is no longer usable as a router interface */
  3852. mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, 1);
  3853. if (mlxsw_sp_port_vlan->fid)
  3854. mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
  3855. return 0;
  3856. err_col_port_add:
  3857. if (!lag->ref_count)
  3858. mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
  3859. return err;
  3860. }
  3861. static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
  3862. struct net_device *lag_dev)
  3863. {
  3864. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  3865. u16 lag_id = mlxsw_sp_port->lag_id;
  3866. struct mlxsw_sp_upper *lag;
  3867. if (!mlxsw_sp_port->lagged)
  3868. return;
  3869. lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
  3870. WARN_ON(lag->ref_count == 0);
  3871. mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
  3872. /* Any VLANs configured on the port are no longer valid */
  3873. mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
  3874. /* Make the LAG and its directly linked uppers leave bridges they
  3875. * are memeber in
  3876. */
  3877. mlxsw_sp_port_lag_uppers_cleanup(mlxsw_sp_port, lag_dev);
  3878. if (lag->ref_count == 1)
  3879. mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
  3880. mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
  3881. mlxsw_sp_port->local_port);
  3882. mlxsw_sp_port->lagged = 0;
  3883. lag->ref_count--;
  3884. mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
  3885. /* Make sure untagged frames are allowed to ingress */
  3886. mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
  3887. }
  3888. static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
  3889. u16 lag_id)
  3890. {
  3891. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  3892. char sldr_pl[MLXSW_REG_SLDR_LEN];
  3893. mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
  3894. mlxsw_sp_port->local_port);
  3895. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
  3896. }
  3897. static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
  3898. u16 lag_id)
  3899. {
  3900. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  3901. char sldr_pl[MLXSW_REG_SLDR_LEN];
  3902. mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
  3903. mlxsw_sp_port->local_port);
  3904. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
  3905. }
  3906. static int
  3907. mlxsw_sp_port_lag_col_dist_enable(struct mlxsw_sp_port *mlxsw_sp_port)
  3908. {
  3909. int err;
  3910. err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port,
  3911. mlxsw_sp_port->lag_id);
  3912. if (err)
  3913. return err;
  3914. err = mlxsw_sp_lag_dist_port_add(mlxsw_sp_port, mlxsw_sp_port->lag_id);
  3915. if (err)
  3916. goto err_dist_port_add;
  3917. return 0;
  3918. err_dist_port_add:
  3919. mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, mlxsw_sp_port->lag_id);
  3920. return err;
  3921. }
  3922. static int
  3923. mlxsw_sp_port_lag_col_dist_disable(struct mlxsw_sp_port *mlxsw_sp_port)
  3924. {
  3925. int err;
  3926. err = mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
  3927. mlxsw_sp_port->lag_id);
  3928. if (err)
  3929. return err;
  3930. err = mlxsw_sp_lag_col_port_disable(mlxsw_sp_port,
  3931. mlxsw_sp_port->lag_id);
  3932. if (err)
  3933. goto err_col_port_disable;
  3934. return 0;
  3935. err_col_port_disable:
  3936. mlxsw_sp_lag_dist_port_add(mlxsw_sp_port, mlxsw_sp_port->lag_id);
  3937. return err;
  3938. }
  3939. static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
  3940. struct netdev_lag_lower_state_info *info)
  3941. {
  3942. if (info->tx_enabled)
  3943. return mlxsw_sp_port_lag_col_dist_enable(mlxsw_sp_port);
  3944. else
  3945. return mlxsw_sp_port_lag_col_dist_disable(mlxsw_sp_port);
  3946. }
  3947. static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port,
  3948. bool enable)
  3949. {
  3950. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  3951. enum mlxsw_reg_spms_state spms_state;
  3952. char *spms_pl;
  3953. u16 vid;
  3954. int err;
  3955. spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING :
  3956. MLXSW_REG_SPMS_STATE_DISCARDING;
  3957. spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
  3958. if (!spms_pl)
  3959. return -ENOMEM;
  3960. mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
  3961. for (vid = 0; vid < VLAN_N_VID; vid++)
  3962. mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
  3963. err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
  3964. kfree(spms_pl);
  3965. return err;
  3966. }
  3967. static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port)
  3968. {
  3969. u16 vid = 1;
  3970. int err;
  3971. err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
  3972. if (err)
  3973. return err;
  3974. err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true);
  3975. if (err)
  3976. goto err_port_stp_set;
  3977. err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
  3978. true, false);
  3979. if (err)
  3980. goto err_port_vlan_set;
  3981. for (; vid <= VLAN_N_VID - 1; vid++) {
  3982. err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
  3983. vid, false);
  3984. if (err)
  3985. goto err_vid_learning_set;
  3986. }
  3987. return 0;
  3988. err_vid_learning_set:
  3989. for (vid--; vid >= 1; vid--)
  3990. mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, true);
  3991. err_port_vlan_set:
  3992. mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
  3993. err_port_stp_set:
  3994. mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
  3995. return err;
  3996. }
  3997. static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port)
  3998. {
  3999. u16 vid;
  4000. for (vid = VLAN_N_VID - 1; vid >= 1; vid--)
  4001. mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
  4002. vid, true);
  4003. mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
  4004. false, false);
  4005. mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
  4006. mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
  4007. }
  4008. static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev,
  4009. struct net_device *dev,
  4010. unsigned long event, void *ptr)
  4011. {
  4012. struct netdev_notifier_changeupper_info *info;
  4013. struct mlxsw_sp_port *mlxsw_sp_port;
  4014. struct netlink_ext_ack *extack;
  4015. struct net_device *upper_dev;
  4016. struct mlxsw_sp *mlxsw_sp;
  4017. int err = 0;
  4018. mlxsw_sp_port = netdev_priv(dev);
  4019. mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  4020. info = ptr;
  4021. extack = netdev_notifier_info_to_extack(&info->info);
  4022. switch (event) {
  4023. case NETDEV_PRECHANGEUPPER:
  4024. upper_dev = info->upper_dev;
  4025. if (!is_vlan_dev(upper_dev) &&
  4026. !netif_is_lag_master(upper_dev) &&
  4027. !netif_is_bridge_master(upper_dev) &&
  4028. !netif_is_ovs_master(upper_dev) &&
  4029. !netif_is_macvlan(upper_dev)) {
  4030. NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
  4031. return -EINVAL;
  4032. }
  4033. if (!info->linking)
  4034. break;
  4035. if (netdev_has_any_upper_dev(upper_dev) &&
  4036. (!netif_is_bridge_master(upper_dev) ||
  4037. !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
  4038. upper_dev))) {
  4039. NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported");
  4040. return -EINVAL;
  4041. }
  4042. if (netif_is_lag_master(upper_dev) &&
  4043. !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
  4044. info->upper_info, extack))
  4045. return -EINVAL;
  4046. if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev)) {
  4047. NL_SET_ERR_MSG_MOD(extack, "Master device is a LAG master and this device has a VLAN");
  4048. return -EINVAL;
  4049. }
  4050. if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
  4051. !netif_is_lag_master(vlan_dev_real_dev(upper_dev))) {
  4052. NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on a LAG port");
  4053. return -EINVAL;
  4054. }
  4055. if (netif_is_macvlan(upper_dev) &&
  4056. !mlxsw_sp_rif_find_by_dev(mlxsw_sp, lower_dev)) {
  4057. NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
  4058. return -EOPNOTSUPP;
  4059. }
  4060. if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev)) {
  4061. NL_SET_ERR_MSG_MOD(extack, "Master device is an OVS master and this device has a VLAN");
  4062. return -EINVAL;
  4063. }
  4064. if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev)) {
  4065. NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on an OVS port");
  4066. return -EINVAL;
  4067. }
  4068. if (is_vlan_dev(upper_dev) &&
  4069. vlan_dev_vlan_id(upper_dev) == 1) {
  4070. NL_SET_ERR_MSG_MOD(extack, "Creating a VLAN device with VID 1 is unsupported: VLAN 1 carries untagged traffic");
  4071. return -EINVAL;
  4072. }
  4073. break;
  4074. case NETDEV_CHANGEUPPER:
  4075. upper_dev = info->upper_dev;
  4076. if (netif_is_bridge_master(upper_dev)) {
  4077. if (info->linking)
  4078. err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
  4079. lower_dev,
  4080. upper_dev,
  4081. extack);
  4082. else
  4083. mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
  4084. lower_dev,
  4085. upper_dev);
  4086. } else if (netif_is_lag_master(upper_dev)) {
  4087. if (info->linking) {
  4088. err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
  4089. upper_dev);
  4090. } else {
  4091. mlxsw_sp_port_lag_col_dist_disable(mlxsw_sp_port);
  4092. mlxsw_sp_port_lag_leave(mlxsw_sp_port,
  4093. upper_dev);
  4094. }
  4095. } else if (netif_is_ovs_master(upper_dev)) {
  4096. if (info->linking)
  4097. err = mlxsw_sp_port_ovs_join(mlxsw_sp_port);
  4098. else
  4099. mlxsw_sp_port_ovs_leave(mlxsw_sp_port);
  4100. } else if (netif_is_macvlan(upper_dev)) {
  4101. if (!info->linking)
  4102. mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
  4103. } else if (is_vlan_dev(upper_dev)) {
  4104. struct net_device *br_dev;
  4105. if (!netif_is_bridge_port(upper_dev))
  4106. break;
  4107. if (info->linking)
  4108. break;
  4109. br_dev = netdev_master_upper_dev_get(upper_dev);
  4110. mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev,
  4111. br_dev);
  4112. }
  4113. break;
  4114. }
  4115. return err;
  4116. }
  4117. static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
  4118. unsigned long event, void *ptr)
  4119. {
  4120. struct netdev_notifier_changelowerstate_info *info;
  4121. struct mlxsw_sp_port *mlxsw_sp_port;
  4122. int err;
  4123. mlxsw_sp_port = netdev_priv(dev);
  4124. info = ptr;
  4125. switch (event) {
  4126. case NETDEV_CHANGELOWERSTATE:
  4127. if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
  4128. err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
  4129. info->lower_state_info);
  4130. if (err)
  4131. netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
  4132. }
  4133. break;
  4134. }
  4135. return 0;
  4136. }
  4137. static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev,
  4138. struct net_device *port_dev,
  4139. unsigned long event, void *ptr)
  4140. {
  4141. switch (event) {
  4142. case NETDEV_PRECHANGEUPPER:
  4143. case NETDEV_CHANGEUPPER:
  4144. return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev,
  4145. event, ptr);
  4146. case NETDEV_CHANGELOWERSTATE:
  4147. return mlxsw_sp_netdevice_port_lower_event(port_dev, event,
  4148. ptr);
  4149. }
  4150. return 0;
  4151. }
  4152. static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
  4153. unsigned long event, void *ptr)
  4154. {
  4155. struct net_device *dev;
  4156. struct list_head *iter;
  4157. int ret;
  4158. netdev_for_each_lower_dev(lag_dev, dev, iter) {
  4159. if (mlxsw_sp_port_dev_check(dev)) {
  4160. ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event,
  4161. ptr);
  4162. if (ret)
  4163. return ret;
  4164. }
  4165. }
  4166. return 0;
  4167. }
  4168. static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev,
  4169. struct net_device *dev,
  4170. unsigned long event, void *ptr,
  4171. u16 vid)
  4172. {
  4173. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  4174. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  4175. struct netdev_notifier_changeupper_info *info = ptr;
  4176. struct netlink_ext_ack *extack;
  4177. struct net_device *upper_dev;
  4178. int err = 0;
  4179. extack = netdev_notifier_info_to_extack(&info->info);
  4180. switch (event) {
  4181. case NETDEV_PRECHANGEUPPER:
  4182. upper_dev = info->upper_dev;
  4183. if (!netif_is_bridge_master(upper_dev) &&
  4184. !netif_is_macvlan(upper_dev)) {
  4185. NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
  4186. return -EINVAL;
  4187. }
  4188. if (!info->linking)
  4189. break;
  4190. if (netdev_has_any_upper_dev(upper_dev) &&
  4191. (!netif_is_bridge_master(upper_dev) ||
  4192. !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
  4193. upper_dev))) {
  4194. NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported");
  4195. return -EINVAL;
  4196. }
  4197. if (netif_is_macvlan(upper_dev) &&
  4198. !mlxsw_sp_rif_find_by_dev(mlxsw_sp, vlan_dev)) {
  4199. NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
  4200. return -EOPNOTSUPP;
  4201. }
  4202. break;
  4203. case NETDEV_CHANGEUPPER:
  4204. upper_dev = info->upper_dev;
  4205. if (netif_is_bridge_master(upper_dev)) {
  4206. if (info->linking)
  4207. err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
  4208. vlan_dev,
  4209. upper_dev,
  4210. extack);
  4211. else
  4212. mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
  4213. vlan_dev,
  4214. upper_dev);
  4215. } else if (netif_is_macvlan(upper_dev)) {
  4216. if (!info->linking)
  4217. mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
  4218. } else {
  4219. err = -EINVAL;
  4220. WARN_ON(1);
  4221. }
  4222. break;
  4223. }
  4224. return err;
  4225. }
  4226. static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev,
  4227. struct net_device *lag_dev,
  4228. unsigned long event,
  4229. void *ptr, u16 vid)
  4230. {
  4231. struct net_device *dev;
  4232. struct list_head *iter;
  4233. int ret;
  4234. netdev_for_each_lower_dev(lag_dev, dev, iter) {
  4235. if (mlxsw_sp_port_dev_check(dev)) {
  4236. ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev,
  4237. event, ptr,
  4238. vid);
  4239. if (ret)
  4240. return ret;
  4241. }
  4242. }
  4243. return 0;
  4244. }
  4245. static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
  4246. unsigned long event, void *ptr)
  4247. {
  4248. struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
  4249. u16 vid = vlan_dev_vlan_id(vlan_dev);
  4250. if (mlxsw_sp_port_dev_check(real_dev))
  4251. return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev,
  4252. event, ptr, vid);
  4253. else if (netif_is_lag_master(real_dev))
  4254. return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev,
  4255. real_dev, event,
  4256. ptr, vid);
  4257. return 0;
  4258. }
  4259. static int mlxsw_sp_netdevice_bridge_event(struct net_device *br_dev,
  4260. unsigned long event, void *ptr)
  4261. {
  4262. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(br_dev);
  4263. struct netdev_notifier_changeupper_info *info = ptr;
  4264. struct netlink_ext_ack *extack;
  4265. struct net_device *upper_dev;
  4266. if (!mlxsw_sp)
  4267. return 0;
  4268. extack = netdev_notifier_info_to_extack(&info->info);
  4269. switch (event) {
  4270. case NETDEV_PRECHANGEUPPER:
  4271. upper_dev = info->upper_dev;
  4272. if (!is_vlan_dev(upper_dev) && !netif_is_macvlan(upper_dev)) {
  4273. NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
  4274. return -EOPNOTSUPP;
  4275. }
  4276. if (!info->linking)
  4277. break;
  4278. if (netif_is_macvlan(upper_dev) &&
  4279. !mlxsw_sp_rif_find_by_dev(mlxsw_sp, br_dev)) {
  4280. NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
  4281. return -EOPNOTSUPP;
  4282. }
  4283. break;
  4284. case NETDEV_CHANGEUPPER:
  4285. upper_dev = info->upper_dev;
  4286. if (info->linking)
  4287. break;
  4288. if (is_vlan_dev(upper_dev))
  4289. mlxsw_sp_rif_destroy_by_dev(mlxsw_sp, upper_dev);
  4290. if (netif_is_macvlan(upper_dev))
  4291. mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
  4292. break;
  4293. }
  4294. return 0;
  4295. }
  4296. static int mlxsw_sp_netdevice_macvlan_event(struct net_device *macvlan_dev,
  4297. unsigned long event, void *ptr)
  4298. {
  4299. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(macvlan_dev);
  4300. struct netdev_notifier_changeupper_info *info = ptr;
  4301. struct netlink_ext_ack *extack;
  4302. if (!mlxsw_sp || event != NETDEV_PRECHANGEUPPER)
  4303. return 0;
  4304. extack = netdev_notifier_info_to_extack(&info->info);
  4305. /* VRF enslavement is handled in mlxsw_sp_netdevice_vrf_event() */
  4306. NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
  4307. return -EOPNOTSUPP;
  4308. }
  4309. static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr)
  4310. {
  4311. struct netdev_notifier_changeupper_info *info = ptr;
  4312. if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER)
  4313. return false;
  4314. return netif_is_l3_master(info->upper_dev);
  4315. }
  4316. static int mlxsw_sp_netdevice_event(struct notifier_block *nb,
  4317. unsigned long event, void *ptr)
  4318. {
  4319. struct net_device *dev = netdev_notifier_info_to_dev(ptr);
  4320. struct mlxsw_sp_span_entry *span_entry;
  4321. struct mlxsw_sp *mlxsw_sp;
  4322. int err = 0;
  4323. mlxsw_sp = container_of(nb, struct mlxsw_sp, netdevice_nb);
  4324. if (event == NETDEV_UNREGISTER) {
  4325. span_entry = mlxsw_sp_span_entry_find_by_port(mlxsw_sp, dev);
  4326. if (span_entry)
  4327. mlxsw_sp_span_entry_invalidate(mlxsw_sp, span_entry);
  4328. }
  4329. mlxsw_sp_span_respin(mlxsw_sp);
  4330. if (mlxsw_sp_netdev_is_ipip_ol(mlxsw_sp, dev))
  4331. err = mlxsw_sp_netdevice_ipip_ol_event(mlxsw_sp, dev,
  4332. event, ptr);
  4333. else if (mlxsw_sp_netdev_is_ipip_ul(mlxsw_sp, dev))
  4334. err = mlxsw_sp_netdevice_ipip_ul_event(mlxsw_sp, dev,
  4335. event, ptr);
  4336. else if (event == NETDEV_CHANGEADDR || event == NETDEV_CHANGEMTU)
  4337. err = mlxsw_sp_netdevice_router_port_event(dev);
  4338. else if (mlxsw_sp_is_vrf_event(event, ptr))
  4339. err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr);
  4340. else if (mlxsw_sp_port_dev_check(dev))
  4341. err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr);
  4342. else if (netif_is_lag_master(dev))
  4343. err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
  4344. else if (is_vlan_dev(dev))
  4345. err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
  4346. else if (netif_is_bridge_master(dev))
  4347. err = mlxsw_sp_netdevice_bridge_event(dev, event, ptr);
  4348. else if (netif_is_macvlan(dev))
  4349. err = mlxsw_sp_netdevice_macvlan_event(dev, event, ptr);
  4350. return notifier_from_errno(err);
  4351. }
  4352. static struct notifier_block mlxsw_sp_inetaddr_valid_nb __read_mostly = {
  4353. .notifier_call = mlxsw_sp_inetaddr_valid_event,
  4354. };
  4355. static struct notifier_block mlxsw_sp_inetaddr_nb __read_mostly = {
  4356. .notifier_call = mlxsw_sp_inetaddr_event,
  4357. };
  4358. static struct notifier_block mlxsw_sp_inet6addr_valid_nb __read_mostly = {
  4359. .notifier_call = mlxsw_sp_inet6addr_valid_event,
  4360. };
  4361. static struct notifier_block mlxsw_sp_inet6addr_nb __read_mostly = {
  4362. .notifier_call = mlxsw_sp_inet6addr_event,
  4363. };
  4364. static const struct pci_device_id mlxsw_sp1_pci_id_table[] = {
  4365. {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
  4366. {0, },
  4367. };
  4368. static struct pci_driver mlxsw_sp1_pci_driver = {
  4369. .name = mlxsw_sp1_driver_name,
  4370. .id_table = mlxsw_sp1_pci_id_table,
  4371. };
  4372. static const struct pci_device_id mlxsw_sp2_pci_id_table[] = {
  4373. {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM2), 0},
  4374. {0, },
  4375. };
  4376. static struct pci_driver mlxsw_sp2_pci_driver = {
  4377. .name = mlxsw_sp2_driver_name,
  4378. .id_table = mlxsw_sp2_pci_id_table,
  4379. };
  4380. static int __init mlxsw_sp_module_init(void)
  4381. {
  4382. int err;
  4383. register_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
  4384. register_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
  4385. register_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
  4386. register_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
  4387. err = mlxsw_core_driver_register(&mlxsw_sp1_driver);
  4388. if (err)
  4389. goto err_sp1_core_driver_register;
  4390. err = mlxsw_core_driver_register(&mlxsw_sp2_driver);
  4391. if (err)
  4392. goto err_sp2_core_driver_register;
  4393. err = mlxsw_pci_driver_register(&mlxsw_sp1_pci_driver);
  4394. if (err)
  4395. goto err_sp1_pci_driver_register;
  4396. err = mlxsw_pci_driver_register(&mlxsw_sp2_pci_driver);
  4397. if (err)
  4398. goto err_sp2_pci_driver_register;
  4399. return 0;
  4400. err_sp2_pci_driver_register:
  4401. mlxsw_pci_driver_unregister(&mlxsw_sp1_pci_driver);
  4402. err_sp1_pci_driver_register:
  4403. mlxsw_core_driver_unregister(&mlxsw_sp2_driver);
  4404. err_sp2_core_driver_register:
  4405. mlxsw_core_driver_unregister(&mlxsw_sp1_driver);
  4406. err_sp1_core_driver_register:
  4407. unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
  4408. unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
  4409. unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
  4410. unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
  4411. return err;
  4412. }
  4413. static void __exit mlxsw_sp_module_exit(void)
  4414. {
  4415. mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver);
  4416. mlxsw_pci_driver_unregister(&mlxsw_sp1_pci_driver);
  4417. mlxsw_core_driver_unregister(&mlxsw_sp2_driver);
  4418. mlxsw_core_driver_unregister(&mlxsw_sp1_driver);
  4419. unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
  4420. unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
  4421. unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
  4422. unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
  4423. }
  4424. module_init(mlxsw_sp_module_init);
  4425. module_exit(mlxsw_sp_module_exit);
  4426. MODULE_LICENSE("Dual BSD/GPL");
  4427. MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
  4428. MODULE_DESCRIPTION("Mellanox Spectrum driver");
  4429. MODULE_DEVICE_TABLE(pci, mlxsw_sp1_pci_id_table);
  4430. MODULE_DEVICE_TABLE(pci, mlxsw_sp2_pci_id_table);
  4431. MODULE_FIRMWARE(MLXSW_SP1_FW_FILENAME);