bna_tx_rx.c 90 KB

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  1. /*
  2. * Linux network driver for QLogic BR-series Converged Network Adapter.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License (GPL) Version 2 as
  6. * published by the Free Software Foundation
  7. *
  8. * This program is distributed in the hope that it will be useful, but
  9. * WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  11. * General Public License for more details.
  12. */
  13. /*
  14. * Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
  15. * Copyright (c) 2014-2015 QLogic Corporation
  16. * All rights reserved
  17. * www.qlogic.com
  18. */
  19. #include "bna.h"
  20. #include "bfi.h"
  21. /* IB */
  22. static void
  23. bna_ib_coalescing_timeo_set(struct bna_ib *ib, u8 coalescing_timeo)
  24. {
  25. ib->coalescing_timeo = coalescing_timeo;
  26. ib->door_bell.doorbell_ack = BNA_DOORBELL_IB_INT_ACK(
  27. (u32)ib->coalescing_timeo, 0);
  28. }
  29. /* RXF */
  30. #define bna_rxf_vlan_cfg_soft_reset(rxf) \
  31. do { \
  32. (rxf)->vlan_pending_bitmask = (u8)BFI_VLAN_BMASK_ALL; \
  33. (rxf)->vlan_strip_pending = true; \
  34. } while (0)
  35. #define bna_rxf_rss_cfg_soft_reset(rxf) \
  36. do { \
  37. if ((rxf)->rss_status == BNA_STATUS_T_ENABLED) \
  38. (rxf)->rss_pending = (BNA_RSS_F_RIT_PENDING | \
  39. BNA_RSS_F_CFG_PENDING | \
  40. BNA_RSS_F_STATUS_PENDING); \
  41. } while (0)
  42. static int bna_rxf_cfg_apply(struct bna_rxf *rxf);
  43. static void bna_rxf_cfg_reset(struct bna_rxf *rxf);
  44. static int bna_rxf_ucast_cfg_apply(struct bna_rxf *rxf);
  45. static int bna_rxf_promisc_cfg_apply(struct bna_rxf *rxf);
  46. static int bna_rxf_allmulti_cfg_apply(struct bna_rxf *rxf);
  47. static int bna_rxf_vlan_strip_cfg_apply(struct bna_rxf *rxf);
  48. static int bna_rxf_ucast_cfg_reset(struct bna_rxf *rxf,
  49. enum bna_cleanup_type cleanup);
  50. static int bna_rxf_promisc_cfg_reset(struct bna_rxf *rxf,
  51. enum bna_cleanup_type cleanup);
  52. static int bna_rxf_allmulti_cfg_reset(struct bna_rxf *rxf,
  53. enum bna_cleanup_type cleanup);
  54. bfa_fsm_state_decl(bna_rxf, stopped, struct bna_rxf,
  55. enum bna_rxf_event);
  56. bfa_fsm_state_decl(bna_rxf, cfg_wait, struct bna_rxf,
  57. enum bna_rxf_event);
  58. bfa_fsm_state_decl(bna_rxf, started, struct bna_rxf,
  59. enum bna_rxf_event);
  60. bfa_fsm_state_decl(bna_rxf, last_resp_wait, struct bna_rxf,
  61. enum bna_rxf_event);
  62. static void
  63. bna_rxf_sm_stopped_entry(struct bna_rxf *rxf)
  64. {
  65. call_rxf_stop_cbfn(rxf);
  66. }
  67. static void
  68. bna_rxf_sm_stopped(struct bna_rxf *rxf, enum bna_rxf_event event)
  69. {
  70. switch (event) {
  71. case RXF_E_START:
  72. bfa_fsm_set_state(rxf, bna_rxf_sm_cfg_wait);
  73. break;
  74. case RXF_E_STOP:
  75. call_rxf_stop_cbfn(rxf);
  76. break;
  77. case RXF_E_FAIL:
  78. /* No-op */
  79. break;
  80. case RXF_E_CONFIG:
  81. call_rxf_cam_fltr_cbfn(rxf);
  82. break;
  83. default:
  84. bfa_sm_fault(event);
  85. }
  86. }
  87. static void
  88. bna_rxf_sm_cfg_wait_entry(struct bna_rxf *rxf)
  89. {
  90. if (!bna_rxf_cfg_apply(rxf)) {
  91. /* No more pending config updates */
  92. bfa_fsm_set_state(rxf, bna_rxf_sm_started);
  93. }
  94. }
  95. static void
  96. bna_rxf_sm_cfg_wait(struct bna_rxf *rxf, enum bna_rxf_event event)
  97. {
  98. switch (event) {
  99. case RXF_E_STOP:
  100. bfa_fsm_set_state(rxf, bna_rxf_sm_last_resp_wait);
  101. break;
  102. case RXF_E_FAIL:
  103. bna_rxf_cfg_reset(rxf);
  104. call_rxf_start_cbfn(rxf);
  105. call_rxf_cam_fltr_cbfn(rxf);
  106. bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
  107. break;
  108. case RXF_E_CONFIG:
  109. /* No-op */
  110. break;
  111. case RXF_E_FW_RESP:
  112. if (!bna_rxf_cfg_apply(rxf)) {
  113. /* No more pending config updates */
  114. bfa_fsm_set_state(rxf, bna_rxf_sm_started);
  115. }
  116. break;
  117. default:
  118. bfa_sm_fault(event);
  119. }
  120. }
  121. static void
  122. bna_rxf_sm_started_entry(struct bna_rxf *rxf)
  123. {
  124. call_rxf_start_cbfn(rxf);
  125. call_rxf_cam_fltr_cbfn(rxf);
  126. }
  127. static void
  128. bna_rxf_sm_started(struct bna_rxf *rxf, enum bna_rxf_event event)
  129. {
  130. switch (event) {
  131. case RXF_E_STOP:
  132. case RXF_E_FAIL:
  133. bna_rxf_cfg_reset(rxf);
  134. bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
  135. break;
  136. case RXF_E_CONFIG:
  137. bfa_fsm_set_state(rxf, bna_rxf_sm_cfg_wait);
  138. break;
  139. default:
  140. bfa_sm_fault(event);
  141. }
  142. }
  143. static void
  144. bna_rxf_sm_last_resp_wait_entry(struct bna_rxf *rxf)
  145. {
  146. }
  147. static void
  148. bna_rxf_sm_last_resp_wait(struct bna_rxf *rxf, enum bna_rxf_event event)
  149. {
  150. switch (event) {
  151. case RXF_E_FAIL:
  152. case RXF_E_FW_RESP:
  153. bna_rxf_cfg_reset(rxf);
  154. bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
  155. break;
  156. default:
  157. bfa_sm_fault(event);
  158. }
  159. }
  160. static void
  161. bna_bfi_ucast_req(struct bna_rxf *rxf, struct bna_mac *mac,
  162. enum bfi_enet_h2i_msgs req_type)
  163. {
  164. struct bfi_enet_ucast_req *req = &rxf->bfi_enet_cmd.ucast_req;
  165. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET, req_type, 0, rxf->rx->rid);
  166. req->mh.num_entries = htons(
  167. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_ucast_req)));
  168. ether_addr_copy(req->mac_addr, mac->addr);
  169. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  170. sizeof(struct bfi_enet_ucast_req), &req->mh);
  171. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  172. }
  173. static void
  174. bna_bfi_mcast_add_req(struct bna_rxf *rxf, struct bna_mac *mac)
  175. {
  176. struct bfi_enet_mcast_add_req *req =
  177. &rxf->bfi_enet_cmd.mcast_add_req;
  178. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET, BFI_ENET_H2I_MAC_MCAST_ADD_REQ,
  179. 0, rxf->rx->rid);
  180. req->mh.num_entries = htons(
  181. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_mcast_add_req)));
  182. ether_addr_copy(req->mac_addr, mac->addr);
  183. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  184. sizeof(struct bfi_enet_mcast_add_req), &req->mh);
  185. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  186. }
  187. static void
  188. bna_bfi_mcast_del_req(struct bna_rxf *rxf, u16 handle)
  189. {
  190. struct bfi_enet_mcast_del_req *req =
  191. &rxf->bfi_enet_cmd.mcast_del_req;
  192. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET, BFI_ENET_H2I_MAC_MCAST_DEL_REQ,
  193. 0, rxf->rx->rid);
  194. req->mh.num_entries = htons(
  195. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_mcast_del_req)));
  196. req->handle = htons(handle);
  197. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  198. sizeof(struct bfi_enet_mcast_del_req), &req->mh);
  199. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  200. }
  201. static void
  202. bna_bfi_mcast_filter_req(struct bna_rxf *rxf, enum bna_status status)
  203. {
  204. struct bfi_enet_enable_req *req = &rxf->bfi_enet_cmd.req;
  205. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  206. BFI_ENET_H2I_MAC_MCAST_FILTER_REQ, 0, rxf->rx->rid);
  207. req->mh.num_entries = htons(
  208. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_enable_req)));
  209. req->enable = status;
  210. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  211. sizeof(struct bfi_enet_enable_req), &req->mh);
  212. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  213. }
  214. static void
  215. bna_bfi_rx_promisc_req(struct bna_rxf *rxf, enum bna_status status)
  216. {
  217. struct bfi_enet_enable_req *req = &rxf->bfi_enet_cmd.req;
  218. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  219. BFI_ENET_H2I_RX_PROMISCUOUS_REQ, 0, rxf->rx->rid);
  220. req->mh.num_entries = htons(
  221. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_enable_req)));
  222. req->enable = status;
  223. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  224. sizeof(struct bfi_enet_enable_req), &req->mh);
  225. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  226. }
  227. static void
  228. bna_bfi_rx_vlan_filter_set(struct bna_rxf *rxf, u8 block_idx)
  229. {
  230. struct bfi_enet_rx_vlan_req *req = &rxf->bfi_enet_cmd.vlan_req;
  231. int i;
  232. int j;
  233. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  234. BFI_ENET_H2I_RX_VLAN_SET_REQ, 0, rxf->rx->rid);
  235. req->mh.num_entries = htons(
  236. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_rx_vlan_req)));
  237. req->block_idx = block_idx;
  238. for (i = 0; i < (BFI_ENET_VLAN_BLOCK_SIZE / 32); i++) {
  239. j = (block_idx * (BFI_ENET_VLAN_BLOCK_SIZE / 32)) + i;
  240. if (rxf->vlan_filter_status == BNA_STATUS_T_ENABLED)
  241. req->bit_mask[i] =
  242. htonl(rxf->vlan_filter_table[j]);
  243. else
  244. req->bit_mask[i] = 0xFFFFFFFF;
  245. }
  246. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  247. sizeof(struct bfi_enet_rx_vlan_req), &req->mh);
  248. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  249. }
  250. static void
  251. bna_bfi_vlan_strip_enable(struct bna_rxf *rxf)
  252. {
  253. struct bfi_enet_enable_req *req = &rxf->bfi_enet_cmd.req;
  254. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  255. BFI_ENET_H2I_RX_VLAN_STRIP_ENABLE_REQ, 0, rxf->rx->rid);
  256. req->mh.num_entries = htons(
  257. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_enable_req)));
  258. req->enable = rxf->vlan_strip_status;
  259. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  260. sizeof(struct bfi_enet_enable_req), &req->mh);
  261. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  262. }
  263. static void
  264. bna_bfi_rit_cfg(struct bna_rxf *rxf)
  265. {
  266. struct bfi_enet_rit_req *req = &rxf->bfi_enet_cmd.rit_req;
  267. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  268. BFI_ENET_H2I_RIT_CFG_REQ, 0, rxf->rx->rid);
  269. req->mh.num_entries = htons(
  270. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_rit_req)));
  271. req->size = htons(rxf->rit_size);
  272. memcpy(&req->table[0], rxf->rit, rxf->rit_size);
  273. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  274. sizeof(struct bfi_enet_rit_req), &req->mh);
  275. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  276. }
  277. static void
  278. bna_bfi_rss_cfg(struct bna_rxf *rxf)
  279. {
  280. struct bfi_enet_rss_cfg_req *req = &rxf->bfi_enet_cmd.rss_req;
  281. int i;
  282. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  283. BFI_ENET_H2I_RSS_CFG_REQ, 0, rxf->rx->rid);
  284. req->mh.num_entries = htons(
  285. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_rss_cfg_req)));
  286. req->cfg.type = rxf->rss_cfg.hash_type;
  287. req->cfg.mask = rxf->rss_cfg.hash_mask;
  288. for (i = 0; i < BFI_ENET_RSS_KEY_LEN; i++)
  289. req->cfg.key[i] =
  290. htonl(rxf->rss_cfg.toeplitz_hash_key[i]);
  291. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  292. sizeof(struct bfi_enet_rss_cfg_req), &req->mh);
  293. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  294. }
  295. static void
  296. bna_bfi_rss_enable(struct bna_rxf *rxf)
  297. {
  298. struct bfi_enet_enable_req *req = &rxf->bfi_enet_cmd.req;
  299. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  300. BFI_ENET_H2I_RSS_ENABLE_REQ, 0, rxf->rx->rid);
  301. req->mh.num_entries = htons(
  302. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_enable_req)));
  303. req->enable = rxf->rss_status;
  304. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  305. sizeof(struct bfi_enet_enable_req), &req->mh);
  306. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  307. }
  308. /* This function gets the multicast MAC that has already been added to CAM */
  309. static struct bna_mac *
  310. bna_rxf_mcmac_get(struct bna_rxf *rxf, const u8 *mac_addr)
  311. {
  312. struct bna_mac *mac;
  313. list_for_each_entry(mac, &rxf->mcast_active_q, qe)
  314. if (ether_addr_equal(mac->addr, mac_addr))
  315. return mac;
  316. list_for_each_entry(mac, &rxf->mcast_pending_del_q, qe)
  317. if (ether_addr_equal(mac->addr, mac_addr))
  318. return mac;
  319. return NULL;
  320. }
  321. static struct bna_mcam_handle *
  322. bna_rxf_mchandle_get(struct bna_rxf *rxf, int handle)
  323. {
  324. struct bna_mcam_handle *mchandle;
  325. list_for_each_entry(mchandle, &rxf->mcast_handle_q, qe)
  326. if (mchandle->handle == handle)
  327. return mchandle;
  328. return NULL;
  329. }
  330. static void
  331. bna_rxf_mchandle_attach(struct bna_rxf *rxf, u8 *mac_addr, int handle)
  332. {
  333. struct bna_mac *mcmac;
  334. struct bna_mcam_handle *mchandle;
  335. mcmac = bna_rxf_mcmac_get(rxf, mac_addr);
  336. mchandle = bna_rxf_mchandle_get(rxf, handle);
  337. if (mchandle == NULL) {
  338. mchandle = bna_mcam_mod_handle_get(&rxf->rx->bna->mcam_mod);
  339. mchandle->handle = handle;
  340. mchandle->refcnt = 0;
  341. list_add_tail(&mchandle->qe, &rxf->mcast_handle_q);
  342. }
  343. mchandle->refcnt++;
  344. mcmac->handle = mchandle;
  345. }
  346. static int
  347. bna_rxf_mcast_del(struct bna_rxf *rxf, struct bna_mac *mac,
  348. enum bna_cleanup_type cleanup)
  349. {
  350. struct bna_mcam_handle *mchandle;
  351. int ret = 0;
  352. mchandle = mac->handle;
  353. if (mchandle == NULL)
  354. return ret;
  355. mchandle->refcnt--;
  356. if (mchandle->refcnt == 0) {
  357. if (cleanup == BNA_HARD_CLEANUP) {
  358. bna_bfi_mcast_del_req(rxf, mchandle->handle);
  359. ret = 1;
  360. }
  361. list_del(&mchandle->qe);
  362. bna_mcam_mod_handle_put(&rxf->rx->bna->mcam_mod, mchandle);
  363. }
  364. mac->handle = NULL;
  365. return ret;
  366. }
  367. static int
  368. bna_rxf_mcast_cfg_apply(struct bna_rxf *rxf)
  369. {
  370. struct bna_mac *mac = NULL;
  371. int ret;
  372. /* First delete multicast entries to maintain the count */
  373. while (!list_empty(&rxf->mcast_pending_del_q)) {
  374. mac = list_first_entry(&rxf->mcast_pending_del_q,
  375. struct bna_mac, qe);
  376. ret = bna_rxf_mcast_del(rxf, mac, BNA_HARD_CLEANUP);
  377. list_move_tail(&mac->qe, bna_mcam_mod_del_q(rxf->rx->bna));
  378. if (ret)
  379. return ret;
  380. }
  381. /* Add multicast entries */
  382. if (!list_empty(&rxf->mcast_pending_add_q)) {
  383. mac = list_first_entry(&rxf->mcast_pending_add_q,
  384. struct bna_mac, qe);
  385. list_move_tail(&mac->qe, &rxf->mcast_active_q);
  386. bna_bfi_mcast_add_req(rxf, mac);
  387. return 1;
  388. }
  389. return 0;
  390. }
  391. static int
  392. bna_rxf_vlan_cfg_apply(struct bna_rxf *rxf)
  393. {
  394. u8 vlan_pending_bitmask;
  395. int block_idx = 0;
  396. if (rxf->vlan_pending_bitmask) {
  397. vlan_pending_bitmask = rxf->vlan_pending_bitmask;
  398. while (!(vlan_pending_bitmask & 0x1)) {
  399. block_idx++;
  400. vlan_pending_bitmask >>= 1;
  401. }
  402. rxf->vlan_pending_bitmask &= ~BIT(block_idx);
  403. bna_bfi_rx_vlan_filter_set(rxf, block_idx);
  404. return 1;
  405. }
  406. return 0;
  407. }
  408. static int
  409. bna_rxf_mcast_cfg_reset(struct bna_rxf *rxf, enum bna_cleanup_type cleanup)
  410. {
  411. struct bna_mac *mac;
  412. int ret;
  413. /* Throw away delete pending mcast entries */
  414. while (!list_empty(&rxf->mcast_pending_del_q)) {
  415. mac = list_first_entry(&rxf->mcast_pending_del_q,
  416. struct bna_mac, qe);
  417. ret = bna_rxf_mcast_del(rxf, mac, cleanup);
  418. list_move_tail(&mac->qe, bna_mcam_mod_del_q(rxf->rx->bna));
  419. if (ret)
  420. return ret;
  421. }
  422. /* Move active mcast entries to pending_add_q */
  423. while (!list_empty(&rxf->mcast_active_q)) {
  424. mac = list_first_entry(&rxf->mcast_active_q,
  425. struct bna_mac, qe);
  426. list_move_tail(&mac->qe, &rxf->mcast_pending_add_q);
  427. if (bna_rxf_mcast_del(rxf, mac, cleanup))
  428. return 1;
  429. }
  430. return 0;
  431. }
  432. static int
  433. bna_rxf_rss_cfg_apply(struct bna_rxf *rxf)
  434. {
  435. if (rxf->rss_pending) {
  436. if (rxf->rss_pending & BNA_RSS_F_RIT_PENDING) {
  437. rxf->rss_pending &= ~BNA_RSS_F_RIT_PENDING;
  438. bna_bfi_rit_cfg(rxf);
  439. return 1;
  440. }
  441. if (rxf->rss_pending & BNA_RSS_F_CFG_PENDING) {
  442. rxf->rss_pending &= ~BNA_RSS_F_CFG_PENDING;
  443. bna_bfi_rss_cfg(rxf);
  444. return 1;
  445. }
  446. if (rxf->rss_pending & BNA_RSS_F_STATUS_PENDING) {
  447. rxf->rss_pending &= ~BNA_RSS_F_STATUS_PENDING;
  448. bna_bfi_rss_enable(rxf);
  449. return 1;
  450. }
  451. }
  452. return 0;
  453. }
  454. static int
  455. bna_rxf_cfg_apply(struct bna_rxf *rxf)
  456. {
  457. if (bna_rxf_ucast_cfg_apply(rxf))
  458. return 1;
  459. if (bna_rxf_mcast_cfg_apply(rxf))
  460. return 1;
  461. if (bna_rxf_promisc_cfg_apply(rxf))
  462. return 1;
  463. if (bna_rxf_allmulti_cfg_apply(rxf))
  464. return 1;
  465. if (bna_rxf_vlan_cfg_apply(rxf))
  466. return 1;
  467. if (bna_rxf_vlan_strip_cfg_apply(rxf))
  468. return 1;
  469. if (bna_rxf_rss_cfg_apply(rxf))
  470. return 1;
  471. return 0;
  472. }
  473. static void
  474. bna_rxf_cfg_reset(struct bna_rxf *rxf)
  475. {
  476. bna_rxf_ucast_cfg_reset(rxf, BNA_SOFT_CLEANUP);
  477. bna_rxf_mcast_cfg_reset(rxf, BNA_SOFT_CLEANUP);
  478. bna_rxf_promisc_cfg_reset(rxf, BNA_SOFT_CLEANUP);
  479. bna_rxf_allmulti_cfg_reset(rxf, BNA_SOFT_CLEANUP);
  480. bna_rxf_vlan_cfg_soft_reset(rxf);
  481. bna_rxf_rss_cfg_soft_reset(rxf);
  482. }
  483. static void
  484. bna_rit_init(struct bna_rxf *rxf, int rit_size)
  485. {
  486. struct bna_rx *rx = rxf->rx;
  487. struct bna_rxp *rxp;
  488. int offset = 0;
  489. rxf->rit_size = rit_size;
  490. list_for_each_entry(rxp, &rx->rxp_q, qe) {
  491. rxf->rit[offset] = rxp->cq.ccb->id;
  492. offset++;
  493. }
  494. }
  495. void
  496. bna_bfi_rxf_cfg_rsp(struct bna_rxf *rxf, struct bfi_msgq_mhdr *msghdr)
  497. {
  498. bfa_fsm_send_event(rxf, RXF_E_FW_RESP);
  499. }
  500. void
  501. bna_bfi_rxf_ucast_set_rsp(struct bna_rxf *rxf,
  502. struct bfi_msgq_mhdr *msghdr)
  503. {
  504. struct bfi_enet_rsp *rsp =
  505. container_of(msghdr, struct bfi_enet_rsp, mh);
  506. if (rsp->error) {
  507. /* Clear ucast from cache */
  508. rxf->ucast_active_set = 0;
  509. }
  510. bfa_fsm_send_event(rxf, RXF_E_FW_RESP);
  511. }
  512. void
  513. bna_bfi_rxf_mcast_add_rsp(struct bna_rxf *rxf,
  514. struct bfi_msgq_mhdr *msghdr)
  515. {
  516. struct bfi_enet_mcast_add_req *req =
  517. &rxf->bfi_enet_cmd.mcast_add_req;
  518. struct bfi_enet_mcast_add_rsp *rsp =
  519. container_of(msghdr, struct bfi_enet_mcast_add_rsp, mh);
  520. bna_rxf_mchandle_attach(rxf, (u8 *)&req->mac_addr,
  521. ntohs(rsp->handle));
  522. bfa_fsm_send_event(rxf, RXF_E_FW_RESP);
  523. }
  524. static void
  525. bna_rxf_init(struct bna_rxf *rxf,
  526. struct bna_rx *rx,
  527. struct bna_rx_config *q_config,
  528. struct bna_res_info *res_info)
  529. {
  530. rxf->rx = rx;
  531. INIT_LIST_HEAD(&rxf->ucast_pending_add_q);
  532. INIT_LIST_HEAD(&rxf->ucast_pending_del_q);
  533. rxf->ucast_pending_set = 0;
  534. rxf->ucast_active_set = 0;
  535. INIT_LIST_HEAD(&rxf->ucast_active_q);
  536. rxf->ucast_pending_mac = NULL;
  537. INIT_LIST_HEAD(&rxf->mcast_pending_add_q);
  538. INIT_LIST_HEAD(&rxf->mcast_pending_del_q);
  539. INIT_LIST_HEAD(&rxf->mcast_active_q);
  540. INIT_LIST_HEAD(&rxf->mcast_handle_q);
  541. rxf->rit = (u8 *)
  542. res_info[BNA_RX_RES_MEM_T_RIT].res_u.mem_info.mdl[0].kva;
  543. bna_rit_init(rxf, q_config->num_paths);
  544. rxf->rss_status = q_config->rss_status;
  545. if (rxf->rss_status == BNA_STATUS_T_ENABLED) {
  546. rxf->rss_cfg = q_config->rss_config;
  547. rxf->rss_pending |= BNA_RSS_F_CFG_PENDING;
  548. rxf->rss_pending |= BNA_RSS_F_RIT_PENDING;
  549. rxf->rss_pending |= BNA_RSS_F_STATUS_PENDING;
  550. }
  551. rxf->vlan_filter_status = BNA_STATUS_T_DISABLED;
  552. memset(rxf->vlan_filter_table, 0,
  553. (sizeof(u32) * (BFI_ENET_VLAN_ID_MAX / 32)));
  554. rxf->vlan_filter_table[0] |= 1; /* for pure priority tagged frames */
  555. rxf->vlan_pending_bitmask = (u8)BFI_VLAN_BMASK_ALL;
  556. rxf->vlan_strip_status = q_config->vlan_strip_status;
  557. bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
  558. }
  559. static void
  560. bna_rxf_uninit(struct bna_rxf *rxf)
  561. {
  562. struct bna_mac *mac;
  563. rxf->ucast_pending_set = 0;
  564. rxf->ucast_active_set = 0;
  565. while (!list_empty(&rxf->ucast_pending_add_q)) {
  566. mac = list_first_entry(&rxf->ucast_pending_add_q,
  567. struct bna_mac, qe);
  568. list_move_tail(&mac->qe, bna_ucam_mod_free_q(rxf->rx->bna));
  569. }
  570. if (rxf->ucast_pending_mac) {
  571. list_add_tail(&rxf->ucast_pending_mac->qe,
  572. bna_ucam_mod_free_q(rxf->rx->bna));
  573. rxf->ucast_pending_mac = NULL;
  574. }
  575. while (!list_empty(&rxf->mcast_pending_add_q)) {
  576. mac = list_first_entry(&rxf->mcast_pending_add_q,
  577. struct bna_mac, qe);
  578. list_move_tail(&mac->qe, bna_mcam_mod_free_q(rxf->rx->bna));
  579. }
  580. rxf->rxmode_pending = 0;
  581. rxf->rxmode_pending_bitmask = 0;
  582. if (rxf->rx->bna->promisc_rid == rxf->rx->rid)
  583. rxf->rx->bna->promisc_rid = BFI_INVALID_RID;
  584. if (rxf->rx->bna->default_mode_rid == rxf->rx->rid)
  585. rxf->rx->bna->default_mode_rid = BFI_INVALID_RID;
  586. rxf->rss_pending = 0;
  587. rxf->vlan_strip_pending = false;
  588. rxf->rx = NULL;
  589. }
  590. static void
  591. bna_rx_cb_rxf_started(struct bna_rx *rx)
  592. {
  593. bfa_fsm_send_event(rx, RX_E_RXF_STARTED);
  594. }
  595. static void
  596. bna_rxf_start(struct bna_rxf *rxf)
  597. {
  598. rxf->start_cbfn = bna_rx_cb_rxf_started;
  599. rxf->start_cbarg = rxf->rx;
  600. bfa_fsm_send_event(rxf, RXF_E_START);
  601. }
  602. static void
  603. bna_rx_cb_rxf_stopped(struct bna_rx *rx)
  604. {
  605. bfa_fsm_send_event(rx, RX_E_RXF_STOPPED);
  606. }
  607. static void
  608. bna_rxf_stop(struct bna_rxf *rxf)
  609. {
  610. rxf->stop_cbfn = bna_rx_cb_rxf_stopped;
  611. rxf->stop_cbarg = rxf->rx;
  612. bfa_fsm_send_event(rxf, RXF_E_STOP);
  613. }
  614. static void
  615. bna_rxf_fail(struct bna_rxf *rxf)
  616. {
  617. bfa_fsm_send_event(rxf, RXF_E_FAIL);
  618. }
  619. enum bna_cb_status
  620. bna_rx_ucast_set(struct bna_rx *rx, const u8 *ucmac)
  621. {
  622. struct bna_rxf *rxf = &rx->rxf;
  623. if (rxf->ucast_pending_mac == NULL) {
  624. rxf->ucast_pending_mac =
  625. bna_cam_mod_mac_get(bna_ucam_mod_free_q(rxf->rx->bna));
  626. if (rxf->ucast_pending_mac == NULL)
  627. return BNA_CB_UCAST_CAM_FULL;
  628. }
  629. ether_addr_copy(rxf->ucast_pending_mac->addr, ucmac);
  630. rxf->ucast_pending_set = 1;
  631. rxf->cam_fltr_cbfn = NULL;
  632. rxf->cam_fltr_cbarg = rx->bna->bnad;
  633. bfa_fsm_send_event(rxf, RXF_E_CONFIG);
  634. return BNA_CB_SUCCESS;
  635. }
  636. enum bna_cb_status
  637. bna_rx_mcast_add(struct bna_rx *rx, const u8 *addr,
  638. void (*cbfn)(struct bnad *, struct bna_rx *))
  639. {
  640. struct bna_rxf *rxf = &rx->rxf;
  641. struct bna_mac *mac;
  642. /* Check if already added or pending addition */
  643. if (bna_mac_find(&rxf->mcast_active_q, addr) ||
  644. bna_mac_find(&rxf->mcast_pending_add_q, addr)) {
  645. if (cbfn)
  646. cbfn(rx->bna->bnad, rx);
  647. return BNA_CB_SUCCESS;
  648. }
  649. mac = bna_cam_mod_mac_get(bna_mcam_mod_free_q(rxf->rx->bna));
  650. if (mac == NULL)
  651. return BNA_CB_MCAST_LIST_FULL;
  652. ether_addr_copy(mac->addr, addr);
  653. list_add_tail(&mac->qe, &rxf->mcast_pending_add_q);
  654. rxf->cam_fltr_cbfn = cbfn;
  655. rxf->cam_fltr_cbarg = rx->bna->bnad;
  656. bfa_fsm_send_event(rxf, RXF_E_CONFIG);
  657. return BNA_CB_SUCCESS;
  658. }
  659. enum bna_cb_status
  660. bna_rx_ucast_listset(struct bna_rx *rx, int count, const u8 *uclist)
  661. {
  662. struct bna_ucam_mod *ucam_mod = &rx->bna->ucam_mod;
  663. struct bna_rxf *rxf = &rx->rxf;
  664. struct list_head list_head;
  665. const u8 *mcaddr;
  666. struct bna_mac *mac, *del_mac;
  667. int i;
  668. /* Purge the pending_add_q */
  669. while (!list_empty(&rxf->ucast_pending_add_q)) {
  670. mac = list_first_entry(&rxf->ucast_pending_add_q,
  671. struct bna_mac, qe);
  672. list_move_tail(&mac->qe, &ucam_mod->free_q);
  673. }
  674. /* Schedule active_q entries for deletion */
  675. while (!list_empty(&rxf->ucast_active_q)) {
  676. mac = list_first_entry(&rxf->ucast_active_q,
  677. struct bna_mac, qe);
  678. del_mac = bna_cam_mod_mac_get(&ucam_mod->del_q);
  679. ether_addr_copy(del_mac->addr, mac->addr);
  680. del_mac->handle = mac->handle;
  681. list_add_tail(&del_mac->qe, &rxf->ucast_pending_del_q);
  682. list_move_tail(&mac->qe, &ucam_mod->free_q);
  683. }
  684. /* Allocate nodes */
  685. INIT_LIST_HEAD(&list_head);
  686. for (i = 0, mcaddr = uclist; i < count; i++) {
  687. mac = bna_cam_mod_mac_get(&ucam_mod->free_q);
  688. if (mac == NULL)
  689. goto err_return;
  690. ether_addr_copy(mac->addr, mcaddr);
  691. list_add_tail(&mac->qe, &list_head);
  692. mcaddr += ETH_ALEN;
  693. }
  694. /* Add the new entries */
  695. while (!list_empty(&list_head)) {
  696. mac = list_first_entry(&list_head, struct bna_mac, qe);
  697. list_move_tail(&mac->qe, &rxf->ucast_pending_add_q);
  698. }
  699. bfa_fsm_send_event(rxf, RXF_E_CONFIG);
  700. return BNA_CB_SUCCESS;
  701. err_return:
  702. while (!list_empty(&list_head)) {
  703. mac = list_first_entry(&list_head, struct bna_mac, qe);
  704. list_move_tail(&mac->qe, &ucam_mod->free_q);
  705. }
  706. return BNA_CB_UCAST_CAM_FULL;
  707. }
  708. enum bna_cb_status
  709. bna_rx_mcast_listset(struct bna_rx *rx, int count, const u8 *mclist)
  710. {
  711. struct bna_mcam_mod *mcam_mod = &rx->bna->mcam_mod;
  712. struct bna_rxf *rxf = &rx->rxf;
  713. struct list_head list_head;
  714. const u8 *mcaddr;
  715. struct bna_mac *mac, *del_mac;
  716. int i;
  717. /* Purge the pending_add_q */
  718. while (!list_empty(&rxf->mcast_pending_add_q)) {
  719. mac = list_first_entry(&rxf->mcast_pending_add_q,
  720. struct bna_mac, qe);
  721. list_move_tail(&mac->qe, &mcam_mod->free_q);
  722. }
  723. /* Schedule active_q entries for deletion */
  724. while (!list_empty(&rxf->mcast_active_q)) {
  725. mac = list_first_entry(&rxf->mcast_active_q,
  726. struct bna_mac, qe);
  727. del_mac = bna_cam_mod_mac_get(&mcam_mod->del_q);
  728. ether_addr_copy(del_mac->addr, mac->addr);
  729. del_mac->handle = mac->handle;
  730. list_add_tail(&del_mac->qe, &rxf->mcast_pending_del_q);
  731. mac->handle = NULL;
  732. list_move_tail(&mac->qe, &mcam_mod->free_q);
  733. }
  734. /* Allocate nodes */
  735. INIT_LIST_HEAD(&list_head);
  736. for (i = 0, mcaddr = mclist; i < count; i++) {
  737. mac = bna_cam_mod_mac_get(&mcam_mod->free_q);
  738. if (mac == NULL)
  739. goto err_return;
  740. ether_addr_copy(mac->addr, mcaddr);
  741. list_add_tail(&mac->qe, &list_head);
  742. mcaddr += ETH_ALEN;
  743. }
  744. /* Add the new entries */
  745. while (!list_empty(&list_head)) {
  746. mac = list_first_entry(&list_head, struct bna_mac, qe);
  747. list_move_tail(&mac->qe, &rxf->mcast_pending_add_q);
  748. }
  749. bfa_fsm_send_event(rxf, RXF_E_CONFIG);
  750. return BNA_CB_SUCCESS;
  751. err_return:
  752. while (!list_empty(&list_head)) {
  753. mac = list_first_entry(&list_head, struct bna_mac, qe);
  754. list_move_tail(&mac->qe, &mcam_mod->free_q);
  755. }
  756. return BNA_CB_MCAST_LIST_FULL;
  757. }
  758. void
  759. bna_rx_mcast_delall(struct bna_rx *rx)
  760. {
  761. struct bna_rxf *rxf = &rx->rxf;
  762. struct bna_mac *mac, *del_mac;
  763. int need_hw_config = 0;
  764. /* Purge all entries from pending_add_q */
  765. while (!list_empty(&rxf->mcast_pending_add_q)) {
  766. mac = list_first_entry(&rxf->mcast_pending_add_q,
  767. struct bna_mac, qe);
  768. list_move_tail(&mac->qe, bna_mcam_mod_free_q(rxf->rx->bna));
  769. }
  770. /* Schedule all entries in active_q for deletion */
  771. while (!list_empty(&rxf->mcast_active_q)) {
  772. mac = list_first_entry(&rxf->mcast_active_q,
  773. struct bna_mac, qe);
  774. list_del(&mac->qe);
  775. del_mac = bna_cam_mod_mac_get(bna_mcam_mod_del_q(rxf->rx->bna));
  776. memcpy(del_mac, mac, sizeof(*del_mac));
  777. list_add_tail(&del_mac->qe, &rxf->mcast_pending_del_q);
  778. mac->handle = NULL;
  779. list_add_tail(&mac->qe, bna_mcam_mod_free_q(rxf->rx->bna));
  780. need_hw_config = 1;
  781. }
  782. if (need_hw_config)
  783. bfa_fsm_send_event(rxf, RXF_E_CONFIG);
  784. }
  785. void
  786. bna_rx_vlan_add(struct bna_rx *rx, int vlan_id)
  787. {
  788. struct bna_rxf *rxf = &rx->rxf;
  789. int index = (vlan_id >> BFI_VLAN_WORD_SHIFT);
  790. int bit = BIT(vlan_id & BFI_VLAN_WORD_MASK);
  791. int group_id = (vlan_id >> BFI_VLAN_BLOCK_SHIFT);
  792. rxf->vlan_filter_table[index] |= bit;
  793. if (rxf->vlan_filter_status == BNA_STATUS_T_ENABLED) {
  794. rxf->vlan_pending_bitmask |= BIT(group_id);
  795. bfa_fsm_send_event(rxf, RXF_E_CONFIG);
  796. }
  797. }
  798. void
  799. bna_rx_vlan_del(struct bna_rx *rx, int vlan_id)
  800. {
  801. struct bna_rxf *rxf = &rx->rxf;
  802. int index = (vlan_id >> BFI_VLAN_WORD_SHIFT);
  803. int bit = BIT(vlan_id & BFI_VLAN_WORD_MASK);
  804. int group_id = (vlan_id >> BFI_VLAN_BLOCK_SHIFT);
  805. rxf->vlan_filter_table[index] &= ~bit;
  806. if (rxf->vlan_filter_status == BNA_STATUS_T_ENABLED) {
  807. rxf->vlan_pending_bitmask |= BIT(group_id);
  808. bfa_fsm_send_event(rxf, RXF_E_CONFIG);
  809. }
  810. }
  811. static int
  812. bna_rxf_ucast_cfg_apply(struct bna_rxf *rxf)
  813. {
  814. struct bna_mac *mac = NULL;
  815. /* Delete MAC addresses previousely added */
  816. if (!list_empty(&rxf->ucast_pending_del_q)) {
  817. mac = list_first_entry(&rxf->ucast_pending_del_q,
  818. struct bna_mac, qe);
  819. bna_bfi_ucast_req(rxf, mac, BFI_ENET_H2I_MAC_UCAST_DEL_REQ);
  820. list_move_tail(&mac->qe, bna_ucam_mod_del_q(rxf->rx->bna));
  821. return 1;
  822. }
  823. /* Set default unicast MAC */
  824. if (rxf->ucast_pending_set) {
  825. rxf->ucast_pending_set = 0;
  826. ether_addr_copy(rxf->ucast_active_mac.addr,
  827. rxf->ucast_pending_mac->addr);
  828. rxf->ucast_active_set = 1;
  829. bna_bfi_ucast_req(rxf, &rxf->ucast_active_mac,
  830. BFI_ENET_H2I_MAC_UCAST_SET_REQ);
  831. return 1;
  832. }
  833. /* Add additional MAC entries */
  834. if (!list_empty(&rxf->ucast_pending_add_q)) {
  835. mac = list_first_entry(&rxf->ucast_pending_add_q,
  836. struct bna_mac, qe);
  837. list_move_tail(&mac->qe, &rxf->ucast_active_q);
  838. bna_bfi_ucast_req(rxf, mac, BFI_ENET_H2I_MAC_UCAST_ADD_REQ);
  839. return 1;
  840. }
  841. return 0;
  842. }
  843. static int
  844. bna_rxf_ucast_cfg_reset(struct bna_rxf *rxf, enum bna_cleanup_type cleanup)
  845. {
  846. struct bna_mac *mac;
  847. /* Throw away delete pending ucast entries */
  848. while (!list_empty(&rxf->ucast_pending_del_q)) {
  849. mac = list_first_entry(&rxf->ucast_pending_del_q,
  850. struct bna_mac, qe);
  851. if (cleanup == BNA_SOFT_CLEANUP)
  852. list_move_tail(&mac->qe,
  853. bna_ucam_mod_del_q(rxf->rx->bna));
  854. else {
  855. bna_bfi_ucast_req(rxf, mac,
  856. BFI_ENET_H2I_MAC_UCAST_DEL_REQ);
  857. list_move_tail(&mac->qe,
  858. bna_ucam_mod_del_q(rxf->rx->bna));
  859. return 1;
  860. }
  861. }
  862. /* Move active ucast entries to pending_add_q */
  863. while (!list_empty(&rxf->ucast_active_q)) {
  864. mac = list_first_entry(&rxf->ucast_active_q,
  865. struct bna_mac, qe);
  866. list_move_tail(&mac->qe, &rxf->ucast_pending_add_q);
  867. if (cleanup == BNA_HARD_CLEANUP) {
  868. bna_bfi_ucast_req(rxf, mac,
  869. BFI_ENET_H2I_MAC_UCAST_DEL_REQ);
  870. return 1;
  871. }
  872. }
  873. if (rxf->ucast_active_set) {
  874. rxf->ucast_pending_set = 1;
  875. rxf->ucast_active_set = 0;
  876. if (cleanup == BNA_HARD_CLEANUP) {
  877. bna_bfi_ucast_req(rxf, &rxf->ucast_active_mac,
  878. BFI_ENET_H2I_MAC_UCAST_CLR_REQ);
  879. return 1;
  880. }
  881. }
  882. return 0;
  883. }
  884. static int
  885. bna_rxf_promisc_cfg_apply(struct bna_rxf *rxf)
  886. {
  887. struct bna *bna = rxf->rx->bna;
  888. /* Enable/disable promiscuous mode */
  889. if (is_promisc_enable(rxf->rxmode_pending,
  890. rxf->rxmode_pending_bitmask)) {
  891. /* move promisc configuration from pending -> active */
  892. promisc_inactive(rxf->rxmode_pending,
  893. rxf->rxmode_pending_bitmask);
  894. rxf->rxmode_active |= BNA_RXMODE_PROMISC;
  895. bna_bfi_rx_promisc_req(rxf, BNA_STATUS_T_ENABLED);
  896. return 1;
  897. } else if (is_promisc_disable(rxf->rxmode_pending,
  898. rxf->rxmode_pending_bitmask)) {
  899. /* move promisc configuration from pending -> active */
  900. promisc_inactive(rxf->rxmode_pending,
  901. rxf->rxmode_pending_bitmask);
  902. rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
  903. bna->promisc_rid = BFI_INVALID_RID;
  904. bna_bfi_rx_promisc_req(rxf, BNA_STATUS_T_DISABLED);
  905. return 1;
  906. }
  907. return 0;
  908. }
  909. static int
  910. bna_rxf_promisc_cfg_reset(struct bna_rxf *rxf, enum bna_cleanup_type cleanup)
  911. {
  912. struct bna *bna = rxf->rx->bna;
  913. /* Clear pending promisc mode disable */
  914. if (is_promisc_disable(rxf->rxmode_pending,
  915. rxf->rxmode_pending_bitmask)) {
  916. promisc_inactive(rxf->rxmode_pending,
  917. rxf->rxmode_pending_bitmask);
  918. rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
  919. bna->promisc_rid = BFI_INVALID_RID;
  920. if (cleanup == BNA_HARD_CLEANUP) {
  921. bna_bfi_rx_promisc_req(rxf, BNA_STATUS_T_DISABLED);
  922. return 1;
  923. }
  924. }
  925. /* Move promisc mode config from active -> pending */
  926. if (rxf->rxmode_active & BNA_RXMODE_PROMISC) {
  927. promisc_enable(rxf->rxmode_pending,
  928. rxf->rxmode_pending_bitmask);
  929. rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
  930. if (cleanup == BNA_HARD_CLEANUP) {
  931. bna_bfi_rx_promisc_req(rxf, BNA_STATUS_T_DISABLED);
  932. return 1;
  933. }
  934. }
  935. return 0;
  936. }
  937. static int
  938. bna_rxf_allmulti_cfg_apply(struct bna_rxf *rxf)
  939. {
  940. /* Enable/disable allmulti mode */
  941. if (is_allmulti_enable(rxf->rxmode_pending,
  942. rxf->rxmode_pending_bitmask)) {
  943. /* move allmulti configuration from pending -> active */
  944. allmulti_inactive(rxf->rxmode_pending,
  945. rxf->rxmode_pending_bitmask);
  946. rxf->rxmode_active |= BNA_RXMODE_ALLMULTI;
  947. bna_bfi_mcast_filter_req(rxf, BNA_STATUS_T_DISABLED);
  948. return 1;
  949. } else if (is_allmulti_disable(rxf->rxmode_pending,
  950. rxf->rxmode_pending_bitmask)) {
  951. /* move allmulti configuration from pending -> active */
  952. allmulti_inactive(rxf->rxmode_pending,
  953. rxf->rxmode_pending_bitmask);
  954. rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
  955. bna_bfi_mcast_filter_req(rxf, BNA_STATUS_T_ENABLED);
  956. return 1;
  957. }
  958. return 0;
  959. }
  960. static int
  961. bna_rxf_allmulti_cfg_reset(struct bna_rxf *rxf, enum bna_cleanup_type cleanup)
  962. {
  963. /* Clear pending allmulti mode disable */
  964. if (is_allmulti_disable(rxf->rxmode_pending,
  965. rxf->rxmode_pending_bitmask)) {
  966. allmulti_inactive(rxf->rxmode_pending,
  967. rxf->rxmode_pending_bitmask);
  968. rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
  969. if (cleanup == BNA_HARD_CLEANUP) {
  970. bna_bfi_mcast_filter_req(rxf, BNA_STATUS_T_ENABLED);
  971. return 1;
  972. }
  973. }
  974. /* Move allmulti mode config from active -> pending */
  975. if (rxf->rxmode_active & BNA_RXMODE_ALLMULTI) {
  976. allmulti_enable(rxf->rxmode_pending,
  977. rxf->rxmode_pending_bitmask);
  978. rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
  979. if (cleanup == BNA_HARD_CLEANUP) {
  980. bna_bfi_mcast_filter_req(rxf, BNA_STATUS_T_ENABLED);
  981. return 1;
  982. }
  983. }
  984. return 0;
  985. }
  986. static int
  987. bna_rxf_promisc_enable(struct bna_rxf *rxf)
  988. {
  989. struct bna *bna = rxf->rx->bna;
  990. int ret = 0;
  991. if (is_promisc_enable(rxf->rxmode_pending,
  992. rxf->rxmode_pending_bitmask) ||
  993. (rxf->rxmode_active & BNA_RXMODE_PROMISC)) {
  994. /* Do nothing if pending enable or already enabled */
  995. } else if (is_promisc_disable(rxf->rxmode_pending,
  996. rxf->rxmode_pending_bitmask)) {
  997. /* Turn off pending disable command */
  998. promisc_inactive(rxf->rxmode_pending,
  999. rxf->rxmode_pending_bitmask);
  1000. } else {
  1001. /* Schedule enable */
  1002. promisc_enable(rxf->rxmode_pending,
  1003. rxf->rxmode_pending_bitmask);
  1004. bna->promisc_rid = rxf->rx->rid;
  1005. ret = 1;
  1006. }
  1007. return ret;
  1008. }
  1009. static int
  1010. bna_rxf_promisc_disable(struct bna_rxf *rxf)
  1011. {
  1012. struct bna *bna = rxf->rx->bna;
  1013. int ret = 0;
  1014. if (is_promisc_disable(rxf->rxmode_pending,
  1015. rxf->rxmode_pending_bitmask) ||
  1016. (!(rxf->rxmode_active & BNA_RXMODE_PROMISC))) {
  1017. /* Do nothing if pending disable or already disabled */
  1018. } else if (is_promisc_enable(rxf->rxmode_pending,
  1019. rxf->rxmode_pending_bitmask)) {
  1020. /* Turn off pending enable command */
  1021. promisc_inactive(rxf->rxmode_pending,
  1022. rxf->rxmode_pending_bitmask);
  1023. bna->promisc_rid = BFI_INVALID_RID;
  1024. } else if (rxf->rxmode_active & BNA_RXMODE_PROMISC) {
  1025. /* Schedule disable */
  1026. promisc_disable(rxf->rxmode_pending,
  1027. rxf->rxmode_pending_bitmask);
  1028. ret = 1;
  1029. }
  1030. return ret;
  1031. }
  1032. static int
  1033. bna_rxf_allmulti_enable(struct bna_rxf *rxf)
  1034. {
  1035. int ret = 0;
  1036. if (is_allmulti_enable(rxf->rxmode_pending,
  1037. rxf->rxmode_pending_bitmask) ||
  1038. (rxf->rxmode_active & BNA_RXMODE_ALLMULTI)) {
  1039. /* Do nothing if pending enable or already enabled */
  1040. } else if (is_allmulti_disable(rxf->rxmode_pending,
  1041. rxf->rxmode_pending_bitmask)) {
  1042. /* Turn off pending disable command */
  1043. allmulti_inactive(rxf->rxmode_pending,
  1044. rxf->rxmode_pending_bitmask);
  1045. } else {
  1046. /* Schedule enable */
  1047. allmulti_enable(rxf->rxmode_pending,
  1048. rxf->rxmode_pending_bitmask);
  1049. ret = 1;
  1050. }
  1051. return ret;
  1052. }
  1053. static int
  1054. bna_rxf_allmulti_disable(struct bna_rxf *rxf)
  1055. {
  1056. int ret = 0;
  1057. if (is_allmulti_disable(rxf->rxmode_pending,
  1058. rxf->rxmode_pending_bitmask) ||
  1059. (!(rxf->rxmode_active & BNA_RXMODE_ALLMULTI))) {
  1060. /* Do nothing if pending disable or already disabled */
  1061. } else if (is_allmulti_enable(rxf->rxmode_pending,
  1062. rxf->rxmode_pending_bitmask)) {
  1063. /* Turn off pending enable command */
  1064. allmulti_inactive(rxf->rxmode_pending,
  1065. rxf->rxmode_pending_bitmask);
  1066. } else if (rxf->rxmode_active & BNA_RXMODE_ALLMULTI) {
  1067. /* Schedule disable */
  1068. allmulti_disable(rxf->rxmode_pending,
  1069. rxf->rxmode_pending_bitmask);
  1070. ret = 1;
  1071. }
  1072. return ret;
  1073. }
  1074. static int
  1075. bna_rxf_vlan_strip_cfg_apply(struct bna_rxf *rxf)
  1076. {
  1077. if (rxf->vlan_strip_pending) {
  1078. rxf->vlan_strip_pending = false;
  1079. bna_bfi_vlan_strip_enable(rxf);
  1080. return 1;
  1081. }
  1082. return 0;
  1083. }
  1084. /* RX */
  1085. #define BNA_GET_RXQS(qcfg) (((qcfg)->rxp_type == BNA_RXP_SINGLE) ? \
  1086. (qcfg)->num_paths : ((qcfg)->num_paths * 2))
  1087. #define SIZE_TO_PAGES(size) (((size) >> PAGE_SHIFT) + ((((size) &\
  1088. (PAGE_SIZE - 1)) + (PAGE_SIZE - 1)) >> PAGE_SHIFT))
  1089. #define call_rx_stop_cbfn(rx) \
  1090. do { \
  1091. if ((rx)->stop_cbfn) { \
  1092. void (*cbfn)(void *, struct bna_rx *); \
  1093. void *cbarg; \
  1094. cbfn = (rx)->stop_cbfn; \
  1095. cbarg = (rx)->stop_cbarg; \
  1096. (rx)->stop_cbfn = NULL; \
  1097. (rx)->stop_cbarg = NULL; \
  1098. cbfn(cbarg, rx); \
  1099. } \
  1100. } while (0)
  1101. #define call_rx_stall_cbfn(rx) \
  1102. do { \
  1103. if ((rx)->rx_stall_cbfn) \
  1104. (rx)->rx_stall_cbfn((rx)->bna->bnad, (rx)); \
  1105. } while (0)
  1106. #define bfi_enet_datapath_q_init(bfi_q, bna_qpt) \
  1107. do { \
  1108. struct bna_dma_addr cur_q_addr = \
  1109. *((struct bna_dma_addr *)((bna_qpt)->kv_qpt_ptr)); \
  1110. (bfi_q)->pg_tbl.a32.addr_lo = (bna_qpt)->hw_qpt_ptr.lsb; \
  1111. (bfi_q)->pg_tbl.a32.addr_hi = (bna_qpt)->hw_qpt_ptr.msb; \
  1112. (bfi_q)->first_entry.a32.addr_lo = cur_q_addr.lsb; \
  1113. (bfi_q)->first_entry.a32.addr_hi = cur_q_addr.msb; \
  1114. (bfi_q)->pages = htons((u16)(bna_qpt)->page_count); \
  1115. (bfi_q)->page_sz = htons((u16)(bna_qpt)->page_size);\
  1116. } while (0)
  1117. static void bna_bfi_rx_enet_start(struct bna_rx *rx);
  1118. static void bna_rx_enet_stop(struct bna_rx *rx);
  1119. static void bna_rx_mod_cb_rx_stopped(void *arg, struct bna_rx *rx);
  1120. bfa_fsm_state_decl(bna_rx, stopped,
  1121. struct bna_rx, enum bna_rx_event);
  1122. bfa_fsm_state_decl(bna_rx, start_wait,
  1123. struct bna_rx, enum bna_rx_event);
  1124. bfa_fsm_state_decl(bna_rx, start_stop_wait,
  1125. struct bna_rx, enum bna_rx_event);
  1126. bfa_fsm_state_decl(bna_rx, rxf_start_wait,
  1127. struct bna_rx, enum bna_rx_event);
  1128. bfa_fsm_state_decl(bna_rx, started,
  1129. struct bna_rx, enum bna_rx_event);
  1130. bfa_fsm_state_decl(bna_rx, rxf_stop_wait,
  1131. struct bna_rx, enum bna_rx_event);
  1132. bfa_fsm_state_decl(bna_rx, stop_wait,
  1133. struct bna_rx, enum bna_rx_event);
  1134. bfa_fsm_state_decl(bna_rx, cleanup_wait,
  1135. struct bna_rx, enum bna_rx_event);
  1136. bfa_fsm_state_decl(bna_rx, failed,
  1137. struct bna_rx, enum bna_rx_event);
  1138. bfa_fsm_state_decl(bna_rx, quiesce_wait,
  1139. struct bna_rx, enum bna_rx_event);
  1140. static void bna_rx_sm_stopped_entry(struct bna_rx *rx)
  1141. {
  1142. call_rx_stop_cbfn(rx);
  1143. }
  1144. static void bna_rx_sm_stopped(struct bna_rx *rx,
  1145. enum bna_rx_event event)
  1146. {
  1147. switch (event) {
  1148. case RX_E_START:
  1149. bfa_fsm_set_state(rx, bna_rx_sm_start_wait);
  1150. break;
  1151. case RX_E_STOP:
  1152. call_rx_stop_cbfn(rx);
  1153. break;
  1154. case RX_E_FAIL:
  1155. /* no-op */
  1156. break;
  1157. default:
  1158. bfa_sm_fault(event);
  1159. break;
  1160. }
  1161. }
  1162. static void bna_rx_sm_start_wait_entry(struct bna_rx *rx)
  1163. {
  1164. bna_bfi_rx_enet_start(rx);
  1165. }
  1166. static void
  1167. bna_rx_sm_stop_wait_entry(struct bna_rx *rx)
  1168. {
  1169. }
  1170. static void
  1171. bna_rx_sm_stop_wait(struct bna_rx *rx, enum bna_rx_event event)
  1172. {
  1173. switch (event) {
  1174. case RX_E_FAIL:
  1175. case RX_E_STOPPED:
  1176. bfa_fsm_set_state(rx, bna_rx_sm_cleanup_wait);
  1177. rx->rx_cleanup_cbfn(rx->bna->bnad, rx);
  1178. break;
  1179. case RX_E_STARTED:
  1180. bna_rx_enet_stop(rx);
  1181. break;
  1182. default:
  1183. bfa_sm_fault(event);
  1184. break;
  1185. }
  1186. }
  1187. static void bna_rx_sm_start_wait(struct bna_rx *rx,
  1188. enum bna_rx_event event)
  1189. {
  1190. switch (event) {
  1191. case RX_E_STOP:
  1192. bfa_fsm_set_state(rx, bna_rx_sm_start_stop_wait);
  1193. break;
  1194. case RX_E_FAIL:
  1195. bfa_fsm_set_state(rx, bna_rx_sm_stopped);
  1196. break;
  1197. case RX_E_STARTED:
  1198. bfa_fsm_set_state(rx, bna_rx_sm_rxf_start_wait);
  1199. break;
  1200. default:
  1201. bfa_sm_fault(event);
  1202. break;
  1203. }
  1204. }
  1205. static void bna_rx_sm_rxf_start_wait_entry(struct bna_rx *rx)
  1206. {
  1207. rx->rx_post_cbfn(rx->bna->bnad, rx);
  1208. bna_rxf_start(&rx->rxf);
  1209. }
  1210. static void
  1211. bna_rx_sm_rxf_stop_wait_entry(struct bna_rx *rx)
  1212. {
  1213. }
  1214. static void
  1215. bna_rx_sm_rxf_stop_wait(struct bna_rx *rx, enum bna_rx_event event)
  1216. {
  1217. switch (event) {
  1218. case RX_E_FAIL:
  1219. bfa_fsm_set_state(rx, bna_rx_sm_cleanup_wait);
  1220. bna_rxf_fail(&rx->rxf);
  1221. call_rx_stall_cbfn(rx);
  1222. rx->rx_cleanup_cbfn(rx->bna->bnad, rx);
  1223. break;
  1224. case RX_E_RXF_STARTED:
  1225. bna_rxf_stop(&rx->rxf);
  1226. break;
  1227. case RX_E_RXF_STOPPED:
  1228. bfa_fsm_set_state(rx, bna_rx_sm_stop_wait);
  1229. call_rx_stall_cbfn(rx);
  1230. bna_rx_enet_stop(rx);
  1231. break;
  1232. default:
  1233. bfa_sm_fault(event);
  1234. break;
  1235. }
  1236. }
  1237. static void
  1238. bna_rx_sm_start_stop_wait_entry(struct bna_rx *rx)
  1239. {
  1240. }
  1241. static void
  1242. bna_rx_sm_start_stop_wait(struct bna_rx *rx, enum bna_rx_event event)
  1243. {
  1244. switch (event) {
  1245. case RX_E_FAIL:
  1246. case RX_E_STOPPED:
  1247. bfa_fsm_set_state(rx, bna_rx_sm_stopped);
  1248. break;
  1249. case RX_E_STARTED:
  1250. bna_rx_enet_stop(rx);
  1251. break;
  1252. default:
  1253. bfa_sm_fault(event);
  1254. }
  1255. }
  1256. static void
  1257. bna_rx_sm_started_entry(struct bna_rx *rx)
  1258. {
  1259. struct bna_rxp *rxp;
  1260. int is_regular = (rx->type == BNA_RX_T_REGULAR);
  1261. /* Start IB */
  1262. list_for_each_entry(rxp, &rx->rxp_q, qe)
  1263. bna_ib_start(rx->bna, &rxp->cq.ib, is_regular);
  1264. bna_ethport_cb_rx_started(&rx->bna->ethport);
  1265. }
  1266. static void
  1267. bna_rx_sm_started(struct bna_rx *rx, enum bna_rx_event event)
  1268. {
  1269. switch (event) {
  1270. case RX_E_STOP:
  1271. bfa_fsm_set_state(rx, bna_rx_sm_rxf_stop_wait);
  1272. bna_ethport_cb_rx_stopped(&rx->bna->ethport);
  1273. bna_rxf_stop(&rx->rxf);
  1274. break;
  1275. case RX_E_FAIL:
  1276. bfa_fsm_set_state(rx, bna_rx_sm_failed);
  1277. bna_ethport_cb_rx_stopped(&rx->bna->ethport);
  1278. bna_rxf_fail(&rx->rxf);
  1279. call_rx_stall_cbfn(rx);
  1280. rx->rx_cleanup_cbfn(rx->bna->bnad, rx);
  1281. break;
  1282. default:
  1283. bfa_sm_fault(event);
  1284. break;
  1285. }
  1286. }
  1287. static void bna_rx_sm_rxf_start_wait(struct bna_rx *rx,
  1288. enum bna_rx_event event)
  1289. {
  1290. switch (event) {
  1291. case RX_E_STOP:
  1292. bfa_fsm_set_state(rx, bna_rx_sm_rxf_stop_wait);
  1293. break;
  1294. case RX_E_FAIL:
  1295. bfa_fsm_set_state(rx, bna_rx_sm_failed);
  1296. bna_rxf_fail(&rx->rxf);
  1297. call_rx_stall_cbfn(rx);
  1298. rx->rx_cleanup_cbfn(rx->bna->bnad, rx);
  1299. break;
  1300. case RX_E_RXF_STARTED:
  1301. bfa_fsm_set_state(rx, bna_rx_sm_started);
  1302. break;
  1303. default:
  1304. bfa_sm_fault(event);
  1305. break;
  1306. }
  1307. }
  1308. static void
  1309. bna_rx_sm_cleanup_wait_entry(struct bna_rx *rx)
  1310. {
  1311. }
  1312. static void
  1313. bna_rx_sm_cleanup_wait(struct bna_rx *rx, enum bna_rx_event event)
  1314. {
  1315. switch (event) {
  1316. case RX_E_FAIL:
  1317. case RX_E_RXF_STOPPED:
  1318. /* No-op */
  1319. break;
  1320. case RX_E_CLEANUP_DONE:
  1321. bfa_fsm_set_state(rx, bna_rx_sm_stopped);
  1322. break;
  1323. default:
  1324. bfa_sm_fault(event);
  1325. break;
  1326. }
  1327. }
  1328. static void
  1329. bna_rx_sm_failed_entry(struct bna_rx *rx)
  1330. {
  1331. }
  1332. static void
  1333. bna_rx_sm_failed(struct bna_rx *rx, enum bna_rx_event event)
  1334. {
  1335. switch (event) {
  1336. case RX_E_START:
  1337. bfa_fsm_set_state(rx, bna_rx_sm_quiesce_wait);
  1338. break;
  1339. case RX_E_STOP:
  1340. bfa_fsm_set_state(rx, bna_rx_sm_cleanup_wait);
  1341. break;
  1342. case RX_E_FAIL:
  1343. case RX_E_RXF_STARTED:
  1344. case RX_E_RXF_STOPPED:
  1345. /* No-op */
  1346. break;
  1347. case RX_E_CLEANUP_DONE:
  1348. bfa_fsm_set_state(rx, bna_rx_sm_stopped);
  1349. break;
  1350. default:
  1351. bfa_sm_fault(event);
  1352. break;
  1353. } }
  1354. static void
  1355. bna_rx_sm_quiesce_wait_entry(struct bna_rx *rx)
  1356. {
  1357. }
  1358. static void
  1359. bna_rx_sm_quiesce_wait(struct bna_rx *rx, enum bna_rx_event event)
  1360. {
  1361. switch (event) {
  1362. case RX_E_STOP:
  1363. bfa_fsm_set_state(rx, bna_rx_sm_cleanup_wait);
  1364. break;
  1365. case RX_E_FAIL:
  1366. bfa_fsm_set_state(rx, bna_rx_sm_failed);
  1367. break;
  1368. case RX_E_CLEANUP_DONE:
  1369. bfa_fsm_set_state(rx, bna_rx_sm_start_wait);
  1370. break;
  1371. default:
  1372. bfa_sm_fault(event);
  1373. break;
  1374. }
  1375. }
  1376. static void
  1377. bna_bfi_rx_enet_start(struct bna_rx *rx)
  1378. {
  1379. struct bfi_enet_rx_cfg_req *cfg_req = &rx->bfi_enet_cmd.cfg_req;
  1380. struct bna_rxp *rxp = NULL;
  1381. struct bna_rxq *q0 = NULL, *q1 = NULL;
  1382. int i;
  1383. bfi_msgq_mhdr_set(cfg_req->mh, BFI_MC_ENET,
  1384. BFI_ENET_H2I_RX_CFG_SET_REQ, 0, rx->rid);
  1385. cfg_req->mh.num_entries = htons(
  1386. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_rx_cfg_req)));
  1387. cfg_req->rx_cfg.frame_size = bna_enet_mtu_get(&rx->bna->enet);
  1388. cfg_req->num_queue_sets = rx->num_paths;
  1389. for (i = 0; i < rx->num_paths; i++) {
  1390. rxp = rxp ? list_next_entry(rxp, qe)
  1391. : list_first_entry(&rx->rxp_q, struct bna_rxp, qe);
  1392. GET_RXQS(rxp, q0, q1);
  1393. switch (rxp->type) {
  1394. case BNA_RXP_SLR:
  1395. case BNA_RXP_HDS:
  1396. /* Small RxQ */
  1397. bfi_enet_datapath_q_init(&cfg_req->q_cfg[i].qs.q,
  1398. &q1->qpt);
  1399. cfg_req->q_cfg[i].qs.rx_buffer_size =
  1400. htons((u16)q1->buffer_size);
  1401. /* Fall through */
  1402. case BNA_RXP_SINGLE:
  1403. /* Large/Single RxQ */
  1404. bfi_enet_datapath_q_init(&cfg_req->q_cfg[i].ql.q,
  1405. &q0->qpt);
  1406. if (q0->multi_buffer)
  1407. /* multi-buffer is enabled by allocating
  1408. * a new rx with new set of resources.
  1409. * q0->buffer_size should be initialized to
  1410. * fragment size.
  1411. */
  1412. cfg_req->rx_cfg.multi_buffer =
  1413. BNA_STATUS_T_ENABLED;
  1414. else
  1415. q0->buffer_size =
  1416. bna_enet_mtu_get(&rx->bna->enet);
  1417. cfg_req->q_cfg[i].ql.rx_buffer_size =
  1418. htons((u16)q0->buffer_size);
  1419. break;
  1420. default:
  1421. BUG_ON(1);
  1422. }
  1423. bfi_enet_datapath_q_init(&cfg_req->q_cfg[i].cq.q,
  1424. &rxp->cq.qpt);
  1425. cfg_req->q_cfg[i].ib.index_addr.a32.addr_lo =
  1426. rxp->cq.ib.ib_seg_host_addr.lsb;
  1427. cfg_req->q_cfg[i].ib.index_addr.a32.addr_hi =
  1428. rxp->cq.ib.ib_seg_host_addr.msb;
  1429. cfg_req->q_cfg[i].ib.intr.msix_index =
  1430. htons((u16)rxp->cq.ib.intr_vector);
  1431. }
  1432. cfg_req->ib_cfg.int_pkt_dma = BNA_STATUS_T_DISABLED;
  1433. cfg_req->ib_cfg.int_enabled = BNA_STATUS_T_ENABLED;
  1434. cfg_req->ib_cfg.int_pkt_enabled = BNA_STATUS_T_DISABLED;
  1435. cfg_req->ib_cfg.continuous_coalescing = BNA_STATUS_T_DISABLED;
  1436. cfg_req->ib_cfg.msix = (rxp->cq.ib.intr_type == BNA_INTR_T_MSIX)
  1437. ? BNA_STATUS_T_ENABLED :
  1438. BNA_STATUS_T_DISABLED;
  1439. cfg_req->ib_cfg.coalescing_timeout =
  1440. htonl((u32)rxp->cq.ib.coalescing_timeo);
  1441. cfg_req->ib_cfg.inter_pkt_timeout =
  1442. htonl((u32)rxp->cq.ib.interpkt_timeo);
  1443. cfg_req->ib_cfg.inter_pkt_count = (u8)rxp->cq.ib.interpkt_count;
  1444. switch (rxp->type) {
  1445. case BNA_RXP_SLR:
  1446. cfg_req->rx_cfg.rxq_type = BFI_ENET_RXQ_LARGE_SMALL;
  1447. break;
  1448. case BNA_RXP_HDS:
  1449. cfg_req->rx_cfg.rxq_type = BFI_ENET_RXQ_HDS;
  1450. cfg_req->rx_cfg.hds.type = rx->hds_cfg.hdr_type;
  1451. cfg_req->rx_cfg.hds.force_offset = rx->hds_cfg.forced_offset;
  1452. cfg_req->rx_cfg.hds.max_header_size = rx->hds_cfg.forced_offset;
  1453. break;
  1454. case BNA_RXP_SINGLE:
  1455. cfg_req->rx_cfg.rxq_type = BFI_ENET_RXQ_SINGLE;
  1456. break;
  1457. default:
  1458. BUG_ON(1);
  1459. }
  1460. cfg_req->rx_cfg.strip_vlan = rx->rxf.vlan_strip_status;
  1461. bfa_msgq_cmd_set(&rx->msgq_cmd, NULL, NULL,
  1462. sizeof(struct bfi_enet_rx_cfg_req), &cfg_req->mh);
  1463. bfa_msgq_cmd_post(&rx->bna->msgq, &rx->msgq_cmd);
  1464. }
  1465. static void
  1466. bna_bfi_rx_enet_stop(struct bna_rx *rx)
  1467. {
  1468. struct bfi_enet_req *req = &rx->bfi_enet_cmd.req;
  1469. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  1470. BFI_ENET_H2I_RX_CFG_CLR_REQ, 0, rx->rid);
  1471. req->mh.num_entries = htons(
  1472. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_req)));
  1473. bfa_msgq_cmd_set(&rx->msgq_cmd, NULL, NULL, sizeof(struct bfi_enet_req),
  1474. &req->mh);
  1475. bfa_msgq_cmd_post(&rx->bna->msgq, &rx->msgq_cmd);
  1476. }
  1477. static void
  1478. bna_rx_enet_stop(struct bna_rx *rx)
  1479. {
  1480. struct bna_rxp *rxp;
  1481. /* Stop IB */
  1482. list_for_each_entry(rxp, &rx->rxp_q, qe)
  1483. bna_ib_stop(rx->bna, &rxp->cq.ib);
  1484. bna_bfi_rx_enet_stop(rx);
  1485. }
  1486. static int
  1487. bna_rx_res_check(struct bna_rx_mod *rx_mod, struct bna_rx_config *rx_cfg)
  1488. {
  1489. if ((rx_mod->rx_free_count == 0) ||
  1490. (rx_mod->rxp_free_count == 0) ||
  1491. (rx_mod->rxq_free_count == 0))
  1492. return 0;
  1493. if (rx_cfg->rxp_type == BNA_RXP_SINGLE) {
  1494. if ((rx_mod->rxp_free_count < rx_cfg->num_paths) ||
  1495. (rx_mod->rxq_free_count < rx_cfg->num_paths))
  1496. return 0;
  1497. } else {
  1498. if ((rx_mod->rxp_free_count < rx_cfg->num_paths) ||
  1499. (rx_mod->rxq_free_count < (2 * rx_cfg->num_paths)))
  1500. return 0;
  1501. }
  1502. return 1;
  1503. }
  1504. static struct bna_rxq *
  1505. bna_rxq_get(struct bna_rx_mod *rx_mod)
  1506. {
  1507. struct bna_rxq *rxq = NULL;
  1508. rxq = list_first_entry(&rx_mod->rxq_free_q, struct bna_rxq, qe);
  1509. list_del(&rxq->qe);
  1510. rx_mod->rxq_free_count--;
  1511. return rxq;
  1512. }
  1513. static void
  1514. bna_rxq_put(struct bna_rx_mod *rx_mod, struct bna_rxq *rxq)
  1515. {
  1516. list_add_tail(&rxq->qe, &rx_mod->rxq_free_q);
  1517. rx_mod->rxq_free_count++;
  1518. }
  1519. static struct bna_rxp *
  1520. bna_rxp_get(struct bna_rx_mod *rx_mod)
  1521. {
  1522. struct bna_rxp *rxp = NULL;
  1523. rxp = list_first_entry(&rx_mod->rxp_free_q, struct bna_rxp, qe);
  1524. list_del(&rxp->qe);
  1525. rx_mod->rxp_free_count--;
  1526. return rxp;
  1527. }
  1528. static void
  1529. bna_rxp_put(struct bna_rx_mod *rx_mod, struct bna_rxp *rxp)
  1530. {
  1531. list_add_tail(&rxp->qe, &rx_mod->rxp_free_q);
  1532. rx_mod->rxp_free_count++;
  1533. }
  1534. static struct bna_rx *
  1535. bna_rx_get(struct bna_rx_mod *rx_mod, enum bna_rx_type type)
  1536. {
  1537. struct bna_rx *rx = NULL;
  1538. BUG_ON(list_empty(&rx_mod->rx_free_q));
  1539. if (type == BNA_RX_T_REGULAR)
  1540. rx = list_first_entry(&rx_mod->rx_free_q, struct bna_rx, qe);
  1541. else
  1542. rx = list_last_entry(&rx_mod->rx_free_q, struct bna_rx, qe);
  1543. rx_mod->rx_free_count--;
  1544. list_move_tail(&rx->qe, &rx_mod->rx_active_q);
  1545. rx->type = type;
  1546. return rx;
  1547. }
  1548. static void
  1549. bna_rx_put(struct bna_rx_mod *rx_mod, struct bna_rx *rx)
  1550. {
  1551. struct list_head *qe;
  1552. list_for_each_prev(qe, &rx_mod->rx_free_q)
  1553. if (((struct bna_rx *)qe)->rid < rx->rid)
  1554. break;
  1555. list_add(&rx->qe, qe);
  1556. rx_mod->rx_free_count++;
  1557. }
  1558. static void
  1559. bna_rxp_add_rxqs(struct bna_rxp *rxp, struct bna_rxq *q0,
  1560. struct bna_rxq *q1)
  1561. {
  1562. switch (rxp->type) {
  1563. case BNA_RXP_SINGLE:
  1564. rxp->rxq.single.only = q0;
  1565. rxp->rxq.single.reserved = NULL;
  1566. break;
  1567. case BNA_RXP_SLR:
  1568. rxp->rxq.slr.large = q0;
  1569. rxp->rxq.slr.small = q1;
  1570. break;
  1571. case BNA_RXP_HDS:
  1572. rxp->rxq.hds.data = q0;
  1573. rxp->rxq.hds.hdr = q1;
  1574. break;
  1575. default:
  1576. break;
  1577. }
  1578. }
  1579. static void
  1580. bna_rxq_qpt_setup(struct bna_rxq *rxq,
  1581. struct bna_rxp *rxp,
  1582. u32 page_count,
  1583. u32 page_size,
  1584. struct bna_mem_descr *qpt_mem,
  1585. struct bna_mem_descr *swqpt_mem,
  1586. struct bna_mem_descr *page_mem)
  1587. {
  1588. u8 *kva;
  1589. u64 dma;
  1590. struct bna_dma_addr bna_dma;
  1591. int i;
  1592. rxq->qpt.hw_qpt_ptr.lsb = qpt_mem->dma.lsb;
  1593. rxq->qpt.hw_qpt_ptr.msb = qpt_mem->dma.msb;
  1594. rxq->qpt.kv_qpt_ptr = qpt_mem->kva;
  1595. rxq->qpt.page_count = page_count;
  1596. rxq->qpt.page_size = page_size;
  1597. rxq->rcb->sw_qpt = (void **) swqpt_mem->kva;
  1598. rxq->rcb->sw_q = page_mem->kva;
  1599. kva = page_mem->kva;
  1600. BNA_GET_DMA_ADDR(&page_mem->dma, dma);
  1601. for (i = 0; i < rxq->qpt.page_count; i++) {
  1602. rxq->rcb->sw_qpt[i] = kva;
  1603. kva += PAGE_SIZE;
  1604. BNA_SET_DMA_ADDR(dma, &bna_dma);
  1605. ((struct bna_dma_addr *)rxq->qpt.kv_qpt_ptr)[i].lsb =
  1606. bna_dma.lsb;
  1607. ((struct bna_dma_addr *)rxq->qpt.kv_qpt_ptr)[i].msb =
  1608. bna_dma.msb;
  1609. dma += PAGE_SIZE;
  1610. }
  1611. }
  1612. static void
  1613. bna_rxp_cqpt_setup(struct bna_rxp *rxp,
  1614. u32 page_count,
  1615. u32 page_size,
  1616. struct bna_mem_descr *qpt_mem,
  1617. struct bna_mem_descr *swqpt_mem,
  1618. struct bna_mem_descr *page_mem)
  1619. {
  1620. u8 *kva;
  1621. u64 dma;
  1622. struct bna_dma_addr bna_dma;
  1623. int i;
  1624. rxp->cq.qpt.hw_qpt_ptr.lsb = qpt_mem->dma.lsb;
  1625. rxp->cq.qpt.hw_qpt_ptr.msb = qpt_mem->dma.msb;
  1626. rxp->cq.qpt.kv_qpt_ptr = qpt_mem->kva;
  1627. rxp->cq.qpt.page_count = page_count;
  1628. rxp->cq.qpt.page_size = page_size;
  1629. rxp->cq.ccb->sw_qpt = (void **) swqpt_mem->kva;
  1630. rxp->cq.ccb->sw_q = page_mem->kva;
  1631. kva = page_mem->kva;
  1632. BNA_GET_DMA_ADDR(&page_mem->dma, dma);
  1633. for (i = 0; i < rxp->cq.qpt.page_count; i++) {
  1634. rxp->cq.ccb->sw_qpt[i] = kva;
  1635. kva += PAGE_SIZE;
  1636. BNA_SET_DMA_ADDR(dma, &bna_dma);
  1637. ((struct bna_dma_addr *)rxp->cq.qpt.kv_qpt_ptr)[i].lsb =
  1638. bna_dma.lsb;
  1639. ((struct bna_dma_addr *)rxp->cq.qpt.kv_qpt_ptr)[i].msb =
  1640. bna_dma.msb;
  1641. dma += PAGE_SIZE;
  1642. }
  1643. }
  1644. static void
  1645. bna_rx_mod_cb_rx_stopped(void *arg, struct bna_rx *rx)
  1646. {
  1647. struct bna_rx_mod *rx_mod = (struct bna_rx_mod *)arg;
  1648. bfa_wc_down(&rx_mod->rx_stop_wc);
  1649. }
  1650. static void
  1651. bna_rx_mod_cb_rx_stopped_all(void *arg)
  1652. {
  1653. struct bna_rx_mod *rx_mod = (struct bna_rx_mod *)arg;
  1654. if (rx_mod->stop_cbfn)
  1655. rx_mod->stop_cbfn(&rx_mod->bna->enet);
  1656. rx_mod->stop_cbfn = NULL;
  1657. }
  1658. static void
  1659. bna_rx_start(struct bna_rx *rx)
  1660. {
  1661. rx->rx_flags |= BNA_RX_F_ENET_STARTED;
  1662. if (rx->rx_flags & BNA_RX_F_ENABLED)
  1663. bfa_fsm_send_event(rx, RX_E_START);
  1664. }
  1665. static void
  1666. bna_rx_stop(struct bna_rx *rx)
  1667. {
  1668. rx->rx_flags &= ~BNA_RX_F_ENET_STARTED;
  1669. if (rx->fsm == (bfa_fsm_t) bna_rx_sm_stopped)
  1670. bna_rx_mod_cb_rx_stopped(&rx->bna->rx_mod, rx);
  1671. else {
  1672. rx->stop_cbfn = bna_rx_mod_cb_rx_stopped;
  1673. rx->stop_cbarg = &rx->bna->rx_mod;
  1674. bfa_fsm_send_event(rx, RX_E_STOP);
  1675. }
  1676. }
  1677. static void
  1678. bna_rx_fail(struct bna_rx *rx)
  1679. {
  1680. /* Indicate Enet is not enabled, and failed */
  1681. rx->rx_flags &= ~BNA_RX_F_ENET_STARTED;
  1682. bfa_fsm_send_event(rx, RX_E_FAIL);
  1683. }
  1684. void
  1685. bna_rx_mod_start(struct bna_rx_mod *rx_mod, enum bna_rx_type type)
  1686. {
  1687. struct bna_rx *rx;
  1688. rx_mod->flags |= BNA_RX_MOD_F_ENET_STARTED;
  1689. if (type == BNA_RX_T_LOOPBACK)
  1690. rx_mod->flags |= BNA_RX_MOD_F_ENET_LOOPBACK;
  1691. list_for_each_entry(rx, &rx_mod->rx_active_q, qe)
  1692. if (rx->type == type)
  1693. bna_rx_start(rx);
  1694. }
  1695. void
  1696. bna_rx_mod_stop(struct bna_rx_mod *rx_mod, enum bna_rx_type type)
  1697. {
  1698. struct bna_rx *rx;
  1699. rx_mod->flags &= ~BNA_RX_MOD_F_ENET_STARTED;
  1700. rx_mod->flags &= ~BNA_RX_MOD_F_ENET_LOOPBACK;
  1701. rx_mod->stop_cbfn = bna_enet_cb_rx_stopped;
  1702. bfa_wc_init(&rx_mod->rx_stop_wc, bna_rx_mod_cb_rx_stopped_all, rx_mod);
  1703. list_for_each_entry(rx, &rx_mod->rx_active_q, qe)
  1704. if (rx->type == type) {
  1705. bfa_wc_up(&rx_mod->rx_stop_wc);
  1706. bna_rx_stop(rx);
  1707. }
  1708. bfa_wc_wait(&rx_mod->rx_stop_wc);
  1709. }
  1710. void
  1711. bna_rx_mod_fail(struct bna_rx_mod *rx_mod)
  1712. {
  1713. struct bna_rx *rx;
  1714. rx_mod->flags &= ~BNA_RX_MOD_F_ENET_STARTED;
  1715. rx_mod->flags &= ~BNA_RX_MOD_F_ENET_LOOPBACK;
  1716. list_for_each_entry(rx, &rx_mod->rx_active_q, qe)
  1717. bna_rx_fail(rx);
  1718. }
  1719. void bna_rx_mod_init(struct bna_rx_mod *rx_mod, struct bna *bna,
  1720. struct bna_res_info *res_info)
  1721. {
  1722. int index;
  1723. struct bna_rx *rx_ptr;
  1724. struct bna_rxp *rxp_ptr;
  1725. struct bna_rxq *rxq_ptr;
  1726. rx_mod->bna = bna;
  1727. rx_mod->flags = 0;
  1728. rx_mod->rx = (struct bna_rx *)
  1729. res_info[BNA_MOD_RES_MEM_T_RX_ARRAY].res_u.mem_info.mdl[0].kva;
  1730. rx_mod->rxp = (struct bna_rxp *)
  1731. res_info[BNA_MOD_RES_MEM_T_RXP_ARRAY].res_u.mem_info.mdl[0].kva;
  1732. rx_mod->rxq = (struct bna_rxq *)
  1733. res_info[BNA_MOD_RES_MEM_T_RXQ_ARRAY].res_u.mem_info.mdl[0].kva;
  1734. /* Initialize the queues */
  1735. INIT_LIST_HEAD(&rx_mod->rx_free_q);
  1736. rx_mod->rx_free_count = 0;
  1737. INIT_LIST_HEAD(&rx_mod->rxq_free_q);
  1738. rx_mod->rxq_free_count = 0;
  1739. INIT_LIST_HEAD(&rx_mod->rxp_free_q);
  1740. rx_mod->rxp_free_count = 0;
  1741. INIT_LIST_HEAD(&rx_mod->rx_active_q);
  1742. /* Build RX queues */
  1743. for (index = 0; index < bna->ioceth.attr.num_rxp; index++) {
  1744. rx_ptr = &rx_mod->rx[index];
  1745. INIT_LIST_HEAD(&rx_ptr->rxp_q);
  1746. rx_ptr->bna = NULL;
  1747. rx_ptr->rid = index;
  1748. rx_ptr->stop_cbfn = NULL;
  1749. rx_ptr->stop_cbarg = NULL;
  1750. list_add_tail(&rx_ptr->qe, &rx_mod->rx_free_q);
  1751. rx_mod->rx_free_count++;
  1752. }
  1753. /* build RX-path queue */
  1754. for (index = 0; index < bna->ioceth.attr.num_rxp; index++) {
  1755. rxp_ptr = &rx_mod->rxp[index];
  1756. list_add_tail(&rxp_ptr->qe, &rx_mod->rxp_free_q);
  1757. rx_mod->rxp_free_count++;
  1758. }
  1759. /* build RXQ queue */
  1760. for (index = 0; index < (bna->ioceth.attr.num_rxp * 2); index++) {
  1761. rxq_ptr = &rx_mod->rxq[index];
  1762. list_add_tail(&rxq_ptr->qe, &rx_mod->rxq_free_q);
  1763. rx_mod->rxq_free_count++;
  1764. }
  1765. }
  1766. void
  1767. bna_rx_mod_uninit(struct bna_rx_mod *rx_mod)
  1768. {
  1769. rx_mod->bna = NULL;
  1770. }
  1771. void
  1772. bna_bfi_rx_enet_start_rsp(struct bna_rx *rx, struct bfi_msgq_mhdr *msghdr)
  1773. {
  1774. struct bfi_enet_rx_cfg_rsp *cfg_rsp = &rx->bfi_enet_cmd.cfg_rsp;
  1775. struct bna_rxp *rxp = NULL;
  1776. struct bna_rxq *q0 = NULL, *q1 = NULL;
  1777. int i;
  1778. bfa_msgq_rsp_copy(&rx->bna->msgq, (u8 *)cfg_rsp,
  1779. sizeof(struct bfi_enet_rx_cfg_rsp));
  1780. rx->hw_id = cfg_rsp->hw_id;
  1781. for (i = 0, rxp = list_first_entry(&rx->rxp_q, struct bna_rxp, qe);
  1782. i < rx->num_paths; i++, rxp = list_next_entry(rxp, qe)) {
  1783. GET_RXQS(rxp, q0, q1);
  1784. /* Setup doorbells */
  1785. rxp->cq.ccb->i_dbell->doorbell_addr =
  1786. rx->bna->pcidev.pci_bar_kva
  1787. + ntohl(cfg_rsp->q_handles[i].i_dbell);
  1788. rxp->hw_id = cfg_rsp->q_handles[i].hw_cqid;
  1789. q0->rcb->q_dbell =
  1790. rx->bna->pcidev.pci_bar_kva
  1791. + ntohl(cfg_rsp->q_handles[i].ql_dbell);
  1792. q0->hw_id = cfg_rsp->q_handles[i].hw_lqid;
  1793. if (q1) {
  1794. q1->rcb->q_dbell =
  1795. rx->bna->pcidev.pci_bar_kva
  1796. + ntohl(cfg_rsp->q_handles[i].qs_dbell);
  1797. q1->hw_id = cfg_rsp->q_handles[i].hw_sqid;
  1798. }
  1799. /* Initialize producer/consumer indexes */
  1800. (*rxp->cq.ccb->hw_producer_index) = 0;
  1801. rxp->cq.ccb->producer_index = 0;
  1802. q0->rcb->producer_index = q0->rcb->consumer_index = 0;
  1803. if (q1)
  1804. q1->rcb->producer_index = q1->rcb->consumer_index = 0;
  1805. }
  1806. bfa_fsm_send_event(rx, RX_E_STARTED);
  1807. }
  1808. void
  1809. bna_bfi_rx_enet_stop_rsp(struct bna_rx *rx, struct bfi_msgq_mhdr *msghdr)
  1810. {
  1811. bfa_fsm_send_event(rx, RX_E_STOPPED);
  1812. }
  1813. void
  1814. bna_rx_res_req(struct bna_rx_config *q_cfg, struct bna_res_info *res_info)
  1815. {
  1816. u32 cq_size, hq_size, dq_size;
  1817. u32 cpage_count, hpage_count, dpage_count;
  1818. struct bna_mem_info *mem_info;
  1819. u32 cq_depth;
  1820. u32 hq_depth;
  1821. u32 dq_depth;
  1822. dq_depth = q_cfg->q0_depth;
  1823. hq_depth = ((q_cfg->rxp_type == BNA_RXP_SINGLE) ? 0 : q_cfg->q1_depth);
  1824. cq_depth = roundup_pow_of_two(dq_depth + hq_depth);
  1825. cq_size = cq_depth * BFI_CQ_WI_SIZE;
  1826. cq_size = ALIGN(cq_size, PAGE_SIZE);
  1827. cpage_count = SIZE_TO_PAGES(cq_size);
  1828. dq_depth = roundup_pow_of_two(dq_depth);
  1829. dq_size = dq_depth * BFI_RXQ_WI_SIZE;
  1830. dq_size = ALIGN(dq_size, PAGE_SIZE);
  1831. dpage_count = SIZE_TO_PAGES(dq_size);
  1832. if (BNA_RXP_SINGLE != q_cfg->rxp_type) {
  1833. hq_depth = roundup_pow_of_two(hq_depth);
  1834. hq_size = hq_depth * BFI_RXQ_WI_SIZE;
  1835. hq_size = ALIGN(hq_size, PAGE_SIZE);
  1836. hpage_count = SIZE_TO_PAGES(hq_size);
  1837. } else
  1838. hpage_count = 0;
  1839. res_info[BNA_RX_RES_MEM_T_CCB].res_type = BNA_RES_T_MEM;
  1840. mem_info = &res_info[BNA_RX_RES_MEM_T_CCB].res_u.mem_info;
  1841. mem_info->mem_type = BNA_MEM_T_KVA;
  1842. mem_info->len = sizeof(struct bna_ccb);
  1843. mem_info->num = q_cfg->num_paths;
  1844. res_info[BNA_RX_RES_MEM_T_RCB].res_type = BNA_RES_T_MEM;
  1845. mem_info = &res_info[BNA_RX_RES_MEM_T_RCB].res_u.mem_info;
  1846. mem_info->mem_type = BNA_MEM_T_KVA;
  1847. mem_info->len = sizeof(struct bna_rcb);
  1848. mem_info->num = BNA_GET_RXQS(q_cfg);
  1849. res_info[BNA_RX_RES_MEM_T_CQPT].res_type = BNA_RES_T_MEM;
  1850. mem_info = &res_info[BNA_RX_RES_MEM_T_CQPT].res_u.mem_info;
  1851. mem_info->mem_type = BNA_MEM_T_DMA;
  1852. mem_info->len = cpage_count * sizeof(struct bna_dma_addr);
  1853. mem_info->num = q_cfg->num_paths;
  1854. res_info[BNA_RX_RES_MEM_T_CSWQPT].res_type = BNA_RES_T_MEM;
  1855. mem_info = &res_info[BNA_RX_RES_MEM_T_CSWQPT].res_u.mem_info;
  1856. mem_info->mem_type = BNA_MEM_T_KVA;
  1857. mem_info->len = cpage_count * sizeof(void *);
  1858. mem_info->num = q_cfg->num_paths;
  1859. res_info[BNA_RX_RES_MEM_T_CQPT_PAGE].res_type = BNA_RES_T_MEM;
  1860. mem_info = &res_info[BNA_RX_RES_MEM_T_CQPT_PAGE].res_u.mem_info;
  1861. mem_info->mem_type = BNA_MEM_T_DMA;
  1862. mem_info->len = PAGE_SIZE * cpage_count;
  1863. mem_info->num = q_cfg->num_paths;
  1864. res_info[BNA_RX_RES_MEM_T_DQPT].res_type = BNA_RES_T_MEM;
  1865. mem_info = &res_info[BNA_RX_RES_MEM_T_DQPT].res_u.mem_info;
  1866. mem_info->mem_type = BNA_MEM_T_DMA;
  1867. mem_info->len = dpage_count * sizeof(struct bna_dma_addr);
  1868. mem_info->num = q_cfg->num_paths;
  1869. res_info[BNA_RX_RES_MEM_T_DSWQPT].res_type = BNA_RES_T_MEM;
  1870. mem_info = &res_info[BNA_RX_RES_MEM_T_DSWQPT].res_u.mem_info;
  1871. mem_info->mem_type = BNA_MEM_T_KVA;
  1872. mem_info->len = dpage_count * sizeof(void *);
  1873. mem_info->num = q_cfg->num_paths;
  1874. res_info[BNA_RX_RES_MEM_T_DPAGE].res_type = BNA_RES_T_MEM;
  1875. mem_info = &res_info[BNA_RX_RES_MEM_T_DPAGE].res_u.mem_info;
  1876. mem_info->mem_type = BNA_MEM_T_DMA;
  1877. mem_info->len = PAGE_SIZE * dpage_count;
  1878. mem_info->num = q_cfg->num_paths;
  1879. res_info[BNA_RX_RES_MEM_T_HQPT].res_type = BNA_RES_T_MEM;
  1880. mem_info = &res_info[BNA_RX_RES_MEM_T_HQPT].res_u.mem_info;
  1881. mem_info->mem_type = BNA_MEM_T_DMA;
  1882. mem_info->len = hpage_count * sizeof(struct bna_dma_addr);
  1883. mem_info->num = (hpage_count ? q_cfg->num_paths : 0);
  1884. res_info[BNA_RX_RES_MEM_T_HSWQPT].res_type = BNA_RES_T_MEM;
  1885. mem_info = &res_info[BNA_RX_RES_MEM_T_HSWQPT].res_u.mem_info;
  1886. mem_info->mem_type = BNA_MEM_T_KVA;
  1887. mem_info->len = hpage_count * sizeof(void *);
  1888. mem_info->num = (hpage_count ? q_cfg->num_paths : 0);
  1889. res_info[BNA_RX_RES_MEM_T_HPAGE].res_type = BNA_RES_T_MEM;
  1890. mem_info = &res_info[BNA_RX_RES_MEM_T_HPAGE].res_u.mem_info;
  1891. mem_info->mem_type = BNA_MEM_T_DMA;
  1892. mem_info->len = PAGE_SIZE * hpage_count;
  1893. mem_info->num = (hpage_count ? q_cfg->num_paths : 0);
  1894. res_info[BNA_RX_RES_MEM_T_IBIDX].res_type = BNA_RES_T_MEM;
  1895. mem_info = &res_info[BNA_RX_RES_MEM_T_IBIDX].res_u.mem_info;
  1896. mem_info->mem_type = BNA_MEM_T_DMA;
  1897. mem_info->len = BFI_IBIDX_SIZE;
  1898. mem_info->num = q_cfg->num_paths;
  1899. res_info[BNA_RX_RES_MEM_T_RIT].res_type = BNA_RES_T_MEM;
  1900. mem_info = &res_info[BNA_RX_RES_MEM_T_RIT].res_u.mem_info;
  1901. mem_info->mem_type = BNA_MEM_T_KVA;
  1902. mem_info->len = BFI_ENET_RSS_RIT_MAX;
  1903. mem_info->num = 1;
  1904. res_info[BNA_RX_RES_T_INTR].res_type = BNA_RES_T_INTR;
  1905. res_info[BNA_RX_RES_T_INTR].res_u.intr_info.intr_type = BNA_INTR_T_MSIX;
  1906. res_info[BNA_RX_RES_T_INTR].res_u.intr_info.num = q_cfg->num_paths;
  1907. }
  1908. struct bna_rx *
  1909. bna_rx_create(struct bna *bna, struct bnad *bnad,
  1910. struct bna_rx_config *rx_cfg,
  1911. const struct bna_rx_event_cbfn *rx_cbfn,
  1912. struct bna_res_info *res_info,
  1913. void *priv)
  1914. {
  1915. struct bna_rx_mod *rx_mod = &bna->rx_mod;
  1916. struct bna_rx *rx;
  1917. struct bna_rxp *rxp;
  1918. struct bna_rxq *q0;
  1919. struct bna_rxq *q1;
  1920. struct bna_intr_info *intr_info;
  1921. struct bna_mem_descr *hqunmap_mem;
  1922. struct bna_mem_descr *dqunmap_mem;
  1923. struct bna_mem_descr *ccb_mem;
  1924. struct bna_mem_descr *rcb_mem;
  1925. struct bna_mem_descr *cqpt_mem;
  1926. struct bna_mem_descr *cswqpt_mem;
  1927. struct bna_mem_descr *cpage_mem;
  1928. struct bna_mem_descr *hqpt_mem;
  1929. struct bna_mem_descr *dqpt_mem;
  1930. struct bna_mem_descr *hsqpt_mem;
  1931. struct bna_mem_descr *dsqpt_mem;
  1932. struct bna_mem_descr *hpage_mem;
  1933. struct bna_mem_descr *dpage_mem;
  1934. u32 dpage_count, hpage_count;
  1935. u32 hq_idx, dq_idx, rcb_idx;
  1936. u32 cq_depth, i;
  1937. u32 page_count;
  1938. if (!bna_rx_res_check(rx_mod, rx_cfg))
  1939. return NULL;
  1940. intr_info = &res_info[BNA_RX_RES_T_INTR].res_u.intr_info;
  1941. ccb_mem = &res_info[BNA_RX_RES_MEM_T_CCB].res_u.mem_info.mdl[0];
  1942. rcb_mem = &res_info[BNA_RX_RES_MEM_T_RCB].res_u.mem_info.mdl[0];
  1943. dqunmap_mem = &res_info[BNA_RX_RES_MEM_T_UNMAPDQ].res_u.mem_info.mdl[0];
  1944. hqunmap_mem = &res_info[BNA_RX_RES_MEM_T_UNMAPHQ].res_u.mem_info.mdl[0];
  1945. cqpt_mem = &res_info[BNA_RX_RES_MEM_T_CQPT].res_u.mem_info.mdl[0];
  1946. cswqpt_mem = &res_info[BNA_RX_RES_MEM_T_CSWQPT].res_u.mem_info.mdl[0];
  1947. cpage_mem = &res_info[BNA_RX_RES_MEM_T_CQPT_PAGE].res_u.mem_info.mdl[0];
  1948. hqpt_mem = &res_info[BNA_RX_RES_MEM_T_HQPT].res_u.mem_info.mdl[0];
  1949. dqpt_mem = &res_info[BNA_RX_RES_MEM_T_DQPT].res_u.mem_info.mdl[0];
  1950. hsqpt_mem = &res_info[BNA_RX_RES_MEM_T_HSWQPT].res_u.mem_info.mdl[0];
  1951. dsqpt_mem = &res_info[BNA_RX_RES_MEM_T_DSWQPT].res_u.mem_info.mdl[0];
  1952. hpage_mem = &res_info[BNA_RX_RES_MEM_T_HPAGE].res_u.mem_info.mdl[0];
  1953. dpage_mem = &res_info[BNA_RX_RES_MEM_T_DPAGE].res_u.mem_info.mdl[0];
  1954. page_count = res_info[BNA_RX_RES_MEM_T_CQPT_PAGE].res_u.mem_info.len /
  1955. PAGE_SIZE;
  1956. dpage_count = res_info[BNA_RX_RES_MEM_T_DPAGE].res_u.mem_info.len /
  1957. PAGE_SIZE;
  1958. hpage_count = res_info[BNA_RX_RES_MEM_T_HPAGE].res_u.mem_info.len /
  1959. PAGE_SIZE;
  1960. rx = bna_rx_get(rx_mod, rx_cfg->rx_type);
  1961. rx->bna = bna;
  1962. rx->rx_flags = 0;
  1963. INIT_LIST_HEAD(&rx->rxp_q);
  1964. rx->stop_cbfn = NULL;
  1965. rx->stop_cbarg = NULL;
  1966. rx->priv = priv;
  1967. rx->rcb_setup_cbfn = rx_cbfn->rcb_setup_cbfn;
  1968. rx->rcb_destroy_cbfn = rx_cbfn->rcb_destroy_cbfn;
  1969. rx->ccb_setup_cbfn = rx_cbfn->ccb_setup_cbfn;
  1970. rx->ccb_destroy_cbfn = rx_cbfn->ccb_destroy_cbfn;
  1971. rx->rx_stall_cbfn = rx_cbfn->rx_stall_cbfn;
  1972. /* Following callbacks are mandatory */
  1973. rx->rx_cleanup_cbfn = rx_cbfn->rx_cleanup_cbfn;
  1974. rx->rx_post_cbfn = rx_cbfn->rx_post_cbfn;
  1975. if (rx->bna->rx_mod.flags & BNA_RX_MOD_F_ENET_STARTED) {
  1976. switch (rx->type) {
  1977. case BNA_RX_T_REGULAR:
  1978. if (!(rx->bna->rx_mod.flags &
  1979. BNA_RX_MOD_F_ENET_LOOPBACK))
  1980. rx->rx_flags |= BNA_RX_F_ENET_STARTED;
  1981. break;
  1982. case BNA_RX_T_LOOPBACK:
  1983. if (rx->bna->rx_mod.flags & BNA_RX_MOD_F_ENET_LOOPBACK)
  1984. rx->rx_flags |= BNA_RX_F_ENET_STARTED;
  1985. break;
  1986. }
  1987. }
  1988. rx->num_paths = rx_cfg->num_paths;
  1989. for (i = 0, hq_idx = 0, dq_idx = 0, rcb_idx = 0;
  1990. i < rx->num_paths; i++) {
  1991. rxp = bna_rxp_get(rx_mod);
  1992. list_add_tail(&rxp->qe, &rx->rxp_q);
  1993. rxp->type = rx_cfg->rxp_type;
  1994. rxp->rx = rx;
  1995. rxp->cq.rx = rx;
  1996. q0 = bna_rxq_get(rx_mod);
  1997. if (BNA_RXP_SINGLE == rx_cfg->rxp_type)
  1998. q1 = NULL;
  1999. else
  2000. q1 = bna_rxq_get(rx_mod);
  2001. if (1 == intr_info->num)
  2002. rxp->vector = intr_info->idl[0].vector;
  2003. else
  2004. rxp->vector = intr_info->idl[i].vector;
  2005. /* Setup IB */
  2006. rxp->cq.ib.ib_seg_host_addr.lsb =
  2007. res_info[BNA_RX_RES_MEM_T_IBIDX].res_u.mem_info.mdl[i].dma.lsb;
  2008. rxp->cq.ib.ib_seg_host_addr.msb =
  2009. res_info[BNA_RX_RES_MEM_T_IBIDX].res_u.mem_info.mdl[i].dma.msb;
  2010. rxp->cq.ib.ib_seg_host_addr_kva =
  2011. res_info[BNA_RX_RES_MEM_T_IBIDX].res_u.mem_info.mdl[i].kva;
  2012. rxp->cq.ib.intr_type = intr_info->intr_type;
  2013. if (intr_info->intr_type == BNA_INTR_T_MSIX)
  2014. rxp->cq.ib.intr_vector = rxp->vector;
  2015. else
  2016. rxp->cq.ib.intr_vector = BIT(rxp->vector);
  2017. rxp->cq.ib.coalescing_timeo = rx_cfg->coalescing_timeo;
  2018. rxp->cq.ib.interpkt_count = BFI_RX_INTERPKT_COUNT;
  2019. rxp->cq.ib.interpkt_timeo = BFI_RX_INTERPKT_TIMEO;
  2020. bna_rxp_add_rxqs(rxp, q0, q1);
  2021. /* Setup large Q */
  2022. q0->rx = rx;
  2023. q0->rxp = rxp;
  2024. q0->rcb = (struct bna_rcb *) rcb_mem[rcb_idx].kva;
  2025. q0->rcb->unmap_q = (void *)dqunmap_mem[dq_idx].kva;
  2026. rcb_idx++; dq_idx++;
  2027. q0->rcb->q_depth = rx_cfg->q0_depth;
  2028. q0->q_depth = rx_cfg->q0_depth;
  2029. q0->multi_buffer = rx_cfg->q0_multi_buf;
  2030. q0->buffer_size = rx_cfg->q0_buf_size;
  2031. q0->num_vecs = rx_cfg->q0_num_vecs;
  2032. q0->rcb->rxq = q0;
  2033. q0->rcb->bnad = bna->bnad;
  2034. q0->rcb->id = 0;
  2035. q0->rx_packets = q0->rx_bytes = 0;
  2036. q0->rx_packets_with_error = q0->rxbuf_alloc_failed = 0;
  2037. q0->rxbuf_map_failed = 0;
  2038. bna_rxq_qpt_setup(q0, rxp, dpage_count, PAGE_SIZE,
  2039. &dqpt_mem[i], &dsqpt_mem[i], &dpage_mem[i]);
  2040. if (rx->rcb_setup_cbfn)
  2041. rx->rcb_setup_cbfn(bnad, q0->rcb);
  2042. /* Setup small Q */
  2043. if (q1) {
  2044. q1->rx = rx;
  2045. q1->rxp = rxp;
  2046. q1->rcb = (struct bna_rcb *) rcb_mem[rcb_idx].kva;
  2047. q1->rcb->unmap_q = (void *)hqunmap_mem[hq_idx].kva;
  2048. rcb_idx++; hq_idx++;
  2049. q1->rcb->q_depth = rx_cfg->q1_depth;
  2050. q1->q_depth = rx_cfg->q1_depth;
  2051. q1->multi_buffer = BNA_STATUS_T_DISABLED;
  2052. q1->num_vecs = 1;
  2053. q1->rcb->rxq = q1;
  2054. q1->rcb->bnad = bna->bnad;
  2055. q1->rcb->id = 1;
  2056. q1->buffer_size = (rx_cfg->rxp_type == BNA_RXP_HDS) ?
  2057. rx_cfg->hds_config.forced_offset
  2058. : rx_cfg->q1_buf_size;
  2059. q1->rx_packets = q1->rx_bytes = 0;
  2060. q1->rx_packets_with_error = q1->rxbuf_alloc_failed = 0;
  2061. q1->rxbuf_map_failed = 0;
  2062. bna_rxq_qpt_setup(q1, rxp, hpage_count, PAGE_SIZE,
  2063. &hqpt_mem[i], &hsqpt_mem[i],
  2064. &hpage_mem[i]);
  2065. if (rx->rcb_setup_cbfn)
  2066. rx->rcb_setup_cbfn(bnad, q1->rcb);
  2067. }
  2068. /* Setup CQ */
  2069. rxp->cq.ccb = (struct bna_ccb *) ccb_mem[i].kva;
  2070. cq_depth = rx_cfg->q0_depth +
  2071. ((rx_cfg->rxp_type == BNA_RXP_SINGLE) ?
  2072. 0 : rx_cfg->q1_depth);
  2073. /* if multi-buffer is enabled sum of q0_depth
  2074. * and q1_depth need not be a power of 2
  2075. */
  2076. cq_depth = roundup_pow_of_two(cq_depth);
  2077. rxp->cq.ccb->q_depth = cq_depth;
  2078. rxp->cq.ccb->cq = &rxp->cq;
  2079. rxp->cq.ccb->rcb[0] = q0->rcb;
  2080. q0->rcb->ccb = rxp->cq.ccb;
  2081. if (q1) {
  2082. rxp->cq.ccb->rcb[1] = q1->rcb;
  2083. q1->rcb->ccb = rxp->cq.ccb;
  2084. }
  2085. rxp->cq.ccb->hw_producer_index =
  2086. (u32 *)rxp->cq.ib.ib_seg_host_addr_kva;
  2087. rxp->cq.ccb->i_dbell = &rxp->cq.ib.door_bell;
  2088. rxp->cq.ccb->intr_type = rxp->cq.ib.intr_type;
  2089. rxp->cq.ccb->intr_vector = rxp->cq.ib.intr_vector;
  2090. rxp->cq.ccb->rx_coalescing_timeo =
  2091. rxp->cq.ib.coalescing_timeo;
  2092. rxp->cq.ccb->pkt_rate.small_pkt_cnt = 0;
  2093. rxp->cq.ccb->pkt_rate.large_pkt_cnt = 0;
  2094. rxp->cq.ccb->bnad = bna->bnad;
  2095. rxp->cq.ccb->id = i;
  2096. bna_rxp_cqpt_setup(rxp, page_count, PAGE_SIZE,
  2097. &cqpt_mem[i], &cswqpt_mem[i], &cpage_mem[i]);
  2098. if (rx->ccb_setup_cbfn)
  2099. rx->ccb_setup_cbfn(bnad, rxp->cq.ccb);
  2100. }
  2101. rx->hds_cfg = rx_cfg->hds_config;
  2102. bna_rxf_init(&rx->rxf, rx, rx_cfg, res_info);
  2103. bfa_fsm_set_state(rx, bna_rx_sm_stopped);
  2104. rx_mod->rid_mask |= BIT(rx->rid);
  2105. return rx;
  2106. }
  2107. void
  2108. bna_rx_destroy(struct bna_rx *rx)
  2109. {
  2110. struct bna_rx_mod *rx_mod = &rx->bna->rx_mod;
  2111. struct bna_rxq *q0 = NULL;
  2112. struct bna_rxq *q1 = NULL;
  2113. struct bna_rxp *rxp;
  2114. struct list_head *qe;
  2115. bna_rxf_uninit(&rx->rxf);
  2116. while (!list_empty(&rx->rxp_q)) {
  2117. rxp = list_first_entry(&rx->rxp_q, struct bna_rxp, qe);
  2118. list_del(&rxp->qe);
  2119. GET_RXQS(rxp, q0, q1);
  2120. if (rx->rcb_destroy_cbfn)
  2121. rx->rcb_destroy_cbfn(rx->bna->bnad, q0->rcb);
  2122. q0->rcb = NULL;
  2123. q0->rxp = NULL;
  2124. q0->rx = NULL;
  2125. bna_rxq_put(rx_mod, q0);
  2126. if (q1) {
  2127. if (rx->rcb_destroy_cbfn)
  2128. rx->rcb_destroy_cbfn(rx->bna->bnad, q1->rcb);
  2129. q1->rcb = NULL;
  2130. q1->rxp = NULL;
  2131. q1->rx = NULL;
  2132. bna_rxq_put(rx_mod, q1);
  2133. }
  2134. rxp->rxq.slr.large = NULL;
  2135. rxp->rxq.slr.small = NULL;
  2136. if (rx->ccb_destroy_cbfn)
  2137. rx->ccb_destroy_cbfn(rx->bna->bnad, rxp->cq.ccb);
  2138. rxp->cq.ccb = NULL;
  2139. rxp->rx = NULL;
  2140. bna_rxp_put(rx_mod, rxp);
  2141. }
  2142. list_for_each(qe, &rx_mod->rx_active_q)
  2143. if (qe == &rx->qe) {
  2144. list_del(&rx->qe);
  2145. break;
  2146. }
  2147. rx_mod->rid_mask &= ~BIT(rx->rid);
  2148. rx->bna = NULL;
  2149. rx->priv = NULL;
  2150. bna_rx_put(rx_mod, rx);
  2151. }
  2152. void
  2153. bna_rx_enable(struct bna_rx *rx)
  2154. {
  2155. if (rx->fsm != (bfa_sm_t)bna_rx_sm_stopped)
  2156. return;
  2157. rx->rx_flags |= BNA_RX_F_ENABLED;
  2158. if (rx->rx_flags & BNA_RX_F_ENET_STARTED)
  2159. bfa_fsm_send_event(rx, RX_E_START);
  2160. }
  2161. void
  2162. bna_rx_disable(struct bna_rx *rx, enum bna_cleanup_type type,
  2163. void (*cbfn)(void *, struct bna_rx *))
  2164. {
  2165. if (type == BNA_SOFT_CLEANUP) {
  2166. /* h/w should not be accessed. Treat we're stopped */
  2167. (*cbfn)(rx->bna->bnad, rx);
  2168. } else {
  2169. rx->stop_cbfn = cbfn;
  2170. rx->stop_cbarg = rx->bna->bnad;
  2171. rx->rx_flags &= ~BNA_RX_F_ENABLED;
  2172. bfa_fsm_send_event(rx, RX_E_STOP);
  2173. }
  2174. }
  2175. void
  2176. bna_rx_cleanup_complete(struct bna_rx *rx)
  2177. {
  2178. bfa_fsm_send_event(rx, RX_E_CLEANUP_DONE);
  2179. }
  2180. void
  2181. bna_rx_vlan_strip_enable(struct bna_rx *rx)
  2182. {
  2183. struct bna_rxf *rxf = &rx->rxf;
  2184. if (rxf->vlan_strip_status == BNA_STATUS_T_DISABLED) {
  2185. rxf->vlan_strip_status = BNA_STATUS_T_ENABLED;
  2186. rxf->vlan_strip_pending = true;
  2187. bfa_fsm_send_event(rxf, RXF_E_CONFIG);
  2188. }
  2189. }
  2190. void
  2191. bna_rx_vlan_strip_disable(struct bna_rx *rx)
  2192. {
  2193. struct bna_rxf *rxf = &rx->rxf;
  2194. if (rxf->vlan_strip_status != BNA_STATUS_T_DISABLED) {
  2195. rxf->vlan_strip_status = BNA_STATUS_T_DISABLED;
  2196. rxf->vlan_strip_pending = true;
  2197. bfa_fsm_send_event(rxf, RXF_E_CONFIG);
  2198. }
  2199. }
  2200. enum bna_cb_status
  2201. bna_rx_mode_set(struct bna_rx *rx, enum bna_rxmode new_mode,
  2202. enum bna_rxmode bitmask)
  2203. {
  2204. struct bna_rxf *rxf = &rx->rxf;
  2205. int need_hw_config = 0;
  2206. /* Error checks */
  2207. if (is_promisc_enable(new_mode, bitmask)) {
  2208. /* If promisc mode is already enabled elsewhere in the system */
  2209. if ((rx->bna->promisc_rid != BFI_INVALID_RID) &&
  2210. (rx->bna->promisc_rid != rxf->rx->rid))
  2211. goto err_return;
  2212. /* If default mode is already enabled in the system */
  2213. if (rx->bna->default_mode_rid != BFI_INVALID_RID)
  2214. goto err_return;
  2215. /* Trying to enable promiscuous and default mode together */
  2216. if (is_default_enable(new_mode, bitmask))
  2217. goto err_return;
  2218. }
  2219. if (is_default_enable(new_mode, bitmask)) {
  2220. /* If default mode is already enabled elsewhere in the system */
  2221. if ((rx->bna->default_mode_rid != BFI_INVALID_RID) &&
  2222. (rx->bna->default_mode_rid != rxf->rx->rid)) {
  2223. goto err_return;
  2224. }
  2225. /* If promiscuous mode is already enabled in the system */
  2226. if (rx->bna->promisc_rid != BFI_INVALID_RID)
  2227. goto err_return;
  2228. }
  2229. /* Process the commands */
  2230. if (is_promisc_enable(new_mode, bitmask)) {
  2231. if (bna_rxf_promisc_enable(rxf))
  2232. need_hw_config = 1;
  2233. } else if (is_promisc_disable(new_mode, bitmask)) {
  2234. if (bna_rxf_promisc_disable(rxf))
  2235. need_hw_config = 1;
  2236. }
  2237. if (is_allmulti_enable(new_mode, bitmask)) {
  2238. if (bna_rxf_allmulti_enable(rxf))
  2239. need_hw_config = 1;
  2240. } else if (is_allmulti_disable(new_mode, bitmask)) {
  2241. if (bna_rxf_allmulti_disable(rxf))
  2242. need_hw_config = 1;
  2243. }
  2244. /* Trigger h/w if needed */
  2245. if (need_hw_config) {
  2246. rxf->cam_fltr_cbfn = NULL;
  2247. rxf->cam_fltr_cbarg = rx->bna->bnad;
  2248. bfa_fsm_send_event(rxf, RXF_E_CONFIG);
  2249. }
  2250. return BNA_CB_SUCCESS;
  2251. err_return:
  2252. return BNA_CB_FAIL;
  2253. }
  2254. void
  2255. bna_rx_vlanfilter_enable(struct bna_rx *rx)
  2256. {
  2257. struct bna_rxf *rxf = &rx->rxf;
  2258. if (rxf->vlan_filter_status == BNA_STATUS_T_DISABLED) {
  2259. rxf->vlan_filter_status = BNA_STATUS_T_ENABLED;
  2260. rxf->vlan_pending_bitmask = (u8)BFI_VLAN_BMASK_ALL;
  2261. bfa_fsm_send_event(rxf, RXF_E_CONFIG);
  2262. }
  2263. }
  2264. void
  2265. bna_rx_coalescing_timeo_set(struct bna_rx *rx, int coalescing_timeo)
  2266. {
  2267. struct bna_rxp *rxp;
  2268. list_for_each_entry(rxp, &rx->rxp_q, qe) {
  2269. rxp->cq.ccb->rx_coalescing_timeo = coalescing_timeo;
  2270. bna_ib_coalescing_timeo_set(&rxp->cq.ib, coalescing_timeo);
  2271. }
  2272. }
  2273. void
  2274. bna_rx_dim_reconfig(struct bna *bna, const u32 vector[][BNA_BIAS_T_MAX])
  2275. {
  2276. int i, j;
  2277. for (i = 0; i < BNA_LOAD_T_MAX; i++)
  2278. for (j = 0; j < BNA_BIAS_T_MAX; j++)
  2279. bna->rx_mod.dim_vector[i][j] = vector[i][j];
  2280. }
  2281. void
  2282. bna_rx_dim_update(struct bna_ccb *ccb)
  2283. {
  2284. struct bna *bna = ccb->cq->rx->bna;
  2285. u32 load, bias;
  2286. u32 pkt_rt, small_rt, large_rt;
  2287. u8 coalescing_timeo;
  2288. if ((ccb->pkt_rate.small_pkt_cnt == 0) &&
  2289. (ccb->pkt_rate.large_pkt_cnt == 0))
  2290. return;
  2291. /* Arrive at preconfigured coalescing timeo value based on pkt rate */
  2292. small_rt = ccb->pkt_rate.small_pkt_cnt;
  2293. large_rt = ccb->pkt_rate.large_pkt_cnt;
  2294. pkt_rt = small_rt + large_rt;
  2295. if (pkt_rt < BNA_PKT_RATE_10K)
  2296. load = BNA_LOAD_T_LOW_4;
  2297. else if (pkt_rt < BNA_PKT_RATE_20K)
  2298. load = BNA_LOAD_T_LOW_3;
  2299. else if (pkt_rt < BNA_PKT_RATE_30K)
  2300. load = BNA_LOAD_T_LOW_2;
  2301. else if (pkt_rt < BNA_PKT_RATE_40K)
  2302. load = BNA_LOAD_T_LOW_1;
  2303. else if (pkt_rt < BNA_PKT_RATE_50K)
  2304. load = BNA_LOAD_T_HIGH_1;
  2305. else if (pkt_rt < BNA_PKT_RATE_60K)
  2306. load = BNA_LOAD_T_HIGH_2;
  2307. else if (pkt_rt < BNA_PKT_RATE_80K)
  2308. load = BNA_LOAD_T_HIGH_3;
  2309. else
  2310. load = BNA_LOAD_T_HIGH_4;
  2311. if (small_rt > (large_rt << 1))
  2312. bias = 0;
  2313. else
  2314. bias = 1;
  2315. ccb->pkt_rate.small_pkt_cnt = 0;
  2316. ccb->pkt_rate.large_pkt_cnt = 0;
  2317. coalescing_timeo = bna->rx_mod.dim_vector[load][bias];
  2318. ccb->rx_coalescing_timeo = coalescing_timeo;
  2319. /* Set it to IB */
  2320. bna_ib_coalescing_timeo_set(&ccb->cq->ib, coalescing_timeo);
  2321. }
  2322. const u32 bna_napi_dim_vector[BNA_LOAD_T_MAX][BNA_BIAS_T_MAX] = {
  2323. {12, 12},
  2324. {6, 10},
  2325. {5, 10},
  2326. {4, 8},
  2327. {3, 6},
  2328. {3, 6},
  2329. {2, 4},
  2330. {1, 2},
  2331. };
  2332. /* TX */
  2333. #define call_tx_stop_cbfn(tx) \
  2334. do { \
  2335. if ((tx)->stop_cbfn) { \
  2336. void (*cbfn)(void *, struct bna_tx *); \
  2337. void *cbarg; \
  2338. cbfn = (tx)->stop_cbfn; \
  2339. cbarg = (tx)->stop_cbarg; \
  2340. (tx)->stop_cbfn = NULL; \
  2341. (tx)->stop_cbarg = NULL; \
  2342. cbfn(cbarg, (tx)); \
  2343. } \
  2344. } while (0)
  2345. static void bna_tx_mod_cb_tx_stopped(void *tx_mod, struct bna_tx *tx);
  2346. static void bna_bfi_tx_enet_start(struct bna_tx *tx);
  2347. static void bna_tx_enet_stop(struct bna_tx *tx);
  2348. enum bna_tx_event {
  2349. TX_E_START = 1,
  2350. TX_E_STOP = 2,
  2351. TX_E_FAIL = 3,
  2352. TX_E_STARTED = 4,
  2353. TX_E_STOPPED = 5,
  2354. TX_E_CLEANUP_DONE = 7,
  2355. TX_E_BW_UPDATE = 8,
  2356. };
  2357. bfa_fsm_state_decl(bna_tx, stopped, struct bna_tx, enum bna_tx_event);
  2358. bfa_fsm_state_decl(bna_tx, start_wait, struct bna_tx, enum bna_tx_event);
  2359. bfa_fsm_state_decl(bna_tx, started, struct bna_tx, enum bna_tx_event);
  2360. bfa_fsm_state_decl(bna_tx, stop_wait, struct bna_tx, enum bna_tx_event);
  2361. bfa_fsm_state_decl(bna_tx, cleanup_wait, struct bna_tx,
  2362. enum bna_tx_event);
  2363. bfa_fsm_state_decl(bna_tx, prio_stop_wait, struct bna_tx,
  2364. enum bna_tx_event);
  2365. bfa_fsm_state_decl(bna_tx, prio_cleanup_wait, struct bna_tx,
  2366. enum bna_tx_event);
  2367. bfa_fsm_state_decl(bna_tx, failed, struct bna_tx, enum bna_tx_event);
  2368. bfa_fsm_state_decl(bna_tx, quiesce_wait, struct bna_tx,
  2369. enum bna_tx_event);
  2370. static void
  2371. bna_tx_sm_stopped_entry(struct bna_tx *tx)
  2372. {
  2373. call_tx_stop_cbfn(tx);
  2374. }
  2375. static void
  2376. bna_tx_sm_stopped(struct bna_tx *tx, enum bna_tx_event event)
  2377. {
  2378. switch (event) {
  2379. case TX_E_START:
  2380. bfa_fsm_set_state(tx, bna_tx_sm_start_wait);
  2381. break;
  2382. case TX_E_STOP:
  2383. call_tx_stop_cbfn(tx);
  2384. break;
  2385. case TX_E_FAIL:
  2386. /* No-op */
  2387. break;
  2388. case TX_E_BW_UPDATE:
  2389. /* No-op */
  2390. break;
  2391. default:
  2392. bfa_sm_fault(event);
  2393. }
  2394. }
  2395. static void
  2396. bna_tx_sm_start_wait_entry(struct bna_tx *tx)
  2397. {
  2398. bna_bfi_tx_enet_start(tx);
  2399. }
  2400. static void
  2401. bna_tx_sm_start_wait(struct bna_tx *tx, enum bna_tx_event event)
  2402. {
  2403. switch (event) {
  2404. case TX_E_STOP:
  2405. tx->flags &= ~BNA_TX_F_BW_UPDATED;
  2406. bfa_fsm_set_state(tx, bna_tx_sm_stop_wait);
  2407. break;
  2408. case TX_E_FAIL:
  2409. tx->flags &= ~BNA_TX_F_BW_UPDATED;
  2410. bfa_fsm_set_state(tx, bna_tx_sm_stopped);
  2411. break;
  2412. case TX_E_STARTED:
  2413. if (tx->flags & BNA_TX_F_BW_UPDATED) {
  2414. tx->flags &= ~BNA_TX_F_BW_UPDATED;
  2415. bfa_fsm_set_state(tx, bna_tx_sm_prio_stop_wait);
  2416. } else
  2417. bfa_fsm_set_state(tx, bna_tx_sm_started);
  2418. break;
  2419. case TX_E_BW_UPDATE:
  2420. tx->flags |= BNA_TX_F_BW_UPDATED;
  2421. break;
  2422. default:
  2423. bfa_sm_fault(event);
  2424. }
  2425. }
  2426. static void
  2427. bna_tx_sm_started_entry(struct bna_tx *tx)
  2428. {
  2429. struct bna_txq *txq;
  2430. int is_regular = (tx->type == BNA_TX_T_REGULAR);
  2431. list_for_each_entry(txq, &tx->txq_q, qe) {
  2432. txq->tcb->priority = txq->priority;
  2433. /* Start IB */
  2434. bna_ib_start(tx->bna, &txq->ib, is_regular);
  2435. }
  2436. tx->tx_resume_cbfn(tx->bna->bnad, tx);
  2437. }
  2438. static void
  2439. bna_tx_sm_started(struct bna_tx *tx, enum bna_tx_event event)
  2440. {
  2441. switch (event) {
  2442. case TX_E_STOP:
  2443. bfa_fsm_set_state(tx, bna_tx_sm_stop_wait);
  2444. tx->tx_stall_cbfn(tx->bna->bnad, tx);
  2445. bna_tx_enet_stop(tx);
  2446. break;
  2447. case TX_E_FAIL:
  2448. bfa_fsm_set_state(tx, bna_tx_sm_failed);
  2449. tx->tx_stall_cbfn(tx->bna->bnad, tx);
  2450. tx->tx_cleanup_cbfn(tx->bna->bnad, tx);
  2451. break;
  2452. case TX_E_BW_UPDATE:
  2453. bfa_fsm_set_state(tx, bna_tx_sm_prio_stop_wait);
  2454. break;
  2455. default:
  2456. bfa_sm_fault(event);
  2457. }
  2458. }
  2459. static void
  2460. bna_tx_sm_stop_wait_entry(struct bna_tx *tx)
  2461. {
  2462. }
  2463. static void
  2464. bna_tx_sm_stop_wait(struct bna_tx *tx, enum bna_tx_event event)
  2465. {
  2466. switch (event) {
  2467. case TX_E_FAIL:
  2468. case TX_E_STOPPED:
  2469. bfa_fsm_set_state(tx, bna_tx_sm_cleanup_wait);
  2470. tx->tx_cleanup_cbfn(tx->bna->bnad, tx);
  2471. break;
  2472. case TX_E_STARTED:
  2473. /**
  2474. * We are here due to start_wait -> stop_wait transition on
  2475. * TX_E_STOP event
  2476. */
  2477. bna_tx_enet_stop(tx);
  2478. break;
  2479. case TX_E_BW_UPDATE:
  2480. /* No-op */
  2481. break;
  2482. default:
  2483. bfa_sm_fault(event);
  2484. }
  2485. }
  2486. static void
  2487. bna_tx_sm_cleanup_wait_entry(struct bna_tx *tx)
  2488. {
  2489. }
  2490. static void
  2491. bna_tx_sm_cleanup_wait(struct bna_tx *tx, enum bna_tx_event event)
  2492. {
  2493. switch (event) {
  2494. case TX_E_FAIL:
  2495. case TX_E_BW_UPDATE:
  2496. /* No-op */
  2497. break;
  2498. case TX_E_CLEANUP_DONE:
  2499. bfa_fsm_set_state(tx, bna_tx_sm_stopped);
  2500. break;
  2501. default:
  2502. bfa_sm_fault(event);
  2503. }
  2504. }
  2505. static void
  2506. bna_tx_sm_prio_stop_wait_entry(struct bna_tx *tx)
  2507. {
  2508. tx->tx_stall_cbfn(tx->bna->bnad, tx);
  2509. bna_tx_enet_stop(tx);
  2510. }
  2511. static void
  2512. bna_tx_sm_prio_stop_wait(struct bna_tx *tx, enum bna_tx_event event)
  2513. {
  2514. switch (event) {
  2515. case TX_E_STOP:
  2516. bfa_fsm_set_state(tx, bna_tx_sm_stop_wait);
  2517. break;
  2518. case TX_E_FAIL:
  2519. bfa_fsm_set_state(tx, bna_tx_sm_failed);
  2520. tx->tx_cleanup_cbfn(tx->bna->bnad, tx);
  2521. break;
  2522. case TX_E_STOPPED:
  2523. bfa_fsm_set_state(tx, bna_tx_sm_prio_cleanup_wait);
  2524. break;
  2525. case TX_E_BW_UPDATE:
  2526. /* No-op */
  2527. break;
  2528. default:
  2529. bfa_sm_fault(event);
  2530. }
  2531. }
  2532. static void
  2533. bna_tx_sm_prio_cleanup_wait_entry(struct bna_tx *tx)
  2534. {
  2535. tx->tx_cleanup_cbfn(tx->bna->bnad, tx);
  2536. }
  2537. static void
  2538. bna_tx_sm_prio_cleanup_wait(struct bna_tx *tx, enum bna_tx_event event)
  2539. {
  2540. switch (event) {
  2541. case TX_E_STOP:
  2542. bfa_fsm_set_state(tx, bna_tx_sm_cleanup_wait);
  2543. break;
  2544. case TX_E_FAIL:
  2545. bfa_fsm_set_state(tx, bna_tx_sm_failed);
  2546. break;
  2547. case TX_E_BW_UPDATE:
  2548. /* No-op */
  2549. break;
  2550. case TX_E_CLEANUP_DONE:
  2551. bfa_fsm_set_state(tx, bna_tx_sm_start_wait);
  2552. break;
  2553. default:
  2554. bfa_sm_fault(event);
  2555. }
  2556. }
  2557. static void
  2558. bna_tx_sm_failed_entry(struct bna_tx *tx)
  2559. {
  2560. }
  2561. static void
  2562. bna_tx_sm_failed(struct bna_tx *tx, enum bna_tx_event event)
  2563. {
  2564. switch (event) {
  2565. case TX_E_START:
  2566. bfa_fsm_set_state(tx, bna_tx_sm_quiesce_wait);
  2567. break;
  2568. case TX_E_STOP:
  2569. bfa_fsm_set_state(tx, bna_tx_sm_cleanup_wait);
  2570. break;
  2571. case TX_E_FAIL:
  2572. /* No-op */
  2573. break;
  2574. case TX_E_CLEANUP_DONE:
  2575. bfa_fsm_set_state(tx, bna_tx_sm_stopped);
  2576. break;
  2577. default:
  2578. bfa_sm_fault(event);
  2579. }
  2580. }
  2581. static void
  2582. bna_tx_sm_quiesce_wait_entry(struct bna_tx *tx)
  2583. {
  2584. }
  2585. static void
  2586. bna_tx_sm_quiesce_wait(struct bna_tx *tx, enum bna_tx_event event)
  2587. {
  2588. switch (event) {
  2589. case TX_E_STOP:
  2590. bfa_fsm_set_state(tx, bna_tx_sm_cleanup_wait);
  2591. break;
  2592. case TX_E_FAIL:
  2593. bfa_fsm_set_state(tx, bna_tx_sm_failed);
  2594. break;
  2595. case TX_E_CLEANUP_DONE:
  2596. bfa_fsm_set_state(tx, bna_tx_sm_start_wait);
  2597. break;
  2598. case TX_E_BW_UPDATE:
  2599. /* No-op */
  2600. break;
  2601. default:
  2602. bfa_sm_fault(event);
  2603. }
  2604. }
  2605. static void
  2606. bna_bfi_tx_enet_start(struct bna_tx *tx)
  2607. {
  2608. struct bfi_enet_tx_cfg_req *cfg_req = &tx->bfi_enet_cmd.cfg_req;
  2609. struct bna_txq *txq = NULL;
  2610. int i;
  2611. bfi_msgq_mhdr_set(cfg_req->mh, BFI_MC_ENET,
  2612. BFI_ENET_H2I_TX_CFG_SET_REQ, 0, tx->rid);
  2613. cfg_req->mh.num_entries = htons(
  2614. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_tx_cfg_req)));
  2615. cfg_req->num_queues = tx->num_txq;
  2616. for (i = 0; i < tx->num_txq; i++) {
  2617. txq = txq ? list_next_entry(txq, qe)
  2618. : list_first_entry(&tx->txq_q, struct bna_txq, qe);
  2619. bfi_enet_datapath_q_init(&cfg_req->q_cfg[i].q.q, &txq->qpt);
  2620. cfg_req->q_cfg[i].q.priority = txq->priority;
  2621. cfg_req->q_cfg[i].ib.index_addr.a32.addr_lo =
  2622. txq->ib.ib_seg_host_addr.lsb;
  2623. cfg_req->q_cfg[i].ib.index_addr.a32.addr_hi =
  2624. txq->ib.ib_seg_host_addr.msb;
  2625. cfg_req->q_cfg[i].ib.intr.msix_index =
  2626. htons((u16)txq->ib.intr_vector);
  2627. }
  2628. cfg_req->ib_cfg.int_pkt_dma = BNA_STATUS_T_ENABLED;
  2629. cfg_req->ib_cfg.int_enabled = BNA_STATUS_T_ENABLED;
  2630. cfg_req->ib_cfg.int_pkt_enabled = BNA_STATUS_T_DISABLED;
  2631. cfg_req->ib_cfg.continuous_coalescing = BNA_STATUS_T_ENABLED;
  2632. cfg_req->ib_cfg.msix = (txq->ib.intr_type == BNA_INTR_T_MSIX)
  2633. ? BNA_STATUS_T_ENABLED : BNA_STATUS_T_DISABLED;
  2634. cfg_req->ib_cfg.coalescing_timeout =
  2635. htonl((u32)txq->ib.coalescing_timeo);
  2636. cfg_req->ib_cfg.inter_pkt_timeout =
  2637. htonl((u32)txq->ib.interpkt_timeo);
  2638. cfg_req->ib_cfg.inter_pkt_count = (u8)txq->ib.interpkt_count;
  2639. cfg_req->tx_cfg.vlan_mode = BFI_ENET_TX_VLAN_WI;
  2640. cfg_req->tx_cfg.vlan_id = htons((u16)tx->txf_vlan_id);
  2641. cfg_req->tx_cfg.admit_tagged_frame = BNA_STATUS_T_ENABLED;
  2642. cfg_req->tx_cfg.apply_vlan_filter = BNA_STATUS_T_DISABLED;
  2643. bfa_msgq_cmd_set(&tx->msgq_cmd, NULL, NULL,
  2644. sizeof(struct bfi_enet_tx_cfg_req), &cfg_req->mh);
  2645. bfa_msgq_cmd_post(&tx->bna->msgq, &tx->msgq_cmd);
  2646. }
  2647. static void
  2648. bna_bfi_tx_enet_stop(struct bna_tx *tx)
  2649. {
  2650. struct bfi_enet_req *req = &tx->bfi_enet_cmd.req;
  2651. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  2652. BFI_ENET_H2I_TX_CFG_CLR_REQ, 0, tx->rid);
  2653. req->mh.num_entries = htons(
  2654. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_req)));
  2655. bfa_msgq_cmd_set(&tx->msgq_cmd, NULL, NULL, sizeof(struct bfi_enet_req),
  2656. &req->mh);
  2657. bfa_msgq_cmd_post(&tx->bna->msgq, &tx->msgq_cmd);
  2658. }
  2659. static void
  2660. bna_tx_enet_stop(struct bna_tx *tx)
  2661. {
  2662. struct bna_txq *txq;
  2663. /* Stop IB */
  2664. list_for_each_entry(txq, &tx->txq_q, qe)
  2665. bna_ib_stop(tx->bna, &txq->ib);
  2666. bna_bfi_tx_enet_stop(tx);
  2667. }
  2668. static void
  2669. bna_txq_qpt_setup(struct bna_txq *txq, int page_count, int page_size,
  2670. struct bna_mem_descr *qpt_mem,
  2671. struct bna_mem_descr *swqpt_mem,
  2672. struct bna_mem_descr *page_mem)
  2673. {
  2674. u8 *kva;
  2675. u64 dma;
  2676. struct bna_dma_addr bna_dma;
  2677. int i;
  2678. txq->qpt.hw_qpt_ptr.lsb = qpt_mem->dma.lsb;
  2679. txq->qpt.hw_qpt_ptr.msb = qpt_mem->dma.msb;
  2680. txq->qpt.kv_qpt_ptr = qpt_mem->kva;
  2681. txq->qpt.page_count = page_count;
  2682. txq->qpt.page_size = page_size;
  2683. txq->tcb->sw_qpt = (void **) swqpt_mem->kva;
  2684. txq->tcb->sw_q = page_mem->kva;
  2685. kva = page_mem->kva;
  2686. BNA_GET_DMA_ADDR(&page_mem->dma, dma);
  2687. for (i = 0; i < page_count; i++) {
  2688. txq->tcb->sw_qpt[i] = kva;
  2689. kva += PAGE_SIZE;
  2690. BNA_SET_DMA_ADDR(dma, &bna_dma);
  2691. ((struct bna_dma_addr *)txq->qpt.kv_qpt_ptr)[i].lsb =
  2692. bna_dma.lsb;
  2693. ((struct bna_dma_addr *)txq->qpt.kv_qpt_ptr)[i].msb =
  2694. bna_dma.msb;
  2695. dma += PAGE_SIZE;
  2696. }
  2697. }
  2698. static struct bna_tx *
  2699. bna_tx_get(struct bna_tx_mod *tx_mod, enum bna_tx_type type)
  2700. {
  2701. struct bna_tx *tx = NULL;
  2702. if (list_empty(&tx_mod->tx_free_q))
  2703. return NULL;
  2704. if (type == BNA_TX_T_REGULAR)
  2705. tx = list_first_entry(&tx_mod->tx_free_q, struct bna_tx, qe);
  2706. else
  2707. tx = list_last_entry(&tx_mod->tx_free_q, struct bna_tx, qe);
  2708. list_del(&tx->qe);
  2709. tx->type = type;
  2710. return tx;
  2711. }
  2712. static void
  2713. bna_tx_free(struct bna_tx *tx)
  2714. {
  2715. struct bna_tx_mod *tx_mod = &tx->bna->tx_mod;
  2716. struct bna_txq *txq;
  2717. struct list_head *qe;
  2718. while (!list_empty(&tx->txq_q)) {
  2719. txq = list_first_entry(&tx->txq_q, struct bna_txq, qe);
  2720. txq->tcb = NULL;
  2721. txq->tx = NULL;
  2722. list_move_tail(&txq->qe, &tx_mod->txq_free_q);
  2723. }
  2724. list_for_each(qe, &tx_mod->tx_active_q) {
  2725. if (qe == &tx->qe) {
  2726. list_del(&tx->qe);
  2727. break;
  2728. }
  2729. }
  2730. tx->bna = NULL;
  2731. tx->priv = NULL;
  2732. list_for_each_prev(qe, &tx_mod->tx_free_q)
  2733. if (((struct bna_tx *)qe)->rid < tx->rid)
  2734. break;
  2735. list_add(&tx->qe, qe);
  2736. }
  2737. static void
  2738. bna_tx_start(struct bna_tx *tx)
  2739. {
  2740. tx->flags |= BNA_TX_F_ENET_STARTED;
  2741. if (tx->flags & BNA_TX_F_ENABLED)
  2742. bfa_fsm_send_event(tx, TX_E_START);
  2743. }
  2744. static void
  2745. bna_tx_stop(struct bna_tx *tx)
  2746. {
  2747. tx->stop_cbfn = bna_tx_mod_cb_tx_stopped;
  2748. tx->stop_cbarg = &tx->bna->tx_mod;
  2749. tx->flags &= ~BNA_TX_F_ENET_STARTED;
  2750. bfa_fsm_send_event(tx, TX_E_STOP);
  2751. }
  2752. static void
  2753. bna_tx_fail(struct bna_tx *tx)
  2754. {
  2755. tx->flags &= ~BNA_TX_F_ENET_STARTED;
  2756. bfa_fsm_send_event(tx, TX_E_FAIL);
  2757. }
  2758. void
  2759. bna_bfi_tx_enet_start_rsp(struct bna_tx *tx, struct bfi_msgq_mhdr *msghdr)
  2760. {
  2761. struct bfi_enet_tx_cfg_rsp *cfg_rsp = &tx->bfi_enet_cmd.cfg_rsp;
  2762. struct bna_txq *txq = NULL;
  2763. int i;
  2764. bfa_msgq_rsp_copy(&tx->bna->msgq, (u8 *)cfg_rsp,
  2765. sizeof(struct bfi_enet_tx_cfg_rsp));
  2766. tx->hw_id = cfg_rsp->hw_id;
  2767. for (i = 0, txq = list_first_entry(&tx->txq_q, struct bna_txq, qe);
  2768. i < tx->num_txq; i++, txq = list_next_entry(txq, qe)) {
  2769. /* Setup doorbells */
  2770. txq->tcb->i_dbell->doorbell_addr =
  2771. tx->bna->pcidev.pci_bar_kva
  2772. + ntohl(cfg_rsp->q_handles[i].i_dbell);
  2773. txq->tcb->q_dbell =
  2774. tx->bna->pcidev.pci_bar_kva
  2775. + ntohl(cfg_rsp->q_handles[i].q_dbell);
  2776. txq->hw_id = cfg_rsp->q_handles[i].hw_qid;
  2777. /* Initialize producer/consumer indexes */
  2778. (*txq->tcb->hw_consumer_index) = 0;
  2779. txq->tcb->producer_index = txq->tcb->consumer_index = 0;
  2780. }
  2781. bfa_fsm_send_event(tx, TX_E_STARTED);
  2782. }
  2783. void
  2784. bna_bfi_tx_enet_stop_rsp(struct bna_tx *tx, struct bfi_msgq_mhdr *msghdr)
  2785. {
  2786. bfa_fsm_send_event(tx, TX_E_STOPPED);
  2787. }
  2788. void
  2789. bna_bfi_bw_update_aen(struct bna_tx_mod *tx_mod)
  2790. {
  2791. struct bna_tx *tx;
  2792. list_for_each_entry(tx, &tx_mod->tx_active_q, qe)
  2793. bfa_fsm_send_event(tx, TX_E_BW_UPDATE);
  2794. }
  2795. void
  2796. bna_tx_res_req(int num_txq, int txq_depth, struct bna_res_info *res_info)
  2797. {
  2798. u32 q_size;
  2799. u32 page_count;
  2800. struct bna_mem_info *mem_info;
  2801. res_info[BNA_TX_RES_MEM_T_TCB].res_type = BNA_RES_T_MEM;
  2802. mem_info = &res_info[BNA_TX_RES_MEM_T_TCB].res_u.mem_info;
  2803. mem_info->mem_type = BNA_MEM_T_KVA;
  2804. mem_info->len = sizeof(struct bna_tcb);
  2805. mem_info->num = num_txq;
  2806. q_size = txq_depth * BFI_TXQ_WI_SIZE;
  2807. q_size = ALIGN(q_size, PAGE_SIZE);
  2808. page_count = q_size >> PAGE_SHIFT;
  2809. res_info[BNA_TX_RES_MEM_T_QPT].res_type = BNA_RES_T_MEM;
  2810. mem_info = &res_info[BNA_TX_RES_MEM_T_QPT].res_u.mem_info;
  2811. mem_info->mem_type = BNA_MEM_T_DMA;
  2812. mem_info->len = page_count * sizeof(struct bna_dma_addr);
  2813. mem_info->num = num_txq;
  2814. res_info[BNA_TX_RES_MEM_T_SWQPT].res_type = BNA_RES_T_MEM;
  2815. mem_info = &res_info[BNA_TX_RES_MEM_T_SWQPT].res_u.mem_info;
  2816. mem_info->mem_type = BNA_MEM_T_KVA;
  2817. mem_info->len = page_count * sizeof(void *);
  2818. mem_info->num = num_txq;
  2819. res_info[BNA_TX_RES_MEM_T_PAGE].res_type = BNA_RES_T_MEM;
  2820. mem_info = &res_info[BNA_TX_RES_MEM_T_PAGE].res_u.mem_info;
  2821. mem_info->mem_type = BNA_MEM_T_DMA;
  2822. mem_info->len = PAGE_SIZE * page_count;
  2823. mem_info->num = num_txq;
  2824. res_info[BNA_TX_RES_MEM_T_IBIDX].res_type = BNA_RES_T_MEM;
  2825. mem_info = &res_info[BNA_TX_RES_MEM_T_IBIDX].res_u.mem_info;
  2826. mem_info->mem_type = BNA_MEM_T_DMA;
  2827. mem_info->len = BFI_IBIDX_SIZE;
  2828. mem_info->num = num_txq;
  2829. res_info[BNA_TX_RES_INTR_T_TXCMPL].res_type = BNA_RES_T_INTR;
  2830. res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info.intr_type =
  2831. BNA_INTR_T_MSIX;
  2832. res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info.num = num_txq;
  2833. }
  2834. struct bna_tx *
  2835. bna_tx_create(struct bna *bna, struct bnad *bnad,
  2836. struct bna_tx_config *tx_cfg,
  2837. const struct bna_tx_event_cbfn *tx_cbfn,
  2838. struct bna_res_info *res_info, void *priv)
  2839. {
  2840. struct bna_intr_info *intr_info;
  2841. struct bna_tx_mod *tx_mod = &bna->tx_mod;
  2842. struct bna_tx *tx;
  2843. struct bna_txq *txq;
  2844. int page_count;
  2845. int i;
  2846. intr_info = &res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info;
  2847. page_count = (res_info[BNA_TX_RES_MEM_T_PAGE].res_u.mem_info.len) /
  2848. PAGE_SIZE;
  2849. /**
  2850. * Get resources
  2851. */
  2852. if ((intr_info->num != 1) && (intr_info->num != tx_cfg->num_txq))
  2853. return NULL;
  2854. /* Tx */
  2855. tx = bna_tx_get(tx_mod, tx_cfg->tx_type);
  2856. if (!tx)
  2857. return NULL;
  2858. tx->bna = bna;
  2859. tx->priv = priv;
  2860. /* TxQs */
  2861. INIT_LIST_HEAD(&tx->txq_q);
  2862. for (i = 0; i < tx_cfg->num_txq; i++) {
  2863. if (list_empty(&tx_mod->txq_free_q))
  2864. goto err_return;
  2865. txq = list_first_entry(&tx_mod->txq_free_q, struct bna_txq, qe);
  2866. list_move_tail(&txq->qe, &tx->txq_q);
  2867. txq->tx = tx;
  2868. }
  2869. /*
  2870. * Initialize
  2871. */
  2872. /* Tx */
  2873. tx->tcb_setup_cbfn = tx_cbfn->tcb_setup_cbfn;
  2874. tx->tcb_destroy_cbfn = tx_cbfn->tcb_destroy_cbfn;
  2875. /* Following callbacks are mandatory */
  2876. tx->tx_stall_cbfn = tx_cbfn->tx_stall_cbfn;
  2877. tx->tx_resume_cbfn = tx_cbfn->tx_resume_cbfn;
  2878. tx->tx_cleanup_cbfn = tx_cbfn->tx_cleanup_cbfn;
  2879. list_add_tail(&tx->qe, &tx_mod->tx_active_q);
  2880. tx->num_txq = tx_cfg->num_txq;
  2881. tx->flags = 0;
  2882. if (tx->bna->tx_mod.flags & BNA_TX_MOD_F_ENET_STARTED) {
  2883. switch (tx->type) {
  2884. case BNA_TX_T_REGULAR:
  2885. if (!(tx->bna->tx_mod.flags &
  2886. BNA_TX_MOD_F_ENET_LOOPBACK))
  2887. tx->flags |= BNA_TX_F_ENET_STARTED;
  2888. break;
  2889. case BNA_TX_T_LOOPBACK:
  2890. if (tx->bna->tx_mod.flags & BNA_TX_MOD_F_ENET_LOOPBACK)
  2891. tx->flags |= BNA_TX_F_ENET_STARTED;
  2892. break;
  2893. }
  2894. }
  2895. /* TxQ */
  2896. i = 0;
  2897. list_for_each_entry(txq, &tx->txq_q, qe) {
  2898. txq->tcb = (struct bna_tcb *)
  2899. res_info[BNA_TX_RES_MEM_T_TCB].res_u.mem_info.mdl[i].kva;
  2900. txq->tx_packets = 0;
  2901. txq->tx_bytes = 0;
  2902. /* IB */
  2903. txq->ib.ib_seg_host_addr.lsb =
  2904. res_info[BNA_TX_RES_MEM_T_IBIDX].res_u.mem_info.mdl[i].dma.lsb;
  2905. txq->ib.ib_seg_host_addr.msb =
  2906. res_info[BNA_TX_RES_MEM_T_IBIDX].res_u.mem_info.mdl[i].dma.msb;
  2907. txq->ib.ib_seg_host_addr_kva =
  2908. res_info[BNA_TX_RES_MEM_T_IBIDX].res_u.mem_info.mdl[i].kva;
  2909. txq->ib.intr_type = intr_info->intr_type;
  2910. txq->ib.intr_vector = (intr_info->num == 1) ?
  2911. intr_info->idl[0].vector :
  2912. intr_info->idl[i].vector;
  2913. if (intr_info->intr_type == BNA_INTR_T_INTX)
  2914. txq->ib.intr_vector = BIT(txq->ib.intr_vector);
  2915. txq->ib.coalescing_timeo = tx_cfg->coalescing_timeo;
  2916. txq->ib.interpkt_timeo = BFI_TX_INTERPKT_TIMEO;
  2917. txq->ib.interpkt_count = BFI_TX_INTERPKT_COUNT;
  2918. /* TCB */
  2919. txq->tcb->q_depth = tx_cfg->txq_depth;
  2920. txq->tcb->unmap_q = (void *)
  2921. res_info[BNA_TX_RES_MEM_T_UNMAPQ].res_u.mem_info.mdl[i].kva;
  2922. txq->tcb->hw_consumer_index =
  2923. (u32 *)txq->ib.ib_seg_host_addr_kva;
  2924. txq->tcb->i_dbell = &txq->ib.door_bell;
  2925. txq->tcb->intr_type = txq->ib.intr_type;
  2926. txq->tcb->intr_vector = txq->ib.intr_vector;
  2927. txq->tcb->txq = txq;
  2928. txq->tcb->bnad = bnad;
  2929. txq->tcb->id = i;
  2930. /* QPT, SWQPT, Pages */
  2931. bna_txq_qpt_setup(txq, page_count, PAGE_SIZE,
  2932. &res_info[BNA_TX_RES_MEM_T_QPT].res_u.mem_info.mdl[i],
  2933. &res_info[BNA_TX_RES_MEM_T_SWQPT].res_u.mem_info.mdl[i],
  2934. &res_info[BNA_TX_RES_MEM_T_PAGE].
  2935. res_u.mem_info.mdl[i]);
  2936. /* Callback to bnad for setting up TCB */
  2937. if (tx->tcb_setup_cbfn)
  2938. (tx->tcb_setup_cbfn)(bna->bnad, txq->tcb);
  2939. if (tx_cfg->num_txq == BFI_TX_MAX_PRIO)
  2940. txq->priority = txq->tcb->id;
  2941. else
  2942. txq->priority = tx_mod->default_prio;
  2943. i++;
  2944. }
  2945. tx->txf_vlan_id = 0;
  2946. bfa_fsm_set_state(tx, bna_tx_sm_stopped);
  2947. tx_mod->rid_mask |= BIT(tx->rid);
  2948. return tx;
  2949. err_return:
  2950. bna_tx_free(tx);
  2951. return NULL;
  2952. }
  2953. void
  2954. bna_tx_destroy(struct bna_tx *tx)
  2955. {
  2956. struct bna_txq *txq;
  2957. list_for_each_entry(txq, &tx->txq_q, qe)
  2958. if (tx->tcb_destroy_cbfn)
  2959. (tx->tcb_destroy_cbfn)(tx->bna->bnad, txq->tcb);
  2960. tx->bna->tx_mod.rid_mask &= ~BIT(tx->rid);
  2961. bna_tx_free(tx);
  2962. }
  2963. void
  2964. bna_tx_enable(struct bna_tx *tx)
  2965. {
  2966. if (tx->fsm != (bfa_sm_t)bna_tx_sm_stopped)
  2967. return;
  2968. tx->flags |= BNA_TX_F_ENABLED;
  2969. if (tx->flags & BNA_TX_F_ENET_STARTED)
  2970. bfa_fsm_send_event(tx, TX_E_START);
  2971. }
  2972. void
  2973. bna_tx_disable(struct bna_tx *tx, enum bna_cleanup_type type,
  2974. void (*cbfn)(void *, struct bna_tx *))
  2975. {
  2976. if (type == BNA_SOFT_CLEANUP) {
  2977. (*cbfn)(tx->bna->bnad, tx);
  2978. return;
  2979. }
  2980. tx->stop_cbfn = cbfn;
  2981. tx->stop_cbarg = tx->bna->bnad;
  2982. tx->flags &= ~BNA_TX_F_ENABLED;
  2983. bfa_fsm_send_event(tx, TX_E_STOP);
  2984. }
  2985. void
  2986. bna_tx_cleanup_complete(struct bna_tx *tx)
  2987. {
  2988. bfa_fsm_send_event(tx, TX_E_CLEANUP_DONE);
  2989. }
  2990. static void
  2991. bna_tx_mod_cb_tx_stopped(void *arg, struct bna_tx *tx)
  2992. {
  2993. struct bna_tx_mod *tx_mod = (struct bna_tx_mod *)arg;
  2994. bfa_wc_down(&tx_mod->tx_stop_wc);
  2995. }
  2996. static void
  2997. bna_tx_mod_cb_tx_stopped_all(void *arg)
  2998. {
  2999. struct bna_tx_mod *tx_mod = (struct bna_tx_mod *)arg;
  3000. if (tx_mod->stop_cbfn)
  3001. tx_mod->stop_cbfn(&tx_mod->bna->enet);
  3002. tx_mod->stop_cbfn = NULL;
  3003. }
  3004. void
  3005. bna_tx_mod_init(struct bna_tx_mod *tx_mod, struct bna *bna,
  3006. struct bna_res_info *res_info)
  3007. {
  3008. int i;
  3009. tx_mod->bna = bna;
  3010. tx_mod->flags = 0;
  3011. tx_mod->tx = (struct bna_tx *)
  3012. res_info[BNA_MOD_RES_MEM_T_TX_ARRAY].res_u.mem_info.mdl[0].kva;
  3013. tx_mod->txq = (struct bna_txq *)
  3014. res_info[BNA_MOD_RES_MEM_T_TXQ_ARRAY].res_u.mem_info.mdl[0].kva;
  3015. INIT_LIST_HEAD(&tx_mod->tx_free_q);
  3016. INIT_LIST_HEAD(&tx_mod->tx_active_q);
  3017. INIT_LIST_HEAD(&tx_mod->txq_free_q);
  3018. for (i = 0; i < bna->ioceth.attr.num_txq; i++) {
  3019. tx_mod->tx[i].rid = i;
  3020. list_add_tail(&tx_mod->tx[i].qe, &tx_mod->tx_free_q);
  3021. list_add_tail(&tx_mod->txq[i].qe, &tx_mod->txq_free_q);
  3022. }
  3023. tx_mod->prio_map = BFI_TX_PRIO_MAP_ALL;
  3024. tx_mod->default_prio = 0;
  3025. tx_mod->iscsi_over_cee = BNA_STATUS_T_DISABLED;
  3026. tx_mod->iscsi_prio = -1;
  3027. }
  3028. void
  3029. bna_tx_mod_uninit(struct bna_tx_mod *tx_mod)
  3030. {
  3031. tx_mod->bna = NULL;
  3032. }
  3033. void
  3034. bna_tx_mod_start(struct bna_tx_mod *tx_mod, enum bna_tx_type type)
  3035. {
  3036. struct bna_tx *tx;
  3037. tx_mod->flags |= BNA_TX_MOD_F_ENET_STARTED;
  3038. if (type == BNA_TX_T_LOOPBACK)
  3039. tx_mod->flags |= BNA_TX_MOD_F_ENET_LOOPBACK;
  3040. list_for_each_entry(tx, &tx_mod->tx_active_q, qe)
  3041. if (tx->type == type)
  3042. bna_tx_start(tx);
  3043. }
  3044. void
  3045. bna_tx_mod_stop(struct bna_tx_mod *tx_mod, enum bna_tx_type type)
  3046. {
  3047. struct bna_tx *tx;
  3048. tx_mod->flags &= ~BNA_TX_MOD_F_ENET_STARTED;
  3049. tx_mod->flags &= ~BNA_TX_MOD_F_ENET_LOOPBACK;
  3050. tx_mod->stop_cbfn = bna_enet_cb_tx_stopped;
  3051. bfa_wc_init(&tx_mod->tx_stop_wc, bna_tx_mod_cb_tx_stopped_all, tx_mod);
  3052. list_for_each_entry(tx, &tx_mod->tx_active_q, qe)
  3053. if (tx->type == type) {
  3054. bfa_wc_up(&tx_mod->tx_stop_wc);
  3055. bna_tx_stop(tx);
  3056. }
  3057. bfa_wc_wait(&tx_mod->tx_stop_wc);
  3058. }
  3059. void
  3060. bna_tx_mod_fail(struct bna_tx_mod *tx_mod)
  3061. {
  3062. struct bna_tx *tx;
  3063. tx_mod->flags &= ~BNA_TX_MOD_F_ENET_STARTED;
  3064. tx_mod->flags &= ~BNA_TX_MOD_F_ENET_LOOPBACK;
  3065. list_for_each_entry(tx, &tx_mod->tx_active_q, qe)
  3066. bna_tx_fail(tx);
  3067. }
  3068. void
  3069. bna_tx_coalescing_timeo_set(struct bna_tx *tx, int coalescing_timeo)
  3070. {
  3071. struct bna_txq *txq;
  3072. list_for_each_entry(txq, &tx->txq_q, qe)
  3073. bna_ib_coalescing_timeo_set(&txq->ib, coalescing_timeo);
  3074. }