bnxt_ethtool.c 87 KB

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  1. /* Broadcom NetXtreme-C/E network driver.
  2. *
  3. * Copyright (c) 2014-2016 Broadcom Corporation
  4. * Copyright (c) 2016-2017 Broadcom Limited
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation.
  9. */
  10. #include <linux/ctype.h>
  11. #include <linux/stringify.h>
  12. #include <linux/ethtool.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/pci.h>
  15. #include <linux/etherdevice.h>
  16. #include <linux/crc32.h>
  17. #include <linux/firmware.h>
  18. #include <linux/utsname.h>
  19. #include <linux/time.h>
  20. #include "bnxt_hsi.h"
  21. #include "bnxt.h"
  22. #include "bnxt_xdp.h"
  23. #include "bnxt_ethtool.h"
  24. #include "bnxt_nvm_defs.h" /* NVRAM content constant and structure defs */
  25. #include "bnxt_fw_hdr.h" /* Firmware hdr constant and structure defs */
  26. #include "bnxt_coredump.h"
  27. #define FLASH_NVRAM_TIMEOUT ((HWRM_CMD_TIMEOUT) * 100)
  28. #define FLASH_PACKAGE_TIMEOUT ((HWRM_CMD_TIMEOUT) * 200)
  29. #define INSTALL_PACKAGE_TIMEOUT ((HWRM_CMD_TIMEOUT) * 200)
  30. static u32 bnxt_get_msglevel(struct net_device *dev)
  31. {
  32. struct bnxt *bp = netdev_priv(dev);
  33. return bp->msg_enable;
  34. }
  35. static void bnxt_set_msglevel(struct net_device *dev, u32 value)
  36. {
  37. struct bnxt *bp = netdev_priv(dev);
  38. bp->msg_enable = value;
  39. }
  40. static int bnxt_get_coalesce(struct net_device *dev,
  41. struct ethtool_coalesce *coal)
  42. {
  43. struct bnxt *bp = netdev_priv(dev);
  44. struct bnxt_coal *hw_coal;
  45. u16 mult;
  46. memset(coal, 0, sizeof(*coal));
  47. coal->use_adaptive_rx_coalesce = bp->flags & BNXT_FLAG_DIM;
  48. hw_coal = &bp->rx_coal;
  49. mult = hw_coal->bufs_per_record;
  50. coal->rx_coalesce_usecs = hw_coal->coal_ticks;
  51. coal->rx_max_coalesced_frames = hw_coal->coal_bufs / mult;
  52. coal->rx_coalesce_usecs_irq = hw_coal->coal_ticks_irq;
  53. coal->rx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult;
  54. hw_coal = &bp->tx_coal;
  55. mult = hw_coal->bufs_per_record;
  56. coal->tx_coalesce_usecs = hw_coal->coal_ticks;
  57. coal->tx_max_coalesced_frames = hw_coal->coal_bufs / mult;
  58. coal->tx_coalesce_usecs_irq = hw_coal->coal_ticks_irq;
  59. coal->tx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult;
  60. coal->stats_block_coalesce_usecs = bp->stats_coal_ticks;
  61. return 0;
  62. }
  63. static int bnxt_set_coalesce(struct net_device *dev,
  64. struct ethtool_coalesce *coal)
  65. {
  66. struct bnxt *bp = netdev_priv(dev);
  67. bool update_stats = false;
  68. struct bnxt_coal *hw_coal;
  69. int rc = 0;
  70. u16 mult;
  71. if (coal->use_adaptive_rx_coalesce) {
  72. bp->flags |= BNXT_FLAG_DIM;
  73. } else {
  74. if (bp->flags & BNXT_FLAG_DIM) {
  75. bp->flags &= ~(BNXT_FLAG_DIM);
  76. goto reset_coalesce;
  77. }
  78. }
  79. hw_coal = &bp->rx_coal;
  80. mult = hw_coal->bufs_per_record;
  81. hw_coal->coal_ticks = coal->rx_coalesce_usecs;
  82. hw_coal->coal_bufs = coal->rx_max_coalesced_frames * mult;
  83. hw_coal->coal_ticks_irq = coal->rx_coalesce_usecs_irq;
  84. hw_coal->coal_bufs_irq = coal->rx_max_coalesced_frames_irq * mult;
  85. hw_coal = &bp->tx_coal;
  86. mult = hw_coal->bufs_per_record;
  87. hw_coal->coal_ticks = coal->tx_coalesce_usecs;
  88. hw_coal->coal_bufs = coal->tx_max_coalesced_frames * mult;
  89. hw_coal->coal_ticks_irq = coal->tx_coalesce_usecs_irq;
  90. hw_coal->coal_bufs_irq = coal->tx_max_coalesced_frames_irq * mult;
  91. if (bp->stats_coal_ticks != coal->stats_block_coalesce_usecs) {
  92. u32 stats_ticks = coal->stats_block_coalesce_usecs;
  93. /* Allow 0, which means disable. */
  94. if (stats_ticks)
  95. stats_ticks = clamp_t(u32, stats_ticks,
  96. BNXT_MIN_STATS_COAL_TICKS,
  97. BNXT_MAX_STATS_COAL_TICKS);
  98. stats_ticks = rounddown(stats_ticks, BNXT_MIN_STATS_COAL_TICKS);
  99. bp->stats_coal_ticks = stats_ticks;
  100. if (bp->stats_coal_ticks)
  101. bp->current_interval =
  102. bp->stats_coal_ticks * HZ / 1000000;
  103. else
  104. bp->current_interval = BNXT_TIMER_INTERVAL;
  105. update_stats = true;
  106. }
  107. reset_coalesce:
  108. if (netif_running(dev)) {
  109. if (update_stats) {
  110. rc = bnxt_close_nic(bp, true, false);
  111. if (!rc)
  112. rc = bnxt_open_nic(bp, true, false);
  113. } else {
  114. rc = bnxt_hwrm_set_coal(bp);
  115. }
  116. }
  117. return rc;
  118. }
  119. #define BNXT_NUM_STATS 21
  120. #define BNXT_RX_STATS_ENTRY(counter) \
  121. { BNXT_RX_STATS_OFFSET(counter), __stringify(counter) }
  122. #define BNXT_TX_STATS_ENTRY(counter) \
  123. { BNXT_TX_STATS_OFFSET(counter), __stringify(counter) }
  124. #define BNXT_RX_STATS_EXT_ENTRY(counter) \
  125. { BNXT_RX_STATS_EXT_OFFSET(counter), __stringify(counter) }
  126. enum {
  127. RX_TOTAL_DISCARDS,
  128. TX_TOTAL_DISCARDS,
  129. };
  130. static struct {
  131. u64 counter;
  132. char string[ETH_GSTRING_LEN];
  133. } bnxt_sw_func_stats[] = {
  134. {0, "rx_total_discard_pkts"},
  135. {0, "tx_total_discard_pkts"},
  136. };
  137. static const struct {
  138. long offset;
  139. char string[ETH_GSTRING_LEN];
  140. } bnxt_port_stats_arr[] = {
  141. BNXT_RX_STATS_ENTRY(rx_64b_frames),
  142. BNXT_RX_STATS_ENTRY(rx_65b_127b_frames),
  143. BNXT_RX_STATS_ENTRY(rx_128b_255b_frames),
  144. BNXT_RX_STATS_ENTRY(rx_256b_511b_frames),
  145. BNXT_RX_STATS_ENTRY(rx_512b_1023b_frames),
  146. BNXT_RX_STATS_ENTRY(rx_1024b_1518b_frames),
  147. BNXT_RX_STATS_ENTRY(rx_good_vlan_frames),
  148. BNXT_RX_STATS_ENTRY(rx_1519b_2047b_frames),
  149. BNXT_RX_STATS_ENTRY(rx_2048b_4095b_frames),
  150. BNXT_RX_STATS_ENTRY(rx_4096b_9216b_frames),
  151. BNXT_RX_STATS_ENTRY(rx_9217b_16383b_frames),
  152. BNXT_RX_STATS_ENTRY(rx_total_frames),
  153. BNXT_RX_STATS_ENTRY(rx_ucast_frames),
  154. BNXT_RX_STATS_ENTRY(rx_mcast_frames),
  155. BNXT_RX_STATS_ENTRY(rx_bcast_frames),
  156. BNXT_RX_STATS_ENTRY(rx_fcs_err_frames),
  157. BNXT_RX_STATS_ENTRY(rx_ctrl_frames),
  158. BNXT_RX_STATS_ENTRY(rx_pause_frames),
  159. BNXT_RX_STATS_ENTRY(rx_pfc_frames),
  160. BNXT_RX_STATS_ENTRY(rx_align_err_frames),
  161. BNXT_RX_STATS_ENTRY(rx_ovrsz_frames),
  162. BNXT_RX_STATS_ENTRY(rx_jbr_frames),
  163. BNXT_RX_STATS_ENTRY(rx_mtu_err_frames),
  164. BNXT_RX_STATS_ENTRY(rx_tagged_frames),
  165. BNXT_RX_STATS_ENTRY(rx_double_tagged_frames),
  166. BNXT_RX_STATS_ENTRY(rx_good_frames),
  167. BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri0),
  168. BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri1),
  169. BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri2),
  170. BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri3),
  171. BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri4),
  172. BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri5),
  173. BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri6),
  174. BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri7),
  175. BNXT_RX_STATS_ENTRY(rx_undrsz_frames),
  176. BNXT_RX_STATS_ENTRY(rx_eee_lpi_events),
  177. BNXT_RX_STATS_ENTRY(rx_eee_lpi_duration),
  178. BNXT_RX_STATS_ENTRY(rx_bytes),
  179. BNXT_RX_STATS_ENTRY(rx_runt_bytes),
  180. BNXT_RX_STATS_ENTRY(rx_runt_frames),
  181. BNXT_RX_STATS_ENTRY(rx_stat_discard),
  182. BNXT_RX_STATS_ENTRY(rx_stat_err),
  183. BNXT_TX_STATS_ENTRY(tx_64b_frames),
  184. BNXT_TX_STATS_ENTRY(tx_65b_127b_frames),
  185. BNXT_TX_STATS_ENTRY(tx_128b_255b_frames),
  186. BNXT_TX_STATS_ENTRY(tx_256b_511b_frames),
  187. BNXT_TX_STATS_ENTRY(tx_512b_1023b_frames),
  188. BNXT_TX_STATS_ENTRY(tx_1024b_1518b_frames),
  189. BNXT_TX_STATS_ENTRY(tx_good_vlan_frames),
  190. BNXT_TX_STATS_ENTRY(tx_1519b_2047b_frames),
  191. BNXT_TX_STATS_ENTRY(tx_2048b_4095b_frames),
  192. BNXT_TX_STATS_ENTRY(tx_4096b_9216b_frames),
  193. BNXT_TX_STATS_ENTRY(tx_9217b_16383b_frames),
  194. BNXT_TX_STATS_ENTRY(tx_good_frames),
  195. BNXT_TX_STATS_ENTRY(tx_total_frames),
  196. BNXT_TX_STATS_ENTRY(tx_ucast_frames),
  197. BNXT_TX_STATS_ENTRY(tx_mcast_frames),
  198. BNXT_TX_STATS_ENTRY(tx_bcast_frames),
  199. BNXT_TX_STATS_ENTRY(tx_pause_frames),
  200. BNXT_TX_STATS_ENTRY(tx_pfc_frames),
  201. BNXT_TX_STATS_ENTRY(tx_jabber_frames),
  202. BNXT_TX_STATS_ENTRY(tx_fcs_err_frames),
  203. BNXT_TX_STATS_ENTRY(tx_err),
  204. BNXT_TX_STATS_ENTRY(tx_fifo_underruns),
  205. BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri0),
  206. BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri1),
  207. BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri2),
  208. BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri3),
  209. BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri4),
  210. BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri5),
  211. BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri6),
  212. BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri7),
  213. BNXT_TX_STATS_ENTRY(tx_eee_lpi_events),
  214. BNXT_TX_STATS_ENTRY(tx_eee_lpi_duration),
  215. BNXT_TX_STATS_ENTRY(tx_total_collisions),
  216. BNXT_TX_STATS_ENTRY(tx_bytes),
  217. BNXT_TX_STATS_ENTRY(tx_xthol_frames),
  218. BNXT_TX_STATS_ENTRY(tx_stat_discard),
  219. BNXT_TX_STATS_ENTRY(tx_stat_error),
  220. };
  221. static const struct {
  222. long offset;
  223. char string[ETH_GSTRING_LEN];
  224. } bnxt_port_stats_ext_arr[] = {
  225. BNXT_RX_STATS_EXT_ENTRY(link_down_events),
  226. BNXT_RX_STATS_EXT_ENTRY(continuous_pause_events),
  227. BNXT_RX_STATS_EXT_ENTRY(resume_pause_events),
  228. BNXT_RX_STATS_EXT_ENTRY(continuous_roce_pause_events),
  229. BNXT_RX_STATS_EXT_ENTRY(resume_roce_pause_events),
  230. };
  231. #define BNXT_NUM_SW_FUNC_STATS ARRAY_SIZE(bnxt_sw_func_stats)
  232. #define BNXT_NUM_PORT_STATS ARRAY_SIZE(bnxt_port_stats_arr)
  233. #define BNXT_NUM_PORT_STATS_EXT ARRAY_SIZE(bnxt_port_stats_ext_arr)
  234. static int bnxt_get_num_stats(struct bnxt *bp)
  235. {
  236. int num_stats = BNXT_NUM_STATS * bp->cp_nr_rings;
  237. num_stats += BNXT_NUM_SW_FUNC_STATS;
  238. if (bp->flags & BNXT_FLAG_PORT_STATS)
  239. num_stats += BNXT_NUM_PORT_STATS;
  240. if (bp->flags & BNXT_FLAG_PORT_STATS_EXT)
  241. num_stats += BNXT_NUM_PORT_STATS_EXT;
  242. return num_stats;
  243. }
  244. static int bnxt_get_sset_count(struct net_device *dev, int sset)
  245. {
  246. struct bnxt *bp = netdev_priv(dev);
  247. switch (sset) {
  248. case ETH_SS_STATS:
  249. return bnxt_get_num_stats(bp);
  250. case ETH_SS_TEST:
  251. if (!bp->num_tests)
  252. return -EOPNOTSUPP;
  253. return bp->num_tests;
  254. default:
  255. return -EOPNOTSUPP;
  256. }
  257. }
  258. static void bnxt_get_ethtool_stats(struct net_device *dev,
  259. struct ethtool_stats *stats, u64 *buf)
  260. {
  261. u32 i, j = 0;
  262. struct bnxt *bp = netdev_priv(dev);
  263. u32 stat_fields = sizeof(struct ctx_hw_stats) / 8;
  264. if (!bp->bnapi)
  265. return;
  266. for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++)
  267. bnxt_sw_func_stats[i].counter = 0;
  268. for (i = 0; i < bp->cp_nr_rings; i++) {
  269. struct bnxt_napi *bnapi = bp->bnapi[i];
  270. struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
  271. __le64 *hw_stats = (__le64 *)cpr->hw_stats;
  272. int k;
  273. for (k = 0; k < stat_fields; j++, k++)
  274. buf[j] = le64_to_cpu(hw_stats[k]);
  275. buf[j++] = cpr->rx_l4_csum_errors;
  276. bnxt_sw_func_stats[RX_TOTAL_DISCARDS].counter +=
  277. le64_to_cpu(cpr->hw_stats->rx_discard_pkts);
  278. bnxt_sw_func_stats[TX_TOTAL_DISCARDS].counter +=
  279. le64_to_cpu(cpr->hw_stats->tx_discard_pkts);
  280. }
  281. for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++, j++)
  282. buf[j] = bnxt_sw_func_stats[i].counter;
  283. if (bp->flags & BNXT_FLAG_PORT_STATS) {
  284. __le64 *port_stats = (__le64 *)bp->hw_rx_port_stats;
  285. for (i = 0; i < BNXT_NUM_PORT_STATS; i++, j++) {
  286. buf[j] = le64_to_cpu(*(port_stats +
  287. bnxt_port_stats_arr[i].offset));
  288. }
  289. }
  290. if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
  291. __le64 *port_stats_ext = (__le64 *)bp->hw_rx_port_stats_ext;
  292. for (i = 0; i < BNXT_NUM_PORT_STATS_EXT; i++, j++) {
  293. buf[j] = le64_to_cpu(*(port_stats_ext +
  294. bnxt_port_stats_ext_arr[i].offset));
  295. }
  296. }
  297. }
  298. static void bnxt_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
  299. {
  300. struct bnxt *bp = netdev_priv(dev);
  301. u32 i;
  302. switch (stringset) {
  303. /* The number of strings must match BNXT_NUM_STATS defined above. */
  304. case ETH_SS_STATS:
  305. for (i = 0; i < bp->cp_nr_rings; i++) {
  306. sprintf(buf, "[%d]: rx_ucast_packets", i);
  307. buf += ETH_GSTRING_LEN;
  308. sprintf(buf, "[%d]: rx_mcast_packets", i);
  309. buf += ETH_GSTRING_LEN;
  310. sprintf(buf, "[%d]: rx_bcast_packets", i);
  311. buf += ETH_GSTRING_LEN;
  312. sprintf(buf, "[%d]: rx_discards", i);
  313. buf += ETH_GSTRING_LEN;
  314. sprintf(buf, "[%d]: rx_drops", i);
  315. buf += ETH_GSTRING_LEN;
  316. sprintf(buf, "[%d]: rx_ucast_bytes", i);
  317. buf += ETH_GSTRING_LEN;
  318. sprintf(buf, "[%d]: rx_mcast_bytes", i);
  319. buf += ETH_GSTRING_LEN;
  320. sprintf(buf, "[%d]: rx_bcast_bytes", i);
  321. buf += ETH_GSTRING_LEN;
  322. sprintf(buf, "[%d]: tx_ucast_packets", i);
  323. buf += ETH_GSTRING_LEN;
  324. sprintf(buf, "[%d]: tx_mcast_packets", i);
  325. buf += ETH_GSTRING_LEN;
  326. sprintf(buf, "[%d]: tx_bcast_packets", i);
  327. buf += ETH_GSTRING_LEN;
  328. sprintf(buf, "[%d]: tx_discards", i);
  329. buf += ETH_GSTRING_LEN;
  330. sprintf(buf, "[%d]: tx_drops", i);
  331. buf += ETH_GSTRING_LEN;
  332. sprintf(buf, "[%d]: tx_ucast_bytes", i);
  333. buf += ETH_GSTRING_LEN;
  334. sprintf(buf, "[%d]: tx_mcast_bytes", i);
  335. buf += ETH_GSTRING_LEN;
  336. sprintf(buf, "[%d]: tx_bcast_bytes", i);
  337. buf += ETH_GSTRING_LEN;
  338. sprintf(buf, "[%d]: tpa_packets", i);
  339. buf += ETH_GSTRING_LEN;
  340. sprintf(buf, "[%d]: tpa_bytes", i);
  341. buf += ETH_GSTRING_LEN;
  342. sprintf(buf, "[%d]: tpa_events", i);
  343. buf += ETH_GSTRING_LEN;
  344. sprintf(buf, "[%d]: tpa_aborts", i);
  345. buf += ETH_GSTRING_LEN;
  346. sprintf(buf, "[%d]: rx_l4_csum_errors", i);
  347. buf += ETH_GSTRING_LEN;
  348. }
  349. for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++) {
  350. strcpy(buf, bnxt_sw_func_stats[i].string);
  351. buf += ETH_GSTRING_LEN;
  352. }
  353. if (bp->flags & BNXT_FLAG_PORT_STATS) {
  354. for (i = 0; i < BNXT_NUM_PORT_STATS; i++) {
  355. strcpy(buf, bnxt_port_stats_arr[i].string);
  356. buf += ETH_GSTRING_LEN;
  357. }
  358. }
  359. if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
  360. for (i = 0; i < BNXT_NUM_PORT_STATS_EXT; i++) {
  361. strcpy(buf, bnxt_port_stats_ext_arr[i].string);
  362. buf += ETH_GSTRING_LEN;
  363. }
  364. }
  365. break;
  366. case ETH_SS_TEST:
  367. if (bp->num_tests)
  368. memcpy(buf, bp->test_info->string,
  369. bp->num_tests * ETH_GSTRING_LEN);
  370. break;
  371. default:
  372. netdev_err(bp->dev, "bnxt_get_strings invalid request %x\n",
  373. stringset);
  374. break;
  375. }
  376. }
  377. static void bnxt_get_ringparam(struct net_device *dev,
  378. struct ethtool_ringparam *ering)
  379. {
  380. struct bnxt *bp = netdev_priv(dev);
  381. ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT;
  382. ering->rx_jumbo_max_pending = BNXT_MAX_RX_JUM_DESC_CNT;
  383. ering->tx_max_pending = BNXT_MAX_TX_DESC_CNT;
  384. ering->rx_pending = bp->rx_ring_size;
  385. ering->rx_jumbo_pending = bp->rx_agg_ring_size;
  386. ering->tx_pending = bp->tx_ring_size;
  387. }
  388. static int bnxt_set_ringparam(struct net_device *dev,
  389. struct ethtool_ringparam *ering)
  390. {
  391. struct bnxt *bp = netdev_priv(dev);
  392. if ((ering->rx_pending > BNXT_MAX_RX_DESC_CNT) ||
  393. (ering->tx_pending > BNXT_MAX_TX_DESC_CNT) ||
  394. (ering->tx_pending <= MAX_SKB_FRAGS))
  395. return -EINVAL;
  396. if (netif_running(dev))
  397. bnxt_close_nic(bp, false, false);
  398. bp->rx_ring_size = ering->rx_pending;
  399. bp->tx_ring_size = ering->tx_pending;
  400. bnxt_set_ring_params(bp);
  401. if (netif_running(dev))
  402. return bnxt_open_nic(bp, false, false);
  403. return 0;
  404. }
  405. static void bnxt_get_channels(struct net_device *dev,
  406. struct ethtool_channels *channel)
  407. {
  408. struct bnxt *bp = netdev_priv(dev);
  409. struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
  410. int max_rx_rings, max_tx_rings, tcs;
  411. int max_tx_sch_inputs;
  412. /* Get the most up-to-date max_tx_sch_inputs. */
  413. if (BNXT_NEW_RM(bp))
  414. bnxt_hwrm_func_resc_qcaps(bp, false);
  415. max_tx_sch_inputs = hw_resc->max_tx_sch_inputs;
  416. bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, true);
  417. if (max_tx_sch_inputs)
  418. max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs);
  419. channel->max_combined = min_t(int, max_rx_rings, max_tx_rings);
  420. if (bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, false)) {
  421. max_rx_rings = 0;
  422. max_tx_rings = 0;
  423. }
  424. if (max_tx_sch_inputs)
  425. max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs);
  426. tcs = netdev_get_num_tc(dev);
  427. if (tcs > 1)
  428. max_tx_rings /= tcs;
  429. channel->max_rx = max_rx_rings;
  430. channel->max_tx = max_tx_rings;
  431. channel->max_other = 0;
  432. if (bp->flags & BNXT_FLAG_SHARED_RINGS) {
  433. channel->combined_count = bp->rx_nr_rings;
  434. if (BNXT_CHIP_TYPE_NITRO_A0(bp))
  435. channel->combined_count--;
  436. } else {
  437. if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) {
  438. channel->rx_count = bp->rx_nr_rings;
  439. channel->tx_count = bp->tx_nr_rings_per_tc;
  440. }
  441. }
  442. }
  443. static int bnxt_set_channels(struct net_device *dev,
  444. struct ethtool_channels *channel)
  445. {
  446. struct bnxt *bp = netdev_priv(dev);
  447. int req_tx_rings, req_rx_rings, tcs;
  448. bool sh = false;
  449. int tx_xdp = 0;
  450. int rc = 0;
  451. if (channel->other_count)
  452. return -EINVAL;
  453. if (!channel->combined_count &&
  454. (!channel->rx_count || !channel->tx_count))
  455. return -EINVAL;
  456. if (channel->combined_count &&
  457. (channel->rx_count || channel->tx_count))
  458. return -EINVAL;
  459. if (BNXT_CHIP_TYPE_NITRO_A0(bp) && (channel->rx_count ||
  460. channel->tx_count))
  461. return -EINVAL;
  462. if (channel->combined_count)
  463. sh = true;
  464. tcs = netdev_get_num_tc(dev);
  465. req_tx_rings = sh ? channel->combined_count : channel->tx_count;
  466. req_rx_rings = sh ? channel->combined_count : channel->rx_count;
  467. if (bp->tx_nr_rings_xdp) {
  468. if (!sh) {
  469. netdev_err(dev, "Only combined mode supported when XDP is enabled.\n");
  470. return -EINVAL;
  471. }
  472. tx_xdp = req_rx_rings;
  473. }
  474. rc = bnxt_check_rings(bp, req_tx_rings, req_rx_rings, sh, tcs, tx_xdp);
  475. if (rc) {
  476. netdev_warn(dev, "Unable to allocate the requested rings\n");
  477. return rc;
  478. }
  479. if (netif_running(dev)) {
  480. if (BNXT_PF(bp)) {
  481. /* TODO CHIMP_FW: Send message to all VF's
  482. * before PF unload
  483. */
  484. }
  485. rc = bnxt_close_nic(bp, true, false);
  486. if (rc) {
  487. netdev_err(bp->dev, "Set channel failure rc :%x\n",
  488. rc);
  489. return rc;
  490. }
  491. }
  492. if (sh) {
  493. bp->flags |= BNXT_FLAG_SHARED_RINGS;
  494. bp->rx_nr_rings = channel->combined_count;
  495. bp->tx_nr_rings_per_tc = channel->combined_count;
  496. } else {
  497. bp->flags &= ~BNXT_FLAG_SHARED_RINGS;
  498. bp->rx_nr_rings = channel->rx_count;
  499. bp->tx_nr_rings_per_tc = channel->tx_count;
  500. }
  501. bp->tx_nr_rings_xdp = tx_xdp;
  502. bp->tx_nr_rings = bp->tx_nr_rings_per_tc + tx_xdp;
  503. if (tcs > 1)
  504. bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs + tx_xdp;
  505. bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
  506. bp->tx_nr_rings + bp->rx_nr_rings;
  507. bp->num_stat_ctxs = bp->cp_nr_rings;
  508. /* After changing number of rx channels, update NTUPLE feature. */
  509. netdev_update_features(dev);
  510. if (netif_running(dev)) {
  511. rc = bnxt_open_nic(bp, true, false);
  512. if ((!rc) && BNXT_PF(bp)) {
  513. /* TODO CHIMP_FW: Send message to all VF's
  514. * to renable
  515. */
  516. }
  517. } else {
  518. rc = bnxt_reserve_rings(bp);
  519. }
  520. return rc;
  521. }
  522. #ifdef CONFIG_RFS_ACCEL
  523. static int bnxt_grxclsrlall(struct bnxt *bp, struct ethtool_rxnfc *cmd,
  524. u32 *rule_locs)
  525. {
  526. int i, j = 0;
  527. cmd->data = bp->ntp_fltr_count;
  528. for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
  529. struct hlist_head *head;
  530. struct bnxt_ntuple_filter *fltr;
  531. head = &bp->ntp_fltr_hash_tbl[i];
  532. rcu_read_lock();
  533. hlist_for_each_entry_rcu(fltr, head, hash) {
  534. if (j == cmd->rule_cnt)
  535. break;
  536. rule_locs[j++] = fltr->sw_id;
  537. }
  538. rcu_read_unlock();
  539. if (j == cmd->rule_cnt)
  540. break;
  541. }
  542. cmd->rule_cnt = j;
  543. return 0;
  544. }
  545. static int bnxt_grxclsrule(struct bnxt *bp, struct ethtool_rxnfc *cmd)
  546. {
  547. struct ethtool_rx_flow_spec *fs =
  548. (struct ethtool_rx_flow_spec *)&cmd->fs;
  549. struct bnxt_ntuple_filter *fltr;
  550. struct flow_keys *fkeys;
  551. int i, rc = -EINVAL;
  552. if (fs->location >= BNXT_NTP_FLTR_MAX_FLTR)
  553. return rc;
  554. for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
  555. struct hlist_head *head;
  556. head = &bp->ntp_fltr_hash_tbl[i];
  557. rcu_read_lock();
  558. hlist_for_each_entry_rcu(fltr, head, hash) {
  559. if (fltr->sw_id == fs->location)
  560. goto fltr_found;
  561. }
  562. rcu_read_unlock();
  563. }
  564. return rc;
  565. fltr_found:
  566. fkeys = &fltr->fkeys;
  567. if (fkeys->basic.n_proto == htons(ETH_P_IP)) {
  568. if (fkeys->basic.ip_proto == IPPROTO_TCP)
  569. fs->flow_type = TCP_V4_FLOW;
  570. else if (fkeys->basic.ip_proto == IPPROTO_UDP)
  571. fs->flow_type = UDP_V4_FLOW;
  572. else
  573. goto fltr_err;
  574. fs->h_u.tcp_ip4_spec.ip4src = fkeys->addrs.v4addrs.src;
  575. fs->m_u.tcp_ip4_spec.ip4src = cpu_to_be32(~0);
  576. fs->h_u.tcp_ip4_spec.ip4dst = fkeys->addrs.v4addrs.dst;
  577. fs->m_u.tcp_ip4_spec.ip4dst = cpu_to_be32(~0);
  578. fs->h_u.tcp_ip4_spec.psrc = fkeys->ports.src;
  579. fs->m_u.tcp_ip4_spec.psrc = cpu_to_be16(~0);
  580. fs->h_u.tcp_ip4_spec.pdst = fkeys->ports.dst;
  581. fs->m_u.tcp_ip4_spec.pdst = cpu_to_be16(~0);
  582. } else {
  583. int i;
  584. if (fkeys->basic.ip_proto == IPPROTO_TCP)
  585. fs->flow_type = TCP_V6_FLOW;
  586. else if (fkeys->basic.ip_proto == IPPROTO_UDP)
  587. fs->flow_type = UDP_V6_FLOW;
  588. else
  589. goto fltr_err;
  590. *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6src[0] =
  591. fkeys->addrs.v6addrs.src;
  592. *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6dst[0] =
  593. fkeys->addrs.v6addrs.dst;
  594. for (i = 0; i < 4; i++) {
  595. fs->m_u.tcp_ip6_spec.ip6src[i] = cpu_to_be32(~0);
  596. fs->m_u.tcp_ip6_spec.ip6dst[i] = cpu_to_be32(~0);
  597. }
  598. fs->h_u.tcp_ip6_spec.psrc = fkeys->ports.src;
  599. fs->m_u.tcp_ip6_spec.psrc = cpu_to_be16(~0);
  600. fs->h_u.tcp_ip6_spec.pdst = fkeys->ports.dst;
  601. fs->m_u.tcp_ip6_spec.pdst = cpu_to_be16(~0);
  602. }
  603. fs->ring_cookie = fltr->rxq;
  604. rc = 0;
  605. fltr_err:
  606. rcu_read_unlock();
  607. return rc;
  608. }
  609. #endif
  610. static u64 get_ethtool_ipv4_rss(struct bnxt *bp)
  611. {
  612. if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4)
  613. return RXH_IP_SRC | RXH_IP_DST;
  614. return 0;
  615. }
  616. static u64 get_ethtool_ipv6_rss(struct bnxt *bp)
  617. {
  618. if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6)
  619. return RXH_IP_SRC | RXH_IP_DST;
  620. return 0;
  621. }
  622. static int bnxt_grxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd)
  623. {
  624. cmd->data = 0;
  625. switch (cmd->flow_type) {
  626. case TCP_V4_FLOW:
  627. if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4)
  628. cmd->data |= RXH_IP_SRC | RXH_IP_DST |
  629. RXH_L4_B_0_1 | RXH_L4_B_2_3;
  630. cmd->data |= get_ethtool_ipv4_rss(bp);
  631. break;
  632. case UDP_V4_FLOW:
  633. if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4)
  634. cmd->data |= RXH_IP_SRC | RXH_IP_DST |
  635. RXH_L4_B_0_1 | RXH_L4_B_2_3;
  636. /* fall through */
  637. case SCTP_V4_FLOW:
  638. case AH_ESP_V4_FLOW:
  639. case AH_V4_FLOW:
  640. case ESP_V4_FLOW:
  641. case IPV4_FLOW:
  642. cmd->data |= get_ethtool_ipv4_rss(bp);
  643. break;
  644. case TCP_V6_FLOW:
  645. if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6)
  646. cmd->data |= RXH_IP_SRC | RXH_IP_DST |
  647. RXH_L4_B_0_1 | RXH_L4_B_2_3;
  648. cmd->data |= get_ethtool_ipv6_rss(bp);
  649. break;
  650. case UDP_V6_FLOW:
  651. if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6)
  652. cmd->data |= RXH_IP_SRC | RXH_IP_DST |
  653. RXH_L4_B_0_1 | RXH_L4_B_2_3;
  654. /* fall through */
  655. case SCTP_V6_FLOW:
  656. case AH_ESP_V6_FLOW:
  657. case AH_V6_FLOW:
  658. case ESP_V6_FLOW:
  659. case IPV6_FLOW:
  660. cmd->data |= get_ethtool_ipv6_rss(bp);
  661. break;
  662. }
  663. return 0;
  664. }
  665. #define RXH_4TUPLE (RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)
  666. #define RXH_2TUPLE (RXH_IP_SRC | RXH_IP_DST)
  667. static int bnxt_srxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd)
  668. {
  669. u32 rss_hash_cfg = bp->rss_hash_cfg;
  670. int tuple, rc = 0;
  671. if (cmd->data == RXH_4TUPLE)
  672. tuple = 4;
  673. else if (cmd->data == RXH_2TUPLE)
  674. tuple = 2;
  675. else if (!cmd->data)
  676. tuple = 0;
  677. else
  678. return -EINVAL;
  679. if (cmd->flow_type == TCP_V4_FLOW) {
  680. rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4;
  681. if (tuple == 4)
  682. rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4;
  683. } else if (cmd->flow_type == UDP_V4_FLOW) {
  684. if (tuple == 4 && !(bp->flags & BNXT_FLAG_UDP_RSS_CAP))
  685. return -EINVAL;
  686. rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4;
  687. if (tuple == 4)
  688. rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4;
  689. } else if (cmd->flow_type == TCP_V6_FLOW) {
  690. rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
  691. if (tuple == 4)
  692. rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
  693. } else if (cmd->flow_type == UDP_V6_FLOW) {
  694. if (tuple == 4 && !(bp->flags & BNXT_FLAG_UDP_RSS_CAP))
  695. return -EINVAL;
  696. rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
  697. if (tuple == 4)
  698. rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
  699. } else if (tuple == 4) {
  700. return -EINVAL;
  701. }
  702. switch (cmd->flow_type) {
  703. case TCP_V4_FLOW:
  704. case UDP_V4_FLOW:
  705. case SCTP_V4_FLOW:
  706. case AH_ESP_V4_FLOW:
  707. case AH_V4_FLOW:
  708. case ESP_V4_FLOW:
  709. case IPV4_FLOW:
  710. if (tuple == 2)
  711. rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4;
  712. else if (!tuple)
  713. rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4;
  714. break;
  715. case TCP_V6_FLOW:
  716. case UDP_V6_FLOW:
  717. case SCTP_V6_FLOW:
  718. case AH_ESP_V6_FLOW:
  719. case AH_V6_FLOW:
  720. case ESP_V6_FLOW:
  721. case IPV6_FLOW:
  722. if (tuple == 2)
  723. rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6;
  724. else if (!tuple)
  725. rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6;
  726. break;
  727. }
  728. if (bp->rss_hash_cfg == rss_hash_cfg)
  729. return 0;
  730. bp->rss_hash_cfg = rss_hash_cfg;
  731. if (netif_running(bp->dev)) {
  732. bnxt_close_nic(bp, false, false);
  733. rc = bnxt_open_nic(bp, false, false);
  734. }
  735. return rc;
  736. }
  737. static int bnxt_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
  738. u32 *rule_locs)
  739. {
  740. struct bnxt *bp = netdev_priv(dev);
  741. int rc = 0;
  742. switch (cmd->cmd) {
  743. #ifdef CONFIG_RFS_ACCEL
  744. case ETHTOOL_GRXRINGS:
  745. cmd->data = bp->rx_nr_rings;
  746. break;
  747. case ETHTOOL_GRXCLSRLCNT:
  748. cmd->rule_cnt = bp->ntp_fltr_count;
  749. cmd->data = BNXT_NTP_FLTR_MAX_FLTR;
  750. break;
  751. case ETHTOOL_GRXCLSRLALL:
  752. rc = bnxt_grxclsrlall(bp, cmd, (u32 *)rule_locs);
  753. break;
  754. case ETHTOOL_GRXCLSRULE:
  755. rc = bnxt_grxclsrule(bp, cmd);
  756. break;
  757. #endif
  758. case ETHTOOL_GRXFH:
  759. rc = bnxt_grxfh(bp, cmd);
  760. break;
  761. default:
  762. rc = -EOPNOTSUPP;
  763. break;
  764. }
  765. return rc;
  766. }
  767. static int bnxt_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
  768. {
  769. struct bnxt *bp = netdev_priv(dev);
  770. int rc;
  771. switch (cmd->cmd) {
  772. case ETHTOOL_SRXFH:
  773. rc = bnxt_srxfh(bp, cmd);
  774. break;
  775. default:
  776. rc = -EOPNOTSUPP;
  777. break;
  778. }
  779. return rc;
  780. }
  781. static u32 bnxt_get_rxfh_indir_size(struct net_device *dev)
  782. {
  783. return HW_HASH_INDEX_SIZE;
  784. }
  785. static u32 bnxt_get_rxfh_key_size(struct net_device *dev)
  786. {
  787. return HW_HASH_KEY_SIZE;
  788. }
  789. static int bnxt_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
  790. u8 *hfunc)
  791. {
  792. struct bnxt *bp = netdev_priv(dev);
  793. struct bnxt_vnic_info *vnic;
  794. int i = 0;
  795. if (hfunc)
  796. *hfunc = ETH_RSS_HASH_TOP;
  797. if (!bp->vnic_info)
  798. return 0;
  799. vnic = &bp->vnic_info[0];
  800. if (indir && vnic->rss_table) {
  801. for (i = 0; i < HW_HASH_INDEX_SIZE; i++)
  802. indir[i] = le16_to_cpu(vnic->rss_table[i]);
  803. }
  804. if (key && vnic->rss_hash_key)
  805. memcpy(key, vnic->rss_hash_key, HW_HASH_KEY_SIZE);
  806. return 0;
  807. }
  808. static void bnxt_get_drvinfo(struct net_device *dev,
  809. struct ethtool_drvinfo *info)
  810. {
  811. struct bnxt *bp = netdev_priv(dev);
  812. strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
  813. strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
  814. strlcpy(info->fw_version, bp->fw_ver_str, sizeof(info->fw_version));
  815. strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
  816. info->n_stats = bnxt_get_num_stats(bp);
  817. info->testinfo_len = bp->num_tests;
  818. /* TODO CHIMP_FW: eeprom dump details */
  819. info->eedump_len = 0;
  820. /* TODO CHIMP FW: reg dump details */
  821. info->regdump_len = 0;
  822. }
  823. static void bnxt_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  824. {
  825. struct bnxt *bp = netdev_priv(dev);
  826. wol->supported = 0;
  827. wol->wolopts = 0;
  828. memset(&wol->sopass, 0, sizeof(wol->sopass));
  829. if (bp->flags & BNXT_FLAG_WOL_CAP) {
  830. wol->supported = WAKE_MAGIC;
  831. if (bp->wol)
  832. wol->wolopts = WAKE_MAGIC;
  833. }
  834. }
  835. static int bnxt_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  836. {
  837. struct bnxt *bp = netdev_priv(dev);
  838. if (wol->wolopts & ~WAKE_MAGIC)
  839. return -EINVAL;
  840. if (wol->wolopts & WAKE_MAGIC) {
  841. if (!(bp->flags & BNXT_FLAG_WOL_CAP))
  842. return -EINVAL;
  843. if (!bp->wol) {
  844. if (bnxt_hwrm_alloc_wol_fltr(bp))
  845. return -EBUSY;
  846. bp->wol = 1;
  847. }
  848. } else {
  849. if (bp->wol) {
  850. if (bnxt_hwrm_free_wol_fltr(bp))
  851. return -EBUSY;
  852. bp->wol = 0;
  853. }
  854. }
  855. return 0;
  856. }
  857. u32 _bnxt_fw_to_ethtool_adv_spds(u16 fw_speeds, u8 fw_pause)
  858. {
  859. u32 speed_mask = 0;
  860. /* TODO: support 25GB, 40GB, 50GB with different cable type */
  861. /* set the advertised speeds */
  862. if (fw_speeds & BNXT_LINK_SPEED_MSK_100MB)
  863. speed_mask |= ADVERTISED_100baseT_Full;
  864. if (fw_speeds & BNXT_LINK_SPEED_MSK_1GB)
  865. speed_mask |= ADVERTISED_1000baseT_Full;
  866. if (fw_speeds & BNXT_LINK_SPEED_MSK_2_5GB)
  867. speed_mask |= ADVERTISED_2500baseX_Full;
  868. if (fw_speeds & BNXT_LINK_SPEED_MSK_10GB)
  869. speed_mask |= ADVERTISED_10000baseT_Full;
  870. if (fw_speeds & BNXT_LINK_SPEED_MSK_40GB)
  871. speed_mask |= ADVERTISED_40000baseCR4_Full;
  872. if ((fw_pause & BNXT_LINK_PAUSE_BOTH) == BNXT_LINK_PAUSE_BOTH)
  873. speed_mask |= ADVERTISED_Pause;
  874. else if (fw_pause & BNXT_LINK_PAUSE_TX)
  875. speed_mask |= ADVERTISED_Asym_Pause;
  876. else if (fw_pause & BNXT_LINK_PAUSE_RX)
  877. speed_mask |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
  878. return speed_mask;
  879. }
  880. #define BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, name)\
  881. { \
  882. if ((fw_speeds) & BNXT_LINK_SPEED_MSK_100MB) \
  883. ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
  884. 100baseT_Full); \
  885. if ((fw_speeds) & BNXT_LINK_SPEED_MSK_1GB) \
  886. ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
  887. 1000baseT_Full); \
  888. if ((fw_speeds) & BNXT_LINK_SPEED_MSK_10GB) \
  889. ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
  890. 10000baseT_Full); \
  891. if ((fw_speeds) & BNXT_LINK_SPEED_MSK_25GB) \
  892. ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
  893. 25000baseCR_Full); \
  894. if ((fw_speeds) & BNXT_LINK_SPEED_MSK_40GB) \
  895. ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
  896. 40000baseCR4_Full);\
  897. if ((fw_speeds) & BNXT_LINK_SPEED_MSK_50GB) \
  898. ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
  899. 50000baseCR2_Full);\
  900. if ((fw_speeds) & BNXT_LINK_SPEED_MSK_100GB) \
  901. ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
  902. 100000baseCR4_Full);\
  903. if ((fw_pause) & BNXT_LINK_PAUSE_RX) { \
  904. ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
  905. Pause); \
  906. if (!((fw_pause) & BNXT_LINK_PAUSE_TX)) \
  907. ethtool_link_ksettings_add_link_mode( \
  908. lk_ksettings, name, Asym_Pause);\
  909. } else if ((fw_pause) & BNXT_LINK_PAUSE_TX) { \
  910. ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
  911. Asym_Pause); \
  912. } \
  913. }
  914. #define BNXT_ETHTOOL_TO_FW_SPDS(fw_speeds, lk_ksettings, name) \
  915. { \
  916. if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
  917. 100baseT_Full) || \
  918. ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
  919. 100baseT_Half)) \
  920. (fw_speeds) |= BNXT_LINK_SPEED_MSK_100MB; \
  921. if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
  922. 1000baseT_Full) || \
  923. ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
  924. 1000baseT_Half)) \
  925. (fw_speeds) |= BNXT_LINK_SPEED_MSK_1GB; \
  926. if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
  927. 10000baseT_Full)) \
  928. (fw_speeds) |= BNXT_LINK_SPEED_MSK_10GB; \
  929. if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
  930. 25000baseCR_Full)) \
  931. (fw_speeds) |= BNXT_LINK_SPEED_MSK_25GB; \
  932. if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
  933. 40000baseCR4_Full)) \
  934. (fw_speeds) |= BNXT_LINK_SPEED_MSK_40GB; \
  935. if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
  936. 50000baseCR2_Full)) \
  937. (fw_speeds) |= BNXT_LINK_SPEED_MSK_50GB; \
  938. if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
  939. 100000baseCR4_Full)) \
  940. (fw_speeds) |= BNXT_LINK_SPEED_MSK_100GB; \
  941. }
  942. static void bnxt_fw_to_ethtool_advertised_spds(struct bnxt_link_info *link_info,
  943. struct ethtool_link_ksettings *lk_ksettings)
  944. {
  945. u16 fw_speeds = link_info->advertising;
  946. u8 fw_pause = 0;
  947. if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
  948. fw_pause = link_info->auto_pause_setting;
  949. BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, advertising);
  950. }
  951. static void bnxt_fw_to_ethtool_lp_adv(struct bnxt_link_info *link_info,
  952. struct ethtool_link_ksettings *lk_ksettings)
  953. {
  954. u16 fw_speeds = link_info->lp_auto_link_speeds;
  955. u8 fw_pause = 0;
  956. if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
  957. fw_pause = link_info->lp_pause;
  958. BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings,
  959. lp_advertising);
  960. }
  961. static void bnxt_fw_to_ethtool_support_spds(struct bnxt_link_info *link_info,
  962. struct ethtool_link_ksettings *lk_ksettings)
  963. {
  964. u16 fw_speeds = link_info->support_speeds;
  965. BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, 0, lk_ksettings, supported);
  966. ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, Pause);
  967. ethtool_link_ksettings_add_link_mode(lk_ksettings, supported,
  968. Asym_Pause);
  969. if (link_info->support_auto_speeds)
  970. ethtool_link_ksettings_add_link_mode(lk_ksettings, supported,
  971. Autoneg);
  972. }
  973. u32 bnxt_fw_to_ethtool_speed(u16 fw_link_speed)
  974. {
  975. switch (fw_link_speed) {
  976. case BNXT_LINK_SPEED_100MB:
  977. return SPEED_100;
  978. case BNXT_LINK_SPEED_1GB:
  979. return SPEED_1000;
  980. case BNXT_LINK_SPEED_2_5GB:
  981. return SPEED_2500;
  982. case BNXT_LINK_SPEED_10GB:
  983. return SPEED_10000;
  984. case BNXT_LINK_SPEED_20GB:
  985. return SPEED_20000;
  986. case BNXT_LINK_SPEED_25GB:
  987. return SPEED_25000;
  988. case BNXT_LINK_SPEED_40GB:
  989. return SPEED_40000;
  990. case BNXT_LINK_SPEED_50GB:
  991. return SPEED_50000;
  992. case BNXT_LINK_SPEED_100GB:
  993. return SPEED_100000;
  994. default:
  995. return SPEED_UNKNOWN;
  996. }
  997. }
  998. static int bnxt_get_link_ksettings(struct net_device *dev,
  999. struct ethtool_link_ksettings *lk_ksettings)
  1000. {
  1001. struct bnxt *bp = netdev_priv(dev);
  1002. struct bnxt_link_info *link_info = &bp->link_info;
  1003. struct ethtool_link_settings *base = &lk_ksettings->base;
  1004. u32 ethtool_speed;
  1005. ethtool_link_ksettings_zero_link_mode(lk_ksettings, supported);
  1006. mutex_lock(&bp->link_lock);
  1007. bnxt_fw_to_ethtool_support_spds(link_info, lk_ksettings);
  1008. ethtool_link_ksettings_zero_link_mode(lk_ksettings, advertising);
  1009. if (link_info->autoneg) {
  1010. bnxt_fw_to_ethtool_advertised_spds(link_info, lk_ksettings);
  1011. ethtool_link_ksettings_add_link_mode(lk_ksettings,
  1012. advertising, Autoneg);
  1013. base->autoneg = AUTONEG_ENABLE;
  1014. if (link_info->phy_link_status == BNXT_LINK_LINK)
  1015. bnxt_fw_to_ethtool_lp_adv(link_info, lk_ksettings);
  1016. ethtool_speed = bnxt_fw_to_ethtool_speed(link_info->link_speed);
  1017. if (!netif_carrier_ok(dev))
  1018. base->duplex = DUPLEX_UNKNOWN;
  1019. else if (link_info->duplex & BNXT_LINK_DUPLEX_FULL)
  1020. base->duplex = DUPLEX_FULL;
  1021. else
  1022. base->duplex = DUPLEX_HALF;
  1023. } else {
  1024. base->autoneg = AUTONEG_DISABLE;
  1025. ethtool_speed =
  1026. bnxt_fw_to_ethtool_speed(link_info->req_link_speed);
  1027. base->duplex = DUPLEX_HALF;
  1028. if (link_info->req_duplex == BNXT_LINK_DUPLEX_FULL)
  1029. base->duplex = DUPLEX_FULL;
  1030. }
  1031. base->speed = ethtool_speed;
  1032. base->port = PORT_NONE;
  1033. if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) {
  1034. base->port = PORT_TP;
  1035. ethtool_link_ksettings_add_link_mode(lk_ksettings, supported,
  1036. TP);
  1037. ethtool_link_ksettings_add_link_mode(lk_ksettings, advertising,
  1038. TP);
  1039. } else {
  1040. ethtool_link_ksettings_add_link_mode(lk_ksettings, supported,
  1041. FIBRE);
  1042. ethtool_link_ksettings_add_link_mode(lk_ksettings, advertising,
  1043. FIBRE);
  1044. if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC)
  1045. base->port = PORT_DA;
  1046. else if (link_info->media_type ==
  1047. PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE)
  1048. base->port = PORT_FIBRE;
  1049. }
  1050. base->phy_address = link_info->phy_addr;
  1051. mutex_unlock(&bp->link_lock);
  1052. return 0;
  1053. }
  1054. static u32 bnxt_get_fw_speed(struct net_device *dev, u32 ethtool_speed)
  1055. {
  1056. struct bnxt *bp = netdev_priv(dev);
  1057. struct bnxt_link_info *link_info = &bp->link_info;
  1058. u16 support_spds = link_info->support_speeds;
  1059. u32 fw_speed = 0;
  1060. switch (ethtool_speed) {
  1061. case SPEED_100:
  1062. if (support_spds & BNXT_LINK_SPEED_MSK_100MB)
  1063. fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB;
  1064. break;
  1065. case SPEED_1000:
  1066. if (support_spds & BNXT_LINK_SPEED_MSK_1GB)
  1067. fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB;
  1068. break;
  1069. case SPEED_2500:
  1070. if (support_spds & BNXT_LINK_SPEED_MSK_2_5GB)
  1071. fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB;
  1072. break;
  1073. case SPEED_10000:
  1074. if (support_spds & BNXT_LINK_SPEED_MSK_10GB)
  1075. fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB;
  1076. break;
  1077. case SPEED_20000:
  1078. if (support_spds & BNXT_LINK_SPEED_MSK_20GB)
  1079. fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB;
  1080. break;
  1081. case SPEED_25000:
  1082. if (support_spds & BNXT_LINK_SPEED_MSK_25GB)
  1083. fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB;
  1084. break;
  1085. case SPEED_40000:
  1086. if (support_spds & BNXT_LINK_SPEED_MSK_40GB)
  1087. fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB;
  1088. break;
  1089. case SPEED_50000:
  1090. if (support_spds & BNXT_LINK_SPEED_MSK_50GB)
  1091. fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB;
  1092. break;
  1093. case SPEED_100000:
  1094. if (support_spds & BNXT_LINK_SPEED_MSK_100GB)
  1095. fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB;
  1096. break;
  1097. default:
  1098. netdev_err(dev, "unsupported speed!\n");
  1099. break;
  1100. }
  1101. return fw_speed;
  1102. }
  1103. u16 bnxt_get_fw_auto_link_speeds(u32 advertising)
  1104. {
  1105. u16 fw_speed_mask = 0;
  1106. /* only support autoneg at speed 100, 1000, and 10000 */
  1107. if (advertising & (ADVERTISED_100baseT_Full |
  1108. ADVERTISED_100baseT_Half)) {
  1109. fw_speed_mask |= BNXT_LINK_SPEED_MSK_100MB;
  1110. }
  1111. if (advertising & (ADVERTISED_1000baseT_Full |
  1112. ADVERTISED_1000baseT_Half)) {
  1113. fw_speed_mask |= BNXT_LINK_SPEED_MSK_1GB;
  1114. }
  1115. if (advertising & ADVERTISED_10000baseT_Full)
  1116. fw_speed_mask |= BNXT_LINK_SPEED_MSK_10GB;
  1117. if (advertising & ADVERTISED_40000baseCR4_Full)
  1118. fw_speed_mask |= BNXT_LINK_SPEED_MSK_40GB;
  1119. return fw_speed_mask;
  1120. }
  1121. static int bnxt_set_link_ksettings(struct net_device *dev,
  1122. const struct ethtool_link_ksettings *lk_ksettings)
  1123. {
  1124. struct bnxt *bp = netdev_priv(dev);
  1125. struct bnxt_link_info *link_info = &bp->link_info;
  1126. const struct ethtool_link_settings *base = &lk_ksettings->base;
  1127. bool set_pause = false;
  1128. u16 fw_advertising = 0;
  1129. u32 speed;
  1130. int rc = 0;
  1131. if (!BNXT_SINGLE_PF(bp))
  1132. return -EOPNOTSUPP;
  1133. mutex_lock(&bp->link_lock);
  1134. if (base->autoneg == AUTONEG_ENABLE) {
  1135. BNXT_ETHTOOL_TO_FW_SPDS(fw_advertising, lk_ksettings,
  1136. advertising);
  1137. link_info->autoneg |= BNXT_AUTONEG_SPEED;
  1138. if (!fw_advertising)
  1139. link_info->advertising = link_info->support_auto_speeds;
  1140. else
  1141. link_info->advertising = fw_advertising;
  1142. /* any change to autoneg will cause link change, therefore the
  1143. * driver should put back the original pause setting in autoneg
  1144. */
  1145. set_pause = true;
  1146. } else {
  1147. u16 fw_speed;
  1148. u8 phy_type = link_info->phy_type;
  1149. if (phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASET ||
  1150. phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE ||
  1151. link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) {
  1152. netdev_err(dev, "10GBase-T devices must autoneg\n");
  1153. rc = -EINVAL;
  1154. goto set_setting_exit;
  1155. }
  1156. if (base->duplex == DUPLEX_HALF) {
  1157. netdev_err(dev, "HALF DUPLEX is not supported!\n");
  1158. rc = -EINVAL;
  1159. goto set_setting_exit;
  1160. }
  1161. speed = base->speed;
  1162. fw_speed = bnxt_get_fw_speed(dev, speed);
  1163. if (!fw_speed) {
  1164. rc = -EINVAL;
  1165. goto set_setting_exit;
  1166. }
  1167. link_info->req_link_speed = fw_speed;
  1168. link_info->req_duplex = BNXT_LINK_DUPLEX_FULL;
  1169. link_info->autoneg = 0;
  1170. link_info->advertising = 0;
  1171. }
  1172. if (netif_running(dev))
  1173. rc = bnxt_hwrm_set_link_setting(bp, set_pause, false);
  1174. set_setting_exit:
  1175. mutex_unlock(&bp->link_lock);
  1176. return rc;
  1177. }
  1178. static void bnxt_get_pauseparam(struct net_device *dev,
  1179. struct ethtool_pauseparam *epause)
  1180. {
  1181. struct bnxt *bp = netdev_priv(dev);
  1182. struct bnxt_link_info *link_info = &bp->link_info;
  1183. if (BNXT_VF(bp))
  1184. return;
  1185. epause->autoneg = !!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL);
  1186. epause->rx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_RX);
  1187. epause->tx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_TX);
  1188. }
  1189. static int bnxt_set_pauseparam(struct net_device *dev,
  1190. struct ethtool_pauseparam *epause)
  1191. {
  1192. int rc = 0;
  1193. struct bnxt *bp = netdev_priv(dev);
  1194. struct bnxt_link_info *link_info = &bp->link_info;
  1195. if (!BNXT_SINGLE_PF(bp))
  1196. return -EOPNOTSUPP;
  1197. if (epause->autoneg) {
  1198. if (!(link_info->autoneg & BNXT_AUTONEG_SPEED))
  1199. return -EINVAL;
  1200. link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
  1201. if (bp->hwrm_spec_code >= 0x10201)
  1202. link_info->req_flow_ctrl =
  1203. PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
  1204. } else {
  1205. /* when transition from auto pause to force pause,
  1206. * force a link change
  1207. */
  1208. if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
  1209. link_info->force_link_chng = true;
  1210. link_info->autoneg &= ~BNXT_AUTONEG_FLOW_CTRL;
  1211. link_info->req_flow_ctrl = 0;
  1212. }
  1213. if (epause->rx_pause)
  1214. link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_RX;
  1215. if (epause->tx_pause)
  1216. link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_TX;
  1217. if (netif_running(dev))
  1218. rc = bnxt_hwrm_set_pause(bp);
  1219. return rc;
  1220. }
  1221. static u32 bnxt_get_link(struct net_device *dev)
  1222. {
  1223. struct bnxt *bp = netdev_priv(dev);
  1224. /* TODO: handle MF, VF, driver close case */
  1225. return bp->link_info.link_up;
  1226. }
  1227. static int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal,
  1228. u16 ext, u16 *index, u32 *item_length,
  1229. u32 *data_length);
  1230. static int bnxt_flash_nvram(struct net_device *dev,
  1231. u16 dir_type,
  1232. u16 dir_ordinal,
  1233. u16 dir_ext,
  1234. u16 dir_attr,
  1235. const u8 *data,
  1236. size_t data_len)
  1237. {
  1238. struct bnxt *bp = netdev_priv(dev);
  1239. int rc;
  1240. struct hwrm_nvm_write_input req = {0};
  1241. dma_addr_t dma_handle;
  1242. u8 *kmem;
  1243. bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_WRITE, -1, -1);
  1244. req.dir_type = cpu_to_le16(dir_type);
  1245. req.dir_ordinal = cpu_to_le16(dir_ordinal);
  1246. req.dir_ext = cpu_to_le16(dir_ext);
  1247. req.dir_attr = cpu_to_le16(dir_attr);
  1248. req.dir_data_length = cpu_to_le32(data_len);
  1249. kmem = dma_alloc_coherent(&bp->pdev->dev, data_len, &dma_handle,
  1250. GFP_KERNEL);
  1251. if (!kmem) {
  1252. netdev_err(dev, "dma_alloc_coherent failure, length = %u\n",
  1253. (unsigned)data_len);
  1254. return -ENOMEM;
  1255. }
  1256. memcpy(kmem, data, data_len);
  1257. req.host_src_addr = cpu_to_le64(dma_handle);
  1258. rc = hwrm_send_message(bp, &req, sizeof(req), FLASH_NVRAM_TIMEOUT);
  1259. dma_free_coherent(&bp->pdev->dev, data_len, kmem, dma_handle);
  1260. if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) {
  1261. netdev_info(dev,
  1262. "PF does not have admin privileges to flash the device\n");
  1263. rc = -EACCES;
  1264. } else if (rc) {
  1265. rc = -EIO;
  1266. }
  1267. return rc;
  1268. }
  1269. static int bnxt_firmware_reset(struct net_device *dev,
  1270. u16 dir_type)
  1271. {
  1272. struct hwrm_fw_reset_input req = {0};
  1273. struct bnxt *bp = netdev_priv(dev);
  1274. int rc;
  1275. bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_RESET, -1, -1);
  1276. /* TODO: Address self-reset of APE/KONG/BONO/TANG or ungraceful reset */
  1277. /* (e.g. when firmware isn't already running) */
  1278. switch (dir_type) {
  1279. case BNX_DIR_TYPE_CHIMP_PATCH:
  1280. case BNX_DIR_TYPE_BOOTCODE:
  1281. case BNX_DIR_TYPE_BOOTCODE_2:
  1282. req.embedded_proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT;
  1283. /* Self-reset ChiMP upon next PCIe reset: */
  1284. req.selfrst_status = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST;
  1285. break;
  1286. case BNX_DIR_TYPE_APE_FW:
  1287. case BNX_DIR_TYPE_APE_PATCH:
  1288. req.embedded_proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT;
  1289. /* Self-reset APE upon next PCIe reset: */
  1290. req.selfrst_status = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST;
  1291. break;
  1292. case BNX_DIR_TYPE_KONG_FW:
  1293. case BNX_DIR_TYPE_KONG_PATCH:
  1294. req.embedded_proc_type =
  1295. FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL;
  1296. break;
  1297. case BNX_DIR_TYPE_BONO_FW:
  1298. case BNX_DIR_TYPE_BONO_PATCH:
  1299. req.embedded_proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE;
  1300. break;
  1301. case BNXT_FW_RESET_CHIP:
  1302. req.embedded_proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP;
  1303. req.selfrst_status = FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP;
  1304. break;
  1305. case BNXT_FW_RESET_AP:
  1306. req.embedded_proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP;
  1307. break;
  1308. default:
  1309. return -EINVAL;
  1310. }
  1311. rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
  1312. if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) {
  1313. netdev_info(dev,
  1314. "PF does not have admin privileges to reset the device\n");
  1315. rc = -EACCES;
  1316. } else if (rc) {
  1317. rc = -EIO;
  1318. }
  1319. return rc;
  1320. }
  1321. static int bnxt_flash_firmware(struct net_device *dev,
  1322. u16 dir_type,
  1323. const u8 *fw_data,
  1324. size_t fw_size)
  1325. {
  1326. int rc = 0;
  1327. u16 code_type;
  1328. u32 stored_crc;
  1329. u32 calculated_crc;
  1330. struct bnxt_fw_header *header = (struct bnxt_fw_header *)fw_data;
  1331. switch (dir_type) {
  1332. case BNX_DIR_TYPE_BOOTCODE:
  1333. case BNX_DIR_TYPE_BOOTCODE_2:
  1334. code_type = CODE_BOOT;
  1335. break;
  1336. case BNX_DIR_TYPE_CHIMP_PATCH:
  1337. code_type = CODE_CHIMP_PATCH;
  1338. break;
  1339. case BNX_DIR_TYPE_APE_FW:
  1340. code_type = CODE_MCTP_PASSTHRU;
  1341. break;
  1342. case BNX_DIR_TYPE_APE_PATCH:
  1343. code_type = CODE_APE_PATCH;
  1344. break;
  1345. case BNX_DIR_TYPE_KONG_FW:
  1346. code_type = CODE_KONG_FW;
  1347. break;
  1348. case BNX_DIR_TYPE_KONG_PATCH:
  1349. code_type = CODE_KONG_PATCH;
  1350. break;
  1351. case BNX_DIR_TYPE_BONO_FW:
  1352. code_type = CODE_BONO_FW;
  1353. break;
  1354. case BNX_DIR_TYPE_BONO_PATCH:
  1355. code_type = CODE_BONO_PATCH;
  1356. break;
  1357. default:
  1358. netdev_err(dev, "Unsupported directory entry type: %u\n",
  1359. dir_type);
  1360. return -EINVAL;
  1361. }
  1362. if (fw_size < sizeof(struct bnxt_fw_header)) {
  1363. netdev_err(dev, "Invalid firmware file size: %u\n",
  1364. (unsigned int)fw_size);
  1365. return -EINVAL;
  1366. }
  1367. if (header->signature != cpu_to_le32(BNXT_FIRMWARE_BIN_SIGNATURE)) {
  1368. netdev_err(dev, "Invalid firmware signature: %08X\n",
  1369. le32_to_cpu(header->signature));
  1370. return -EINVAL;
  1371. }
  1372. if (header->code_type != code_type) {
  1373. netdev_err(dev, "Expected firmware type: %d, read: %d\n",
  1374. code_type, header->code_type);
  1375. return -EINVAL;
  1376. }
  1377. if (header->device != DEVICE_CUMULUS_FAMILY) {
  1378. netdev_err(dev, "Expected firmware device family %d, read: %d\n",
  1379. DEVICE_CUMULUS_FAMILY, header->device);
  1380. return -EINVAL;
  1381. }
  1382. /* Confirm the CRC32 checksum of the file: */
  1383. stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size -
  1384. sizeof(stored_crc)));
  1385. calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc));
  1386. if (calculated_crc != stored_crc) {
  1387. netdev_err(dev, "Firmware file CRC32 checksum (%08lX) does not match calculated checksum (%08lX)\n",
  1388. (unsigned long)stored_crc,
  1389. (unsigned long)calculated_crc);
  1390. return -EINVAL;
  1391. }
  1392. rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST,
  1393. 0, 0, fw_data, fw_size);
  1394. if (rc == 0) /* Firmware update successful */
  1395. rc = bnxt_firmware_reset(dev, dir_type);
  1396. return rc;
  1397. }
  1398. static int bnxt_flash_microcode(struct net_device *dev,
  1399. u16 dir_type,
  1400. const u8 *fw_data,
  1401. size_t fw_size)
  1402. {
  1403. struct bnxt_ucode_trailer *trailer;
  1404. u32 calculated_crc;
  1405. u32 stored_crc;
  1406. int rc = 0;
  1407. if (fw_size < sizeof(struct bnxt_ucode_trailer)) {
  1408. netdev_err(dev, "Invalid microcode file size: %u\n",
  1409. (unsigned int)fw_size);
  1410. return -EINVAL;
  1411. }
  1412. trailer = (struct bnxt_ucode_trailer *)(fw_data + (fw_size -
  1413. sizeof(*trailer)));
  1414. if (trailer->sig != cpu_to_le32(BNXT_UCODE_TRAILER_SIGNATURE)) {
  1415. netdev_err(dev, "Invalid microcode trailer signature: %08X\n",
  1416. le32_to_cpu(trailer->sig));
  1417. return -EINVAL;
  1418. }
  1419. if (le16_to_cpu(trailer->dir_type) != dir_type) {
  1420. netdev_err(dev, "Expected microcode type: %d, read: %d\n",
  1421. dir_type, le16_to_cpu(trailer->dir_type));
  1422. return -EINVAL;
  1423. }
  1424. if (le16_to_cpu(trailer->trailer_length) <
  1425. sizeof(struct bnxt_ucode_trailer)) {
  1426. netdev_err(dev, "Invalid microcode trailer length: %d\n",
  1427. le16_to_cpu(trailer->trailer_length));
  1428. return -EINVAL;
  1429. }
  1430. /* Confirm the CRC32 checksum of the file: */
  1431. stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size -
  1432. sizeof(stored_crc)));
  1433. calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc));
  1434. if (calculated_crc != stored_crc) {
  1435. netdev_err(dev,
  1436. "CRC32 (%08lX) does not match calculated: %08lX\n",
  1437. (unsigned long)stored_crc,
  1438. (unsigned long)calculated_crc);
  1439. return -EINVAL;
  1440. }
  1441. rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST,
  1442. 0, 0, fw_data, fw_size);
  1443. return rc;
  1444. }
  1445. static bool bnxt_dir_type_is_ape_bin_format(u16 dir_type)
  1446. {
  1447. switch (dir_type) {
  1448. case BNX_DIR_TYPE_CHIMP_PATCH:
  1449. case BNX_DIR_TYPE_BOOTCODE:
  1450. case BNX_DIR_TYPE_BOOTCODE_2:
  1451. case BNX_DIR_TYPE_APE_FW:
  1452. case BNX_DIR_TYPE_APE_PATCH:
  1453. case BNX_DIR_TYPE_KONG_FW:
  1454. case BNX_DIR_TYPE_KONG_PATCH:
  1455. case BNX_DIR_TYPE_BONO_FW:
  1456. case BNX_DIR_TYPE_BONO_PATCH:
  1457. return true;
  1458. }
  1459. return false;
  1460. }
  1461. static bool bnxt_dir_type_is_other_exec_format(u16 dir_type)
  1462. {
  1463. switch (dir_type) {
  1464. case BNX_DIR_TYPE_AVS:
  1465. case BNX_DIR_TYPE_EXP_ROM_MBA:
  1466. case BNX_DIR_TYPE_PCIE:
  1467. case BNX_DIR_TYPE_TSCF_UCODE:
  1468. case BNX_DIR_TYPE_EXT_PHY:
  1469. case BNX_DIR_TYPE_CCM:
  1470. case BNX_DIR_TYPE_ISCSI_BOOT:
  1471. case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
  1472. case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
  1473. return true;
  1474. }
  1475. return false;
  1476. }
  1477. static bool bnxt_dir_type_is_executable(u16 dir_type)
  1478. {
  1479. return bnxt_dir_type_is_ape_bin_format(dir_type) ||
  1480. bnxt_dir_type_is_other_exec_format(dir_type);
  1481. }
  1482. static int bnxt_flash_firmware_from_file(struct net_device *dev,
  1483. u16 dir_type,
  1484. const char *filename)
  1485. {
  1486. const struct firmware *fw;
  1487. int rc;
  1488. rc = request_firmware(&fw, filename, &dev->dev);
  1489. if (rc != 0) {
  1490. netdev_err(dev, "Error %d requesting firmware file: %s\n",
  1491. rc, filename);
  1492. return rc;
  1493. }
  1494. if (bnxt_dir_type_is_ape_bin_format(dir_type) == true)
  1495. rc = bnxt_flash_firmware(dev, dir_type, fw->data, fw->size);
  1496. else if (bnxt_dir_type_is_other_exec_format(dir_type) == true)
  1497. rc = bnxt_flash_microcode(dev, dir_type, fw->data, fw->size);
  1498. else
  1499. rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST,
  1500. 0, 0, fw->data, fw->size);
  1501. release_firmware(fw);
  1502. return rc;
  1503. }
  1504. static int bnxt_flash_package_from_file(struct net_device *dev,
  1505. char *filename, u32 install_type)
  1506. {
  1507. struct bnxt *bp = netdev_priv(dev);
  1508. struct hwrm_nvm_install_update_output *resp = bp->hwrm_cmd_resp_addr;
  1509. struct hwrm_nvm_install_update_input install = {0};
  1510. const struct firmware *fw;
  1511. int rc, hwrm_err = 0;
  1512. u32 item_len;
  1513. u16 index;
  1514. bnxt_hwrm_fw_set_time(bp);
  1515. if (bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE,
  1516. BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE,
  1517. &index, &item_len, NULL) != 0) {
  1518. netdev_err(dev, "PKG update area not created in nvram\n");
  1519. return -ENOBUFS;
  1520. }
  1521. rc = request_firmware(&fw, filename, &dev->dev);
  1522. if (rc != 0) {
  1523. netdev_err(dev, "PKG error %d requesting file: %s\n",
  1524. rc, filename);
  1525. return rc;
  1526. }
  1527. if (fw->size > item_len) {
  1528. netdev_err(dev, "PKG insufficient update area in nvram: %lu",
  1529. (unsigned long)fw->size);
  1530. rc = -EFBIG;
  1531. } else {
  1532. dma_addr_t dma_handle;
  1533. u8 *kmem;
  1534. struct hwrm_nvm_modify_input modify = {0};
  1535. bnxt_hwrm_cmd_hdr_init(bp, &modify, HWRM_NVM_MODIFY, -1, -1);
  1536. modify.dir_idx = cpu_to_le16(index);
  1537. modify.len = cpu_to_le32(fw->size);
  1538. kmem = dma_alloc_coherent(&bp->pdev->dev, fw->size,
  1539. &dma_handle, GFP_KERNEL);
  1540. if (!kmem) {
  1541. netdev_err(dev,
  1542. "dma_alloc_coherent failure, length = %u\n",
  1543. (unsigned int)fw->size);
  1544. rc = -ENOMEM;
  1545. } else {
  1546. memcpy(kmem, fw->data, fw->size);
  1547. modify.host_src_addr = cpu_to_le64(dma_handle);
  1548. hwrm_err = hwrm_send_message(bp, &modify,
  1549. sizeof(modify),
  1550. FLASH_PACKAGE_TIMEOUT);
  1551. dma_free_coherent(&bp->pdev->dev, fw->size, kmem,
  1552. dma_handle);
  1553. }
  1554. }
  1555. release_firmware(fw);
  1556. if (rc || hwrm_err)
  1557. goto err_exit;
  1558. if ((install_type & 0xffff) == 0)
  1559. install_type >>= 16;
  1560. bnxt_hwrm_cmd_hdr_init(bp, &install, HWRM_NVM_INSTALL_UPDATE, -1, -1);
  1561. install.install_type = cpu_to_le32(install_type);
  1562. mutex_lock(&bp->hwrm_cmd_lock);
  1563. hwrm_err = _hwrm_send_message(bp, &install, sizeof(install),
  1564. INSTALL_PACKAGE_TIMEOUT);
  1565. if (hwrm_err) {
  1566. u8 error_code = ((struct hwrm_err_output *)resp)->cmd_err;
  1567. if (resp->error_code && error_code ==
  1568. NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR) {
  1569. install.flags |= cpu_to_le16(
  1570. NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG);
  1571. hwrm_err = _hwrm_send_message(bp, &install,
  1572. sizeof(install),
  1573. INSTALL_PACKAGE_TIMEOUT);
  1574. }
  1575. if (hwrm_err)
  1576. goto flash_pkg_exit;
  1577. }
  1578. if (resp->result) {
  1579. netdev_err(dev, "PKG install error = %d, problem_item = %d\n",
  1580. (s8)resp->result, (int)resp->problem_item);
  1581. rc = -ENOPKG;
  1582. }
  1583. flash_pkg_exit:
  1584. mutex_unlock(&bp->hwrm_cmd_lock);
  1585. err_exit:
  1586. if (hwrm_err == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) {
  1587. netdev_info(dev,
  1588. "PF does not have admin privileges to flash the device\n");
  1589. rc = -EACCES;
  1590. } else if (hwrm_err) {
  1591. rc = -EOPNOTSUPP;
  1592. }
  1593. return rc;
  1594. }
  1595. static int bnxt_flash_device(struct net_device *dev,
  1596. struct ethtool_flash *flash)
  1597. {
  1598. if (!BNXT_PF((struct bnxt *)netdev_priv(dev))) {
  1599. netdev_err(dev, "flashdev not supported from a virtual function\n");
  1600. return -EINVAL;
  1601. }
  1602. if (flash->region == ETHTOOL_FLASH_ALL_REGIONS ||
  1603. flash->region > 0xffff)
  1604. return bnxt_flash_package_from_file(dev, flash->data,
  1605. flash->region);
  1606. return bnxt_flash_firmware_from_file(dev, flash->region, flash->data);
  1607. }
  1608. static int nvm_get_dir_info(struct net_device *dev, u32 *entries, u32 *length)
  1609. {
  1610. struct bnxt *bp = netdev_priv(dev);
  1611. int rc;
  1612. struct hwrm_nvm_get_dir_info_input req = {0};
  1613. struct hwrm_nvm_get_dir_info_output *output = bp->hwrm_cmd_resp_addr;
  1614. bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_GET_DIR_INFO, -1, -1);
  1615. mutex_lock(&bp->hwrm_cmd_lock);
  1616. rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
  1617. if (!rc) {
  1618. *entries = le32_to_cpu(output->entries);
  1619. *length = le32_to_cpu(output->entry_length);
  1620. }
  1621. mutex_unlock(&bp->hwrm_cmd_lock);
  1622. return rc;
  1623. }
  1624. static int bnxt_get_eeprom_len(struct net_device *dev)
  1625. {
  1626. struct bnxt *bp = netdev_priv(dev);
  1627. if (BNXT_VF(bp))
  1628. return 0;
  1629. /* The -1 return value allows the entire 32-bit range of offsets to be
  1630. * passed via the ethtool command-line utility.
  1631. */
  1632. return -1;
  1633. }
  1634. static int bnxt_get_nvram_directory(struct net_device *dev, u32 len, u8 *data)
  1635. {
  1636. struct bnxt *bp = netdev_priv(dev);
  1637. int rc;
  1638. u32 dir_entries;
  1639. u32 entry_length;
  1640. u8 *buf;
  1641. size_t buflen;
  1642. dma_addr_t dma_handle;
  1643. struct hwrm_nvm_get_dir_entries_input req = {0};
  1644. rc = nvm_get_dir_info(dev, &dir_entries, &entry_length);
  1645. if (rc != 0)
  1646. return rc;
  1647. /* Insert 2 bytes of directory info (count and size of entries) */
  1648. if (len < 2)
  1649. return -EINVAL;
  1650. *data++ = dir_entries;
  1651. *data++ = entry_length;
  1652. len -= 2;
  1653. memset(data, 0xff, len);
  1654. buflen = dir_entries * entry_length;
  1655. buf = dma_alloc_coherent(&bp->pdev->dev, buflen, &dma_handle,
  1656. GFP_KERNEL);
  1657. if (!buf) {
  1658. netdev_err(dev, "dma_alloc_coherent failure, length = %u\n",
  1659. (unsigned)buflen);
  1660. return -ENOMEM;
  1661. }
  1662. bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_GET_DIR_ENTRIES, -1, -1);
  1663. req.host_dest_addr = cpu_to_le64(dma_handle);
  1664. rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
  1665. if (rc == 0)
  1666. memcpy(data, buf, len > buflen ? buflen : len);
  1667. dma_free_coherent(&bp->pdev->dev, buflen, buf, dma_handle);
  1668. return rc;
  1669. }
  1670. static int bnxt_get_nvram_item(struct net_device *dev, u32 index, u32 offset,
  1671. u32 length, u8 *data)
  1672. {
  1673. struct bnxt *bp = netdev_priv(dev);
  1674. int rc;
  1675. u8 *buf;
  1676. dma_addr_t dma_handle;
  1677. struct hwrm_nvm_read_input req = {0};
  1678. if (!length)
  1679. return -EINVAL;
  1680. buf = dma_alloc_coherent(&bp->pdev->dev, length, &dma_handle,
  1681. GFP_KERNEL);
  1682. if (!buf) {
  1683. netdev_err(dev, "dma_alloc_coherent failure, length = %u\n",
  1684. (unsigned)length);
  1685. return -ENOMEM;
  1686. }
  1687. bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_READ, -1, -1);
  1688. req.host_dest_addr = cpu_to_le64(dma_handle);
  1689. req.dir_idx = cpu_to_le16(index);
  1690. req.offset = cpu_to_le32(offset);
  1691. req.len = cpu_to_le32(length);
  1692. rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
  1693. if (rc == 0)
  1694. memcpy(data, buf, length);
  1695. dma_free_coherent(&bp->pdev->dev, length, buf, dma_handle);
  1696. return rc;
  1697. }
  1698. static int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal,
  1699. u16 ext, u16 *index, u32 *item_length,
  1700. u32 *data_length)
  1701. {
  1702. struct bnxt *bp = netdev_priv(dev);
  1703. int rc;
  1704. struct hwrm_nvm_find_dir_entry_input req = {0};
  1705. struct hwrm_nvm_find_dir_entry_output *output = bp->hwrm_cmd_resp_addr;
  1706. bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_FIND_DIR_ENTRY, -1, -1);
  1707. req.enables = 0;
  1708. req.dir_idx = 0;
  1709. req.dir_type = cpu_to_le16(type);
  1710. req.dir_ordinal = cpu_to_le16(ordinal);
  1711. req.dir_ext = cpu_to_le16(ext);
  1712. req.opt_ordinal = NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ;
  1713. mutex_lock(&bp->hwrm_cmd_lock);
  1714. rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
  1715. if (rc == 0) {
  1716. if (index)
  1717. *index = le16_to_cpu(output->dir_idx);
  1718. if (item_length)
  1719. *item_length = le32_to_cpu(output->dir_item_length);
  1720. if (data_length)
  1721. *data_length = le32_to_cpu(output->dir_data_length);
  1722. }
  1723. mutex_unlock(&bp->hwrm_cmd_lock);
  1724. return rc;
  1725. }
  1726. static char *bnxt_parse_pkglog(int desired_field, u8 *data, size_t datalen)
  1727. {
  1728. char *retval = NULL;
  1729. char *p;
  1730. char *value;
  1731. int field = 0;
  1732. if (datalen < 1)
  1733. return NULL;
  1734. /* null-terminate the log data (removing last '\n'): */
  1735. data[datalen - 1] = 0;
  1736. for (p = data; *p != 0; p++) {
  1737. field = 0;
  1738. retval = NULL;
  1739. while (*p != 0 && *p != '\n') {
  1740. value = p;
  1741. while (*p != 0 && *p != '\t' && *p != '\n')
  1742. p++;
  1743. if (field == desired_field)
  1744. retval = value;
  1745. if (*p != '\t')
  1746. break;
  1747. *p = 0;
  1748. field++;
  1749. p++;
  1750. }
  1751. if (*p == 0)
  1752. break;
  1753. *p = 0;
  1754. }
  1755. return retval;
  1756. }
  1757. static void bnxt_get_pkgver(struct net_device *dev)
  1758. {
  1759. struct bnxt *bp = netdev_priv(dev);
  1760. u16 index = 0;
  1761. char *pkgver;
  1762. u32 pkglen;
  1763. u8 *pkgbuf;
  1764. int len;
  1765. if (bnxt_find_nvram_item(dev, BNX_DIR_TYPE_PKG_LOG,
  1766. BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE,
  1767. &index, NULL, &pkglen) != 0)
  1768. return;
  1769. pkgbuf = kzalloc(pkglen, GFP_KERNEL);
  1770. if (!pkgbuf) {
  1771. dev_err(&bp->pdev->dev, "Unable to allocate memory for pkg version, length = %u\n",
  1772. pkglen);
  1773. return;
  1774. }
  1775. if (bnxt_get_nvram_item(dev, index, 0, pkglen, pkgbuf))
  1776. goto err;
  1777. pkgver = bnxt_parse_pkglog(BNX_PKG_LOG_FIELD_IDX_PKG_VERSION, pkgbuf,
  1778. pkglen);
  1779. if (pkgver && *pkgver != 0 && isdigit(*pkgver)) {
  1780. len = strlen(bp->fw_ver_str);
  1781. snprintf(bp->fw_ver_str + len, FW_VER_STR_LEN - len - 1,
  1782. "/pkg %s", pkgver);
  1783. }
  1784. err:
  1785. kfree(pkgbuf);
  1786. }
  1787. static int bnxt_get_eeprom(struct net_device *dev,
  1788. struct ethtool_eeprom *eeprom,
  1789. u8 *data)
  1790. {
  1791. u32 index;
  1792. u32 offset;
  1793. if (eeprom->offset == 0) /* special offset value to get directory */
  1794. return bnxt_get_nvram_directory(dev, eeprom->len, data);
  1795. index = eeprom->offset >> 24;
  1796. offset = eeprom->offset & 0xffffff;
  1797. if (index == 0) {
  1798. netdev_err(dev, "unsupported index value: %d\n", index);
  1799. return -EINVAL;
  1800. }
  1801. return bnxt_get_nvram_item(dev, index - 1, offset, eeprom->len, data);
  1802. }
  1803. static int bnxt_erase_nvram_directory(struct net_device *dev, u8 index)
  1804. {
  1805. struct bnxt *bp = netdev_priv(dev);
  1806. struct hwrm_nvm_erase_dir_entry_input req = {0};
  1807. bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_ERASE_DIR_ENTRY, -1, -1);
  1808. req.dir_idx = cpu_to_le16(index);
  1809. return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
  1810. }
  1811. static int bnxt_set_eeprom(struct net_device *dev,
  1812. struct ethtool_eeprom *eeprom,
  1813. u8 *data)
  1814. {
  1815. struct bnxt *bp = netdev_priv(dev);
  1816. u8 index, dir_op;
  1817. u16 type, ext, ordinal, attr;
  1818. if (!BNXT_PF(bp)) {
  1819. netdev_err(dev, "NVM write not supported from a virtual function\n");
  1820. return -EINVAL;
  1821. }
  1822. type = eeprom->magic >> 16;
  1823. if (type == 0xffff) { /* special value for directory operations */
  1824. index = eeprom->magic & 0xff;
  1825. dir_op = eeprom->magic >> 8;
  1826. if (index == 0)
  1827. return -EINVAL;
  1828. switch (dir_op) {
  1829. case 0x0e: /* erase */
  1830. if (eeprom->offset != ~eeprom->magic)
  1831. return -EINVAL;
  1832. return bnxt_erase_nvram_directory(dev, index - 1);
  1833. default:
  1834. return -EINVAL;
  1835. }
  1836. }
  1837. /* Create or re-write an NVM item: */
  1838. if (bnxt_dir_type_is_executable(type) == true)
  1839. return -EOPNOTSUPP;
  1840. ext = eeprom->magic & 0xffff;
  1841. ordinal = eeprom->offset >> 16;
  1842. attr = eeprom->offset & 0xffff;
  1843. return bnxt_flash_nvram(dev, type, ordinal, ext, attr, data,
  1844. eeprom->len);
  1845. }
  1846. static int bnxt_set_eee(struct net_device *dev, struct ethtool_eee *edata)
  1847. {
  1848. struct bnxt *bp = netdev_priv(dev);
  1849. struct ethtool_eee *eee = &bp->eee;
  1850. struct bnxt_link_info *link_info = &bp->link_info;
  1851. u32 advertising =
  1852. _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
  1853. int rc = 0;
  1854. if (!BNXT_SINGLE_PF(bp))
  1855. return -EOPNOTSUPP;
  1856. if (!(bp->flags & BNXT_FLAG_EEE_CAP))
  1857. return -EOPNOTSUPP;
  1858. if (!edata->eee_enabled)
  1859. goto eee_ok;
  1860. if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
  1861. netdev_warn(dev, "EEE requires autoneg\n");
  1862. return -EINVAL;
  1863. }
  1864. if (edata->tx_lpi_enabled) {
  1865. if (bp->lpi_tmr_hi && (edata->tx_lpi_timer > bp->lpi_tmr_hi ||
  1866. edata->tx_lpi_timer < bp->lpi_tmr_lo)) {
  1867. netdev_warn(dev, "Valid LPI timer range is %d and %d microsecs\n",
  1868. bp->lpi_tmr_lo, bp->lpi_tmr_hi);
  1869. return -EINVAL;
  1870. } else if (!bp->lpi_tmr_hi) {
  1871. edata->tx_lpi_timer = eee->tx_lpi_timer;
  1872. }
  1873. }
  1874. if (!edata->advertised) {
  1875. edata->advertised = advertising & eee->supported;
  1876. } else if (edata->advertised & ~advertising) {
  1877. netdev_warn(dev, "EEE advertised %x must be a subset of autoneg advertised speeds %x\n",
  1878. edata->advertised, advertising);
  1879. return -EINVAL;
  1880. }
  1881. eee->advertised = edata->advertised;
  1882. eee->tx_lpi_enabled = edata->tx_lpi_enabled;
  1883. eee->tx_lpi_timer = edata->tx_lpi_timer;
  1884. eee_ok:
  1885. eee->eee_enabled = edata->eee_enabled;
  1886. if (netif_running(dev))
  1887. rc = bnxt_hwrm_set_link_setting(bp, false, true);
  1888. return rc;
  1889. }
  1890. static int bnxt_get_eee(struct net_device *dev, struct ethtool_eee *edata)
  1891. {
  1892. struct bnxt *bp = netdev_priv(dev);
  1893. if (!(bp->flags & BNXT_FLAG_EEE_CAP))
  1894. return -EOPNOTSUPP;
  1895. *edata = bp->eee;
  1896. if (!bp->eee.eee_enabled) {
  1897. /* Preserve tx_lpi_timer so that the last value will be used
  1898. * by default when it is re-enabled.
  1899. */
  1900. edata->advertised = 0;
  1901. edata->tx_lpi_enabled = 0;
  1902. }
  1903. if (!bp->eee.eee_active)
  1904. edata->lp_advertised = 0;
  1905. return 0;
  1906. }
  1907. static int bnxt_read_sfp_module_eeprom_info(struct bnxt *bp, u16 i2c_addr,
  1908. u16 page_number, u16 start_addr,
  1909. u16 data_length, u8 *buf)
  1910. {
  1911. struct hwrm_port_phy_i2c_read_input req = {0};
  1912. struct hwrm_port_phy_i2c_read_output *output = bp->hwrm_cmd_resp_addr;
  1913. int rc, byte_offset = 0;
  1914. bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_I2C_READ, -1, -1);
  1915. req.i2c_slave_addr = i2c_addr;
  1916. req.page_number = cpu_to_le16(page_number);
  1917. req.port_id = cpu_to_le16(bp->pf.port_id);
  1918. do {
  1919. u16 xfer_size;
  1920. xfer_size = min_t(u16, data_length, BNXT_MAX_PHY_I2C_RESP_SIZE);
  1921. data_length -= xfer_size;
  1922. req.page_offset = cpu_to_le16(start_addr + byte_offset);
  1923. req.data_length = xfer_size;
  1924. req.enables = cpu_to_le32(start_addr + byte_offset ?
  1925. PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET : 0);
  1926. mutex_lock(&bp->hwrm_cmd_lock);
  1927. rc = _hwrm_send_message(bp, &req, sizeof(req),
  1928. HWRM_CMD_TIMEOUT);
  1929. if (!rc)
  1930. memcpy(buf + byte_offset, output->data, xfer_size);
  1931. mutex_unlock(&bp->hwrm_cmd_lock);
  1932. byte_offset += xfer_size;
  1933. } while (!rc && data_length > 0);
  1934. return rc;
  1935. }
  1936. static int bnxt_get_module_info(struct net_device *dev,
  1937. struct ethtool_modinfo *modinfo)
  1938. {
  1939. u8 data[SFF_DIAG_SUPPORT_OFFSET + 1];
  1940. struct bnxt *bp = netdev_priv(dev);
  1941. int rc;
  1942. /* No point in going further if phy status indicates
  1943. * module is not inserted or if it is powered down or
  1944. * if it is of type 10GBase-T
  1945. */
  1946. if (bp->link_info.module_status >
  1947. PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG)
  1948. return -EOPNOTSUPP;
  1949. /* This feature is not supported in older firmware versions */
  1950. if (bp->hwrm_spec_code < 0x10202)
  1951. return -EOPNOTSUPP;
  1952. rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0,
  1953. SFF_DIAG_SUPPORT_OFFSET + 1,
  1954. data);
  1955. if (!rc) {
  1956. u8 module_id = data[0];
  1957. u8 diag_supported = data[SFF_DIAG_SUPPORT_OFFSET];
  1958. switch (module_id) {
  1959. case SFF_MODULE_ID_SFP:
  1960. modinfo->type = ETH_MODULE_SFF_8472;
  1961. modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
  1962. if (!diag_supported)
  1963. modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
  1964. break;
  1965. case SFF_MODULE_ID_QSFP:
  1966. case SFF_MODULE_ID_QSFP_PLUS:
  1967. modinfo->type = ETH_MODULE_SFF_8436;
  1968. modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
  1969. break;
  1970. case SFF_MODULE_ID_QSFP28:
  1971. modinfo->type = ETH_MODULE_SFF_8636;
  1972. modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
  1973. break;
  1974. default:
  1975. rc = -EOPNOTSUPP;
  1976. break;
  1977. }
  1978. }
  1979. return rc;
  1980. }
  1981. static int bnxt_get_module_eeprom(struct net_device *dev,
  1982. struct ethtool_eeprom *eeprom,
  1983. u8 *data)
  1984. {
  1985. struct bnxt *bp = netdev_priv(dev);
  1986. u16 start = eeprom->offset, length = eeprom->len;
  1987. int rc = 0;
  1988. memset(data, 0, eeprom->len);
  1989. /* Read A0 portion of the EEPROM */
  1990. if (start < ETH_MODULE_SFF_8436_LEN) {
  1991. if (start + eeprom->len > ETH_MODULE_SFF_8436_LEN)
  1992. length = ETH_MODULE_SFF_8436_LEN - start;
  1993. rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0,
  1994. start, length, data);
  1995. if (rc)
  1996. return rc;
  1997. start += length;
  1998. data += length;
  1999. length = eeprom->len - length;
  2000. }
  2001. /* Read A2 portion of the EEPROM */
  2002. if (length) {
  2003. start -= ETH_MODULE_SFF_8436_LEN;
  2004. rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A2, 1,
  2005. start, length, data);
  2006. }
  2007. return rc;
  2008. }
  2009. static int bnxt_nway_reset(struct net_device *dev)
  2010. {
  2011. int rc = 0;
  2012. struct bnxt *bp = netdev_priv(dev);
  2013. struct bnxt_link_info *link_info = &bp->link_info;
  2014. if (!BNXT_SINGLE_PF(bp))
  2015. return -EOPNOTSUPP;
  2016. if (!(link_info->autoneg & BNXT_AUTONEG_SPEED))
  2017. return -EINVAL;
  2018. if (netif_running(dev))
  2019. rc = bnxt_hwrm_set_link_setting(bp, true, false);
  2020. return rc;
  2021. }
  2022. static int bnxt_set_phys_id(struct net_device *dev,
  2023. enum ethtool_phys_id_state state)
  2024. {
  2025. struct hwrm_port_led_cfg_input req = {0};
  2026. struct bnxt *bp = netdev_priv(dev);
  2027. struct bnxt_pf_info *pf = &bp->pf;
  2028. struct bnxt_led_cfg *led_cfg;
  2029. u8 led_state;
  2030. __le16 duration;
  2031. int i, rc;
  2032. if (!bp->num_leds || BNXT_VF(bp))
  2033. return -EOPNOTSUPP;
  2034. if (state == ETHTOOL_ID_ACTIVE) {
  2035. led_state = PORT_LED_CFG_REQ_LED0_STATE_BLINKALT;
  2036. duration = cpu_to_le16(500);
  2037. } else if (state == ETHTOOL_ID_INACTIVE) {
  2038. led_state = PORT_LED_CFG_REQ_LED1_STATE_DEFAULT;
  2039. duration = cpu_to_le16(0);
  2040. } else {
  2041. return -EINVAL;
  2042. }
  2043. bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_CFG, -1, -1);
  2044. req.port_id = cpu_to_le16(pf->port_id);
  2045. req.num_leds = bp->num_leds;
  2046. led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
  2047. for (i = 0; i < bp->num_leds; i++, led_cfg++) {
  2048. req.enables |= BNXT_LED_DFLT_ENABLES(i);
  2049. led_cfg->led_id = bp->leds[i].led_id;
  2050. led_cfg->led_state = led_state;
  2051. led_cfg->led_blink_on = duration;
  2052. led_cfg->led_blink_off = duration;
  2053. led_cfg->led_group_id = bp->leds[i].led_group_id;
  2054. }
  2055. rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
  2056. if (rc)
  2057. rc = -EIO;
  2058. return rc;
  2059. }
  2060. static int bnxt_hwrm_selftest_irq(struct bnxt *bp, u16 cmpl_ring)
  2061. {
  2062. struct hwrm_selftest_irq_input req = {0};
  2063. bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_SELFTEST_IRQ, cmpl_ring, -1);
  2064. return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
  2065. }
  2066. static int bnxt_test_irq(struct bnxt *bp)
  2067. {
  2068. int i;
  2069. for (i = 0; i < bp->cp_nr_rings; i++) {
  2070. u16 cmpl_ring = bp->grp_info[i].cp_fw_ring_id;
  2071. int rc;
  2072. rc = bnxt_hwrm_selftest_irq(bp, cmpl_ring);
  2073. if (rc)
  2074. return rc;
  2075. }
  2076. return 0;
  2077. }
  2078. static int bnxt_hwrm_mac_loopback(struct bnxt *bp, bool enable)
  2079. {
  2080. struct hwrm_port_mac_cfg_input req = {0};
  2081. bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_MAC_CFG, -1, -1);
  2082. req.enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_LPBK);
  2083. if (enable)
  2084. req.lpbk = PORT_MAC_CFG_REQ_LPBK_LOCAL;
  2085. else
  2086. req.lpbk = PORT_MAC_CFG_REQ_LPBK_NONE;
  2087. return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
  2088. }
  2089. static int bnxt_query_force_speeds(struct bnxt *bp, u16 *force_speeds)
  2090. {
  2091. struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
  2092. struct hwrm_port_phy_qcaps_input req = {0};
  2093. int rc;
  2094. bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1);
  2095. mutex_lock(&bp->hwrm_cmd_lock);
  2096. rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
  2097. if (!rc)
  2098. *force_speeds = le16_to_cpu(resp->supported_speeds_force_mode);
  2099. mutex_unlock(&bp->hwrm_cmd_lock);
  2100. return rc;
  2101. }
  2102. static int bnxt_disable_an_for_lpbk(struct bnxt *bp,
  2103. struct hwrm_port_phy_cfg_input *req)
  2104. {
  2105. struct bnxt_link_info *link_info = &bp->link_info;
  2106. u16 fw_advertising;
  2107. u16 fw_speed;
  2108. int rc;
  2109. if (!link_info->autoneg)
  2110. return 0;
  2111. rc = bnxt_query_force_speeds(bp, &fw_advertising);
  2112. if (rc)
  2113. return rc;
  2114. fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB;
  2115. if (netif_carrier_ok(bp->dev))
  2116. fw_speed = bp->link_info.link_speed;
  2117. else if (fw_advertising & BNXT_LINK_SPEED_MSK_10GB)
  2118. fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB;
  2119. else if (fw_advertising & BNXT_LINK_SPEED_MSK_25GB)
  2120. fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB;
  2121. else if (fw_advertising & BNXT_LINK_SPEED_MSK_40GB)
  2122. fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB;
  2123. else if (fw_advertising & BNXT_LINK_SPEED_MSK_50GB)
  2124. fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB;
  2125. req->force_link_speed = cpu_to_le16(fw_speed);
  2126. req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE |
  2127. PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
  2128. rc = hwrm_send_message(bp, req, sizeof(*req), HWRM_CMD_TIMEOUT);
  2129. req->flags = 0;
  2130. req->force_link_speed = cpu_to_le16(0);
  2131. return rc;
  2132. }
  2133. static int bnxt_hwrm_phy_loopback(struct bnxt *bp, bool enable, bool ext)
  2134. {
  2135. struct hwrm_port_phy_cfg_input req = {0};
  2136. bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
  2137. if (enable) {
  2138. bnxt_disable_an_for_lpbk(bp, &req);
  2139. if (ext)
  2140. req.lpbk = PORT_PHY_CFG_REQ_LPBK_EXTERNAL;
  2141. else
  2142. req.lpbk = PORT_PHY_CFG_REQ_LPBK_LOCAL;
  2143. } else {
  2144. req.lpbk = PORT_PHY_CFG_REQ_LPBK_NONE;
  2145. }
  2146. req.enables = cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_LPBK);
  2147. return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
  2148. }
  2149. static int bnxt_rx_loopback(struct bnxt *bp, struct bnxt_napi *bnapi,
  2150. u32 raw_cons, int pkt_size)
  2151. {
  2152. struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
  2153. struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
  2154. struct bnxt_sw_rx_bd *rx_buf;
  2155. struct rx_cmp *rxcmp;
  2156. u16 cp_cons, cons;
  2157. u8 *data;
  2158. u32 len;
  2159. int i;
  2160. cp_cons = RING_CMP(raw_cons);
  2161. rxcmp = (struct rx_cmp *)
  2162. &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
  2163. cons = rxcmp->rx_cmp_opaque;
  2164. rx_buf = &rxr->rx_buf_ring[cons];
  2165. data = rx_buf->data_ptr;
  2166. len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
  2167. if (len != pkt_size)
  2168. return -EIO;
  2169. i = ETH_ALEN;
  2170. if (!ether_addr_equal(data + i, bnapi->bp->dev->dev_addr))
  2171. return -EIO;
  2172. i += ETH_ALEN;
  2173. for ( ; i < pkt_size; i++) {
  2174. if (data[i] != (u8)(i & 0xff))
  2175. return -EIO;
  2176. }
  2177. return 0;
  2178. }
  2179. static int bnxt_poll_loopback(struct bnxt *bp, int pkt_size)
  2180. {
  2181. struct bnxt_napi *bnapi = bp->bnapi[0];
  2182. struct bnxt_cp_ring_info *cpr;
  2183. struct tx_cmp *txcmp;
  2184. int rc = -EIO;
  2185. u32 raw_cons;
  2186. u32 cons;
  2187. int i;
  2188. cpr = &bnapi->cp_ring;
  2189. raw_cons = cpr->cp_raw_cons;
  2190. for (i = 0; i < 200; i++) {
  2191. cons = RING_CMP(raw_cons);
  2192. txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
  2193. if (!TX_CMP_VALID(txcmp, raw_cons)) {
  2194. udelay(5);
  2195. continue;
  2196. }
  2197. /* The valid test of the entry must be done first before
  2198. * reading any further.
  2199. */
  2200. dma_rmb();
  2201. if (TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_CMP) {
  2202. rc = bnxt_rx_loopback(bp, bnapi, raw_cons, pkt_size);
  2203. raw_cons = NEXT_RAW_CMP(raw_cons);
  2204. raw_cons = NEXT_RAW_CMP(raw_cons);
  2205. break;
  2206. }
  2207. raw_cons = NEXT_RAW_CMP(raw_cons);
  2208. }
  2209. cpr->cp_raw_cons = raw_cons;
  2210. return rc;
  2211. }
  2212. static int bnxt_run_loopback(struct bnxt *bp)
  2213. {
  2214. struct bnxt_tx_ring_info *txr = &bp->tx_ring[0];
  2215. int pkt_size, i = 0;
  2216. struct sk_buff *skb;
  2217. dma_addr_t map;
  2218. u8 *data;
  2219. int rc;
  2220. pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_copy_thresh);
  2221. skb = netdev_alloc_skb(bp->dev, pkt_size);
  2222. if (!skb)
  2223. return -ENOMEM;
  2224. data = skb_put(skb, pkt_size);
  2225. eth_broadcast_addr(data);
  2226. i += ETH_ALEN;
  2227. ether_addr_copy(&data[i], bp->dev->dev_addr);
  2228. i += ETH_ALEN;
  2229. for ( ; i < pkt_size; i++)
  2230. data[i] = (u8)(i & 0xff);
  2231. map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size,
  2232. PCI_DMA_TODEVICE);
  2233. if (dma_mapping_error(&bp->pdev->dev, map)) {
  2234. dev_kfree_skb(skb);
  2235. return -EIO;
  2236. }
  2237. bnxt_xmit_xdp(bp, txr, map, pkt_size, 0);
  2238. /* Sync BD data before updating doorbell */
  2239. wmb();
  2240. bnxt_db_write(bp, txr->tx_doorbell, DB_KEY_TX | txr->tx_prod);
  2241. rc = bnxt_poll_loopback(bp, pkt_size);
  2242. dma_unmap_single(&bp->pdev->dev, map, pkt_size, PCI_DMA_TODEVICE);
  2243. dev_kfree_skb(skb);
  2244. return rc;
  2245. }
  2246. static int bnxt_run_fw_tests(struct bnxt *bp, u8 test_mask, u8 *test_results)
  2247. {
  2248. struct hwrm_selftest_exec_output *resp = bp->hwrm_cmd_resp_addr;
  2249. struct hwrm_selftest_exec_input req = {0};
  2250. int rc;
  2251. bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_SELFTEST_EXEC, -1, -1);
  2252. mutex_lock(&bp->hwrm_cmd_lock);
  2253. resp->test_success = 0;
  2254. req.flags = test_mask;
  2255. rc = _hwrm_send_message(bp, &req, sizeof(req), bp->test_info->timeout);
  2256. *test_results = resp->test_success;
  2257. mutex_unlock(&bp->hwrm_cmd_lock);
  2258. return rc;
  2259. }
  2260. #define BNXT_DRV_TESTS 4
  2261. #define BNXT_MACLPBK_TEST_IDX (bp->num_tests - BNXT_DRV_TESTS)
  2262. #define BNXT_PHYLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 1)
  2263. #define BNXT_EXTLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 2)
  2264. #define BNXT_IRQ_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 3)
  2265. static void bnxt_self_test(struct net_device *dev, struct ethtool_test *etest,
  2266. u64 *buf)
  2267. {
  2268. struct bnxt *bp = netdev_priv(dev);
  2269. bool do_ext_lpbk = false;
  2270. bool offline = false;
  2271. u8 test_results = 0;
  2272. u8 test_mask = 0;
  2273. int rc = 0, i;
  2274. if (!bp->num_tests || !BNXT_SINGLE_PF(bp))
  2275. return;
  2276. memset(buf, 0, sizeof(u64) * bp->num_tests);
  2277. if (!netif_running(dev)) {
  2278. etest->flags |= ETH_TEST_FL_FAILED;
  2279. return;
  2280. }
  2281. if ((etest->flags & ETH_TEST_FL_EXTERNAL_LB) &&
  2282. (bp->test_info->flags & BNXT_TEST_FL_EXT_LPBK))
  2283. do_ext_lpbk = true;
  2284. if (etest->flags & ETH_TEST_FL_OFFLINE) {
  2285. if (bp->pf.active_vfs) {
  2286. etest->flags |= ETH_TEST_FL_FAILED;
  2287. netdev_warn(dev, "Offline tests cannot be run with active VFs\n");
  2288. return;
  2289. }
  2290. offline = true;
  2291. }
  2292. for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) {
  2293. u8 bit_val = 1 << i;
  2294. if (!(bp->test_info->offline_mask & bit_val))
  2295. test_mask |= bit_val;
  2296. else if (offline)
  2297. test_mask |= bit_val;
  2298. }
  2299. if (!offline) {
  2300. bnxt_run_fw_tests(bp, test_mask, &test_results);
  2301. } else {
  2302. rc = bnxt_close_nic(bp, false, false);
  2303. if (rc)
  2304. return;
  2305. bnxt_run_fw_tests(bp, test_mask, &test_results);
  2306. buf[BNXT_MACLPBK_TEST_IDX] = 1;
  2307. bnxt_hwrm_mac_loopback(bp, true);
  2308. msleep(250);
  2309. rc = bnxt_half_open_nic(bp);
  2310. if (rc) {
  2311. bnxt_hwrm_mac_loopback(bp, false);
  2312. etest->flags |= ETH_TEST_FL_FAILED;
  2313. return;
  2314. }
  2315. if (bnxt_run_loopback(bp))
  2316. etest->flags |= ETH_TEST_FL_FAILED;
  2317. else
  2318. buf[BNXT_MACLPBK_TEST_IDX] = 0;
  2319. bnxt_hwrm_mac_loopback(bp, false);
  2320. bnxt_hwrm_phy_loopback(bp, true, false);
  2321. msleep(1000);
  2322. if (bnxt_run_loopback(bp)) {
  2323. buf[BNXT_PHYLPBK_TEST_IDX] = 1;
  2324. etest->flags |= ETH_TEST_FL_FAILED;
  2325. }
  2326. if (do_ext_lpbk) {
  2327. etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
  2328. bnxt_hwrm_phy_loopback(bp, true, true);
  2329. msleep(1000);
  2330. if (bnxt_run_loopback(bp)) {
  2331. buf[BNXT_EXTLPBK_TEST_IDX] = 1;
  2332. etest->flags |= ETH_TEST_FL_FAILED;
  2333. }
  2334. }
  2335. bnxt_hwrm_phy_loopback(bp, false, false);
  2336. bnxt_half_close_nic(bp);
  2337. rc = bnxt_open_nic(bp, false, true);
  2338. }
  2339. if (rc || bnxt_test_irq(bp)) {
  2340. buf[BNXT_IRQ_TEST_IDX] = 1;
  2341. etest->flags |= ETH_TEST_FL_FAILED;
  2342. }
  2343. for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) {
  2344. u8 bit_val = 1 << i;
  2345. if ((test_mask & bit_val) && !(test_results & bit_val)) {
  2346. buf[i] = 1;
  2347. etest->flags |= ETH_TEST_FL_FAILED;
  2348. }
  2349. }
  2350. }
  2351. static int bnxt_reset(struct net_device *dev, u32 *flags)
  2352. {
  2353. struct bnxt *bp = netdev_priv(dev);
  2354. int rc = 0;
  2355. if (!BNXT_PF(bp)) {
  2356. netdev_err(dev, "Reset is not supported from a VF\n");
  2357. return -EOPNOTSUPP;
  2358. }
  2359. if (pci_vfs_assigned(bp->pdev)) {
  2360. netdev_err(dev,
  2361. "Reset not allowed when VFs are assigned to VMs\n");
  2362. return -EBUSY;
  2363. }
  2364. if (*flags == ETH_RESET_ALL) {
  2365. /* This feature is not supported in older firmware versions */
  2366. if (bp->hwrm_spec_code < 0x10803)
  2367. return -EOPNOTSUPP;
  2368. rc = bnxt_firmware_reset(dev, BNXT_FW_RESET_CHIP);
  2369. if (!rc) {
  2370. netdev_info(dev, "Reset request successful. Reload driver to complete reset\n");
  2371. *flags = 0;
  2372. }
  2373. } else if (*flags == ETH_RESET_AP) {
  2374. /* This feature is not supported in older firmware versions */
  2375. if (bp->hwrm_spec_code < 0x10803)
  2376. return -EOPNOTSUPP;
  2377. rc = bnxt_firmware_reset(dev, BNXT_FW_RESET_AP);
  2378. if (!rc) {
  2379. netdev_info(dev, "Reset Application Processor request successful.\n");
  2380. *flags = 0;
  2381. }
  2382. } else {
  2383. rc = -EINVAL;
  2384. }
  2385. return rc;
  2386. }
  2387. static int bnxt_hwrm_dbg_dma_data(struct bnxt *bp, void *msg, int msg_len,
  2388. struct bnxt_hwrm_dbg_dma_info *info)
  2389. {
  2390. struct hwrm_dbg_cmn_output *cmn_resp = bp->hwrm_cmd_resp_addr;
  2391. struct hwrm_dbg_cmn_input *cmn_req = msg;
  2392. __le16 *seq_ptr = msg + info->seq_off;
  2393. u16 seq = 0, len, segs_off;
  2394. void *resp = cmn_resp;
  2395. dma_addr_t dma_handle;
  2396. int rc, off = 0;
  2397. void *dma_buf;
  2398. dma_buf = dma_alloc_coherent(&bp->pdev->dev, info->dma_len, &dma_handle,
  2399. GFP_KERNEL);
  2400. if (!dma_buf)
  2401. return -ENOMEM;
  2402. segs_off = offsetof(struct hwrm_dbg_coredump_list_output,
  2403. total_segments);
  2404. cmn_req->host_dest_addr = cpu_to_le64(dma_handle);
  2405. cmn_req->host_buf_len = cpu_to_le32(info->dma_len);
  2406. mutex_lock(&bp->hwrm_cmd_lock);
  2407. while (1) {
  2408. *seq_ptr = cpu_to_le16(seq);
  2409. rc = _hwrm_send_message(bp, msg, msg_len, HWRM_CMD_TIMEOUT);
  2410. if (rc)
  2411. break;
  2412. len = le16_to_cpu(*((__le16 *)(resp + info->data_len_off)));
  2413. if (!seq &&
  2414. cmn_req->req_type == cpu_to_le16(HWRM_DBG_COREDUMP_LIST)) {
  2415. info->segs = le16_to_cpu(*((__le16 *)(resp +
  2416. segs_off)));
  2417. if (!info->segs) {
  2418. rc = -EIO;
  2419. break;
  2420. }
  2421. info->dest_buf_size = info->segs *
  2422. sizeof(struct coredump_segment_record);
  2423. info->dest_buf = kmalloc(info->dest_buf_size,
  2424. GFP_KERNEL);
  2425. if (!info->dest_buf) {
  2426. rc = -ENOMEM;
  2427. break;
  2428. }
  2429. }
  2430. if (info->dest_buf) {
  2431. if ((info->seg_start + off + len) <=
  2432. BNXT_COREDUMP_BUF_LEN(info->buf_len)) {
  2433. memcpy(info->dest_buf + off, dma_buf, len);
  2434. } else {
  2435. rc = -ENOBUFS;
  2436. break;
  2437. }
  2438. }
  2439. if (cmn_req->req_type ==
  2440. cpu_to_le16(HWRM_DBG_COREDUMP_RETRIEVE))
  2441. info->dest_buf_size += len;
  2442. if (!(cmn_resp->flags & HWRM_DBG_CMN_FLAGS_MORE))
  2443. break;
  2444. seq++;
  2445. off += len;
  2446. }
  2447. mutex_unlock(&bp->hwrm_cmd_lock);
  2448. dma_free_coherent(&bp->pdev->dev, info->dma_len, dma_buf, dma_handle);
  2449. return rc;
  2450. }
  2451. static int bnxt_hwrm_dbg_coredump_list(struct bnxt *bp,
  2452. struct bnxt_coredump *coredump)
  2453. {
  2454. struct hwrm_dbg_coredump_list_input req = {0};
  2455. struct bnxt_hwrm_dbg_dma_info info = {NULL};
  2456. int rc;
  2457. bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_COREDUMP_LIST, -1, -1);
  2458. info.dma_len = COREDUMP_LIST_BUF_LEN;
  2459. info.seq_off = offsetof(struct hwrm_dbg_coredump_list_input, seq_no);
  2460. info.data_len_off = offsetof(struct hwrm_dbg_coredump_list_output,
  2461. data_len);
  2462. rc = bnxt_hwrm_dbg_dma_data(bp, &req, sizeof(req), &info);
  2463. if (!rc) {
  2464. coredump->data = info.dest_buf;
  2465. coredump->data_size = info.dest_buf_size;
  2466. coredump->total_segs = info.segs;
  2467. }
  2468. return rc;
  2469. }
  2470. static int bnxt_hwrm_dbg_coredump_initiate(struct bnxt *bp, u16 component_id,
  2471. u16 segment_id)
  2472. {
  2473. struct hwrm_dbg_coredump_initiate_input req = {0};
  2474. bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_COREDUMP_INITIATE, -1, -1);
  2475. req.component_id = cpu_to_le16(component_id);
  2476. req.segment_id = cpu_to_le16(segment_id);
  2477. return hwrm_send_message(bp, &req, sizeof(req), HWRM_COREDUMP_TIMEOUT);
  2478. }
  2479. static int bnxt_hwrm_dbg_coredump_retrieve(struct bnxt *bp, u16 component_id,
  2480. u16 segment_id, u32 *seg_len,
  2481. void *buf, u32 buf_len, u32 offset)
  2482. {
  2483. struct hwrm_dbg_coredump_retrieve_input req = {0};
  2484. struct bnxt_hwrm_dbg_dma_info info = {NULL};
  2485. int rc;
  2486. bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_COREDUMP_RETRIEVE, -1, -1);
  2487. req.component_id = cpu_to_le16(component_id);
  2488. req.segment_id = cpu_to_le16(segment_id);
  2489. info.dma_len = COREDUMP_RETRIEVE_BUF_LEN;
  2490. info.seq_off = offsetof(struct hwrm_dbg_coredump_retrieve_input,
  2491. seq_no);
  2492. info.data_len_off = offsetof(struct hwrm_dbg_coredump_retrieve_output,
  2493. data_len);
  2494. if (buf) {
  2495. info.dest_buf = buf + offset;
  2496. info.buf_len = buf_len;
  2497. info.seg_start = offset;
  2498. }
  2499. rc = bnxt_hwrm_dbg_dma_data(bp, &req, sizeof(req), &info);
  2500. if (!rc)
  2501. *seg_len = info.dest_buf_size;
  2502. return rc;
  2503. }
  2504. static void
  2505. bnxt_fill_coredump_seg_hdr(struct bnxt *bp,
  2506. struct bnxt_coredump_segment_hdr *seg_hdr,
  2507. struct coredump_segment_record *seg_rec, u32 seg_len,
  2508. int status, u32 duration, u32 instance)
  2509. {
  2510. memset(seg_hdr, 0, sizeof(*seg_hdr));
  2511. memcpy(seg_hdr->signature, "sEgM", 4);
  2512. if (seg_rec) {
  2513. seg_hdr->component_id = (__force __le32)seg_rec->component_id;
  2514. seg_hdr->segment_id = (__force __le32)seg_rec->segment_id;
  2515. seg_hdr->low_version = seg_rec->version_low;
  2516. seg_hdr->high_version = seg_rec->version_hi;
  2517. } else {
  2518. /* For hwrm_ver_get response Component id = 2
  2519. * and Segment id = 0
  2520. */
  2521. seg_hdr->component_id = cpu_to_le32(2);
  2522. seg_hdr->segment_id = 0;
  2523. }
  2524. seg_hdr->function_id = cpu_to_le16(bp->pdev->devfn);
  2525. seg_hdr->length = cpu_to_le32(seg_len);
  2526. seg_hdr->status = cpu_to_le32(status);
  2527. seg_hdr->duration = cpu_to_le32(duration);
  2528. seg_hdr->data_offset = cpu_to_le32(sizeof(*seg_hdr));
  2529. seg_hdr->instance = cpu_to_le32(instance);
  2530. }
  2531. static void
  2532. bnxt_fill_coredump_record(struct bnxt *bp, struct bnxt_coredump_record *record,
  2533. time64_t start, s16 start_utc, u16 total_segs,
  2534. int status)
  2535. {
  2536. time64_t end = ktime_get_real_seconds();
  2537. u32 os_ver_major = 0, os_ver_minor = 0;
  2538. struct tm tm;
  2539. time64_to_tm(start, 0, &tm);
  2540. memset(record, 0, sizeof(*record));
  2541. memcpy(record->signature, "cOrE", 4);
  2542. record->flags = 0;
  2543. record->low_version = 0;
  2544. record->high_version = 1;
  2545. record->asic_state = 0;
  2546. strlcpy(record->system_name, utsname()->nodename,
  2547. sizeof(record->system_name));
  2548. record->year = cpu_to_le16(tm.tm_year + 1900);
  2549. record->month = cpu_to_le16(tm.tm_mon + 1);
  2550. record->day = cpu_to_le16(tm.tm_mday);
  2551. record->hour = cpu_to_le16(tm.tm_hour);
  2552. record->minute = cpu_to_le16(tm.tm_min);
  2553. record->second = cpu_to_le16(tm.tm_sec);
  2554. record->utc_bias = cpu_to_le16(start_utc);
  2555. strcpy(record->commandline, "ethtool -w");
  2556. record->total_segments = cpu_to_le32(total_segs);
  2557. sscanf(utsname()->release, "%u.%u", &os_ver_major, &os_ver_minor);
  2558. record->os_ver_major = cpu_to_le32(os_ver_major);
  2559. record->os_ver_minor = cpu_to_le32(os_ver_minor);
  2560. strlcpy(record->os_name, utsname()->sysname, 32);
  2561. time64_to_tm(end, 0, &tm);
  2562. record->end_year = cpu_to_le16(tm.tm_year + 1900);
  2563. record->end_month = cpu_to_le16(tm.tm_mon + 1);
  2564. record->end_day = cpu_to_le16(tm.tm_mday);
  2565. record->end_hour = cpu_to_le16(tm.tm_hour);
  2566. record->end_minute = cpu_to_le16(tm.tm_min);
  2567. record->end_second = cpu_to_le16(tm.tm_sec);
  2568. record->end_utc_bias = cpu_to_le16(sys_tz.tz_minuteswest * 60);
  2569. record->asic_id1 = cpu_to_le32(bp->chip_num << 16 |
  2570. bp->ver_resp.chip_rev << 8 |
  2571. bp->ver_resp.chip_metal);
  2572. record->asic_id2 = 0;
  2573. record->coredump_status = cpu_to_le32(status);
  2574. record->ioctl_low_version = 0;
  2575. record->ioctl_high_version = 0;
  2576. }
  2577. static int bnxt_get_coredump(struct bnxt *bp, void *buf, u32 *dump_len)
  2578. {
  2579. u32 ver_get_resp_len = sizeof(struct hwrm_ver_get_output);
  2580. u32 offset = 0, seg_hdr_len, seg_record_len, buf_len = 0;
  2581. struct coredump_segment_record *seg_record = NULL;
  2582. struct bnxt_coredump_segment_hdr seg_hdr;
  2583. struct bnxt_coredump coredump = {NULL};
  2584. time64_t start_time;
  2585. u16 start_utc;
  2586. int rc = 0, i;
  2587. if (buf)
  2588. buf_len = *dump_len;
  2589. start_time = ktime_get_real_seconds();
  2590. start_utc = sys_tz.tz_minuteswest * 60;
  2591. seg_hdr_len = sizeof(seg_hdr);
  2592. /* First segment should be hwrm_ver_get response */
  2593. *dump_len = seg_hdr_len + ver_get_resp_len;
  2594. if (buf) {
  2595. bnxt_fill_coredump_seg_hdr(bp, &seg_hdr, NULL, ver_get_resp_len,
  2596. 0, 0, 0);
  2597. memcpy(buf + offset, &seg_hdr, seg_hdr_len);
  2598. offset += seg_hdr_len;
  2599. memcpy(buf + offset, &bp->ver_resp, ver_get_resp_len);
  2600. offset += ver_get_resp_len;
  2601. }
  2602. rc = bnxt_hwrm_dbg_coredump_list(bp, &coredump);
  2603. if (rc) {
  2604. netdev_err(bp->dev, "Failed to get coredump segment list\n");
  2605. goto err;
  2606. }
  2607. *dump_len += seg_hdr_len * coredump.total_segs;
  2608. seg_record = (struct coredump_segment_record *)coredump.data;
  2609. seg_record_len = sizeof(*seg_record);
  2610. for (i = 0; i < coredump.total_segs; i++) {
  2611. u16 comp_id = le16_to_cpu(seg_record->component_id);
  2612. u16 seg_id = le16_to_cpu(seg_record->segment_id);
  2613. u32 duration = 0, seg_len = 0;
  2614. unsigned long start, end;
  2615. if (buf && ((offset + seg_hdr_len) >
  2616. BNXT_COREDUMP_BUF_LEN(buf_len))) {
  2617. rc = -ENOBUFS;
  2618. goto err;
  2619. }
  2620. start = jiffies;
  2621. rc = bnxt_hwrm_dbg_coredump_initiate(bp, comp_id, seg_id);
  2622. if (rc) {
  2623. netdev_err(bp->dev,
  2624. "Failed to initiate coredump for seg = %d\n",
  2625. seg_record->segment_id);
  2626. goto next_seg;
  2627. }
  2628. /* Write segment data into the buffer */
  2629. rc = bnxt_hwrm_dbg_coredump_retrieve(bp, comp_id, seg_id,
  2630. &seg_len, buf, buf_len,
  2631. offset + seg_hdr_len);
  2632. if (rc && rc == -ENOBUFS)
  2633. goto err;
  2634. else if (rc)
  2635. netdev_err(bp->dev,
  2636. "Failed to retrieve coredump for seg = %d\n",
  2637. seg_record->segment_id);
  2638. next_seg:
  2639. end = jiffies;
  2640. duration = jiffies_to_msecs(end - start);
  2641. bnxt_fill_coredump_seg_hdr(bp, &seg_hdr, seg_record, seg_len,
  2642. rc, duration, 0);
  2643. if (buf) {
  2644. /* Write segment header into the buffer */
  2645. memcpy(buf + offset, &seg_hdr, seg_hdr_len);
  2646. offset += seg_hdr_len + seg_len;
  2647. }
  2648. *dump_len += seg_len;
  2649. seg_record =
  2650. (struct coredump_segment_record *)((u8 *)seg_record +
  2651. seg_record_len);
  2652. }
  2653. err:
  2654. if (buf)
  2655. bnxt_fill_coredump_record(bp, buf + offset, start_time,
  2656. start_utc, coredump.total_segs + 1,
  2657. rc);
  2658. kfree(coredump.data);
  2659. *dump_len += sizeof(struct bnxt_coredump_record);
  2660. if (rc == -ENOBUFS)
  2661. netdev_err(bp->dev, "Firmware returned large coredump buffer");
  2662. return rc;
  2663. }
  2664. static int bnxt_get_dump_flag(struct net_device *dev, struct ethtool_dump *dump)
  2665. {
  2666. struct bnxt *bp = netdev_priv(dev);
  2667. if (bp->hwrm_spec_code < 0x10801)
  2668. return -EOPNOTSUPP;
  2669. dump->version = bp->ver_resp.hwrm_fw_maj_8b << 24 |
  2670. bp->ver_resp.hwrm_fw_min_8b << 16 |
  2671. bp->ver_resp.hwrm_fw_bld_8b << 8 |
  2672. bp->ver_resp.hwrm_fw_rsvd_8b;
  2673. return bnxt_get_coredump(bp, NULL, &dump->len);
  2674. }
  2675. static int bnxt_get_dump_data(struct net_device *dev, struct ethtool_dump *dump,
  2676. void *buf)
  2677. {
  2678. struct bnxt *bp = netdev_priv(dev);
  2679. if (bp->hwrm_spec_code < 0x10801)
  2680. return -EOPNOTSUPP;
  2681. memset(buf, 0, dump->len);
  2682. return bnxt_get_coredump(bp, buf, &dump->len);
  2683. }
  2684. void bnxt_ethtool_init(struct bnxt *bp)
  2685. {
  2686. struct hwrm_selftest_qlist_output *resp = bp->hwrm_cmd_resp_addr;
  2687. struct hwrm_selftest_qlist_input req = {0};
  2688. struct bnxt_test_info *test_info;
  2689. struct net_device *dev = bp->dev;
  2690. int i, rc;
  2691. bnxt_get_pkgver(dev);
  2692. if (bp->hwrm_spec_code < 0x10704 || !BNXT_SINGLE_PF(bp))
  2693. return;
  2694. bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_SELFTEST_QLIST, -1, -1);
  2695. mutex_lock(&bp->hwrm_cmd_lock);
  2696. rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
  2697. if (rc)
  2698. goto ethtool_init_exit;
  2699. test_info = kzalloc(sizeof(*bp->test_info), GFP_KERNEL);
  2700. if (!test_info)
  2701. goto ethtool_init_exit;
  2702. bp->test_info = test_info;
  2703. bp->num_tests = resp->num_tests + BNXT_DRV_TESTS;
  2704. if (bp->num_tests > BNXT_MAX_TEST)
  2705. bp->num_tests = BNXT_MAX_TEST;
  2706. test_info->offline_mask = resp->offline_tests;
  2707. test_info->timeout = le16_to_cpu(resp->test_timeout);
  2708. if (!test_info->timeout)
  2709. test_info->timeout = HWRM_CMD_TIMEOUT;
  2710. for (i = 0; i < bp->num_tests; i++) {
  2711. char *str = test_info->string[i];
  2712. char *fw_str = resp->test0_name + i * 32;
  2713. if (i == BNXT_MACLPBK_TEST_IDX) {
  2714. strcpy(str, "Mac loopback test (offline)");
  2715. } else if (i == BNXT_PHYLPBK_TEST_IDX) {
  2716. strcpy(str, "Phy loopback test (offline)");
  2717. } else if (i == BNXT_EXTLPBK_TEST_IDX) {
  2718. strcpy(str, "Ext loopback test (offline)");
  2719. } else if (i == BNXT_IRQ_TEST_IDX) {
  2720. strcpy(str, "Interrupt_test (offline)");
  2721. } else {
  2722. strlcpy(str, fw_str, ETH_GSTRING_LEN);
  2723. strncat(str, " test", ETH_GSTRING_LEN - strlen(str));
  2724. if (test_info->offline_mask & (1 << i))
  2725. strncat(str, " (offline)",
  2726. ETH_GSTRING_LEN - strlen(str));
  2727. else
  2728. strncat(str, " (online)",
  2729. ETH_GSTRING_LEN - strlen(str));
  2730. }
  2731. }
  2732. ethtool_init_exit:
  2733. mutex_unlock(&bp->hwrm_cmd_lock);
  2734. }
  2735. void bnxt_ethtool_free(struct bnxt *bp)
  2736. {
  2737. kfree(bp->test_info);
  2738. bp->test_info = NULL;
  2739. }
  2740. const struct ethtool_ops bnxt_ethtool_ops = {
  2741. .get_link_ksettings = bnxt_get_link_ksettings,
  2742. .set_link_ksettings = bnxt_set_link_ksettings,
  2743. .get_pauseparam = bnxt_get_pauseparam,
  2744. .set_pauseparam = bnxt_set_pauseparam,
  2745. .get_drvinfo = bnxt_get_drvinfo,
  2746. .get_wol = bnxt_get_wol,
  2747. .set_wol = bnxt_set_wol,
  2748. .get_coalesce = bnxt_get_coalesce,
  2749. .set_coalesce = bnxt_set_coalesce,
  2750. .get_msglevel = bnxt_get_msglevel,
  2751. .set_msglevel = bnxt_set_msglevel,
  2752. .get_sset_count = bnxt_get_sset_count,
  2753. .get_strings = bnxt_get_strings,
  2754. .get_ethtool_stats = bnxt_get_ethtool_stats,
  2755. .set_ringparam = bnxt_set_ringparam,
  2756. .get_ringparam = bnxt_get_ringparam,
  2757. .get_channels = bnxt_get_channels,
  2758. .set_channels = bnxt_set_channels,
  2759. .get_rxnfc = bnxt_get_rxnfc,
  2760. .set_rxnfc = bnxt_set_rxnfc,
  2761. .get_rxfh_indir_size = bnxt_get_rxfh_indir_size,
  2762. .get_rxfh_key_size = bnxt_get_rxfh_key_size,
  2763. .get_rxfh = bnxt_get_rxfh,
  2764. .flash_device = bnxt_flash_device,
  2765. .get_eeprom_len = bnxt_get_eeprom_len,
  2766. .get_eeprom = bnxt_get_eeprom,
  2767. .set_eeprom = bnxt_set_eeprom,
  2768. .get_link = bnxt_get_link,
  2769. .get_eee = bnxt_get_eee,
  2770. .set_eee = bnxt_set_eee,
  2771. .get_module_info = bnxt_get_module_info,
  2772. .get_module_eeprom = bnxt_get_module_eeprom,
  2773. .nway_reset = bnxt_nway_reset,
  2774. .set_phys_id = bnxt_set_phys_id,
  2775. .self_test = bnxt_self_test,
  2776. .reset = bnxt_reset,
  2777. .get_dump_flag = bnxt_get_dump_flag,
  2778. .get_dump_data = bnxt_get_dump_data,
  2779. };