card_base.h 19 KB

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  1. #ifndef __CARD_BASE_H__
  2. #define __CARD_BASE_H__
  3. /**
  4. * IBM Accelerator Family 'GenWQE'
  5. *
  6. * (C) Copyright IBM Corp. 2013
  7. *
  8. * Author: Frank Haverkamp <haver@linux.vnet.ibm.com>
  9. * Author: Joerg-Stephan Vogt <jsvogt@de.ibm.com>
  10. * Author: Michael Jung <mijung@gmx.net>
  11. * Author: Michael Ruettger <michael@ibmra.de>
  12. *
  13. * This program is free software; you can redistribute it and/or modify
  14. * it under the terms of the GNU General Public License (version 2 only)
  15. * as published by the Free Software Foundation.
  16. *
  17. * This program is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. */
  22. /*
  23. * Interfaces within the GenWQE module. Defines genwqe_card and
  24. * ddcb_queue as well as ddcb_requ.
  25. */
  26. #include <linux/kernel.h>
  27. #include <linux/types.h>
  28. #include <linux/cdev.h>
  29. #include <linux/stringify.h>
  30. #include <linux/pci.h>
  31. #include <linux/semaphore.h>
  32. #include <linux/uaccess.h>
  33. #include <linux/io.h>
  34. #include <linux/debugfs.h>
  35. #include <linux/slab.h>
  36. #include <linux/genwqe/genwqe_card.h>
  37. #include "genwqe_driver.h"
  38. #define GENWQE_MSI_IRQS 4 /* Just one supported, no MSIx */
  39. #define GENWQE_MAX_VFS 15 /* maximum 15 VFs are possible */
  40. #define GENWQE_MAX_FUNCS 16 /* 1 PF and 15 VFs */
  41. #define GENWQE_CARD_NO_MAX (16 * GENWQE_MAX_FUNCS)
  42. /* Compile parameters, some of them appear in debugfs for later adjustment */
  43. #define GENWQE_DDCB_MAX 32 /* DDCBs on the work-queue */
  44. #define GENWQE_POLLING_ENABLED 0 /* in case of irqs not working */
  45. #define GENWQE_DDCB_SOFTWARE_TIMEOUT 10 /* timeout per DDCB in seconds */
  46. #define GENWQE_KILL_TIMEOUT 8 /* time until process gets killed */
  47. #define GENWQE_VF_JOBTIMEOUT_MSEC 250 /* 250 msec */
  48. #define GENWQE_PF_JOBTIMEOUT_MSEC 8000 /* 8 sec should be ok */
  49. #define GENWQE_HEALTH_CHECK_INTERVAL 4 /* <= 0: disabled */
  50. /* Sysfs attribute groups used when we create the genwqe device */
  51. extern const struct attribute_group *genwqe_attribute_groups[];
  52. /*
  53. * Config space for Genwqe5 A7:
  54. * 00:[14 10 4b 04]40 00 10 00[00 00 00 12]00 00 00 00
  55. * 10: 0c 00 00 f0 07 3c 00 00 00 00 00 00 00 00 00 00
  56. * 20: 00 00 00 00 00 00 00 00 00 00 00 00[14 10 4b 04]
  57. * 30: 00 00 00 00 50 00 00 00 00 00 00 00 00 00 00 00
  58. */
  59. #define PCI_DEVICE_GENWQE 0x044b /* Genwqe DeviceID */
  60. #define PCI_SUBSYSTEM_ID_GENWQE5 0x035f /* Genwqe A5 Subsystem-ID */
  61. #define PCI_SUBSYSTEM_ID_GENWQE5_NEW 0x044b /* Genwqe A5 Subsystem-ID */
  62. #define PCI_CLASSCODE_GENWQE5 0x1200 /* UNKNOWN */
  63. #define PCI_SUBVENDOR_ID_IBM_SRIOV 0x0000
  64. #define PCI_SUBSYSTEM_ID_GENWQE5_SRIOV 0x0000 /* Genwqe A5 Subsystem-ID */
  65. #define PCI_CLASSCODE_GENWQE5_SRIOV 0x1200 /* UNKNOWN */
  66. #define GENWQE_SLU_ARCH_REQ 2 /* Required SLU architecture level */
  67. /**
  68. * struct genwqe_reg - Genwqe data dump functionality
  69. */
  70. struct genwqe_reg {
  71. u32 addr;
  72. u32 idx;
  73. u64 val;
  74. };
  75. /*
  76. * enum genwqe_dbg_type - Specify chip unit to dump/debug
  77. */
  78. enum genwqe_dbg_type {
  79. GENWQE_DBG_UNIT0 = 0, /* captured before prev errs cleared */
  80. GENWQE_DBG_UNIT1 = 1,
  81. GENWQE_DBG_UNIT2 = 2,
  82. GENWQE_DBG_UNIT3 = 3,
  83. GENWQE_DBG_UNIT4 = 4,
  84. GENWQE_DBG_UNIT5 = 5,
  85. GENWQE_DBG_UNIT6 = 6,
  86. GENWQE_DBG_UNIT7 = 7,
  87. GENWQE_DBG_REGS = 8,
  88. GENWQE_DBG_DMA = 9,
  89. GENWQE_DBG_UNITS = 10, /* max number of possible debug units */
  90. };
  91. /* Software error injection to simulate card failures */
  92. #define GENWQE_INJECT_HARDWARE_FAILURE 0x00000001 /* injects -1 reg reads */
  93. #define GENWQE_INJECT_BUS_RESET_FAILURE 0x00000002 /* pci_bus_reset fail */
  94. #define GENWQE_INJECT_GFIR_FATAL 0x00000004 /* GFIR = 0x0000ffff */
  95. #define GENWQE_INJECT_GFIR_INFO 0x00000008 /* GFIR = 0xffff0000 */
  96. /*
  97. * Genwqe card description and management data.
  98. *
  99. * Error-handling in case of card malfunction
  100. * ------------------------------------------
  101. *
  102. * If the card is detected to be defective the outside environment
  103. * will cause the PCI layer to call deinit (the cleanup function for
  104. * probe). This is the same effect like doing a unbind/bind operation
  105. * on the card.
  106. *
  107. * The genwqe card driver implements a health checking thread which
  108. * verifies the card function. If this detects a problem the cards
  109. * device is being shutdown and restarted again, along with a reset of
  110. * the card and queue.
  111. *
  112. * All functions accessing the card device return either -EIO or -ENODEV
  113. * code to indicate the malfunction to the user. The user has to close
  114. * the file descriptor and open a new one, once the card becomes
  115. * available again.
  116. *
  117. * If the open file descriptor is setup to receive SIGIO, the signal is
  118. * genereated for the application which has to provide a handler to
  119. * react on it. If the application does not close the open
  120. * file descriptor a SIGKILL is send to enforce freeing the cards
  121. * resources.
  122. *
  123. * I did not find a different way to prevent kernel problems due to
  124. * reference counters for the cards character devices getting out of
  125. * sync. The character device deallocation does not block, even if
  126. * there is still an open file descriptor pending. If this pending
  127. * descriptor is closed, the data structures used by the character
  128. * device is reinstantiated, which will lead to the reference counter
  129. * dropping below the allowed values.
  130. *
  131. * Card recovery
  132. * -------------
  133. *
  134. * To test the internal driver recovery the following command can be used:
  135. * sudo sh -c 'echo 0xfffff > /sys/class/genwqe/genwqe0_card/err_inject'
  136. */
  137. /**
  138. * struct dma_mapping_type - Mapping type definition
  139. *
  140. * To avoid memcpying data arround we use user memory directly. To do
  141. * this we need to pin/swap-in the memory and request a DMA address
  142. * for it.
  143. */
  144. enum dma_mapping_type {
  145. GENWQE_MAPPING_RAW = 0, /* contignous memory buffer */
  146. GENWQE_MAPPING_SGL_TEMP, /* sglist dynamically used */
  147. GENWQE_MAPPING_SGL_PINNED, /* sglist used with pinning */
  148. };
  149. /**
  150. * struct dma_mapping - Information about memory mappings done by the driver
  151. */
  152. struct dma_mapping {
  153. enum dma_mapping_type type;
  154. void *u_vaddr; /* user-space vaddr/non-aligned */
  155. void *k_vaddr; /* kernel-space vaddr/non-aligned */
  156. dma_addr_t dma_addr; /* physical DMA address */
  157. struct page **page_list; /* list of pages used by user buff */
  158. dma_addr_t *dma_list; /* list of dma addresses per page */
  159. unsigned int nr_pages; /* number of pages */
  160. unsigned int size; /* size in bytes */
  161. struct list_head card_list; /* list of usr_maps for card */
  162. struct list_head pin_list; /* list of pinned memory for dev */
  163. int write; /* writable map? useful in unmapping */
  164. };
  165. static inline void genwqe_mapping_init(struct dma_mapping *m,
  166. enum dma_mapping_type type)
  167. {
  168. memset(m, 0, sizeof(*m));
  169. m->type = type;
  170. m->write = 1; /* Assume the maps we create are R/W */
  171. }
  172. /**
  173. * struct ddcb_queue - DDCB queue data
  174. * @ddcb_max: Number of DDCBs on the queue
  175. * @ddcb_next: Next free DDCB
  176. * @ddcb_act: Next DDCB supposed to finish
  177. * @ddcb_seq: Sequence number of last DDCB
  178. * @ddcbs_in_flight: Currently enqueued DDCBs
  179. * @ddcbs_completed: Number of already completed DDCBs
  180. * @return_on_busy: Number of -EBUSY returns on full queue
  181. * @wait_on_busy: Number of waits on full queue
  182. * @ddcb_daddr: DMA address of first DDCB in the queue
  183. * @ddcb_vaddr: Kernel virtual address of first DDCB in the queue
  184. * @ddcb_req: Associated requests (one per DDCB)
  185. * @ddcb_waitqs: Associated wait queues (one per DDCB)
  186. * @ddcb_lock: Lock to protect queuing operations
  187. * @ddcb_waitq: Wait on next DDCB finishing
  188. */
  189. struct ddcb_queue {
  190. int ddcb_max; /* amount of DDCBs */
  191. int ddcb_next; /* next available DDCB num */
  192. int ddcb_act; /* DDCB to be processed */
  193. u16 ddcb_seq; /* slc seq num */
  194. unsigned int ddcbs_in_flight; /* number of ddcbs in processing */
  195. unsigned int ddcbs_completed;
  196. unsigned int ddcbs_max_in_flight;
  197. unsigned int return_on_busy; /* how many times -EBUSY? */
  198. unsigned int wait_on_busy;
  199. dma_addr_t ddcb_daddr; /* DMA address */
  200. struct ddcb *ddcb_vaddr; /* kernel virtual addr for DDCBs */
  201. struct ddcb_requ **ddcb_req; /* ddcb processing parameter */
  202. wait_queue_head_t *ddcb_waitqs; /* waitqueue per ddcb */
  203. spinlock_t ddcb_lock; /* exclusive access to queue */
  204. wait_queue_head_t busy_waitq; /* wait for ddcb processing */
  205. /* registers or the respective queue to be used */
  206. u32 IO_QUEUE_CONFIG;
  207. u32 IO_QUEUE_STATUS;
  208. u32 IO_QUEUE_SEGMENT;
  209. u32 IO_QUEUE_INITSQN;
  210. u32 IO_QUEUE_WRAP;
  211. u32 IO_QUEUE_OFFSET;
  212. u32 IO_QUEUE_WTIME;
  213. u32 IO_QUEUE_ERRCNTS;
  214. u32 IO_QUEUE_LRW;
  215. };
  216. /*
  217. * GFIR, SLU_UNITCFG, APP_UNITCFG
  218. * 8 Units with FIR/FEC + 64 * 2ndary FIRS/FEC.
  219. */
  220. #define GENWQE_FFDC_REGS (3 + (8 * (2 + 2 * 64)))
  221. struct genwqe_ffdc {
  222. unsigned int entries;
  223. struct genwqe_reg *regs;
  224. };
  225. /**
  226. * struct genwqe_dev - GenWQE device information
  227. * @card_state: Card operation state, see above
  228. * @ffdc: First Failure Data Capture buffers for each unit
  229. * @card_thread: Working thread to operate the DDCB queue
  230. * @card_waitq: Wait queue used in card_thread
  231. * @queue: DDCB queue
  232. * @health_thread: Card monitoring thread (only for PFs)
  233. * @health_waitq: Wait queue used in health_thread
  234. * @pci_dev: Associated PCI device (function)
  235. * @mmio: Base address of 64-bit register space
  236. * @mmio_len: Length of register area
  237. * @file_lock: Lock to protect access to file_list
  238. * @file_list: List of all processes with open GenWQE file descriptors
  239. *
  240. * This struct contains all information needed to communicate with a
  241. * GenWQE card. It is initialized when a GenWQE device is found and
  242. * destroyed when it goes away. It holds data to maintain the queue as
  243. * well as data needed to feed the user interfaces.
  244. */
  245. struct genwqe_dev {
  246. enum genwqe_card_state card_state;
  247. spinlock_t print_lock;
  248. int card_idx; /* card index 0..CARD_NO_MAX-1 */
  249. u64 flags; /* general flags */
  250. /* FFDC data gathering */
  251. struct genwqe_ffdc ffdc[GENWQE_DBG_UNITS];
  252. /* DDCB workqueue */
  253. struct task_struct *card_thread;
  254. wait_queue_head_t queue_waitq;
  255. struct ddcb_queue queue; /* genwqe DDCB queue */
  256. unsigned int irqs_processed;
  257. /* Card health checking thread */
  258. struct task_struct *health_thread;
  259. wait_queue_head_t health_waitq;
  260. int use_platform_recovery; /* use platform recovery mechanisms */
  261. /* char device */
  262. dev_t devnum_genwqe; /* major/minor num card */
  263. struct class *class_genwqe; /* reference to class object */
  264. struct device *dev; /* for device creation */
  265. struct cdev cdev_genwqe; /* char device for card */
  266. struct dentry *debugfs_root; /* debugfs card root directory */
  267. struct dentry *debugfs_genwqe; /* debugfs driver root directory */
  268. /* pci resources */
  269. struct pci_dev *pci_dev; /* PCI device */
  270. void __iomem *mmio; /* BAR-0 MMIO start */
  271. unsigned long mmio_len;
  272. int num_vfs;
  273. u32 vf_jobtimeout_msec[GENWQE_MAX_VFS];
  274. int is_privileged; /* access to all regs possible */
  275. /* config regs which we need often */
  276. u64 slu_unitcfg;
  277. u64 app_unitcfg;
  278. u64 softreset;
  279. u64 err_inject;
  280. u64 last_gfir;
  281. char app_name[5];
  282. spinlock_t file_lock; /* lock for open files */
  283. struct list_head file_list; /* list of open files */
  284. /* debugfs parameters */
  285. int ddcb_software_timeout; /* wait until DDCB times out */
  286. int skip_recovery; /* circumvention if recovery fails */
  287. int kill_timeout; /* wait after sending SIGKILL */
  288. };
  289. /**
  290. * enum genwqe_requ_state - State of a DDCB execution request
  291. */
  292. enum genwqe_requ_state {
  293. GENWQE_REQU_NEW = 0,
  294. GENWQE_REQU_ENQUEUED = 1,
  295. GENWQE_REQU_TAPPED = 2,
  296. GENWQE_REQU_FINISHED = 3,
  297. GENWQE_REQU_STATE_MAX,
  298. };
  299. /**
  300. * struct genwqe_sgl - Scatter gather list describing user-space memory
  301. * @sgl: scatter gather list needs to be 128 byte aligned
  302. * @sgl_dma_addr: dma address of sgl
  303. * @sgl_size: size of area used for sgl
  304. * @user_addr: user-space address of memory area
  305. * @user_size: size of user-space memory area
  306. * @page: buffer for partial pages if needed
  307. * @page_dma_addr: dma address partial pages
  308. * @write: should we write it back to userspace?
  309. */
  310. struct genwqe_sgl {
  311. dma_addr_t sgl_dma_addr;
  312. struct sg_entry *sgl;
  313. size_t sgl_size; /* size of sgl */
  314. void __user *user_addr; /* user-space base-address */
  315. size_t user_size; /* size of memory area */
  316. int write;
  317. unsigned long nr_pages;
  318. unsigned long fpage_offs;
  319. size_t fpage_size;
  320. size_t lpage_size;
  321. void *fpage;
  322. dma_addr_t fpage_dma_addr;
  323. void *lpage;
  324. dma_addr_t lpage_dma_addr;
  325. };
  326. int genwqe_alloc_sync_sgl(struct genwqe_dev *cd, struct genwqe_sgl *sgl,
  327. void __user *user_addr, size_t user_size, int write);
  328. int genwqe_setup_sgl(struct genwqe_dev *cd, struct genwqe_sgl *sgl,
  329. dma_addr_t *dma_list);
  330. int genwqe_free_sync_sgl(struct genwqe_dev *cd, struct genwqe_sgl *sgl);
  331. /**
  332. * struct ddcb_requ - Kernel internal representation of the DDCB request
  333. * @cmd: User space representation of the DDCB execution request
  334. */
  335. struct ddcb_requ {
  336. /* kernel specific content */
  337. enum genwqe_requ_state req_state; /* request status */
  338. int num; /* ddcb_no for this request */
  339. struct ddcb_queue *queue; /* associated queue */
  340. struct dma_mapping dma_mappings[DDCB_FIXUPS];
  341. struct genwqe_sgl sgls[DDCB_FIXUPS];
  342. /* kernel/user shared content */
  343. struct genwqe_ddcb_cmd cmd; /* ddcb_no for this request */
  344. struct genwqe_debug_data debug_data;
  345. };
  346. /**
  347. * struct genwqe_file - Information for open GenWQE devices
  348. */
  349. struct genwqe_file {
  350. struct genwqe_dev *cd;
  351. struct genwqe_driver *client;
  352. struct file *filp;
  353. struct fasync_struct *async_queue;
  354. struct pid *opener;
  355. struct list_head list; /* entry in list of open files */
  356. spinlock_t map_lock; /* lock for dma_mappings */
  357. struct list_head map_list; /* list of dma_mappings */
  358. spinlock_t pin_lock; /* lock for pinned memory */
  359. struct list_head pin_list; /* list of pinned memory */
  360. };
  361. int genwqe_setup_service_layer(struct genwqe_dev *cd); /* for PF only */
  362. int genwqe_finish_queue(struct genwqe_dev *cd);
  363. int genwqe_release_service_layer(struct genwqe_dev *cd);
  364. /**
  365. * genwqe_get_slu_id() - Read Service Layer Unit Id
  366. * Return: 0x00: Development code
  367. * 0x01: SLC1 (old)
  368. * 0x02: SLC2 (sept2012)
  369. * 0x03: SLC2 (feb2013, generic driver)
  370. */
  371. static inline int genwqe_get_slu_id(struct genwqe_dev *cd)
  372. {
  373. return (int)((cd->slu_unitcfg >> 32) & 0xff);
  374. }
  375. int genwqe_ddcbs_in_flight(struct genwqe_dev *cd);
  376. u8 genwqe_card_type(struct genwqe_dev *cd);
  377. int genwqe_card_reset(struct genwqe_dev *cd);
  378. int genwqe_set_interrupt_capability(struct genwqe_dev *cd, int count);
  379. void genwqe_reset_interrupt_capability(struct genwqe_dev *cd);
  380. int genwqe_device_create(struct genwqe_dev *cd);
  381. int genwqe_device_remove(struct genwqe_dev *cd);
  382. /* debugfs */
  383. int genwqe_init_debugfs(struct genwqe_dev *cd);
  384. void genqwe_exit_debugfs(struct genwqe_dev *cd);
  385. int genwqe_read_softreset(struct genwqe_dev *cd);
  386. /* Hardware Circumventions */
  387. int genwqe_recovery_on_fatal_gfir_required(struct genwqe_dev *cd);
  388. int genwqe_flash_readback_fails(struct genwqe_dev *cd);
  389. /**
  390. * genwqe_write_vreg() - Write register in VF window
  391. * @cd: genwqe device
  392. * @reg: register address
  393. * @val: value to write
  394. * @func: 0: PF, 1: VF0, ..., 15: VF14
  395. */
  396. int genwqe_write_vreg(struct genwqe_dev *cd, u32 reg, u64 val, int func);
  397. /**
  398. * genwqe_read_vreg() - Read register in VF window
  399. * @cd: genwqe device
  400. * @reg: register address
  401. * @func: 0: PF, 1: VF0, ..., 15: VF14
  402. *
  403. * Return: content of the register
  404. */
  405. u64 genwqe_read_vreg(struct genwqe_dev *cd, u32 reg, int func);
  406. /* FFDC Buffer Management */
  407. int genwqe_ffdc_buff_size(struct genwqe_dev *cd, int unit_id);
  408. int genwqe_ffdc_buff_read(struct genwqe_dev *cd, int unit_id,
  409. struct genwqe_reg *regs, unsigned int max_regs);
  410. int genwqe_read_ffdc_regs(struct genwqe_dev *cd, struct genwqe_reg *regs,
  411. unsigned int max_regs, int all);
  412. int genwqe_ffdc_dump_dma(struct genwqe_dev *cd,
  413. struct genwqe_reg *regs, unsigned int max_regs);
  414. int genwqe_init_debug_data(struct genwqe_dev *cd,
  415. struct genwqe_debug_data *d);
  416. void genwqe_init_crc32(void);
  417. int genwqe_read_app_id(struct genwqe_dev *cd, char *app_name, int len);
  418. /* Memory allocation/deallocation; dma address handling */
  419. int genwqe_user_vmap(struct genwqe_dev *cd, struct dma_mapping *m,
  420. void *uaddr, unsigned long size);
  421. int genwqe_user_vunmap(struct genwqe_dev *cd, struct dma_mapping *m);
  422. static inline bool dma_mapping_used(struct dma_mapping *m)
  423. {
  424. if (!m)
  425. return false;
  426. return m->size != 0;
  427. }
  428. /**
  429. * __genwqe_execute_ddcb() - Execute DDCB request with addr translation
  430. *
  431. * This function will do the address translation changes to the DDCBs
  432. * according to the definitions required by the ATS field. It looks up
  433. * the memory allocation buffer or does vmap/vunmap for the respective
  434. * user-space buffers, inclusive page pinning and scatter gather list
  435. * buildup and teardown.
  436. */
  437. int __genwqe_execute_ddcb(struct genwqe_dev *cd,
  438. struct genwqe_ddcb_cmd *cmd, unsigned int f_flags);
  439. /**
  440. * __genwqe_execute_raw_ddcb() - Execute DDCB request without addr translation
  441. *
  442. * This version will not do address translation or any modification of
  443. * the DDCB data. It is used e.g. for the MoveFlash DDCB which is
  444. * entirely prepared by the driver itself. That means the appropriate
  445. * DMA addresses are already in the DDCB and do not need any
  446. * modification.
  447. */
  448. int __genwqe_execute_raw_ddcb(struct genwqe_dev *cd,
  449. struct genwqe_ddcb_cmd *cmd,
  450. unsigned int f_flags);
  451. int __genwqe_enqueue_ddcb(struct genwqe_dev *cd,
  452. struct ddcb_requ *req,
  453. unsigned int f_flags);
  454. int __genwqe_wait_ddcb(struct genwqe_dev *cd, struct ddcb_requ *req);
  455. int __genwqe_purge_ddcb(struct genwqe_dev *cd, struct ddcb_requ *req);
  456. /* register access */
  457. int __genwqe_writeq(struct genwqe_dev *cd, u64 byte_offs, u64 val);
  458. u64 __genwqe_readq(struct genwqe_dev *cd, u64 byte_offs);
  459. int __genwqe_writel(struct genwqe_dev *cd, u64 byte_offs, u32 val);
  460. u32 __genwqe_readl(struct genwqe_dev *cd, u64 byte_offs);
  461. void *__genwqe_alloc_consistent(struct genwqe_dev *cd, size_t size,
  462. dma_addr_t *dma_handle);
  463. void __genwqe_free_consistent(struct genwqe_dev *cd, size_t size,
  464. void *vaddr, dma_addr_t dma_handle);
  465. /* Base clock frequency in MHz */
  466. int genwqe_base_clock_frequency(struct genwqe_dev *cd);
  467. /* Before FFDC is captured the traps should be stopped. */
  468. void genwqe_stop_traps(struct genwqe_dev *cd);
  469. void genwqe_start_traps(struct genwqe_dev *cd);
  470. /* Hardware circumvention */
  471. bool genwqe_need_err_masking(struct genwqe_dev *cd);
  472. /**
  473. * genwqe_is_privileged() - Determine operation mode for PCI function
  474. *
  475. * On Intel with SRIOV support we see:
  476. * PF: is_physfn = 1 is_virtfn = 0
  477. * VF: is_physfn = 0 is_virtfn = 1
  478. *
  479. * On Systems with no SRIOV support _and_ virtualized systems we get:
  480. * is_physfn = 0 is_virtfn = 0
  481. *
  482. * Other vendors have individual pci device ids to distinguish between
  483. * virtual function drivers and physical function drivers. GenWQE
  484. * unfortunately has just on pci device id for both, VFs and PF.
  485. *
  486. * The following code is used to distinguish if the card is running in
  487. * privileged mode, either as true PF or in a virtualized system with
  488. * full register access e.g. currently on PowerPC.
  489. *
  490. * if (pci_dev->is_virtfn)
  491. * cd->is_privileged = 0;
  492. * else
  493. * cd->is_privileged = (__genwqe_readq(cd, IO_SLU_BITSTREAM)
  494. * != IO_ILLEGAL_VALUE);
  495. */
  496. static inline int genwqe_is_privileged(struct genwqe_dev *cd)
  497. {
  498. return cd->is_privileged;
  499. }
  500. #endif /* __CARD_BASE_H__ */