rts5227.c 11 KB

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  1. /* Driver for Realtek PCI-Express card reader
  2. *
  3. * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License as published by the
  7. * Free Software Foundation; either version 2, or (at your option) any
  8. * later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along
  16. * with this program; if not, see <http://www.gnu.org/licenses/>.
  17. *
  18. * Author:
  19. * Wei WANG <wei_wang@realsil.com.cn>
  20. * Roger Tseng <rogerable@realtek.com>
  21. */
  22. #include <linux/module.h>
  23. #include <linux/delay.h>
  24. #include <linux/rtsx_pci.h>
  25. #include "rtsx_pcr.h"
  26. static u8 rts5227_get_ic_version(struct rtsx_pcr *pcr)
  27. {
  28. u8 val;
  29. rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
  30. return val & 0x0F;
  31. }
  32. static void rts5227_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
  33. {
  34. u8 driving_3v3[4][3] = {
  35. {0x13, 0x13, 0x13},
  36. {0x96, 0x96, 0x96},
  37. {0x7F, 0x7F, 0x7F},
  38. {0x96, 0x96, 0x96},
  39. };
  40. u8 driving_1v8[4][3] = {
  41. {0x99, 0x99, 0x99},
  42. {0xAA, 0xAA, 0xAA},
  43. {0xFE, 0xFE, 0xFE},
  44. {0xB3, 0xB3, 0xB3},
  45. };
  46. u8 (*driving)[3], drive_sel;
  47. if (voltage == OUTPUT_3V3) {
  48. driving = driving_3v3;
  49. drive_sel = pcr->sd30_drive_sel_3v3;
  50. } else {
  51. driving = driving_1v8;
  52. drive_sel = pcr->sd30_drive_sel_1v8;
  53. }
  54. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
  55. 0xFF, driving[drive_sel][0]);
  56. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
  57. 0xFF, driving[drive_sel][1]);
  58. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
  59. 0xFF, driving[drive_sel][2]);
  60. }
  61. static void rts5227_fetch_vendor_settings(struct rtsx_pcr *pcr)
  62. {
  63. u32 reg;
  64. rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, &reg);
  65. pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
  66. if (!rtsx_vendor_setting_valid(reg))
  67. return;
  68. pcr->aspm_en = rtsx_reg_to_aspm(reg);
  69. pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
  70. pcr->card_drive_sel &= 0x3F;
  71. pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
  72. rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, &reg);
  73. pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
  74. pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
  75. if (rtsx_reg_check_reverse_socket(reg))
  76. pcr->flags |= PCR_REVERSE_SOCKET;
  77. }
  78. static void rts5227_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
  79. {
  80. /* Set relink_time to 0 */
  81. rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, 0xFF, 0);
  82. rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, 0xFF, 0);
  83. rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, 0x01, 0);
  84. if (pm_state == HOST_ENTER_S3)
  85. rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x10);
  86. rtsx_pci_write_register(pcr, FPDCTL, 0x03, 0x03);
  87. }
  88. static int rts5227_extra_init_hw(struct rtsx_pcr *pcr)
  89. {
  90. u16 cap;
  91. rtsx_pci_init_cmd(pcr);
  92. /* Configure GPIO as output */
  93. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
  94. /* Reset ASPM state to default value */
  95. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
  96. /* Switch LDO3318 source from DV33 to card_3v3 */
  97. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
  98. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
  99. /* LED shine disabled, set initial shine cycle period */
  100. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
  101. /* Configure LTR */
  102. pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &cap);
  103. if (cap & PCI_EXP_DEVCTL2_LTR_EN)
  104. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LTR_CTL, 0xFF, 0xA3);
  105. /* Configure OBFF */
  106. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OBFF_CFG, 0x03, 0x03);
  107. /* Configure driving */
  108. rts5227_fill_driving(pcr, OUTPUT_3V3);
  109. /* Configure force_clock_req */
  110. if (pcr->flags & PCR_REVERSE_SOCKET)
  111. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB8, 0xB8);
  112. else
  113. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB8, 0x88);
  114. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, pcr->reg_pm_ctrl3, 0x10, 0x00);
  115. return rtsx_pci_send_cmd(pcr, 100);
  116. }
  117. static int rts5227_optimize_phy(struct rtsx_pcr *pcr)
  118. {
  119. int err;
  120. err = rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00);
  121. if (err < 0)
  122. return err;
  123. /* Optimize RX sensitivity */
  124. return rtsx_pci_write_phy_register(pcr, 0x00, 0xBA42);
  125. }
  126. static int rts5227_turn_on_led(struct rtsx_pcr *pcr)
  127. {
  128. return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
  129. }
  130. static int rts5227_turn_off_led(struct rtsx_pcr *pcr)
  131. {
  132. return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
  133. }
  134. static int rts5227_enable_auto_blink(struct rtsx_pcr *pcr)
  135. {
  136. return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
  137. }
  138. static int rts5227_disable_auto_blink(struct rtsx_pcr *pcr)
  139. {
  140. return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
  141. }
  142. static int rts5227_card_power_on(struct rtsx_pcr *pcr, int card)
  143. {
  144. int err;
  145. rtsx_pci_init_cmd(pcr);
  146. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
  147. SD_POWER_MASK, SD_PARTIAL_POWER_ON);
  148. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
  149. LDO3318_PWR_MASK, 0x02);
  150. err = rtsx_pci_send_cmd(pcr, 100);
  151. if (err < 0)
  152. return err;
  153. /* To avoid too large in-rush current */
  154. udelay(150);
  155. rtsx_pci_init_cmd(pcr);
  156. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
  157. SD_POWER_MASK, SD_POWER_ON);
  158. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
  159. LDO3318_PWR_MASK, 0x06);
  160. return rtsx_pci_send_cmd(pcr, 100);
  161. }
  162. static int rts5227_card_power_off(struct rtsx_pcr *pcr, int card)
  163. {
  164. rtsx_pci_init_cmd(pcr);
  165. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
  166. SD_POWER_MASK | PMOS_STRG_MASK,
  167. SD_POWER_OFF | PMOS_STRG_400mA);
  168. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
  169. LDO3318_PWR_MASK, 0X00);
  170. return rtsx_pci_send_cmd(pcr, 100);
  171. }
  172. static int rts5227_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
  173. {
  174. int err;
  175. if (voltage == OUTPUT_3V3) {
  176. err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4FC0 | 0x24);
  177. if (err < 0)
  178. return err;
  179. } else if (voltage == OUTPUT_1V8) {
  180. err = rtsx_pci_write_phy_register(pcr, 0x11, 0x3C02);
  181. if (err < 0)
  182. return err;
  183. err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4C80 | 0x24);
  184. if (err < 0)
  185. return err;
  186. } else {
  187. return -EINVAL;
  188. }
  189. /* set pad drive */
  190. rtsx_pci_init_cmd(pcr);
  191. rts5227_fill_driving(pcr, voltage);
  192. return rtsx_pci_send_cmd(pcr, 100);
  193. }
  194. static const struct pcr_ops rts5227_pcr_ops = {
  195. .fetch_vendor_settings = rts5227_fetch_vendor_settings,
  196. .extra_init_hw = rts5227_extra_init_hw,
  197. .optimize_phy = rts5227_optimize_phy,
  198. .turn_on_led = rts5227_turn_on_led,
  199. .turn_off_led = rts5227_turn_off_led,
  200. .enable_auto_blink = rts5227_enable_auto_blink,
  201. .disable_auto_blink = rts5227_disable_auto_blink,
  202. .card_power_on = rts5227_card_power_on,
  203. .card_power_off = rts5227_card_power_off,
  204. .switch_output_voltage = rts5227_switch_output_voltage,
  205. .cd_deglitch = NULL,
  206. .conv_clk_and_div_n = NULL,
  207. .force_power_down = rts5227_force_power_down,
  208. };
  209. /* SD Pull Control Enable:
  210. * SD_DAT[3:0] ==> pull up
  211. * SD_CD ==> pull up
  212. * SD_WP ==> pull up
  213. * SD_CMD ==> pull up
  214. * SD_CLK ==> pull down
  215. */
  216. static const u32 rts5227_sd_pull_ctl_enable_tbl[] = {
  217. RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
  218. RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
  219. 0,
  220. };
  221. /* SD Pull Control Disable:
  222. * SD_DAT[3:0] ==> pull down
  223. * SD_CD ==> pull up
  224. * SD_WP ==> pull down
  225. * SD_CMD ==> pull down
  226. * SD_CLK ==> pull down
  227. */
  228. static const u32 rts5227_sd_pull_ctl_disable_tbl[] = {
  229. RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
  230. RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
  231. 0,
  232. };
  233. /* MS Pull Control Enable:
  234. * MS CD ==> pull up
  235. * others ==> pull down
  236. */
  237. static const u32 rts5227_ms_pull_ctl_enable_tbl[] = {
  238. RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
  239. RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
  240. 0,
  241. };
  242. /* MS Pull Control Disable:
  243. * MS CD ==> pull up
  244. * others ==> pull down
  245. */
  246. static const u32 rts5227_ms_pull_ctl_disable_tbl[] = {
  247. RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
  248. RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
  249. 0,
  250. };
  251. void rts5227_init_params(struct rtsx_pcr *pcr)
  252. {
  253. pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
  254. pcr->num_slots = 2;
  255. pcr->ops = &rts5227_pcr_ops;
  256. pcr->flags = 0;
  257. pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
  258. pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
  259. pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
  260. pcr->aspm_en = ASPM_L1_EN;
  261. pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 15);
  262. pcr->rx_initial_phase = SET_CLOCK_PHASE(30, 7, 7);
  263. pcr->ic_version = rts5227_get_ic_version(pcr);
  264. pcr->sd_pull_ctl_enable_tbl = rts5227_sd_pull_ctl_enable_tbl;
  265. pcr->sd_pull_ctl_disable_tbl = rts5227_sd_pull_ctl_disable_tbl;
  266. pcr->ms_pull_ctl_enable_tbl = rts5227_ms_pull_ctl_enable_tbl;
  267. pcr->ms_pull_ctl_disable_tbl = rts5227_ms_pull_ctl_disable_tbl;
  268. pcr->reg_pm_ctrl3 = PM_CTRL3;
  269. }
  270. static int rts522a_optimize_phy(struct rtsx_pcr *pcr)
  271. {
  272. int err;
  273. err = rtsx_pci_write_register(pcr, RTS522A_PM_CTRL3, D3_DELINK_MODE_EN,
  274. 0x00);
  275. if (err < 0)
  276. return err;
  277. if (is_version(pcr, 0x522A, IC_VER_A)) {
  278. err = rtsx_pci_write_phy_register(pcr, PHY_RCR2,
  279. PHY_RCR2_INIT_27S);
  280. if (err)
  281. return err;
  282. rtsx_pci_write_phy_register(pcr, PHY_RCR1, PHY_RCR1_INIT_27S);
  283. rtsx_pci_write_phy_register(pcr, PHY_FLD0, PHY_FLD0_INIT_27S);
  284. rtsx_pci_write_phy_register(pcr, PHY_FLD3, PHY_FLD3_INIT_27S);
  285. rtsx_pci_write_phy_register(pcr, PHY_FLD4, PHY_FLD4_INIT_27S);
  286. }
  287. return 0;
  288. }
  289. static int rts522a_extra_init_hw(struct rtsx_pcr *pcr)
  290. {
  291. rts5227_extra_init_hw(pcr);
  292. rtsx_pci_write_register(pcr, FUNC_FORCE_CTL, FUNC_FORCE_UPME_XMT_DBG,
  293. FUNC_FORCE_UPME_XMT_DBG);
  294. rtsx_pci_write_register(pcr, PCLK_CTL, 0x04, 0x04);
  295. rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
  296. rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, 0xFF, 0x11);
  297. return 0;
  298. }
  299. /* rts522a operations mainly derived from rts5227, except phy/hw init setting.
  300. */
  301. static const struct pcr_ops rts522a_pcr_ops = {
  302. .fetch_vendor_settings = rts5227_fetch_vendor_settings,
  303. .extra_init_hw = rts522a_extra_init_hw,
  304. .optimize_phy = rts522a_optimize_phy,
  305. .turn_on_led = rts5227_turn_on_led,
  306. .turn_off_led = rts5227_turn_off_led,
  307. .enable_auto_blink = rts5227_enable_auto_blink,
  308. .disable_auto_blink = rts5227_disable_auto_blink,
  309. .card_power_on = rts5227_card_power_on,
  310. .card_power_off = rts5227_card_power_off,
  311. .switch_output_voltage = rts5227_switch_output_voltage,
  312. .cd_deglitch = NULL,
  313. .conv_clk_and_div_n = NULL,
  314. .force_power_down = rts5227_force_power_down,
  315. };
  316. void rts522a_init_params(struct rtsx_pcr *pcr)
  317. {
  318. rts5227_init_params(pcr);
  319. pcr->ops = &rts522a_pcr_ops;
  320. pcr->tx_initial_phase = SET_CLOCK_PHASE(20, 20, 11);
  321. pcr->reg_pm_ctrl3 = RTS522A_PM_CTRL3;
  322. }