t7l66xb.c 11 KB

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  1. /*
  2. *
  3. * Toshiba T7L66XB core mfd support
  4. *
  5. * Copyright (c) 2005, 2007, 2008 Ian Molton
  6. * Copyright (c) 2008 Dmitry Baryshkov
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. * T7L66 features:
  13. *
  14. * Supported in this driver:
  15. * SD/MMC
  16. * SM/NAND flash controller
  17. *
  18. * As yet not supported
  19. * GPIO interface (on NAND pins)
  20. * Serial interface
  21. * TFT 'interface converter'
  22. * PCMCIA interface logic
  23. */
  24. #include <linux/kernel.h>
  25. #include <linux/module.h>
  26. #include <linux/err.h>
  27. #include <linux/io.h>
  28. #include <linux/slab.h>
  29. #include <linux/irq.h>
  30. #include <linux/clk.h>
  31. #include <linux/platform_device.h>
  32. #include <linux/mfd/core.h>
  33. #include <linux/mfd/tmio.h>
  34. #include <linux/mfd/t7l66xb.h>
  35. enum {
  36. T7L66XB_CELL_NAND,
  37. T7L66XB_CELL_MMC,
  38. };
  39. static const struct resource t7l66xb_mmc_resources[] = {
  40. {
  41. .start = 0x800,
  42. .end = 0x9ff,
  43. .flags = IORESOURCE_MEM,
  44. },
  45. {
  46. .start = IRQ_T7L66XB_MMC,
  47. .end = IRQ_T7L66XB_MMC,
  48. .flags = IORESOURCE_IRQ,
  49. },
  50. };
  51. #define SCR_REVID 0x08 /* b Revision ID */
  52. #define SCR_IMR 0x42 /* b Interrupt Mask */
  53. #define SCR_DEV_CTL 0xe0 /* b Device control */
  54. #define SCR_ISR 0xe1 /* b Interrupt Status */
  55. #define SCR_GPO_OC 0xf0 /* b GPO output control */
  56. #define SCR_GPO_OS 0xf1 /* b GPO output enable */
  57. #define SCR_GPI_S 0xf2 /* w GPI status */
  58. #define SCR_APDC 0xf8 /* b Active pullup down ctrl */
  59. #define SCR_DEV_CTL_USB BIT(0) /* USB enable */
  60. #define SCR_DEV_CTL_MMC BIT(1) /* MMC enable */
  61. /*--------------------------------------------------------------------------*/
  62. struct t7l66xb {
  63. void __iomem *scr;
  64. /* Lock to protect registers requiring read/modify/write ops. */
  65. raw_spinlock_t lock;
  66. struct resource rscr;
  67. struct clk *clk48m;
  68. struct clk *clk32k;
  69. int irq;
  70. int irq_base;
  71. };
  72. /*--------------------------------------------------------------------------*/
  73. static int t7l66xb_mmc_enable(struct platform_device *mmc)
  74. {
  75. struct platform_device *dev = to_platform_device(mmc->dev.parent);
  76. struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
  77. unsigned long flags;
  78. u8 dev_ctl;
  79. int ret;
  80. ret = clk_prepare_enable(t7l66xb->clk32k);
  81. if (ret)
  82. return ret;
  83. raw_spin_lock_irqsave(&t7l66xb->lock, flags);
  84. dev_ctl = tmio_ioread8(t7l66xb->scr + SCR_DEV_CTL);
  85. dev_ctl |= SCR_DEV_CTL_MMC;
  86. tmio_iowrite8(dev_ctl, t7l66xb->scr + SCR_DEV_CTL);
  87. raw_spin_unlock_irqrestore(&t7l66xb->lock, flags);
  88. tmio_core_mmc_enable(t7l66xb->scr + 0x200, 0,
  89. t7l66xb_mmc_resources[0].start & 0xfffe);
  90. return 0;
  91. }
  92. static int t7l66xb_mmc_disable(struct platform_device *mmc)
  93. {
  94. struct platform_device *dev = to_platform_device(mmc->dev.parent);
  95. struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
  96. unsigned long flags;
  97. u8 dev_ctl;
  98. raw_spin_lock_irqsave(&t7l66xb->lock, flags);
  99. dev_ctl = tmio_ioread8(t7l66xb->scr + SCR_DEV_CTL);
  100. dev_ctl &= ~SCR_DEV_CTL_MMC;
  101. tmio_iowrite8(dev_ctl, t7l66xb->scr + SCR_DEV_CTL);
  102. raw_spin_unlock_irqrestore(&t7l66xb->lock, flags);
  103. clk_disable_unprepare(t7l66xb->clk32k);
  104. return 0;
  105. }
  106. static void t7l66xb_mmc_pwr(struct platform_device *mmc, int state)
  107. {
  108. struct platform_device *dev = to_platform_device(mmc->dev.parent);
  109. struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
  110. tmio_core_mmc_pwr(t7l66xb->scr + 0x200, 0, state);
  111. }
  112. static void t7l66xb_mmc_clk_div(struct platform_device *mmc, int state)
  113. {
  114. struct platform_device *dev = to_platform_device(mmc->dev.parent);
  115. struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
  116. tmio_core_mmc_clk_div(t7l66xb->scr + 0x200, 0, state);
  117. }
  118. /*--------------------------------------------------------------------------*/
  119. static struct tmio_mmc_data t7166xb_mmc_data = {
  120. .hclk = 24000000,
  121. .set_pwr = t7l66xb_mmc_pwr,
  122. .set_clk_div = t7l66xb_mmc_clk_div,
  123. };
  124. static const struct resource t7l66xb_nand_resources[] = {
  125. {
  126. .start = 0xc00,
  127. .end = 0xc07,
  128. .flags = IORESOURCE_MEM,
  129. },
  130. {
  131. .start = 0x0100,
  132. .end = 0x01ff,
  133. .flags = IORESOURCE_MEM,
  134. },
  135. {
  136. .start = IRQ_T7L66XB_NAND,
  137. .end = IRQ_T7L66XB_NAND,
  138. .flags = IORESOURCE_IRQ,
  139. },
  140. };
  141. static struct mfd_cell t7l66xb_cells[] = {
  142. [T7L66XB_CELL_MMC] = {
  143. .name = "tmio-mmc",
  144. .enable = t7l66xb_mmc_enable,
  145. .disable = t7l66xb_mmc_disable,
  146. .platform_data = &t7166xb_mmc_data,
  147. .pdata_size = sizeof(t7166xb_mmc_data),
  148. .num_resources = ARRAY_SIZE(t7l66xb_mmc_resources),
  149. .resources = t7l66xb_mmc_resources,
  150. },
  151. [T7L66XB_CELL_NAND] = {
  152. .name = "tmio-nand",
  153. .num_resources = ARRAY_SIZE(t7l66xb_nand_resources),
  154. .resources = t7l66xb_nand_resources,
  155. },
  156. };
  157. /*--------------------------------------------------------------------------*/
  158. /* Handle the T7L66XB interrupt mux */
  159. static void t7l66xb_irq(struct irq_desc *desc)
  160. {
  161. struct t7l66xb *t7l66xb = irq_desc_get_handler_data(desc);
  162. unsigned int isr;
  163. unsigned int i, irq_base;
  164. irq_base = t7l66xb->irq_base;
  165. while ((isr = tmio_ioread8(t7l66xb->scr + SCR_ISR) &
  166. ~tmio_ioread8(t7l66xb->scr + SCR_IMR)))
  167. for (i = 0; i < T7L66XB_NR_IRQS; i++)
  168. if (isr & (1 << i))
  169. generic_handle_irq(irq_base + i);
  170. }
  171. static void t7l66xb_irq_mask(struct irq_data *data)
  172. {
  173. struct t7l66xb *t7l66xb = irq_data_get_irq_chip_data(data);
  174. unsigned long flags;
  175. u8 imr;
  176. raw_spin_lock_irqsave(&t7l66xb->lock, flags);
  177. imr = tmio_ioread8(t7l66xb->scr + SCR_IMR);
  178. imr |= 1 << (data->irq - t7l66xb->irq_base);
  179. tmio_iowrite8(imr, t7l66xb->scr + SCR_IMR);
  180. raw_spin_unlock_irqrestore(&t7l66xb->lock, flags);
  181. }
  182. static void t7l66xb_irq_unmask(struct irq_data *data)
  183. {
  184. struct t7l66xb *t7l66xb = irq_data_get_irq_chip_data(data);
  185. unsigned long flags;
  186. u8 imr;
  187. raw_spin_lock_irqsave(&t7l66xb->lock, flags);
  188. imr = tmio_ioread8(t7l66xb->scr + SCR_IMR);
  189. imr &= ~(1 << (data->irq - t7l66xb->irq_base));
  190. tmio_iowrite8(imr, t7l66xb->scr + SCR_IMR);
  191. raw_spin_unlock_irqrestore(&t7l66xb->lock, flags);
  192. }
  193. static struct irq_chip t7l66xb_chip = {
  194. .name = "t7l66xb",
  195. .irq_ack = t7l66xb_irq_mask,
  196. .irq_mask = t7l66xb_irq_mask,
  197. .irq_unmask = t7l66xb_irq_unmask,
  198. };
  199. /*--------------------------------------------------------------------------*/
  200. /* Install the IRQ handler */
  201. static void t7l66xb_attach_irq(struct platform_device *dev)
  202. {
  203. struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
  204. unsigned int irq, irq_base;
  205. irq_base = t7l66xb->irq_base;
  206. for (irq = irq_base; irq < irq_base + T7L66XB_NR_IRQS; irq++) {
  207. irq_set_chip_and_handler(irq, &t7l66xb_chip, handle_level_irq);
  208. irq_set_chip_data(irq, t7l66xb);
  209. }
  210. irq_set_irq_type(t7l66xb->irq, IRQ_TYPE_EDGE_FALLING);
  211. irq_set_chained_handler_and_data(t7l66xb->irq, t7l66xb_irq, t7l66xb);
  212. }
  213. static void t7l66xb_detach_irq(struct platform_device *dev)
  214. {
  215. struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
  216. unsigned int irq, irq_base;
  217. irq_base = t7l66xb->irq_base;
  218. irq_set_chained_handler_and_data(t7l66xb->irq, NULL, NULL);
  219. for (irq = irq_base; irq < irq_base + T7L66XB_NR_IRQS; irq++) {
  220. irq_set_chip(irq, NULL);
  221. irq_set_chip_data(irq, NULL);
  222. }
  223. }
  224. /*--------------------------------------------------------------------------*/
  225. #ifdef CONFIG_PM
  226. static int t7l66xb_suspend(struct platform_device *dev, pm_message_t state)
  227. {
  228. struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
  229. struct t7l66xb_platform_data *pdata = dev_get_platdata(&dev->dev);
  230. if (pdata && pdata->suspend)
  231. pdata->suspend(dev);
  232. clk_disable_unprepare(t7l66xb->clk48m);
  233. return 0;
  234. }
  235. static int t7l66xb_resume(struct platform_device *dev)
  236. {
  237. struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
  238. struct t7l66xb_platform_data *pdata = dev_get_platdata(&dev->dev);
  239. int ret;
  240. ret = clk_prepare_enable(t7l66xb->clk48m);
  241. if (ret)
  242. return ret;
  243. if (pdata && pdata->resume)
  244. pdata->resume(dev);
  245. tmio_core_mmc_enable(t7l66xb->scr + 0x200, 0,
  246. t7l66xb_mmc_resources[0].start & 0xfffe);
  247. return 0;
  248. }
  249. #else
  250. #define t7l66xb_suspend NULL
  251. #define t7l66xb_resume NULL
  252. #endif
  253. /*--------------------------------------------------------------------------*/
  254. static int t7l66xb_probe(struct platform_device *dev)
  255. {
  256. struct t7l66xb_platform_data *pdata = dev_get_platdata(&dev->dev);
  257. struct t7l66xb *t7l66xb;
  258. struct resource *iomem, *rscr;
  259. int ret;
  260. if (!pdata)
  261. return -EINVAL;
  262. iomem = platform_get_resource(dev, IORESOURCE_MEM, 0);
  263. if (!iomem)
  264. return -EINVAL;
  265. t7l66xb = kzalloc(sizeof *t7l66xb, GFP_KERNEL);
  266. if (!t7l66xb)
  267. return -ENOMEM;
  268. raw_spin_lock_init(&t7l66xb->lock);
  269. platform_set_drvdata(dev, t7l66xb);
  270. ret = platform_get_irq(dev, 0);
  271. if (ret >= 0)
  272. t7l66xb->irq = ret;
  273. else
  274. goto err_noirq;
  275. t7l66xb->irq_base = pdata->irq_base;
  276. t7l66xb->clk32k = clk_get(&dev->dev, "CLK_CK32K");
  277. if (IS_ERR(t7l66xb->clk32k)) {
  278. ret = PTR_ERR(t7l66xb->clk32k);
  279. goto err_clk32k_get;
  280. }
  281. t7l66xb->clk48m = clk_get(&dev->dev, "CLK_CK48M");
  282. if (IS_ERR(t7l66xb->clk48m)) {
  283. ret = PTR_ERR(t7l66xb->clk48m);
  284. goto err_clk48m_get;
  285. }
  286. rscr = &t7l66xb->rscr;
  287. rscr->name = "t7l66xb-core";
  288. rscr->start = iomem->start;
  289. rscr->end = iomem->start + 0xff;
  290. rscr->flags = IORESOURCE_MEM;
  291. ret = request_resource(iomem, rscr);
  292. if (ret)
  293. goto err_request_scr;
  294. t7l66xb->scr = ioremap(rscr->start, resource_size(rscr));
  295. if (!t7l66xb->scr) {
  296. ret = -ENOMEM;
  297. goto err_ioremap;
  298. }
  299. ret = clk_prepare_enable(t7l66xb->clk48m);
  300. if (ret)
  301. goto err_clk_enable;
  302. if (pdata->enable)
  303. pdata->enable(dev);
  304. /* Mask all interrupts */
  305. tmio_iowrite8(0xbf, t7l66xb->scr + SCR_IMR);
  306. printk(KERN_INFO "%s rev %d @ 0x%08lx, irq %d\n",
  307. dev->name, tmio_ioread8(t7l66xb->scr + SCR_REVID),
  308. (unsigned long)iomem->start, t7l66xb->irq);
  309. t7l66xb_attach_irq(dev);
  310. t7l66xb_cells[T7L66XB_CELL_NAND].platform_data = pdata->nand_data;
  311. t7l66xb_cells[T7L66XB_CELL_NAND].pdata_size = sizeof(*pdata->nand_data);
  312. ret = mfd_add_devices(&dev->dev, dev->id,
  313. t7l66xb_cells, ARRAY_SIZE(t7l66xb_cells),
  314. iomem, t7l66xb->irq_base, NULL);
  315. if (!ret)
  316. return 0;
  317. t7l66xb_detach_irq(dev);
  318. clk_disable_unprepare(t7l66xb->clk48m);
  319. err_clk_enable:
  320. iounmap(t7l66xb->scr);
  321. err_ioremap:
  322. release_resource(&t7l66xb->rscr);
  323. err_request_scr:
  324. clk_put(t7l66xb->clk48m);
  325. err_clk48m_get:
  326. clk_put(t7l66xb->clk32k);
  327. err_clk32k_get:
  328. err_noirq:
  329. kfree(t7l66xb);
  330. return ret;
  331. }
  332. static int t7l66xb_remove(struct platform_device *dev)
  333. {
  334. struct t7l66xb_platform_data *pdata = dev_get_platdata(&dev->dev);
  335. struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
  336. int ret;
  337. ret = pdata->disable(dev);
  338. clk_disable_unprepare(t7l66xb->clk48m);
  339. clk_put(t7l66xb->clk48m);
  340. clk_disable_unprepare(t7l66xb->clk32k);
  341. clk_put(t7l66xb->clk32k);
  342. t7l66xb_detach_irq(dev);
  343. iounmap(t7l66xb->scr);
  344. release_resource(&t7l66xb->rscr);
  345. mfd_remove_devices(&dev->dev);
  346. kfree(t7l66xb);
  347. return ret;
  348. }
  349. static struct platform_driver t7l66xb_platform_driver = {
  350. .driver = {
  351. .name = "t7l66xb",
  352. },
  353. .suspend = t7l66xb_suspend,
  354. .resume = t7l66xb_resume,
  355. .probe = t7l66xb_probe,
  356. .remove = t7l66xb_remove,
  357. };
  358. /*--------------------------------------------------------------------------*/
  359. module_platform_driver(t7l66xb_platform_driver);
  360. MODULE_DESCRIPTION("Toshiba T7L66XB core driver");
  361. MODULE_LICENSE("GPL v2");
  362. MODULE_AUTHOR("Ian Molton");
  363. MODULE_ALIAS("platform:t7l66xb");